View TPS61170DRV_3488748.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features description applications tps61170 slvs789 ? november 2007 www.ti.com 1.2a high voltage boost converter in 2x2mm 2 qfn package 3-v to 18-v input voltage range high output voltage: up to 38 v the tps61170 is a monolithic high voltage switching regulator with integrated 1.2-a, 40-v power mosfet. 1.2-a integrated switch it can be configured in several standard 1.2-mhz fixed switching frequency switching-regulator topologies, including boost and 12 v at 300 ma and 24 v at 150 ma from 5-v sepic. the device has a wide input-voltage range to input (typical) support applications with input voltage from multi-cell batteries or regulated 5-v, 12-v power rails. up to 93% efficiency the tps61170 uses a 1.2-mhz switching frequency, on-the-fly output voltage reprogramming allowing the use low-profile inductors and low-value skip-switching cycle for output regulation at ceramic input and output capacitors. the external light load loop compensation gives the user flexibility to built-in soft start optimize loop compensation and transient response. the device has built-in protection features, such as 6-pin, 2 mm 2 mm qfn package pulse-by-pulse overcurrent limit, soft start and thermal shutdown. 5-v to 12-v and 24-v, 12-v to 24-v boost the feedback reference voltage of the fb pin is converter 1.229v. it can be lowered using a 1-wire digital interface (easyscale? protocol) through the ctrl buck boost regulation using sepic topology pin. alternatively, a pulsewidth-modulation (pwm) adsl modems signal can be applied to the ctrl pin. the duty cycle of the signal reduces the feedback reference voltage proportionally. the tps61170 is available in a 6-pin 2 mm 2 mm qfn package, allowing a compact power-supply solution. figure 1. typical application 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. vin 5 v l1 10 h m d1 vin sw fb gnd ctrl comp c2 4.7 f m c3 680 pf tps 61170 r1 87.6 k w vout 12 v/ 300 ma r2 10 k w r3 10 k w c1 4.7 f m l1: toko#a915_y-100m c1: murata grm188r61a475k c2: murata grm21br61e475k d1: onsemi mbr0540t1 *r3, c3: compensation rc network
absolute maximum ratings dissipation ratings recommended operating conditions tps61170 slvs789 ? november 2007 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. ordering information (1) t a package (2) package marking ? 40 c to 85 c TPS61170DRV bzs (1) for the most current package and ordering information, see the ti web site at www.ti.com . (2) the drv package is available in tape and reel. add r suffix (TPS61170DRVr) to order quantities of 3000 parts per reel or add t suffix (TPS61170DRVt) to order 250 parts per reel. over operating free-air temperature range (unless otherwise noted) (1) value unit supply voltages on vin (2) ? 0.3 to 20 v voltages on ctrl (2) ? 0.3 to 20 v v i voltage on fb and comp (2) ? 0.3 to 3 v voltage on sw (2) ? 0.3 to 40 v p d continuous power dissipation see dissipation rating table t j operating junction temperature range ? 40 to 150 c t stg storage temperature range ? 65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. derating factor board package r q jc r q ja t a < 25 c t a = 70 c t a = 85 c above t a = 25 c low-k (1) drv 20 c/w 140 c/w 7.1 mw/ c 715 mw 395 mw 285 mw high-k (2) drv 20 c/w 65 c/w 15.4 mw/ c 1540 mw 845 mw 615 mw (1) the jedec low-k (1s) board used to derive this data was a 3in 3in, two-layer board with 2-ounce copper traces on top of the board. (2) the jedec high-k (2s2p) board used to derive this data was a 3in 3in, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. min typ max unit v i input voltage range, vin 3 18 v v o output voltage range vin 38 v l inductor (1) 10 22 m h c i input capacitor 1 m f c o output capacitor 1 10 m f t a operating ambient temperature ? 40 85 c t j operating junction temperature ? 40 125 c (1) these values are recommended values that have been successfully tested in several applications. other values may be acceptable in other applications but should be fully tested by the user. 2 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com
electrical characteristics tps61170 slvs789 ? november 2007 vin = 3.6 v, ctrl = vin, t a = ? 40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit supply current v i input voltage range, vin 3.0 18 v i q operating quiescent current into vin device pwm switching no load 2.3 ma i sd shutdown current crtl=gnd, vin = 4.2 v 1 m a uvlo under-voltage lockout threshold vin falling 2.2 2.5 v v hys under-voltage lockout hysterisis 70 mv enable and reference control v (ctrlh) ctrl logic high voltage vin = 3 v to 18 v 1.2 v v (ctrl) ctrl logic low voltage vin = 3 v to 18 v 0.4 v r (ctrl) ctrl pull down resistor 400 800 1600 k ? t off ctrl pulse width to shutdown ctrl high to low 2.5 ms t es_det easy scale detection time (1) ctrl pin low 260 m s t es_delay easy scale detection delay 100 m s t es_win easy scale detection window time 1 ms voltage and current control v ref voltage feedback regulation voltage 1.204 1.229 1.254 v voltage feedback regulation voltage under v (ref_pwm) v fb = 492 mv 477 492 507 mv reprogram i fb voltage feedback input bias current v fb = 1.229 v 200 na f s oscillator frequency 1.0 1.2 1.5 mhz d max maximum duty cycle v fb = 100 mv 90% 93% t min_on minimum on pulse width 40 ns i sink comp pin sink current 100 m a i source comp pin source current 100 m a g ea error amplifier transconductance 240 320 400 umho r ea error amplifier output resistance 5 pf connected to comp 6 m ? f ea error amplifier crossover frequency 5 pf connected to comp 500 khz power switch vin = 3.6 v 0.3 0.6 r ds(on) n-channel mosfet on-resistance ? vin = 3.0 v 0.7 i ln_nfet n-channel leakage current v sw = 35 v, t a = 25 c 1 m a oc and ss i lim n-channel mosfet current limit d = d max 0.96 1.2 1.44 a i lim_start start up current limit d = d max 0.7 a t half_lim time step for half current limit 5 ms t ref vref filter time constant 180 m s t step v ref ramp up time 213 m s (1) easyscale communication is allowed immediately after the ctrl pin has been low for more than t es_det . to select easyscale? mode, the ctrl pin must be low for more than t es_det the end of t es_win . copyright ? 2007, texas instruments incorporated submit documentation feedback 3 product folder link(s): tps61170 www.ti.com
pin assignments tps61170 slvs789 ? november 2007 electrical characteristics (continued) vin = 3.6 v, ctrl = vin, t a = ? 40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit easyscale timing t start start time of program stream 2 m s t eos end time of program stream 2 360 m s t h_lb high time low bit logic 0 2 180 m s t l_lb low time low bit logic 0 2 t h_lb 360 m s t h_hb high time high bit logic 1 2 t l_hb 360 m s t l_hb low time high bit logic 1 2 180 m s v acknl acknowledge output voltage low open drain, r pullup =15 k ? to vin 0.4 v t valackn acknowledge valid time see (2) 2 m s t ackn duration of acknowledge condition see (2) 512 m s thermal shutdown t shutdown thermal shutdown threshold 160 c t hysteresis thermal shutdown threshold hysteresis 15 c (2) acknowledge condition active 0, this condition will only be applied if the rfa bit is set. open drain output, line needs to be pulled high by the host with resistor load. terminal functions terminal i/o description name no. vin 6 i the input supply pin for the ic. connect vin to a supply voltage between 3 v and 18 v. sw 4 i this is the switching node of the ic. connect sw to the switched side of the inductor. gnd 3 o ground fb 1 i feedback pin for current. connect to the center tap of a resistor divider to program the output voltage. output of the transconductance error amplifier. connect an external rc network to this pin to compensate comp 2 o the regulator. control pin of the boost regulator. ctrl is a multi-functional pin which can be used for enable the device ctrl 5 i and control the feedback voltage with a pwm signal and digital communications. the thermal pad should be soldered to the analog ground plane to avoid thermal issue. if possible, use thermal pad thermal via to connect to ground plane for ideal power dissipation. 4 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com vinctrl sw fb comp gnd top view thermal pad 6-pin 2mm x 2mm x 0.8mm qfn
functional block diagram typical characteristics table of graphs tps61170 slvs789 ? november 2007 circuit of figure 1, l = toko a915_y-100m, d1 = onsemi mbr0540t1, unless otherwise noted. figure efficiency vin = 5v; vout = 12v,18v,24v,30v; figure 2 efficiency vin = 5v, 8.5v, 12v; vout = 24v; figure 3 output voltage accuracy i load = 100 ma figure 4 switch current limit t a = 25 c figure 5 switch current limit figure 6 error amplifier transconductance figure 7 easyscale step figure 8 pwm switching operation vin = 5v; vout = 12v; i load = 250ma; figure 9 load transient response vin = 5v; vout = 12v; i load = 50ma to 150ma; figure 10 start-up vin = 5v; vout = 12v; i load = 250ma; figure 11 skip-cycle switching vin = 9v ; vout = 12v, i load = 100 m a ; figure 12 copyright ? 2007, texas instruments incorporated submit documentation feedback 5 product folder link(s): tps61170 www.ti.com sw ramp generator oscillator current sensor ctrl gnd c3 l1 + fb band gap d1 error amplifer 2 1 r2 c2 vin c1 pwm control 4 6 soft start-up 5 3 comp r1 r3
tps61170 slvs789 ? november 2007 efficiency efficiency vs vs output current output current figure 2. figure 3. output voltage switch current limit vs vs input voltage duty cycle figure 4. figure 5. switch current limit error amplifier transconductance vs vs temperature temperature figure 6. figure 7. 6 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com 40 50 60 70 80 90 100 0 50 100 150 200 250 300 vout = 24 v vin = 8.5 v vin = 5 v vin = 12 v efficiency - % output current - ma 40 50 60 70 80 90 100 0 50 100 150 200 250 300 vout = 12 v vout = 18 v vout = 24 v vout = 30 v efficiency - % output current - ma vin = 5 v 11.88 11.90 11.92 11.94 11.96 3 4 5 6 7 8 9 10 11 v - input voltage - v i t = 25c a i = 100 ma load v - output voltage - v o t = 85c a t = -40c a 800 900 1000 1100 1200 1300 1400 1500 1600 20 30 40 50 60 70 80 90 duty cycle - % switch current limit - a 800 900 1000 1100 1200 1300 1400 1500 1600 -40 -20 0 20 40 60 80 100 120 140 temperature - c switch current limit - ma 0 100 200 300 400 500 -40 -20 0 20 40 60 80 100 120 140 temperature - c error amplifier transconductance - mhos
tps61170 slvs789 ? november 2007 fb voltage vs easy scale step pwm switching operation figure 8. figure 9. load transient response start-up figure 10. figure 11. skip-cycle switching figure 12. copyright ? 2007, texas instruments incorporated submit documentation feedback 7 product folder link(s): tps61170 www.ti.com sw 5 v/div vout 100 mv/div ac i 500 ma/div l t - 400 ns/div 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 easy scale step fb voltage - v ctrl 5 v/div vout 5 v/div comp 500 mv/div i 500 ma/div l t - 1 ms/div vout 200 mv/div ac i 100 ma/div load t - 40 s/div m sw 5 v/div vout 20 mv/div ac i 50 ma/div l t - 400 ns/div
detailed description operation soft start-up overcurrent protection undervoltage lockout (uvlo) thermal shutdown enable and shutdown tps61170 slvs789 ? november 2007 the tps61170 integrates a 40-v low side fet for up to 38-v output voltages. the device regulates the output with current mode pwm (pulse width modulation) control. the switching frequency of pwm is fixed at 1.2mhz. the pwm control circuitry turns on the switch at the beginning of each switching cycle. the input voltage is applied across the inductor and stores the energy as inductor current ramps up. during this portion of the switching cycle, the load current is provided by the output capacitor. when the inductor current rises to the threshold set by the error amplifier output, the power switch turns off and the external schottky diode is forward biased. the inductor transfers stored energy to replenish the output capacitor and supply the load current. this operation repeats in every switching cycle. as shown in the block diagram, the duty cycle of the converter is determined by the pwm control comparator which compares the error amplifier output and the current signal. a ramp signal from oscillator is added to the current ramp. this slope compensation is to avoid sub-harmonic oscillation that is intrinsic to the current mode control at duty cycle higher than 50%. the feedback loop regulates the fb pin to a reference voltage through an error amplifier. the output of the error amplifier is connected to the comp pin. an external rc compensation network is connected to the comp pin to optimize the feedback loop for stability and transient response. soft-start circuitry is integrated into the ic to avoid a high inrush current during start-up. after the device is enabled by a logic high signal on the ctrl pin, the fb pin reference voltage ramps up in 32 steps, each step takes 213 m s. this ensures that the output voltage rises slowly to reduce inrush current. additionally, for the first 5msec after the comp voltage ramps, the current limit of the pwm switch is set to half of the normal current limit spec. therefore, during this period the input current is kept below 700ma (typical). see the start-up waveform for a typical example, figure 11 . tps61170 has a cycle-by-cycle overcurrent limit feature that turns off the power switch once the inductor current reaches the overcurrent limit. the pwm circuitry resets itself at the beginning of the next switch cycle. during an over-current event, this results in a decrease of output voltage with respect to load. the current limit threshold as well as input voltage, output voltage, switching frequency and inductor value determine the maximum available output current. larger inductor values increases the current output capability because of the reduced current ripple. see the application information section for the output current calculation. an undervoltage lockout prevents mis-operation of the device at input voltages below typical 2.2v. when the input voltage is below the undervoltage threshold, the device remains off and the internal switch fet is turned off. the undervoltage lockout threshold is set below minimum operating voltage of 3v to avoid any transient vin dip triggering the uvlo and causing the device to reset. for the input voltages between uvlo threshold and 3v, the device maintains its operation, but the specifications are not ensured. an internal thermal shutdown turns off the device when the typical junction temperature of 160 c is exceeded. the ic restarts when the junction temperature drops by 15 c. the tps61170 enters shutdown when the ctrl voltage is less than 0.4v for more than 2.5ms. in shutdown, the input supply current for the device is less than 1 m a (max). the ctrl pin has an internal 800k ? pull down resistor to disable the device when the pin is left unconnected. 8 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com
feedback reference program mode selection pwm program mode (1) tps61170 slvs789 ? november 2007 the ctrl pin is used for changing the fb pin reference voltage on-the-fly. there are two methods to program the reference voltage, pwm signal and 1 wire interface (easyscale?). the program mode is selected each time the device is enabled. the default mode is the pwm signal which uses the duty cycle of the ctrl pin signal to modulate the reference voltage. to enter the 1 wire interface mode, the following digital pattern on the ctrl pin must be recognized by the ic every time the ic starts from the shutdown mode. 1. pull ctrl pin high to enable the tps61170 and to start the 1 wire mode detection window. 2. after the easyscale detection delay (t es_delay , 100 m sec) expires, drive ctrl low for more than the easyscale detection time (t es_detect , 260 m sec). 3. the ctrl pin has to be low for more than easyscale detection time before the easyscale detection window (t es_win , 1msec) expires. easyscale detection window starts from the first ctrl pin low to high transition. the ic immediately enters the 1 wire mode once the above 3 conditions are met. the easyscale communication can start before the detection window expires. once the mode is programmed, it can not be changed without another start up. this means the ic needs to be shutdown by pulling the ctrl low for 2.5ms and restarts. see the mode detection of feedback reference program figure (figure 13 ) for a graphical explanation. figure 13. mode detection of feedback reference program when the ctrl pin is constantly high, the fb voltage is regulated to 1.229v typically. however, the ctrl pin allows a pwm signal to reduce this regulation voltage. the relationship between the duty cycle and fb voltage is given in equation 1 : where: duty = duty cycle of the pwm signal 1.229 v = internal reference voltage as shown in figure 14 , the ic chops up the internal 1.229v reference voltage at the duty cycle of the pwm signal. the pulse signal is then filtered by an internal low pass filter. the output of the filter is connected to the error amplifier as the reference voltage for the fb pin regulation. the regulation voltage is independent of the pwm logic voltage level which often has large variations. for optimum performance, use the pwm mode in the range of 5khz to 100khz. the requirement of minimum frequency comes from the easyscale detection delay and detection time specification for the mode selection. the device can mistakenly enter 1 wire mode if the pwm signal frequency is less than 5khz. since the ctrl pin is logic only pin, adding external rc filter to the pin does not work. copyright ? 2007, texas instruments incorporated submit documentation feedback 9 product folder link(s): tps61170 www.ti.com ctrl low high fb 200mv x duty cycle insert battery ctrl low high fb insert battery programming code fb ramp shutdown delay t enter es mode timing window programming code 50mv 50mv enter es mode pwm signal startup delay pwmmode startup delay fb ramp programmed value (if not programmed, 200mv default ) shutdown delay ic shutdown startup delay fb ramp es mode es detect delay es detect time v fb duty 1.229 v
1 wire program mode easyscale? tps61170 slvs789 ? november 2007 figure 14. block diagram of programmable fb voltage using pwm signal the ctrl pin features a simple digital interface to control the feedback reference voltage. the 1 wire mode can save the processor power and battery life as it does not require a pwm signal all the time, and the processor can enter idle mode if available. the tps61170 adopts the easyscale? protocol, which can program the fb voltage to any of the 32 steps with single command. see the table 1 for the fb pin voltage steps. the programmed reference voltage is stored in an internal register. the default value is full scale when the device is first enabled (v fb = 1.229v). a power reset clears the register value and reset it to default. easyscale is a simple but very flexible one pin interface to configure the fb voltage. the interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. figure 15 and table 1 give an overview of the protocol. the protocol consists of a device specific address byte and a data byte. the device specific address byte is fixed to 72 hex. the data byte consists of five bits for information, two address bits, and the rfa bit. the rfa bit set to high indicates the request for acknowledge condition. the acknowledge condition is only applied if the protocol was received correctly. the advantage of easyscale compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. it can automatically detect bit rates between 1.7kbit/sec and up to 160kbit/sec. table 1. selectable fb voltage fb voltage d4 d3 d2 d1 d0 (mv) 0 0.000 0 0 0 0 0 1 0.031 0 0 0 0 1 2 0.049 0 0 0 1 0 3 0.068 0 0 0 1 1 4 0.086 0 0 1 0 0 5 0.104 0 0 1 0 1 6 0.123 0 0 1 1 0 7 0.141 0 0 1 1 1 8 0.160 0 1 0 0 0 9 0.178 0 1 0 0 1 10 0.197 0 1 0 1 0 11 0.215 0 1 0 1 1 12 0.234 0 1 1 0 0 13 0.270 0 1 1 0 1 14 0.307 0 1 1 1 0 10 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com vbg 1.229 v ctrl erroramplifier fb
tps61170 slvs789 ? november 2007 table 1. selectable fb voltage (continued) fb voltage d4 d3 d2 d1 d0 (mv) 15 0.344 0 1 1 1 1 16 0.381 1 0 0 0 0 17 0.418 1 0 0 0 1 18 0.455 1 0 0 1 0 19 0.492 1 0 0 1 1 20 0.528 1 0 1 0 0 21 0.565 1 0 1 0 1 22 0.602 1 0 1 1 0 23 0.639 1 0 1 1 1 24 0.713 1 1 0 0 0 25 0.787 1 1 0 0 1 26 0.860 1 1 0 1 0 27 0.934 1 1 0 1 1 28 1.008 1 1 1 0 0 29 1.082 1 1 1 0 1 30 1.155 1 1 1 1 0 31 1.229 1 1 1 1 1 figure 15. easyscale? protocol overview table 2. easyscale? bit description bit transmission byte name description number direction 7 da7 0 msb device address 6 da6 1 5 da5 1 device 4 da4 1 address in byte 3 da3 0 72 hex 2 da2 0 1 da1 1 0 da0 0 lsb device address 7 (msb) rfa request for acknowledge. if high, acknowledge is applied by device 6 a1 0 address bit 1 5 a0 0 address bit 0 4 d4 data bit 4 data byte in 3 d3 data bit 3 2 d2 data bit 2 1 d1 data bit 1 0 (lsb) d0 data bit 0 copyright ? 2007, texas instruments incorporated submit documentation feedback 11 product folder link(s): tps61170 www.ti.com data in start data out ack rfa a1 a0 d4 d3 d2 d1 d0 da7 0 da6 1 da5 1 da4 1 da3 0 da2 0 da1 1 da0 0 device address databyte eos start eos start
tps61170 slvs789 ? november 2007 table 2. easyscale? bit description (continued) bit transmission byte name description number direction acknowledge condition active 0, this condition will only be applied in case rfa bit is set. open drain output, line needs to be pulled high by the host with a pullup ack out resistor. this feature can only be used if the master has an open drain output stage. in case of a push pull output stage acknowledge condition may not be requested! figure 16. easyscale? ? bit coding all bits are transmitted msb first and lsb last. figure 16 shows the protocol without acknowledge request (bit rfa = 0), figure 16 with acknowledge (bit rfa = 1) request. prior to both bytes, device address byte and data byte, a start condition must be applied. for this, the ctrl pin must be pulled high for at least t start (2 m s) before the bit transmission starts with the falling edge. if the ctrl pin is already at high level, no start condition is needed prior to the device address byte. the transmission of each byte is closed with an end of stream condition for at least t eos (2 m s). 12 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com low bit (logic 0) high bit (logic 1) t low t high t low t high easy scale timing, without acknowledge rfa = 0 da7 0 t start static high static high data in t start t eos t eos da0 0 rfa 0 d0 1 address byte data byte easy scale timing, with acknowledge rfa = 1 static high t ackn acknowledgetrue , data line pulled down bydevice data in data out acknowledgefalse , no pull down controller needs topullup data line via a resistor to detect ackn ackn da7 0 static high t eos t valack da0 0 rfa 1 d0 1 t start t start address byte data byte
tps61170 slvs789 ? november 2007 the bit detection is based on a logic detection scheme, where the criterion is the relation between t low and t high . it can be simplified to: high bit: t high > t low , but with t high at least 2x t low , see figure 16 . low bit: t high < t low , but with t low at least 2x t high , see figure 16 . the bit detection starts with a falling edge on the ctrl pin and ends with the next falling edge. depending on the relation between t high and t low , the logic 0 or 1 is detected. the acknowledge condition is only applied if: acknowledge is requested by a set rfa bit. the transmitted device address matches with the device address of the device. 16 bits is received correctly. if the device turns on the internal ackn-mosfet and pulls the ctrl pin low for the time t ackn , which is 512 m s maximum then the acknowledge condition is valid after an internal delay time t valack . this means that the internal ackn-mosfet is turned on after t valack , when the last falling edge of the protocol was detected. the master controller keeps the line low in this period. the master device can detect the acknowledge condition with its input by releasing the ctrl pin after t valack and read back a logic 0. the ctrl pin can be used again after the acknowledge condition ends. note that the acknowledge condition may only be requested if the master device has an open drain output. for the push-pull output stage, the use a series resistor in the crtl line to limit the current to 500 m a is recommended for such cases as: an accidentally requested acknowledge, or to protect the internal ackn-mosfet. copyright ? 2007, texas instruments incorporated submit documentation feedback 13 product folder link(s): tps61170 www.ti.com
application information program output voltage (2) maximum output current (3) (4) tps61170 slvs789 ? november 2007 figure 17. program output voltage to program the output voltage, select the values of r1 and r2 (see figure 17 ) according to equation 2 . considering the leakage current through the resistor divider and noise decoupling to fb pin, an optimum value for r2 is around 10k. the output voltage tolerance depends on the vfb accuracy and the tolerance of r1 and r2. the overcurrent limit in a boost converter limits the maximum input current, and thus the maximum input power for a given input voltage. the maximum output power is less than the maximum input power due to power conversion losses. therefore, the current-limit setting, input voltage, output voltage and efficiency can all affect the maximum output current. the current limit clamps the peak inductor current; therefore, the ripple must be subtracted to derive the maximum dc current. the ripple current is a function of the switching frequency, inductor value and duty cycle. the following equations take into account of all the above factors for maximum output current calculation. where: i p = inductor peak to peak ripple l = inductor value v f = schottky diode forward voltage f s = switching frequency v out = output voltage where: i out_max = maximum output current of the boost converter i lim = overcurrent limit h = efficiency for instance, when v in is 5 v, v out is 12 v, the inductor is 10 m h, the schottky forward voltage is 0.2 v; and then the maximum output current is 300 ma in typical operation. 14 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com fb tps61170 r2 r1 vout r1 vout vout = 1.229 v x + 1 r1 = r2 x 1 r2 1.229 v - ? ? ? ? ? ? ? ? ? ? + - + = ) v 1 v v v 1 ( f l 1 i in in f out s p out p lim in max _ out v ) 2 i i( v i h - =
switch duty cycle (5) inductor selection (6) tps61170 slvs789 ? november 2007 the maximum switch duty cycle (d) of the tps61170 is 90% (min). the duty cycle of a boost converter under continuous conduction mode (ccm) is given by: for a 5v to 12v application, the duty cycle is 58.3%, and for a 5v to 24v application, the duty cycle is 79.2%. the duty cycle must be lower than the maximum specification of 90% in the application; otherwise, the output voltage can not be regulated. once the pwm switch is turned on, the tps61170 has minimum on pulse width. this sets the limit of the minimum duty cycle. for operating low duty cycle, the tps61170 enters pulse-skipping mode. in this mode, the device keeps the power switch off for several switching cycles to keep the output voltage in regulation. this operation typically occurs in light load condition when the pwm operates in discontinuous mode. see the figure 12 . the selection of the inductor affects steady state operation as well as transient behavior and loop stability. these factors make it the most important component in power regulator design. there are three important inductor specifications, inductor value, dc resistance and saturation current. considering inductor value alone is not enough. the inductor ? s value determines the inductor ripple current. it is recommended that the peak-to-peak ripple current given by equation 3 be set to 30 ? 40% of the dc current. also, the inductor value should not be beyond the range in the recommended operating conditions table. it is a good compromise of power losses and inductor size. inductor dc current can be calculated as inductor values can have 20% tolerance with no current bias. when the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0a value depending on how the inductor vendor defines saturation current. using an inductor with a smaller inductance value forces discontinuous pwm where the inductor current ramps down to zero before the end of each switching cycle. this reduces the boost converter ? s maximum output current, causes large input voltage ripple and reduces efficiency. in general, large inductance value provides much more output and higher conversion efficiency. small inductance value can give better the load transient response. for these reasons, a 10 m h to 22 m h inductor value range is recommended. table 3 lists the recommended inductor for the tps61170. tps61170 has built-in slope compensation to avoid sub-harmonic oscillation associated with current mode control. if the inductor value is lower than 10 m h, the slope compensation may not be adequate, and the loop can be unstable. therefore, customers need to verify the inductor in their application if it is different from the recommended values. table 3. recommended inductors for tps61170 l dcr max saturation current size part number vendor ( m h) (m ? ) (a) (l w h mm) a915_y-100m 10 90 1.3 5.2 5.2 3.0 toko vlcf5020t-100m1r1-1 10 237 1.1 5 5 2.0 tdk cdrh4d22/hp 10 144 1.2 5 5 2.4 sumida lqh43pn100mr0 10 247 0.84 4.5 3.2 2.0 murata copyright ? 2007, texas instruments incorporated submit documentation feedback 15 product folder link(s): tps61170 www.ti.com d vout vin vout i in_dc vout iout vin
schottky diode selection compensation capacitor selection (7) (8) (9) (10) (11) input and output capacitor selection (12) tps61170 slvs789 ? november 2007 the high switching frequency of the tps61170 demands a high-speed rectification for optimum efficiency. ensure that the diode ? s average and peak current rating exceeds the average output current and peak inductor current. in addition, the diode ? s reverse breakdown voltage must exceed the switch fet rating voltage of 40v. so, the onsemi mbr0540 is recommended for tps61170. however, schottky diode of low rating voltage can be used for low output to save the solution size and cost. for example, 12v output with 20v diode is a good choice. the tps61170 has an external compensation, comp pin, which allows the loop response to be optimized for each application. the comp pin is the output of the internal error amplifier. an external resistor r3 and ceramic capacitors c3 are connected to comp pin to provide a pole and a zero. this pole and zero, along with the inherent pole an zero in a current mode control boost converter, determine the close loop frequency response. this is important to a converter stability and transient response. the following equations summarize the poles, zeros and dc gain in tps61170, as shown in the block diagram. they include the dominant pole (f p1 ), the output pole (f p2 ) of a boost converter, the right-half-plane zero (f rhpz ) of a boost converter, the zero (f z ) generated by r3 and c3, and the dc gain (a). where rout is the load resistance, gea is the error amplifier transconductance located in the electrical characteristics table, rsense (100m ? ) is a sense resistor in the current control loop. these equations helps generate a simple bode plot for tps61170 loop analysis. increasing r3 or reducing c3 increases the close loop bandwidth which improves the transient response. adjusting r3 and c3 toward opposite direction increase the phase, and help loop stability. for most of the applications, the recommended value of 10k and 680pf makes an ideal compromise between transient response and loop stability. to optimize the compensation, use c3 in the range of 100pf to 10nf, and r3 of 10k. see the ti application report for thorough analysis and description of the boost converter small signal model and compensation design. the output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. this ripple voltage is related to the capacitor ? s capacitance and its equivalent series resistance (esr). assuming a capacitor with zero esr, the minimum capacitance needed for a given ripple can be calculated using equation 12 . where, v ripple = peak-to-peak output ripple. the additional output ripple component caused by esr is calculated using: due to its low esr, vripple_esr can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used. 16 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com p1 1 f = 2 x 6 m x c3 p w p2 2 f = 2 x rout x c2 p 2 rhpz rout f = x 2 x l vin vout p ? ? ? ? z 1 f = 2 x r3 x c3 p 1.229 a = vout vin 1 x gea x 6 m x x rout x vout x rsense 2 w c out v out v in i out v out fs v ripple v ripple_esr i out r esr
layout considerations thermal considerations tps61170 slvs789 ? november 2007 care must be taken when evaluating a ceramic capacitor ? s derating under dc bias, aging and ac signal. for example, larger form factor capacitors (in 1206 size) have a resonant frequencies in the range of the switching frequency. so, the effective capacitance is significantly lower. the dc bias can also significantly reduce capacitance. ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. therefore, choose a ceramic capacitor with a voltage rating at least 1.5x its expected dc bias voltage. the capacitor in the range of 1 m f to 4.7 m f is recommended for input side. the output requires a capacitor in the range of 1 m f to 10 m f. the output capacitor affects the loop stability of the boost regulator. if the output capacitor is below the range, the boost regulator can potentially become unstable. the popular vendors for high value ceramic capacitors are: tdk (http://www.component.tdk.com/components.php ) murata (http://www.murata.com/cap/index.html ) as for all switching power supplies, especially those high frequency and high current ones, layout is an important design step. if layout is not carefully done, the regulator could suffer from instability as well as noise problems. to maximize efficiency, switch rise and fall times are made as short as possible. to prevent radiation of high frequency resonance problems, proper layout of the high frequency switching path is essential. minimize the length and area of all traces connected to the sw pin and always use a ground plane under the switching regulator to minimize interplane coupling. the high current path including the switch, schottky diode, and output capacitor, contains nanosecond rise and fall times and should be kept as short as possible. the input capacitor needs not only to be close to the vin pin, but also to the gnd pin in order to reduce the ic supply ripple. figure 18 shows a sample layout figure 18. pcb layout recommendation the maximum ic junction temperature should be restricted to 125 c under normal operating conditions. this restriction limits the power dissipation of the tps61170. calculate the maximum allowable dissipation, p d(max) , and keep the actual dissipation less than or equal to p d(max) . the maximum-power-dissipation limit is determined using equation 13 : copyright ? 2007, texas instruments incorporated submit documentation feedback 17 product folder link(s): tps61170 www.ti.com ctrl gnd c3 l1 r2 vin ctrl sw fb comp gnd c1 vin c2 vout minimize thearea of this trace place enoughvias around thermal pad to enhance thermal performance r3 r1 note: minimize the trace area at fb pin and comp pin
(13) additional typical applications tps61170 slvs789 ? november 2007 where, t a is the maximum ambient temperature for the application. r q ja is the thermal resistance junction-to-ambient given in power dissipation table. the tps61170 comes in a thermally enhanced qfn package. this package includes a thermal pad that improves the thermal capabilities of the package. the r q ja of the qfn package greatly depends on the pcb layout and thermal pad connection. the thermal pad must be soldered to the analog ground on the pcb. using thermal vias underneath the thermal pad as illustrated in the layout example. also see the qfn/son pcb attachment application report (slua271 ). figure 19. 12v to 24v dcdc power conversion figure 20. 5v to 12v dcdc power conversion with programmable feedback reference voltage 18 submit documentation feedback copyright ? 2007, texas instruments incorporated product folder link(s): tps61170 www.ti.com p d(max) 125 c t a r ja d1 vin sw fb gnd ctrl comp c3 680 pf tps 61170 l1 10 h m c1 4.7 f m c2 4.7 f m r1 185.1 k w r2 10 k w r3 10 k w l1: toko#a915_y-100m c1: murata grm188r61a475k c2: murata grm32er71h475k d1: onsemi mbr0540t1 vin 12 v vout 24 v/ 300 ma vin 5 v d1 vin sw fb gnd ctrl comp c3 680pf tps 61170 on/ off program fb l1 10 h m r1 87.6 k w r2 10 k w r3 10 k w c1 4.7 f m vout 12 v/ 300 ma c2 4.7 f m l1: toko#a915_y-100m c1: murata grm188r61a475k c2: murata grm21br61e475k d1: onsemi mbr0540t1
tps61170 slvs789 ? november 2007 figure 21. 12v sepic (buck-boost) converter copyright ? 2007, texas instruments incorporated submit documentation feedback 19 product folder link(s): tps61170 www.ti.com vin 9 v to 15 v d1 vin sw fb gnd ctrl comp c3 220 nf tps 61170 on /off dimming control l1 10 h m r1 87.6 k w c1 4.7 f m vout 12 v/ 300 ma c4 1 f m c2 4.7 f m l2 10 h m r2 10 k w l1: toko#a915_y-100m c1: murata grm188r61a475k c2: murata grm21br61e475k d1: onsemi mbr0540t1 *l1, l2 can be replaced by 1:1 transformer
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TPS61170DRVr active son drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TPS61170DRVt active son drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 19-nov-2007 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com telephony www.ti.com/telephony low power www.ti.com/lpw video & imaging www.ti.com/video wireless wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2007, texas instruments incorporated

▲Up To Search▲

Price & Availability of TPS61170DRV

	To Download TPS61170DRV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .