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low voltage 1.15 v to 5.5 v, 8-channel bidirectional logic level translator ADG3300 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features bidirectional le vel trans l ation operates from 1.15 v to 5.5 v low quiescent current <1 a no direction pin applic ati o ns low voltage asic leve l transl ation smart card rea d ers cell phones an d cell phone cradles portable commu nications dev i ces telecommunications equipm ent network switches and router s storage syste m s (san/ n as) computing/server applications gps portable pos systems low cost serial interfaces func tio n a l block di agram a1 y1 gnd v ccy v cca a8 y8 a7 y7 a6 y6 a5 y5 a4 y4 a3 y3 a2 y2 en 05061-001 fi g u r e 1 . general description the ad g 330 0 is a b i dir e c t io nal log i c l e ve l trans l a t o r tha t c o n - ta i n s eig h t b i d i r e c t io na l cha n nels. i t ca n b e us e d in m u l t i v olt a ge dig i t a l sys t em a p p l ica t io n s s u ch as da t a tra n sf er betw een a lo w v o l t a g e d s p/con t r o l l er a n d a hi g h er v o l t a g e de vice . the i n t e r n al a r chi t e c t u r e a l lo ws t h e de vic e to p e r f o r m b i dir e c t io na l lo g i c lev e l tra n s l a t i o n w i t h o u t a n a d di ti o n al si gn al t o se t th e d i r e cti o n o f th e tra n sla t i o n . the v o l t a g e a p plie d t o v cc a s e ts th e log i c le v e l s o n the a side o f t h e de vice , w h i l e v cc y s e ts t h e le v e l s o n t h e y si de . f o r p r o p er op e r a t i o n , v cc a m u s t al wa ys b e les s tha n v cc y . t h e v cc a -co m - p a tib l e log i c sig n als a p p l ie d t o th e a side o f t h e de vice a p p e a r as v cc y - c om p a t i bl e l e vel s on t h e y s i d e . si m i l a r l y , v cc y -co m p a t i b l e log i c le v e l s a p p l ie d t o t h e y side o f th e device a p p e a r as v cc a - co m p a t i b le log i c le v e l s o n t h e a side . the ena b l e p i n p r o v ides t h r e e-st a t e o p era t io n of t h e y side pin s . w h en t h e enab l e p i n (e n) is p u l l e d lo w , t h e a1 t o a8 p i ns a r e in t e r n al l y p u l l e d do wn b y 6 k? r e sis t o r s, while th e y t e r m inals a r e in t h e hig h im p e dance s t a t e . the en pin is refer r e d t o v cc a s u p p l y v o l t a g e and dr i v en hig h fo r n o r m al o p er a t io n. the ad g 330 0 is a v a i lab l e in a c o m p ac t 2 0 -l ead t s s o p p a cka g e , a nd i t is gua r an teed t o o p era t e o v er th e 1.15 v to 5.5 v s u p p l y v o l t a g e ra n g e and ext e n d e d ?4 0c t o +85c t e m p er a t ur e ra n g e . product highlights 1. bidir e c t io na l le vel t r a n sla t ion. 2. f u l l y gua r a n t e e d o v er th e 1.15 v t o 5.5 v s u p p ly ra n g e . 3. n o dir e c t ion p i n. 4. 20-lead t sso p p a c k a g e . 4 .com u datasheet
ADG3300 rev. 0 | page 2 of 20 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 te s t c i rc u it s ..................................................................................... 12 te r m i no l o g y .................................................................................... 14 theory of operation ...................................................................... 15 level translator architecture .................................................... 15 input driving requirements ..................................................... 15 output load requirements ...................................................... 15 enable operation ....................................................................... 15 power supplies ............................................................................ 15 data rate ..................................................................................... 16 applications ..................................................................................... 17 layout guidelines ....................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 4/05revision 0: initial version 4 .com u datasheet
ADG3300 rev. 0 | page 3 of 20 specifications 1 v ccy = 1.65 v to 5.5 v, v cca = 1.15 v to v ccy , gnd = 0 v. all specifications t min to t max , unless otherwise noted. table 1. parameter symbol conditions min typ 2 max unit logic inputs/outputs a side input high voltage 3 v iha v cca = 1.15 v v cca ? 0.3 v v iha v cca = 1.2 v to 5.5 v v cca ? 0.4 v input low voltage 3 v ila 0.4 v output high voltage v oha v y = v ccy , i oh = 20 a, figure 27 v cca ? 0.4 v output low voltage v ola v y = 0 v, i ol = 20 a, figure 27 0.4 v three-state pull-down resistance r a,hiz en = 0 4.2 6 8.4 k? y side input low voltage 3 v ihy v ccy ? 0.4 v input high voltage 3 v ily 0.4 v output high voltage v ohy v a = v cca , i oh = 20 a, figure 28 v ccy ? 0.4 v output low voltage v oly v a = 0 v, i ol = 20 a, figure 28 0.4 v capacitance 3 c y f = 1 mhz, en = 0, figure 31 6 pf leakage current i ly, hiz v y = 0 v/v ccy , en = 0, figure 29 1 a enable (en) input high voltage 3 v ihen v cca = 1.15 v v cca ? 0.3 v v ihen v cca = 1.2 v to 5.5 v v cca ? 0.4 v input low voltage 3 v ilen 0.4 v leakage current i len v en = 0 v/v cca , v a = 0 v, figure 30 1 a capacitance 3 c en 3 pf enable time 3 t en r s = r t = 50 ?, v a = 0 v/v cca (a y), figure 32 1 1.8 s switching characteristics 3 3.3 v 0.3 v v cca v ccy , v ccy = 5 v 0.5 v a y level translation r s = r t = 50 ?, c l = 50 pf, figure 33 propagation delay t p, a-y 6 10 ns rise time t r, a-y 2 3.5 ns fall time t f, a-y 2 3.5 ns maximum data rate d max, a-y 50 mbps channel-to-channel skew t skew, a-y 2 4 ns part-to-part skew t ppskew, a-y 3 ns y a level translation r s = r t = 50 ?, c l = 15 pf, figure 34 propagation delay t p, y-a 4 7 ns rise time t r, y-a 1 3 ns fall time t f, y-a 3 7 ns maximum data rate d max, y-a 50 mbps channel-to-channel skew t skew, y-a 2 3.5 ns part-to-part skew t ppskew, y-a 2 ns 1.8 v 0.15 v v cca v ccy , v ccy = 3.3 v 0.3 v a y translation r s = r t = 50 ?, c l = 50 pf, figure 33 propagation delay t p, a-y 8 11 ns rise time t r, a-y 2 5 ns fall time t f, a-y 2 5 ns maximum data rate d max, a-y 50 mbps channel-to-channel skew t skew, a-y 2 4 ns part-to-part skew t ppskew, a-y 4 ns 4 .com u datasheet
ADG3300 rev. 0 | page 4 of 20 parameter symbol conditions min typ 2 max unit y a translation r s = r t = 50 ?, c l = 15 pf, figure 34 propagation delay t p, y-a 5 8 ns rise time t r, y-a 2 3.5 ns fall time t f, y-a 2 3.5 ns maximum data rate d max, y-a 50 mbps channel-to-channel skew t skew, y-a 2 3 ns part-to-part skew t ppskew, y-a 3 ns 1.15 v to 1.3 v v cca v ccy , v ccy = 3.3 v 0.3 v a y translation r s = r t = 50 ?, c l = 50 pf, figure 33 propagation delay t p, a-y 9 18 ns rise time t r, a-y 3 5 ns fall time t f, a-y 2 5 ns maximum data rate d max, a-y 40 mbps channel-to-channel skew t skew, a-y 2 5 ns part-to-part skew t ppskew, a-y 10 ns y a translation r s = r t = 50 ?, c l = 15 pf, figure 34 propagation delay t p, y-a 5 9 ns rise time t r, y-a 2 4 ns fall time t f, y-a 2 4 ns maximum data rate d max, y-a 40 mbps channel-to-channel skew t skew, y-a 2 4 ns part-to-part skew t ppskew, y-a 4 ns 1.15 v to 1.3 v v cca v ccy , v ccy = 1.8 v 0.3 v a y translation r s = r t = 50 ?, c l = 50 pf, figure 33 propagation delay t p, a-y 12 25 ns rise time t r, a-y 7 12 ns fall time t f, a-y 3 5 ns maximum data rate d max, a-y 25 mbps channel-to-channel skew t skew, a-y 2 5 ns part-to-part skew t ppskew, a-y 15 ns y a translation r s = r t = 50 ?, c l = 15 pf, figure 34 propagation delay t p, y-a 14 35 ns rise time t r, y-a 5 16 ns fall time t f, y-a 2.5 6.5 ns maximum data rate d max, y-a 25 mbps channel-to-channel skew t skew, y-a 3 6.5 ns part-to-part skew t ppskew, y-a 23.5 ns 2.5 v 0.2 v v cca v ccy , v ccy = 3.3 v 0.3 v a y translation r s = r t = 50 ?, c l = 50 pf, figure 33 propagation delay t p, a-y 7 10 ns rise time t r, a-y 2.5 4 ns fall time t f, a-y 2 5 ns maximum data rate d max, a-y 60 mbps channel-to-channel skew t skew, a-y 1.5 2 ns part-to-part skew t ppskew, a-y 4 ns y a translation r s = r t = 50 ?, c l = 15 pf, figure 34 propagation delay t p, y-a 5 8 ns rise time t r, y-a 1 4 ns fall time t f, y-a 3 5 ns maximum data rate d max, y-a 60 mbps channel-to-channel skew t skew, y-a 2 3 ns part-to-part skew t ppskew, y-a 3 ns 4 .com u datasheet
ADG3300 rev. 0 | page 5 of 20 parameter symbol conditions min typ 2 max unit power requirements power supply voltages v cca v cca v ccy 1.15 5.5 v v ccy 1.65 5.5 v quiescent power supply current i cca v a = 0 v/v cca , v y = 0 v/v ccy , v cca = v ccy = 5.5 v, en = 1 0.17 5 a i ccy v a = 0 v/v cca , v y = 0 v/v ccy , v cca = v ccy = 5.5 v, en = 1 0.27 5 a three-state mode power supply current i hiza v cca = v ccy = 5.5 v, en = 0 0.1 5 a i hizy v cca = v ccy = 5.5 v, en = 0 0.1 5 a 1 temperature range is a follows: b version: ?40c to +85c. 2 all typical values are at t a = 25c, unless otherwise noted. 3 guaranteed by design; not subject to production test. 4 .com u datasheet
ADG3300 rev. 0 | page 6 of 2 0 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e not e d. ta bl e 2. p a r a m e t e r r a t i n g v cca to gnd ?0.3 v to +7 v v ccy to gnd v cca to +7 v digtal inputs (a) ?0.3 v to (v cca + 0.3 v) digtal inputs (y) ?0.3 v to (v ccy + 0.3 v) en to gnd ?0.3 v to +7 v operating tem p erature range indus t rial (b vers io n) ?40c to +85c storage temperature range ?65c to +150c junction tempe r ature 150c ja thermal impedance (4-layer board) 20-lead tssop 78c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 260c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t d e vi ce r e li a b ili t y . onl y o n e a b s o l u t e m a xim u m ra ti n g ma y b e ap p l i e d a t a n y o n e t i m e . esd c a ution esd (electrostatic discharge) se nsitive device. electrosta tic char ges as high as 4 000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprietary esd protection circ uitry, permane n t dama ge may occur on devices subj ected to high energy electrostatic discharge s . ther efore, pr oper esd precautio n s ar e rec o m m ended to av oid perform a n c e degradation or l o ss of functiona l ity. 4 .com u datasheet
ADG3300 rev. 0 | page 7 of 2 0 pin conf igura t ion and fu nction descriptions y8 gnd y7 en a1 v cca a2 a5 a6 y6 y1 a7 a8 v ccy y2 y3 y4 y5 a3 a4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ADG3300 top view (not to scale) 05061-002 f i gure 2. pin config ur ation ta bl e 3. pi n f u nct i o n d e s c ri pt i o ns pin. no. mnemonic description 1 a1 input/ output a 1 . referenced to v cca . 2 v cca power supply voltage input for the a1 to a8 i/o pins (1.15 v v cca < v ccy ). 3 a2 input/ output a 2 . referenced to v cca . 4 a3 input/ output a 3 . referenced to v cca . 5 a4 input/ output a 4 . referenced to v cca . 6 a5 input/ output a 5 . referenced to v cca . 7 a6 input/ output a 6 . referenced to v cca . 8 a7 input/ output a 7 . referenced to v cca . 9 a8 input/ output a 8 . referenced to v cca . 10 en active high enable input. 1 1 g n d g r o u n d . 12 y8 input/ output y 8 . referenced to v ccy . 13 y7 input/ output y 7 . referenced to v ccy . 14 y6 input/ output y 6 . referenced to v ccy . 15 y5 input/ output y 5 . referenced to v ccy . 16 y4 input/ output y 4 . referenced to v ccy . 17 y3 input/ output y 3 . referenced to v ccy . 18 y2 input/ output y 2 . referenced to v ccy . 1 9 v ccy power supply voltage input for the y1 to y8 i/ o pins (1.65 v v ccy 5.5 v). 20 y1 input/ output y 1 . referenced to v ccy . 4 .com u datasheet
ADG3300 rev. 0 | page 8 of 2 0 typical perf orm ance cha r acte ristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) t a = 25c 1 channel c l = 50pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v i cca (ma) 05061-003 fi g u r e 3 . i cc a v s . d a ta ra te (a y l e vel t r ans l at i o n) 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) t a = 25c 1 channel c l = 50pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v i ccy (ma) 05061-004 fi g u r e 4 . i cc y vs . d a ta ra t e ( a y l e vel t r ans l at io n) 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) i cca (ma) t a = 25c 1 channel c l = 15pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v 05061-005 fi g u r e 5 . i cc a vs . d a ta r a t e ( y a l e vel t r ans l at i o n) 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) i ccy (ma) t a = 25c 1 channel c l = 15pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v 05061-006 fi g u r e 6 . i cc y v s . d a ta rate ( y a l e ve l t r ans l at io n) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 13 23 33 43 53 63 73 capacitive load (pf) i ccy (ma) 05061-007 20mbps 10mbps 5mbps 1mbps t a =2 5 c 1 channel v cca = 1.2v v ccy = 1.8v fi g u r e 7 . i cc y v s . ca pac i t i ve l o ad at p i n y f o r a y ( 1 .2 v 1. 8 v ) l e vel t r ans l at i o n 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 13 23 33 43 53 capacitive load (pf) i cca (ma) 05061-008 20mbps 10mbps 5mbps 1mbps t a = 25c 1 channel v cca = 1.2v v ccy =1.8v fi g u r e 8 . i cc a v s . ca pac i t i ve l o ad at p i n a f o r y a (1 .8 v 1. 2 v ) l e vel t r ans l at i o n 4 .com u datasheet
ADG3300 rev. 0 | page 9 of 2 0 0 1 2 3 4 5 6 7 8 9 i ccy (ma) 13 23 33 43 53 63 73 capacitive load (pf) 05061-009 t a = 25c 1 channel v cca = 1.8v v ccy = 3.3v 30mbps 20mbps 10mbps 5mbps 50mbps fi g u r e 9 . i cc y v s . ca pac i t i ve l o ad at p i n y f o r a y ( 1 .8 v 3. 3 v ) l e vel t r ans l at i o n 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 i cca (ma) 13 23 33 43 53 capacitive load (pf) 05061-010 50mbps t a = 25c 1 channel v cca = 1.8v v ccy = 3.3v 5mbps 10mbps 20mbps 30mbps f i g u re 10. i cc a v s . capa cit i ve l oad at pin a f o r y a ( 3 .3 v 1. 8 v ) l e vel t r ans l at i o n 0 2 4 6 8 10 12 i ccy (ma) 13 23 33 43 53 63 73 capacitive load (pf) 05061-011 t a = 25c 1 channel v cca = 3.3v v ccy = 5v 50mbps 30mbps 20mbps 10mbps 5mbps f i g u re 11. i cc y v s . capa cit i ve l oad at pin y f o r a y ( 3 .3 v 5 v ) l e vel t r ans l at i o n 0 2 4 6 i cca (ma) 13 23 33 43 53 capacitive load (pf) 05061-012 t a = 25c 1 channel v cca = 3.3v v ccy = 5v 50mbps 30mbps 20mbps 10mbps 5mbps 1 3 5 7 f i g u re 12. i cc a v s . capa cit i ve l oad at pin a f o r y a ( 5 v 3. 3 v ) l e vel t r ans l at i o n 0 1 2 3 4 5 6 7 8 9 10 13 23 33 43 53 63 73 capacitive load (pf) r i se tim e ( n s) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 05061-013 f i gure 13. r i se t i m e v s . capa citive l o ad at p i n y (a y l e v e l t r ans l at io n) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 13 23 33 43 53 63 73 capacitive load (pf) fall time (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v v cca = 1.2v, v ccy = 1.8v 05061-014 f i gure 14. f a l l ti me v s . capac i tive l o a d at pin y (a y l e vel t r ans l at i o n) 4 .com u datasheet
ADG3300 rev. 0 | page 10 of 20 0 1 2 3 4 5 6 7 8 9 10 13 18 23 28 33 38 43 48 53 r i se tim e ( n s) capacitive load (pf) t a = 25 c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 05061-015 f i g u re 15. r i s e ti m e v s . capa cit i ve l o ad at p i n a ( y a l e vel t r ans l at io n) 13 18 23 28 33 38 43 48 53 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fall time (ns) capacitive load (pf) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 05061-016 f i gure 16. f a l l ti me v s . capac i tive l o a d at pin a ( y a l e ve l t r ans l at i o n) 0 2 4 6 8 10 12 14 13 23 33 43 53 63 73 capacitive load (pf) p r op agation de lay (ns ) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 05061-017 f i g u re 17. p r opag a t ion d e l a y (t plh ) vs . capa cit i ve l oad at p i n y (a y l e v e l t r ansl ation) 05061-018 0 2 4 6 8 10 12 13 23 33 43 53 63 73 p r op agation de lay (ns ) capacitive load (pf) data rate = 50kbps t a = 25 c 1 channel v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v f i g u re 18. p r opag a t ion d e l a y (t phl ) vs . capa cit i ve l oad at p i n y (a y l e v e l t r ansl ation) 0 1 2 3 4 5 6 7 8 9 13 18 23 28 33 38 43 48 53 capacitive load (pf) p r op agation de lay (ns ) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 05061-019 f i g u re 19. p r opag a t ion d e l a y (t plh ) vs . capa cit i ve l oad at p i n a ( y a l e v e l t r ansl a t io n) 0 1 2 3 4 5 6 7 8 9 13 18 23 28 33 38 43 48 53 capacitive load (pf) p r op agation de lay (ns ) 05061-020 t a = 25 c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v f i g u re 20. p r opag a t ion d e l a y ( t phl ) vs . capa cit i ve l oad at p i n a ( y a l e v e l t r ansl a t io n) 4 .com u datasheet
ADG3300 rev. 0 | page 11 of 20 5ns/div 05061-021 200mv/div t a = 25c data rate = 25mbps c l = 50pf 1 channel f i g u re 21. eye d i ag r a m at y o u t p ut (1. 2 v t o 1.8 v l e vel t r ans l at io n, 25 m bps ) t a = 25c data rate = 25mbps c l = 50pf 1 channel 5ns/div 05061-022 400mv/div f i g u re 22. eye d i ag r a m at a o u t p ut (1. 8 v t o 1.2 v l e vel t r ans l at io n, 25 m bps ) t a = 25c data rate = 50mbps 3ns/div 05061-023 500mv/div c l = 50pf 1 channel f i g u re 23. eye d i ag r a m at y o u t p ut (1. 8 v t o 3.3 v l e vel t r ans l at io n, 50 m bps ) t a = 25 c data rate = 50mbps c l = 15pf 1 channel 3ns/div 05061-024 400mv/div f i g u re 24. eye d i ag r a m at a o u t p ut (3. 3 v t o 1.8 v l e vel t r ans l at io n, 50 m bps ) t a = 25 c data rate = 50mbps cl = 50pf 1 channel 3ns/div 05061-025 1v/div f i g u re 25. eye d i ag r a m at y o u t p ut (3. 3 v t o 5 v l e vel t r a n s l at i o n, 5 0 m bps ) t a = 25c data rate = 50mbps c l = 15pf 1 channel 3ns/div 05061-026 800mv/div f i g u re 26. eye d i ag r a m at a o u t p ut (5 v to 3.3 v l e vel t r a n s l at i o n, 5 0 m bps ) 4 .com u datasheet
ADG3300 rev. 0 | page 12 of 20 test circuits ADG3300 a y gnd v cca v ccy en k1 k2 i oh i ol 05061- 027 0.1 f 0.1 f f i g u re 27. v oh /v ol v o lt ag es at pin a ADG3300 y a gnd v ccy v cca en k1 k2 i oh i ol 05061- 028 0.1 f 0.1 f f i g u re 28. v oh /v ol v o lt ag es at pin y ADG3300 a y gnd v cca v ccy k 05061-030 0.1 f 0.1 f en a f i g u re 29. th r e e - st ate l e ak ag e cu rren t at p i n y ADG3300 a y gnd v cca v ccy k 05061-031 0.1 f 0.1 f en a f i g u re 30. e n p i n l e ak ag e cur r ent 05061-033 ADG3300 a y gnd v cca v ccy en capacitance meter f i gure 31.capa cit a nc e at p i n y 4 .com u datasheet
ADG3300 rev. 0 | page 13 of 20 90% v en v y t en1 v a v cca 0v v cca 0v v ccy 0v 10% v en v y t en2 v a v cca 0v 0v v ccy 0v notes 1. t en is whichever is larger between t en1 and t en2 . signal source v en r t 50 ? v a ADG3300 en gnd r s 50 ? 0.1 f v cca a 1m ? v y 50pf 1m ? v ccy y k2 05061-034 z 0 = 50 ? k1 10 f + 0.1 f 10 f + v cca f i g u re 32. e n ab le ti me 50% 50% 10% 90% v a v y t f,a-y t r,a-y t p,a-y t p,a-y ADG3300 gnd signal source v a r t 50 ? r s 50 ? en v cca v ccy v y 50pf 05061- 035 z 0 = 50 ? ya 0.1 f 10 f + 0.1 f 10 f + f i gure 3 3 . s w i t chin g cha r a c teri sti c s ( a y l e vel t r ans l at i o n ) 50% 50% 10% 90% v y v a t f,y-a t r,y-a t p,y-a t p,y-a ADG3300 gnd signal source v y r t 50 ? r s 50 ? en v cca v ccy v a 15pf 05061-036 z 0 = 50 ? ya 0.1 f 10 f + 0.1 f 10 f + f i gure 3 4 . s w i t chin g cha r a c teri sti c s ( y a l e vel t r ans l at io n ) 4 .com u datasheet
ADG3300 rev. 0 | page 14 of 20 terminology table 4. symbol description v iha logic input high voltage at pins a1 to a8. v ila logic input low voltage at pins a1 to a8. v oha logic output high voltage at pins a1 to a8. v ola logic output low voltage at pins a1 to a8. r a,hiz pull-down resistance measured at pins a1 to a8 when en = 0. v ihy logic input high voltage at pins y1 to y8. v ily logic input low voltage at pins y1 to y8. v ohy logic output high voltage at pins y1 to y8. v oly logic output low voltage at pins y1 to y8. c y capacitance measured at pins y1 to y8 (en = 0). i ly, hiz leakage current at pins y1 to y8 when en = 0 (high impedance state at pins y1 to y8). v ihen logic input high voltage at the en pin. v ilen logic input low voltage at the en pin. c en capacitance measured at en pin. i len enable (en) pin leakage curent. t en three-state enable time for pins y1 to y8. t p, a-y propagation delay when translating logic levels in the a y direction. t r, a-y rise time when translating logic levels in the a y direction. t f, a-y fall time when translating logic levels in the a y direction. d max, a-y guaranteed data rate when translating logic levels in the a y direction under the driving and loading conditions specified in table 1. t skew, a-y difference between propagation delays on any two channels when translating logic levels in the a y direction. t ppskew, a-y difference in propagation delay between any one channel and the same channel on a different part (under the same driving/loading conditions) when translating logic levels in the a y direction. t p, y-a propagation delay when translating logic levels in the y a direction. t r, y-a rise time when translating logic levels in the y a direction. t f, y-a fall time when translating logic levels in the y a direction. d max, y-a guaranteed data rate when translating logic levels in the y a direction under the driving and loading conditions specified in table 1. t skew, y-a difference between propagation delays on any two channels when translating logic levels in the y a direction. t ppskew, y-a difference in propagation delay between any one channel and the same channel on a different part (under the same driving/loading conditions ) when translating in the y a direction. v cca v cca supply voltage. v ccy v ccy supply voltage. i cca v cca supply current. i ccy v ccy supply current. i hiza v cca supply current during three-state mode (en = 0). i hizy v ccy supply current during three-state mode (en = 0). 4 .com u datasheet
ADG3300 rev. 0 | page 15 of 20 theor y of opera tion the a d g 330 0 l e vel t r an sl a t o r al lo ws t h e l e ve l shif t i n g ne ce s s a r y fo r da t a t r a n sfer in a syst em w h er e m u l t i p le s u ppl y v o l t a g es a r e us e d . th e de vic e r e q u ir es tw o su p p lies, v cc a a nd v cc y (v cc a v cc y ). th es e s u p p lies s e t t h e log i c le v e l s o n e a ch side o f t h e de vice . w h e n dr i v in g t h e a p i ns, t h e de vice t r an s l a t es t h e v cc a - co m p a t i b le log i c le v e l s t o v cc y -co m p a t i b l e log i c le v e l s a v a i lab l e a t t h e y p i n s . si mi l a rl y , si nc e t h e de v i ce is c a p a ble o f b i dire c t ional t r a n sl a t ion, w h e n dr i v in g t h e y p i n s , t h e v cc y -c o m p a t i b l e log i c l e vel s are t r ans l a t e d to v cc a -co m p a t i b l e log i c le v e l s a v a i l a b l e a t t h e a p i n s . w h e n en = 0, t h e a 1 t o a8 a r e i n t e r n al l y p u l l e d do wn w i t h 6 k? r e sis t o r s w h i l e y1 t o y8 p i ns a r e t h r e e-s t a t e d . w h en e n is dr iv en hig h , the ad g3300 g o es in t o n o r m al o p er a t ion m o de a nd p e r f o r m s le vel t r an sl a t ion. level tr ansl a t or ar chitec ture the ad g3300 co n s is ts o f eig h t b i dir e c t ional cha n n e ls. e a c h cha n n e l ca n t r an s l a t e log i c le v e ls in ei t h er t h e a y o r t h e y a dir e c t io n. i t us e s a o n e-sh ot acc e ler a to r a r chi t e c t u r e , w h ich en s u r e s exce l l en t swi t chin g c h a r ac t e r i s t ics. f i gur e 35 s h o w s a sim p lif i e d b l o c k di a g r a m o f a b i dir e c t io na l channel. one-shot generator 6k ? 6k ? y v cca v ccy t2 t1 t3 t4 a 05061-037 p n u1 u2 u4 u3 f i g u re 35. si mpl i f i e d bl ock d i ag r a m of an a d g 3 30 0 ch an nel the log i c le v e l t r a n s l a t io n in t h e a y dir e c t ion is p e r f o r m e d u s i n g a l e vel t r ansl a t or ( u 1 ) a n d an i n ve r t e r ( u 2 ) , and t h e tra n s l a t i o n in t h e y a d i r e c t i o n is p e rf o r m e d usin g t h e in v e r t e r s u3 an d u4. th e o n e - sh o t g e n e r a t o r dete c t s a r i sin g o r fal l in g ed g e p r e s en t o n e i th e r th e a si de o r th e y si de o f th e c h a n n e l . i t s e n d s a sh o r t p u ls e tha t t u r n s on the pmos tran sis t o r s (t1 C t2 ) fo r a r i sin g e d g e , o r th e nmos t r a n sis t o r s (t3C t4) fo r a fal l in g edg e . th is ch a r ge s / di sch a rg e s t h e c a p a c i t i ve l o a d f a s t e r , w h i c h re su l t s in f a st r i s e and f a l l t i me s . the in p u ts o f t h e un us ed c h a n ne ls (a o r y) s h ou ld be tied t o t h eir co r r es p o ndin g v cc ra il (v cc a or v cc y ) o r t o gnd . i n p u t d r iv in g req u i r emen t s t o en s u r e co r r e c t o p era t ion o f th e ad g3300, t h e cir c ui t tha t dr i ves t h e i n p u t o f an a d g33 00 channe ls sho u l d ha ve an out p u t im p e dan c e o f les s tha n o r eq ual t o 150 ? a n d a minim u m c u r r en t dr i v in g ca p a b i li ty o f 36 ma. outpu t l o ad require m ent s the ad g3300 l e v e l tran s l a t o r is desig n e d t o dr i v e cm os- co m p a t i b le lo ad s. i f c u rr en t dr i v in g c a p a b i l i ty is r e q u ir e d , i t is r e co mmen d e d to us e b u f f ers betw een t h e ad g 3300 o u t p u t s a nd t h e lo ad . enable ope r a t ion the ad g3300 p r o v ides thr e e-sta t e o p era t io n a t th e y i/o p i n s b y usin g t h e enab le (en) p i n as s h own i n t a b l e 5. ta bl e 5. trut h ta bl e en y i/o pins a i/o pins 0 h i - z 1 6 k? pull-d o wn to gnd 1 n o r m a l ope rati on 2 normal ope rati on 2 1 h i gh imped anc e stat e . 2 i n nor mal oper a t i o n, the ad g3300 p e r f or ms lev e l tr ansla t ion. w h en e n = 0, th e ad g3300 en t e rs in t o thr ee-sta t e mo de . i n t h i s m o d e th e cu rr e n t c o n s u m p t i o n fr o m b o th th e v cc a a nd v cc y s u p p lies is r e d u ced , al lo win g th e us er t o s a v e p o w e r , which is cr i t ical , es p e c i al l y fo r b a t t er y-o p era t e d sys t ems. th e e n i n p u t p i n c a n b e dr i v e n w i t h ei t h er v cc a - o r v cc y -co m p a t i b l e log i c l e vel s . po wer supplies f o r p r o p er o p era t io n o f t h e ad g3300, th e v o l t a g e a p p l ied t o th e v cc a m u s t alwa ys b e l e ss t h an o r e q ua l t o t h e v o l t a g e a p p l ie d to v cc y . t o m eet th i s co n d i ti o n , th e r e co mm en ded po w e r - u p seq u en c e i s v ccy f i rst a nd t h en v cc a . the ad g 3300 o p era t es p r op e r ly on ly af te r b o t h su p p ly vol t age s re ach t h e i r nom i na l val u es. i t is n o t r e co mme n d e d to us e t h e p a r t i n a sys t em w h er e v cc a mig h t b e g r e a ter t h a n v cc y du r i n g p o w e r - up du e t o a s i g - nif i can t i n cr e a s e in t h e c u r r en t t a k e n f r o m t h e v cc a su p p ly . f o r opt i m u m p e r f or m a n c e, t h e v cc a a nd v cc y pi ns s h ou l d b e de co u p le d to g n d as clo s e a s p o ssi b le to t h e de vice. 4 .com u datasheet
ADG3300 rev. 0 | page 16 of 20 data rate the maximum data rate at which the device is guaranteed to operate is a function of the v cca and v ccy supply voltage combination and the load capacitance. it is given by the maximum frequency of a square wave that can be applied to the device, which meets the v oh and v ol levels at the output and does not exceed the maximum junction temperature (see table 2) . table 6 shows t he guar ante e d d at a r ate s at w hich t he ADG3300 can operate in both directions (a y and y a level translation) for various v cca and v ccy supply combinations. table 6. guaranteed data rate (mbps) 1 v ccy v cca 1.8 v (1.65 v to 1.95 v) 2.5 v (2.3 v to 2.7 v) 3.3 v (3.0 v to 3.6 v) 5 v (4.5 v to 5.5 v) 1.2 v (1.15 v to 1.3 v) 25 30 40 40 1.8 v (1.65 v to 1.95 v) - 45 50 50 2.5 v (2.3 v to 2.7 v) - - 60 50 3.3 v (3.0 v to 3.6 v) - - - 50 5 v (4.5 v to 5.5 v) - - - - 1 the load capacitance used is 50 pf when translating in the a y direction and 15 pf when translating in the y a direction. 4 .com u datasheet
ADG3300 rev. 0 | page 17 of 20 appli c a t ions the ad g3300 is desig n e d f o r dig i tal cir c ui ts tha t o p er a t e a t dif f er en t s u p p l y v o l t a g es; t h er efo r e , log i c le v e l t r a n s l a t io n is r e q u ir e d . th e lo w e r v o l t a g e log i c sig n als a r e co nn e c t e d t o t h e a p i n s , and t h e hig h er v o l t a g e l o g i c sig n als a r e co nne c t e d t o t h e y p i n s . the ad g3300 ca n p r o v ide leve l tra n sla t io n in bo t h dire c t ion s f r om a y and y a o n all e i g h t c h a n n e ls, e l imi n a t in g th e n e e d f o r a le v e l tra n sla t o r i c f o r eac h dir e c t io n. th e in t e r n al a r c h i t e c t u r e al lo ws th e ad g330 0 t o p e r f o r m b i dir e c t io nal le ve l tra n s l a t i o n wi t h o u t a n ad di ti o n al si gn al t o set t h e d i r e cti o n o f th e tra n s l a t ion. i t als o al lo ws si m u l t an eo us da t a f l o w in bo t h dir e c t io n s on the s a m e p a r t , f o r exa m p l e , f o ur c h a n n e ls tra n sla t e in t h e a y dir e c t io n w h i l e t h e ot h e r fo ur t r a n s l a t e i n t h e y a dir e c t io n. this s i m p lif i es t h e de sig n b y e l imi n a t in g t h e t i m i n g r e q u ir em e n ts for t h e dir e c t ion s i g n al an d r e d u c e s t h e n u m b er o f i c s us e d f o r le ve l tra n sla t ion. f i gur e 36 s h o w s a n a p p l ic a t ion wher e a 1.8 v micr o p r o ces s o r ca n r e ad o r wr i t e da t a t o o r f r o m a 3.3 v p e r i ph eral de vice usin g a n 8 - bi t bu s . v ccy y1 y2 y3 y4 en gnd a4 a3 a2 a1 v cca microprocessor/ microcontroller/ dsp 1.8v 3.3v peripheral device 100nf 100nf i/o l 1 i/o l 4 i/o l 3 i/o l 2 i/o h 1 i/o h 4 i/o h 3 i/o h 2 gnd 05061- 038 gnd y5 y6 y7 y8 a8 a7 a6 a5 ad g3300 i/o l 5 i/o l 8 i/o l 7 i/o l 6 i/o h 5 i/o h 8 i/o h 7 i/o h 6 f i g u re 36. 1. 8 v t o 3 . 3 v 8-bit l e ve l t r a n s l at i o n c i rcuit w h e n t h e ap p l i c at i o n r e q u i r e s l e v e l t r a n s l at i o n b e t w e e n a micr o p r o ces s o r a nd m u l t i p le p e r i p h eral de vices , th e ad g3300 y i/o p i n s (y1 to y8) ca n be three-s t a t ed b y s e t t in g en = 0. this fe a t ur e al lo ws t h e ad g330 0 t o s h a r e t h e da t a b u s e s wi t h o t h e r d e v i c e s w i t h o u t c a us ing c o n t e n t i on issue s . fi g u r e 3 7 shows a n a p p l i c a t i o n w h er e a 3.3 v mic r o p r o ces s o r is co nn ec t e d t o 1.8 v p e r i p h eral de vices usin g t h e thr ee-s t a t e f e a t ur e . 05061-039 y1 v cc y y2 y3 y4 y5 y6 y7 y8 en gn d a8 a7 a6 a5 a4 a3 a2 a1 v cc a adg3 300 mi c r o p r o c esso r / m i c r o c on t r ol l e r / ds p i/ o h 1 cs 3.3v 1.8v p e r i p he ra l d evi c e 1 10 0 n f 1 0 0 n f i/ o h 2 i/ o h 8 i/ o h 7 i/ o h 6 i/ o h 5 i/ o h 4 i/ o h 3 i/ o l 1 i/ o l 2 i/ o l 8 i/ o l 7 i/ o l 6 i/ o l 5 i/ o l 4 i/ o l 3 gn d 1.8v 10 0n f 1 0 0 n f i/ o l 1 i/ o l 2 i/ o l 8 i/ o l 7 i/ o l 6 i/ o l 5 i/ o l 4 i/ o l 3 gn d gn d p e r i p he ra l d evi c e 2 v ccy y1 y2 y3 y4 y5 y6 y7 y8 en gn d a8 a7 a6 a5 a4 a3 a2 a1 adg3 3 00 v cca f i g u re 37. 1. 8 v t o 3 . 3 v l e vel t r ans l at i o n c i rcuit using the th r e e - st ate f e atur e l a y o ut guidelines a s wi t h an y hig h sp e e d dig i t a l ic, t h e p r in te d ci r c ui t b o a r d la y o u t is im p o r t a n t in t h e o v e r al l ci r c ui t pe rf o r ma n c e . c a re shou l d b e t a k e n to e n su re p r op e r p o we r su p p ly b y p a ss and r e t u r n p a th s fo r th e hig h sp e e d sig n als. e a c h v cc pi n ( v cc a a nd v cc y ) s h o u ld b e b y p a s s e d usin g lo w ef fe c t i v e s e ries r e sis t a n c e (es r ) a nd ef f e c t i v e ser i es in d u c t a n ce (es i ) c a p a ci t o r s p l ac ed as clos e as p o s s i b le t o t h e v cc a an d v cc y pi ns . t h e p a r a s i t i c i n du c - t a nce o f t h e hig h s p e e d sig n al t r ack mig h t c a us e sig n if ican t o v ers h o o t. this ef fe c t ca n b e r e d u ce d b y k e e p i n g t h e le n g t h o f t h e t r acks as sh o r t as p o ssi b l e . a s o lid cop p e r pla n e fo r t h e r e t u r n p a t h (g nd) is a l s o r e co mmende d . 4 .com u datasheet
ADG3300 rev. 0 | page 18 of 20 outline dimensions 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10 f i gure 38 . 2 0 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 20) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ADG3300bruz 1 ?40c to +85c tssop ru-20 ADG3300bruz- reel 1 ?40c to +85c tssop ru-20 ADG3300bruz- reel7 1 ?40c to +85c tssop ru-20 1 z = pb-free part. 4 .com u datasheet
ADG3300 rev. 0 | page 19 of 20 notes 4 .com u datasheet
ADG3300 rev. 0 | page 20 of 20 notes ? 2005 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d05061C0C 4/05(0) 4 .com u datasheet

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