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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. o1911 sy/81011 sy 20110210-s00002 no.a1928-1/18 LC01707PLF overview LC01707PLF is a vehicle-mounted fm multiple tuner ic with fm-fe, if, if-filter, pll, fm-demo and lpf incorporated. an fm multiple tuner can be developed with this one chip. it makes up a small-sized fm multiple tuners which can be mounted on pnd. functions ? it is the fm tuner ic exclusively for the fm multiple. ? lna is incorporated ? image reduction complex bpf is incorporated ? wide / narrow band rf agc is incorporated ? narrow band if agc is incorporated ? image rejection is adopted ? dll detection method is adopted for the fm detection circuit, and it is not necessary to adjust. ? lpf for the carrier removal is incorporated. ? ic requires fewer external components. ? it is a bus control tuner ic which can be controlled by controlled by i 2 c bus. specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v dd max 4.3 v maximum input voltage v dd h 4.3 v maximum output voltage v dd l 4.3 v power dissipation pd max ta = 85 c *1 700 mw operating ambient topr -40 to 85 c storage temperature tstg -55 to 150 c maximum junction temperature tj max 150 c *1: board size: 80mm 70mm 1.6mm glass epox y double-sided board cmos lsi fm multiple tuner ic orderin g numbe r : ena1928a
LC01707PLF no.a1928-2/18 recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage range v dd 3.0 to 3.6 v recommended supply temperature v dd 3.3 v electrical characteristics at ta = 25 c, v dd = 3.3v, fc = 83mhz, vin=60db vemf, fm=1khz, audio filte r: hpf=100hz, lpf=15khz resister setting: if agc (02h) =6(110), rf agc (00h) =0(0000) dll demodulator loop gain setting (09h) =1 (01), mono multi center setting (09h) =7(0111) parameter symbol conditions ratings unit min typ max practical sensitivity 1 (s/n30db) sn30 22.5khz dev, fm=1khz, s/n=30db input level 12 20 db emf practical sensitivity 2 (s/n10db) sn10 7.5k hz dev, fm=76khz, s/n=10db input level *1 27 db emf s/n1 sn1 22.5khz dev, fm=1khz 34 44 db s/n2 sn2 7.5khz dev, fm=76khz *1 21 db total harmonic distortion rate 1 thd_1 22.5khz dev, fm=1khz 0.5 % total harmonic distortion rate 2 thd_2 75.0khz dev, fm=1khz 0.5 % am suppression ratio amr am 30% mod 34 44 db image rejection ratio imr 22.5k\hz dev, fm=1khz 32 db audio output level 1 ad01 7.5khz dev, fm=1khz *1 26 39 70 mvrms audio output level 2 ad02 7.5khz dev, fm=76khz *1 15 23 41 mvrms consumption current idd no signal input 106 170 ma *1: audio filter: hpf=100hz, lpf=off package dimensions unit : mm (typ) 3408 sanyo : vqfn44k(6.0x6.0) 6.0 6.0 0.85 max 0.0 nom (0.8) top view side view side view bottom view (4.0) (4.0) 0.5 44 1 1 2 2 (1.0) 0.4 0.16
LC01707PLF no.a1928-3/18 example of applied circuit (constant is tentative) * culprits oscillation circuit is used in this ic as a crystal oscillation circuit. caution is required for layout of the board because oscillation between pin25 and power source and gnd line. * the margin of crystal oscillation changes due to the combina tion of the ic, a crystal oscillator and a board layout. this independent ic does not quarantine the oscillation operation. * this ic uses the signal of fm band frequency (vco divided into 1/4) which leaks into ant pin. if the vco leakage affects the performance of the system, make sure to connect an isolator on ant pin path. component parameter value type supplier l1/l2 local osc coil 2.7nh c2012h-2n7d-rd sagami l3 differential input coil 120nh c2012h-r12g-rc sagami x1 crystal 7.2mhz smd-49 kds at-49 kds exs00a-a01145 ndk exs00a-a01146 ndk nagc lim demo freq.count + - 37 36 39 38 lpf 41 40 43 42 44 35 34 n_agc w_agc mix i mix q injection div if agc if agc lna 1 2 3 4 5 6 7 8 9 10 11 19 20 17 18 15 16 13 14 12 21 22 33 32 31 30 29 28 27 26 25 24 23 c bank mix i mix q div bpf i/f lock det pd cp ref count prog count x_tal freq.count 1.8mhz f0:600khz f0:1.2mhz 0.22 f wagc 10nf v ss nc nc v dd + 0.022 f 0.68 f 22 f v dd v ss 27pf 47pf lna_p lna_n 120nh 100pf nc nc v ss cp v dd v dd 0.022 f 0.022 f v ss 2.7nh 2.7nh nc nc nc nc v ss devar 10pf 100pf xtal sd nc nc nc int scl sda v dd 7.2mhz 18pf com 0.022 f gnd nc nc nc nc demco 56pf lpfi demco lpfo 220pf 0.22 f decoder v dd smeter 0.022 f 0.68 f complex bpf complex bpf
LC01707PLF no.a1928-4/18 pin description pin no. pin name i/o function 1 nagc o narrow band agc detection capacitance connecting pin 2 wagc o wide band agc detection capacitance connecting pin 3 v ss p gnd pin for if 4 nc - 5 nc - 6 v dd p supply pin for lna 7 lna_a i lna +input pin 8 v ss p gnd pin for lna 9 lna_n i lna ?input pin 10 nc - 11 nc - 12 v ss p gnd pin for 1 st mixer 13 cp o pll charge pump capacitance connecting pin 14 v dd p supply pin 1 st mixer 15 v dd p supply pin for local oscillation 16 lo_1 o inductor connectin g pin for local oscillation 17 v ss p gnd pin for local oscillation 18 lo_2 o inductor connectin g pin for local oscillation 19 nc - 20 nc - 21 nc - 22 nc - 23 dever i device address setting pin 24 v ss p gnd pin for pll and logic 25 xtal i crystal resonator connecting pin (clock input pin) 26 sd o station detector pin 27 nc - 28 nc - 29 nc - 30 int o test pin 31 scl i serial data clock input 32 sda i serial data input-output 33 v dd p supply pin for pll and logic 34 smeter o s-meter output 35 v dd p supply pin for if 36 lpfo o demodulation output (after band limitation) 37 demoo o demodulation output 38 lpfi i demodulation signal input pin 39 democ o capacitance connecting pin for demodulation detection 40 nc - 41 nc - 42 nc - 43 nc - 44 gnd p gnd pin
LC01707PLF no.a1928-5/18 pin function pin no. pin name function equivalent circuit 1 nagc narrow band agc detection capacitor connection pin. 1 v dd v dd 2 wagc wide band agc detection capacitor connection pin. 2 v dd v dd 3 v ss gnd pin for if. 4 nc no connection. 5 nc no connection. 6 v dd supply pin for lna. 7 8 9 lna_p v ss lna_n pin 7 is + input pin for lna. pin 8 is gnd pin for lna. pin 9 is - input pin for lna. 9 v dd v dd v dd 7 10 nc no connection. 11 nc no connection. 12 v ss gnd pin 1st mixer for the 1 st mixer. 13 cp pll charge pump capacitor connection pin. 13 v dd v dd v dd 14 v dd supply pin for the 1 st mixer. 15 v dd supply pin for local oscillator. continued on next page.
LC01707PLF no.a1928-6/18 continued from preceding page. pin no. pin name function equivalent circuit 16 17 18 lo_1 v ss lo_2 pin 16 is inductor connection pin for local oscillator. pin 17 is gnd pin for local oscillator. pin 18 is inductor connection pin for local oscillator. 16 v dd 17 cap bank cap bank v dd 18 to pin13 19 nc no connection. 20 nc no connection. 21 nc no connection. 22 nc no connection. 23 devar device address setting pin. 23 v dd v dd 24 v ss pll_logic gnd pin. 25 xtal crystal oscillator connection pin (clock input pin). 25 v dd v dd 20pf 10pf 5pf 26 30 sd int station detector pin. test monitor pin. 26 v dd v dd 30 27 nc no connection. 28 nc no connection. 29 nc no connection. continued on next page.
LC01707PLF no.a1928-7/18 continued from preceding page. pin no. pin name function equivalent circuit 31 scl serial data clock input. 31 v dd v dd 32 sda serial data input/ output. 32 v dd 33 v dd pll_logic supply voltage pin. 34 smeter s-meter output. 34 v dd v dd 35 v dd if supply voltage pin 36 lpfo demodulator output (after band limit). 36 v dd v dd 4pf 37 demoo demodulator output. 37 v dd v dd 20.4pf 1pf 38 lpfi demodulator signal input pin. 38 v dd 1pf + - continued on next page.
LC01707PLF no.a1928-8/18 continued from preceding page. pin no. pin name function equivalent circuit 39 democ capacitor connection pin for demodulator detection. 39 v dd v dd 40 nc no connection. 41 nc no connection. 42 nc no connection. 43 nc no connection. 44 gnd gnd pin. 44 (pin_3) v ss v ss v ss v ss v ss (pin_8) (pin_12) (pin_17) (pin_24)
LC01707PLF no.a1928-9/18 communication specification communication specifications are indicated as below: serial interface (i 2 c-bus); sending and receiving data through i 2 c-bus that consists of two bus lines of a serial data line (sda) and a serial clock line (scl). this bus enables 8-bit bi-direc tional serial data to transmit at the maximum speed of 400kbits (fast mode). this is not compatible with hs mode. terms used in i 2 c the following terms are used in i 2 c terms description transmitter device to send data to the bus receiver device to receive from the bus master device to start data transmission, ge nerate signal, and terminate data transmission slave device of which address is designated master [start] and [stop] conditions [start] condition is required at the start of data communica tion and [stop] condition at the end of data communication. the condition in which the sda line changes from [h] to [l] with scl at [h] is called the [start] condition. the condition in which the sda line changes from [l] to [h] with scl at [h] is called the [start] condition. data transmission the length of each byte which is output to sda line is al ways 8 bits. an acknowledge bit is needed after each byte. data is transmitted sequentially from the most significant bit (msb). during the data transfer, the slave address is transmitted after the [start] condition (s). data transfer is always ended by the [s top] condition (p) generated by the master. d7 d6 d1 d0 p sr 1 2 7 sr or p s or sr 8 9 12 3-8 9 sda scl ack:acknowledgement msb start or repeated start condition ack signal from slave byte complate, interrupt within slave clock line held low while interrrupts are serviced clock pulse for ack clock pulse for ack ack signal from receiver stop or repeated start condition sda scl s p sda scl start condition stop condition
LC01707PLF no.a1928-10/18 acknowledge (receive acknowledge) when the master generates the acknowledge clock pulse, the transmitter opens the sda line. (sda line enters the [h] state.) when the acknowledge clock pulse is in the [h] stat e, the receiver sets the sda lin e to [l] each time it receives one byte (eight bits) data. when the master works as a rece iver, the master informs the sl ave of the end of data by omitting acknowledge at the end of data sent from the slave. software reset if the communication is interrupted (microcomputer reset, etc. ), it is possible to communicat e normally by entering the below signals and resetting the cpu in software. *these signal timings restore the communication after its interruption. the register setting is never reset. *software reset command is incompatible with i 2 c-bus format. s 1 2 8 9 release the sda line(high) nack(master is receiver) ack(master is transmitter) data output by transmitter data output by receiver scl from master start condition clock pulse for ack ack:acknowledgement nack:not acknowledgement sda scl s 1 27 8 9 sr p start condition repeated start condition stop cindition
LC01707PLF no.a1928-11/18 electrical specification an d timing for i/o stages bus line characteristics characteristic symbol fast -mode unit example at scl = 100khz min max scl clock frequency fscl 400 khz 100 fall time of sda and scl t1 20+0.1cb 300 ns rise time of sda and scl t2 20+0.1cb 300 ns scl ?h? time t3 0.6 s 3 scl ?l? time t4 1.3 s 7 [start] condition holding time t5 0.6 s 10 data holding time for i 2 c bus device t6 0.3 s data setup time t7 0.1 s 3 [stop] condition setup time t8 0.6 s 10 bus free time between [stop] and [start] t9 1.3 s 20 [start] condition setup time t10 0.6 s bus line capacitive load cb 400 pf serial interface voltage level v dd : communication bus voltage characteristic min max unit high level input voltage 0.7v dd v dd v low level input voltage 0.0 0.3v dd v high level output voltage (open drain) v dd *2 v low level output voltage (open drain) 0.0 0.2v dd v *2: output impedance of open drain beco mes high at the high level output voltage. output voltage equals to v dd (voltage =v dd ) since drain is pulled up to v dd . t1 t10 t5 start condition t4 t2 t6 t3 t7 t1 t2 sd sc t9 t8 stop condition
LC01707PLF no.a1928-12/18 definition of each bit 1) slave address the slave address consists of seven-bit fixed address "1110000" or "1110001", which is unique to a chip, and the eighth-bit data direction bit(r/w). send ing (writing) is processed when the da ta direction bit is"0", and receiving (reading) is processed when it is "1". the fixed address is set to "1110001" at devar=1 and it is set to "1110000" at devar=0. r/w bit read 1 write 0 2) register address since the total number of internal register is 34, 2-bit data set on the msb side becomes invalid. 64 addresses are accepted 6 bits are used, but on ly 34 registers are used. 3) register data each register data consists of eight bits. 1/0 r/w msb 1 1 1 00 0 lsb fixed address a1 a0 msb 0 0 a5 a4 a3 a2 lsb invakid address valid address d1 d0 msb d7 d6 d5 d4 d3 d2 lsb
LC01707PLF no.a1928-13/18 command format 1) individual registers data writing 2) individual registers data reading s 1 0 11 0 0 1/0 0 0 0 0 1/0 1/0 1/0 1/0 1/0 1/0 0 sda start condition slave address ack register address ack 1/0 1/0 1/0 1/0 1/0 1/0 0 1/0 1/0 p register data ack stop condition from master to slave from slave to master write invalid address s 1 0 11 0 0 1/0 0 0 0 0 1/0 1/0 1/0 1/0 1/0 1/0 0 sda start condition slave address ack register address ack 1/0 1/0 1/0 1/0 1/0 1/0 1 1/0 1/0 p register data nack stop condition from master to slave from slave to master write invalid address sr 1 0 11 0 0 1/0 1 0 read repeated start condition slave address ack
LC01707PLF no.a1928-14/18 register map 1 * hex value is set by default. : unused bit register address bit bit name function bit operation read/ write binary value hex value 00h 7 0 h?00 6 sd_sl[2] sd level detection setting 0:drs0 1:drs1 2:drs2 3:drs3 4:drs4 5:drs5 6:drs6 7:drs7 r/w 0 5 sd_sl[1] r/w 0 4 sd_sl[0] r/w 0 3 dwag[3] wide band agc level setting 0:15.6mvp-p 1:31.3mvp-p 2:46.9mvp-p 3:62.5mvp-p 4:78.1mvp-p 5:93.8mvp-p 6:109.4mvp-p 7:125.0mvp-p 8:140.6mvp-p 9:156.3mvp-p 10:171.9mvp-p 11:187.5mvp-p 12:203.1mvp-p 13:218.8mvp-p 14:234.4mvp-p 15:250mvp-p r/w 0 2 dwag[2] r/w 0 1 dwag[1] r/w 0 0 dwag[0] r/w 0 01h 7 0 h?00 6 0 5 0 4 0 3 0 2 0 1 imsd_sl[1] unused 0 0 imsd_sl[0] 0 02h 7 clkin xtal current setting 1:normal 0:twice r/w 1 h?99 6 dlocksel lockdet output waveform selection 1:number of comparing 6 0:munber of comparing 3 r/w 0 5 dfsel[1] phase comparison frequency selection 0:100khz 1:50khz 2:50khz 3:25khz r/w 0 4 dfsel[0] r/w 1 3 enpe entire circuit enable 1:on 0:off (entire circuit off) r/w 1 2 dnga[2] narrow band agc level setting 0:35mvp-p 1:111mvp-p 2:187mvp-p 3:263mvp-p 4:339mvp-p 5:415mvp-p 6:491mvp-p 7:567mvp-p (when the setting value is ether 0 or 1 and msk=4%, error is detected in ber.) r/w 0 1 dnga[1] r/w 0 0 dnga[0] r/w 1 03h 7 encplevel charge pump level comparison selection 1:on 0:off r/w 1 h?ff 6 denpro program counter enable 1:on 0:off r/w 1 5 denpd phase comparison enable 1:on 0:off r/w 1 4 dencp charge pump enable 1:on 0:off r/w 1 3 denref s-meter enable 1:on 0:off r/w 1 2 denxtal xtal enable 1:on 0:off r/w 1 1 debdemo demodulator enable 1:on 0:off r/w 1 0 enfst complex bpf block, if agc block enable 1:on 0:off r/w 1 04h 7 denleveldet capacitor bank control circuit enable 1:on 0:off r/w 0 h?7f 6 enrfmix rfmix enable 1:on 0:off r/w 1 5 eniflpf if lpf enable 1:on 0:off r/w 1 4 endet wide band agc, narrow band agc block enable 1:on 0:off r/w 1 3 enlna lna block enable 1:on 0:off r/w 1 2 densmeter reference counter enable 1:on 0:off r/w 1 1 dloen local oscillation enable 1:on 0:off r/w 1 0 denpll pll block enable 1:on 0:off r/w 1 05h 7 0 h?03 6 0 5 0 4 0 3 0 2 0 1 dnbagc if agc detection selector (narrow band agc) 1:on 0:off r/w 1 0 dwbagc rf agc detection selector (wide band agc) 1:on 0:off r/w 1 06h 7 df0osc[7] capacitor band value oscillation frequency adjustment for master time constant setting r/w 1 h?80 6 df0osc[6] r/w 0 5 df0osc[5] r/w 0 4 df0osc[4] r/w 0 3 df0osc[3] r/w 0 2 df0osc[2] r/w 0 1 df0osc[1] r/w 0 0 df0osc[0] r/w 0 07h 7 dbpfo[7] capacitor bank value complex bpf f0 adjustment r/w 1 h?80 6 dbpfo[6] r/w 0 5 dbpfo[5] r/w 0 4 dbpfo[4] r/w 0 3 dbpfo[3] r/w 0 2 dbpfo[2] r/w 0 1 dbpfo[1] r/w 0 0 dbpfo[0] r/w 0
LC01707PLF no.a1928-15/18 register map 2 * hex value is set by default. : unused bit register address bit bit name function bit operation read/ write binary value hex value 08h 7 d2bpf[7] capacitor bank value 2 nd if bpf f0 adjustment r/w 1 h?80 6 d2bpf[6] r/w 0 5 d2bpf[5] r/w 0 4 d2bpf[4] r/w 0 3 d2bpf[3] r/w 0 2 d2bpf[2] r/w 0 1 d2bpf[1] r/w 0 0 d2bpf[0] r/w 0 09h 7 0 h?17 6 0 5 ddemog[1] dll demodulator loop gain setting r/w 0 4 ddemog[0] r/w 1 3 dmonoc[3] mono multi center setting r/w 0 2 dmonoc[2] r/w 1 1 dmonoc[1] r/w 1 0 dmonoc[0] r/w 1 0ah 7 0 h?02 6 0 5 0 4 0 3 0 2 0 1 enimrssi xtal osc fet size setting 1:normal 0:twice r/w 1 0 diqc complex bpf injection changeover 1:lower 0:upper r/w 0 0bh 7 0 h?40 6 dbl[6] iq balance adjustment r/w 1 5 dbl[5] r/w 0 4 dbl[4] r/w 0 3 dbl[3] r/w 0 2 dbl[2] r/w 0 1 dbl[1] r/w 0 0 dbl[0] r/w 0 0ch 7 0 h?0a 6 0 5 0 4 0 3 dcp1ref[3] charge pump output current value setting 0:0.1ma 1:0.2ma 2:0.3ma 3:0.4ma 4:0.5ma 5:0.6ma 6:0.7ma 7:0.8ma 8:0.9ma a:1ma b:1.1ma c:1.2ma d: unused e: unused f: unused r/w 1 2 dcp1ref[2] r/w 0 1 dcp1ref[1] r/w 1 0 dcp1ref[0] r/w 0 0dh 7 dpcnt_l[7] n value of frequency divider (low 8 bits) n value of frequency divider = ((4 received frequency) (4 1 st if frequency)) / (4 channel step frequency) * 1 st if frequency is 1.2mhz r/w * h?** 6 dpcnt_l[6] r/w * 5 dpcnt_l[5] r/w * 4 dpcnt_l[4] r/w * 3 dpcnt_l[3] r/w * 2 dpcnt_l[2] r/w * 1 dpcnt_l[1] r/w * 0 dpcnt_l[0] r/w * 0eh 7 dpcnt_h[7] n value of frequency divider (high 8 bits) r/w * h?** 6 dpcnt_h[6] r/w * 5 dpcnt_h[5] r/w * 4 dpcnt_h[4] r/w * 3 dpcnt_h[3] r/w * 2 dpcnt_h[2] r/w * 1 dpcnt_h[1] r/w * 0 dpcnt_h[0] r/w * 0fh 7 dcbank_l[7] local oscillator capacitor bank setting (low 8 bits) r/w 0 h?00 6 dcbank_l[6] r/w 0 5 dcbank_l[5] r/w 0 4 dcbank_l[4] r/w 0 3 dcbank_l[3] r/w 0 2 dcbank_l[2] r/w 0 1 dcbank_l[1] r/w 0 0 dcbank_l[0] r/w 0
LC01707PLF no.a1928-16/18 register map 3 * hex value is set by default. : unused bit register address bit bit name function bit operation read/ write binary value hex value 10h 7 0 h?01 6 0 5 0 4 0 3 0 2 0 1 0 0 dcbank_h[8] local oscillator capacitor bank setting (high 1 bit) r/w 1 11h 7 0 h?0f 6 0 5 0 4 dcben unused 0 3 dloalc[3] local oscillation level setting r/w 1 2 dloalc[2] r/w 1 1 dloalc[1] r/w 1 0 dloalc[0] r/w 1 12h 7 0 h?00 6 denifcount frequency counter (analog block) enable 1:on 0:off r/w 0 5 denf0osc f0 detection oscillation circuit enable 1:on 0:off r/w 0 4 deniffreq logic part reference clock enable 1:on 0:off r/w 0 3 0 2 dsctcount[2] count frequency selection 0:unused 1:if frequency 2:prescaler frequency 3:freacaler frequency 4:f0 detection oscillation frequency 5:f0 detection oscillation frequency 6:unused 7:if frequency r/w 0 1 dsctcount[1] r/w 0 0 dsctcount[0] r/w 0 13h 7 0 h?01 6 0 5 0 4 0 3 0 2 cte counter start trigger 1:on (frequency counter start) charge to 0 automatically r/w 0 1 gt[1] frequency counter gate time selection 0:4ms 1:8ms 2:32ms 3:64ms r/w 0 0 gt[0] r/w 1 14h 7 lofq_l[7] lo_count value (low 8 bits) measurement frequency = counter value / gt[ms] r * h?00 6 lofq_l[6] r * 5 lofq_l[5] r * 4 lofq_l[4] r * 3 lofq_l[3] r * 2 lofq_l[2] r * 1 lofq_l[1] r * 0 lofq_l[0] r * 15h 7 lofq_h[7] lo_count value (upper 8 bits) r * h?00 6 lofq_h[6] r * 5 lofq_h[5] r * 4 lofq_h[4] r * 3 lofq_h[3] r * 2 lofq_h[2] r * 1 lofq_h[1] r * 0 lofq_h[0] r * 16h 7 0 h?10 6 0 5 countsel 0 4 lockdetsel 1 3 lockdet_dig 0 2 lockdet lock detection 1:lock 0:unlock r/w 0 1 phlevel[1] charge pump voltage level detection 0:less than 0.5v 1:0.5v to 2.8v 2:unused 3:more than 2.8v r/w 0 0 phlevel[0] r/w 0 17h 7 * h?0* 6 * 5 * 4 * 3 imrssi[3] reset detection circuit 0:reset 1:reset cancellation r * 2 imrssi[2] r * 1 imrssi[1] r * 0 imrssi[0] r *
LC01707PLF no.a1928-17/18 register map 4 * hex value is set by default. : unused bit register address bit bit name function bit operation read/ write binary value hex value 18h 7 0 h?** 6 drs[6] s-meter detection level detection range can be changed by setting to dnga (02h) r * 5 drs[5] r * 4 drs[4] r * 3 drs[3] r * 2 drs[2] r * 1 drs[1] r * 0 drs[0] r * 19h 7 ifcount_l[7] if count value (low 8 bits) 2 nd if frequency measurement results r * h?** 6 ifcount_l[6] r * 5 ifcount_l[5] r * 4 ifcount_l[4] r * 3 ifcount_l[3] r * 2 ifcount_l[2] r * 1 ifcount_l[1] r * 0 ifcount_l[0] r * 1ah 7 ifcount_h[7] if count value (high 8 bits) r * h?** 6 ifcount_h[6] r * 5 ifcount_h[5] r * 4 ifcount_h[4] r * 3 ifcount_h[3] r * 2 ifcount_h[2] r * 1 ifcount_h[1] r * 0 ifcount_h[0] r * 1bh 7 imcount_l[7] unused r * h?** 6 imcount_l[6] r * 5 imcount_l[5] r * 4 imcount_l[4] r * 3 imcount_l[3] r * 2 imcount_l[2] r * 1 imcount_l[1] r * 0 imcount_l[0] r * 1ch 7 imcount_h[7] unused r * h?** 6 imcount_h[6] r * 5 imcount_h[5] r * 4 imcount_h[4] r * 3 imcount_h[3] r * 2 imcount_h[2] r * 1 imcount_h[1] r * 0 imcount_h[0] r * 1dh 7 f0_l[7] f0 detection oscillation frequency count value (low 8 bits) frequency measurement result for master time constant setting r * h?** 6 f0_l[6] r * 5 f0_l[5] r * 4 f0_l[4] r * 3 f0_l[3] r * 2 f0_l[2] r * 1 f0_l[1] r * 0 f0_l[0] r * 1eh 7 f0_h[7] f0 detection oscillation frequency count value (high 8 bits) r * h?** 6 f0_h[6] r * 5 f0_h[5] r * 4 f0_h[4] r * 3 f0_h[3] r * 2 f0_h[2] r * 1 f0_h[1] r * 0 f0_h[0] r * 1fh 7 0 h?02 6 0 5 0 4 0 3 0 2 doutsel register for test r/w 0 1 dcntest register for test r/w 1 0 douttest register for test r/w 0 continued on next page.
LC01707PLF ps no.a1928-18/18 continued from preceding page. register address bit bit name function bit operation read/ write binary value hex value 20h 7 0 h?0a 6 err2 local oscillator capacitor bank control error flag 2 r/w 0 5 err1 local oscillator capacitor bank control error flag 1 r/w 0 4 dcosel2 local oscillator capacitor bank value changeover 1:cap bank control value 0:i 2 c input value r/w 0 3 dcosel1 local oscillator capacitor bank control process changeover 1:correcting process after sequential comparison 0:no correcting process after sequential comparison r/w 1 2 dcosel0 local oscillator capacitor bank control process changeover (micro alignment) 1:micro adjustment process 0:no micro adjustment process r/w 0 1 dwaitsel[1] pll operation check wait time after local oscillator capacitor bank adjustment 0:200 s 1: 400 s 2:800 s 3:1600 s r/w 1 0 dwaitsel[0] r/w 0 21h 7 0 h?0a 6 0 5 denint register for test r/w 0 4 masksel register for test r/w 0 3 losel register for test r/w 1 2 intph register for test r/w 0 1 intim register for test r/w 1 0 intlo register for test r/w 0 22h 7 testsel[2] register for test r/w 0 h?15 6 testsel[1] register for test r/w 0 5 testsel[0] register for test r/w 0 4 dsw pll loop filter on/off 1:on 0:off r/w 1 3 timesel2[1] local oscillator capacitor bank control correcting circuit operation clock setting 0:200 s 1: 400 s 2:800 s 3:1600 s r/w 0 2 timesel2[0] r/w 1 1 timesel[1] local oscillator capacitor bank control sequential comparison control operation clock setting 0:10 s 1: 20 s 2:40 s 3:80 s r/w 0 0 timesel[0] r/w 1 sd pin specification sd voltage level v dd : supply voltage item min max unit high level output voltage v dd -0.8 v dd v low level output voltage 0 0.4 v this catalog provides information as of october, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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