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-??? x ? ? page 2 of 8 w ww.cd4 p ower.com +25c 0 t o +70c C55 t o +12 5 c analog input min. typ. max. min. typ. max. min. typ. max. units input volta g e ran ge unipolar 0 to C5.5v 0 to C5.5v 0 to C5.5v volts bipolar 2.75 2.75 2.75 volts input resistance (pin 3) 400 400 400 7 (pin 2) 480 480 480 7 input capacitance 10 15 10 15 10 15 pf digital input s l og i c l eve l s logic "1" +2.0 +2.0 +2.0 volts logic "0" +0.8 +0.8 +0.8 volts logic loading "1" +20 +20 +20 a l og i c l oa di ng " 0 " ? ? ?20 ? ? ?20 ? ? ?20 a s tart convert positive pulse width ? 20 50 20 50 20 50 ns s tati c perf o rman c e r eso luti on 16 16 16 bits inte g ral nonlinearit y 1 1.5 2 lsb di ff erential nonlinearit y ( f in = 10khz) C0.95 0.5 +1.0 C0.95 0.5 +1.0 C0.95 0.5 +1.5 lsb full scale absolute accurac y 0.15 0.3 0.3 0.5 0.5 0.8 %fsr bipolar ero erro r (tech note 2) 0.1 0.2 0.2 0.4 0.4 0.6 %fsr bipolar offset erro r (tech note 2) 0.1 0.2 0.2 0.4 0.4 0.6 %fsr g ain error (tech note 2) 0.15 0.3 0.3 0.5 0.5 0.8 % n o missin g code s ( f in = 10khz) 16 16 16 bits dynamic performance p ea k h armon i cs (C0.5db) dc to 500khz C87 C82 C87 C82 C82 C78 db 500khz to 2.45mhz C82 C80 C82 C80 C78 C78 db t ota l h armon i c di stort i o n (C0.5db ) dc to 500khz C86 C81 C86 C81 C81 C76 db 500khz to 2.45mhz C81 C80 C81 C80 C77 C76 db s ignal-to-noise rati o (w / o distortion, C0.5db) dc to 500khz 84 86 84 86 77 80 db 500khz to 2.45mhz 83 85 83 85 77 80 db signal-to-noise rati o ? ( & distortion, C0.5db) dc to 500khz 80 82 80 82 76 78 db 500khz to 2.45mhz 79 81 79 81 76 75 db n o i s e 80 80 80 vrms t wo- t one i ntermo d u l at i o n di stort i o n ( f in = 200 kh z , 240khz , f s = 5mhz, C0.5db) C87 C85 C87 C85 C87 C82 db i n p ut b an d w id t h (C3db ) small signal (C20db input) 25 25 25 mhz large signal (C0.5db input) 15 25 15 mhz f ee d t h roug h r e j ect i o n ( f in = 1mhz) 90 90 90 db s lew rate 400 400 400 v/s a perture d e l ay ti m e 4 4 4 ns aperture uncertaint y 2 2 2 ps rms s /h ac q uisition tim e ( to 0.001%fsr, 5.5v step) 80 80 90 ns o vervoltage recovery time ? 200 200 200 ns a / d c onversion rat e 5 5 5 mhz parameters min. typ. max. units o peratin g temp. ran g e, case ads-935mc 0 +70 c ADS-935MM C55 +125 c t hermal impedance q jc 4 c/watt q ca 18 c/watt stora g e temperature ran ge C65 +150 c package typ e 40-pin, metal-sealed, ceramic tdip w eigh t 0.56 ounces (16 grams) a bsolute maximum ratings parameters limits units +5v s uppl y (pins 31, 38) 0 to +6 volts C 5v s upply (pin 37) 0 to C6 volts +12v/+15v s upply (pin 40) 0 to +16v volts C 12v/C15v s uppl y (pin 39) 0 to +16v volts di g i ta l i nputs (pins 8, 9, 12, 34, 35) C0.3 to +v dd +0.3 volts a na l og i nput (pin 3) 5 volts l ead temperature (10 seconds) +300 c p hy s ical / environmental f u n c ti o nal s pe c ifi c ati o n s ( t a = +25c, v a cc = 12/15v, +v dd = 5v, 5mhz sampling rate, and a minimum 3 minute warm-up ~ unless otherwise s p ecified.)
-??? x p age 3 of 8 ? ? www.cd4 p ower.com +25c 0 to +70c C55 to +125c dynami c perf o rman c e ( c ont.) min. typ. max. min. typ. max. min. typ. max. units a nal og o utpu t i nt e rn a l r efe r e n ce voltage +3.2 +3.2 +3.2 volts drift 30 30 30 ppm/c e xternal c urren t 5 5 5 ma d i g ital ou tp u t s l og i c l eve l s logic "1" +2.4 +2.4 +2.4 volts logic "0" +0.4 +0.4 +0.4 volts logic loading "1" C4 C4 C4 ma logic loading "0" +4 +4 +4 ma o utput codin g ? (offset) binar y / complementar y (offset) binar y / two's complement / complementar y two's complement power re q uirement s p ower s upply ranges ? +5v supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 volts C5v supply C4.75 C5.0 C5.25 C4.75 C5.0 C5.25 C4.9 C5.0 C5.25 volts +12v s uppl y ? +11.5 +12.0 +12.5 +11.5 +12.0 +12.5 +11.5 +12.0 +12.5 volts ?12v s uppl y ? ?11.5 ?12.0 ?12.5 ?11.5 ?12.0 ?12.5 ?11.5 ?12.0 ?12.5 volts +15v s uppl y ? +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 volts ?15v s uppl y ? ?14.5 ?15.0 ?15.5 ?14.5 ?15.0 ?15.5 ?14.5 ?15.0 ?15.5 volts p ower s upply currents +5v supply +200 +220 +220 ma C5v supply C100 C150 C150 ma C12 / 15v s uppl y ? ? ?65 ? ? ?65 ? ? ? ? ma +12 / 15v s uppl y ? ? +85 ? ? +85 ? ? ? ? ma p ower dissi p ation 2.85 3.1 2.85 3.5 2.85 3.5 watts p ower s upply rejection 0.07 0.07 0.07 %fsr/%v f oo tn o t es: ? effective bits is equal to: ~ all power supplies must be on before applying a start convert pulse. all supplies and the clock (start convert) must be present during warm-up per i o d s. th e d ev i ce must b e cont i nuous l y convert i ng d ur i ng t hi s t i me. when comp. bits (pin 35) is low, lo g ic loadin g "0" will be ?350a. ? a 5mhz clock with a 50nsec positive pulse width is used f or all production testin g . s ee timin g dia g ram for more details. 6 .0 2 (snr + distortion) C 1.76 + 20 log full s cale am p litude a ctua l i n p ut a m pli tu d e ? this is the time required before the a/d output data is valid once the analo g input is back within the specified ran g e. ? s ee table 2a, s ettin g o utput c odin g s election. ? the minimum supply voltages of +4.9v and ?4.9v for v dd are required for ?55c operation only. the minimum limits are +4.75v and ?4.75v when o perating at +125c. ? 12v onl y or 15v onl y required. technical note s 1. obtainin g full y specified performance from the ads-935 r equires careful attention to pc-card la y out and power suppl y d ecoup li ng. th e d ev i ce ' s ana l og an d di g i ta l groun d systems a re connected to each other internally. for optimal per f or- m ance, tie all ground pins ( 4, 7, 30 and 36 ) directly to a large a na l og groun d p l ane b eneat h t h e pac k age. for the best per f ormance it is recommended to use a single p ower source f or both the +5v analog and +5v digital supplies. by pass all power supplies and the +3.2v reference output to g round with 4.7f tantalum capacitors in parallel with 0.1f c eramic capacitors. locate the b y pass capacitors as close to the unit as p ossible. 2. the ads-935 achieves its s p ecified accuracies without the n eed f or external calibration. i f required, the device's small i nitial o ff set and gain errors can be reduced to zero using t h e a dj ustment c i rcu i try s h own i n fi gure 2. wh en us i ng t hi s c ircuitry, or any similar o ff set and gain calibration hardware, m ake ad j ustments followin g warm-up. to avoid interaction, a lwa y s ad j ust offset before g ain. tie pins 5 and 6 to analog g round (pin 4) if not usin g offset and g ain ad j ust circuits. 3 . pin 35 (comp. bits) is used to select the di g ital output codin g format of the ads-935. see tables 2a and 2b. when this pin has a ttl lo g ic "0" applied, it complements all of the ads-935s di g ital outputs. when pin 35 has a lo g ic "1" applied, the output codin g is complementary (o ff set) binary. applying a logic "0" to pin 35 changes the coding to (offset) binary. using the m s b output (pin 29) instead of the m s b output (pin 28) changes the respect i ve output co di ngs to comp l ementary two ' s com p lement and two's com p lement. pi n 35 i s ttl compat ibl e an d can b e di rect l y d r i ven w i t h di g ital lo g ic in applications requirin g d y namic control over its function. there is an internal p ull-u p resistor on p in 35 allowin g it to be either connected to +5v or left open when a lo g ic "1" is required. 4 . to enable the three-state out p uts, connect output enable ( pin 34 ) to a logic "0" ( low ) . to disable, connect pin 34 to a logic "1" ( high ) .
-??? x ? ? page 4 of 8 w ww.cd4 p ower.com d elay pin tran s iti o n min. typ. max. u nit s direct mode to fifo enabled 8 C 10 20 ns fifo enabled to direct mode 8 C 10 20 ns fifo read to output data valid 9 C C 40 ns fifo read to status update when chan g in g f rom -??? x p age 5 of 8 ? ? www.cd4 p ower.com l ed's to the digital outputs and per f orming adjustments until c ertain led's "flicker" equally between on and off. o ther a pproaches employ digital comparators or microcontrollers to d etect when the outputs chan g e from one code to the next. f or the ads-935, offset ad j ustin g is normall y accomplished w hen the analo g input is 0 minus ? lsb (C42v). see table 2 b for the proper bipolar output codin g . g ain ad j ustin g is accomplished when the analo g input i s at nominal full scale minus 1? lsb's ( +2.749874v or C 5.499874v ) . n ote: c onnect pin 5 to anal og g r o und (pin 4) for o peration without zero / offset adjustment. c onnect pin 6 to p in 4 f or operation without gain adjustment. z ero /o ffset adjust procedur e 1 . apply a train of pulses to the s tart co nvert input (pin 12 ) so that the converter is continuously converting. 2 . for zero / offset adjust, apply C42v to the anal og input ( pin 3 ) . 3 . for bipolar operation - adjust the o ff set potentiometer until the code flickers between 1 000 0000 0000 0000 and 0 111 1111 1111 1111 with pin 35 tied hi g h (complementar y offset binar y ) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binar y ). for unipolar operation - ad j ust the offset potentiometer until all out p uts are 1's and the lsb flickers between 0 and 1 with pin 35 tied high ( complementary binary ) or until all outputs are 0's and the l s b flickers between 0 and 1 with pin 35 tied low ( binary ) . 4. for bipolar, two's complement coding requires using bit 1 (m s b) (pin 29). with pin 35 tied low, adjust the trimpot until the out p ut code flickers between all 0s and all 1s. g ain ad j ust procedur e 1 . for gain adjust, f or bipolar apply +2.749874v and f or unipo- lar mode 5.499874v to the analog input (pin 3) . 2 . adj ust t h e ga i n potent i ometer unt il a ll output bi ts are 0 s an d the lsb flickers between a 1 and 0 with pin 35 tied hi g h (complementar y (offset) binar y ) or until all output bits are 1s and the lsb flickers between a 1 and 0 with p in 35 tied low ((offset) binar y ) . 3 . for bipolar, two's complement codin g requires usin g bit 1 (m s b) (pin 29). with pin 35 tied low, adjust the gain trimpot until the output code f lickers equally between 0111 1111 1111 1111 an d 0111 1111 1111 1110. 4 . to con f irm proper operation o f the device, vary the applied i nput vo l tage to o b ta i n t h e output co di ng li ste d i n t a bl e 2 b . complementar y (offset) binar y 1 ( o ffset) binary 0 complementary twos complement 1 (usin g m s b, pin 29) twos c omplement 0 (using msb, pin 29) ou tp u t f o rmat pin 35 l og i c leve l table 2a. setting output coding selection (pin 35 ) fi g ure 2. connection dia g ra m c alibrati o n pr oc ed u re connect the converter per fi g ure 2. an y offset/ g ain calibration p rocedures should not be im p lemented until the device is full y warmed up. to avoid interaction, ad j ust offset before g ain. the ran g es of ad j ustment for the circuits in figure 2 are guaranteed to compensate for the ad s -935s initial accuracy errors and may not be able to compensate f or a ddi t i ona l system errors. a / d converters are calibrated by positioning their digital outputs exact l y on t h e trans i t i on po i nt b etween two a dj acent di g ital output codes. this is accomplished b y connectin g !$3 7 7 / 6%2&, / 7 %/# " )4- 3 " " )4- 3 " " )4 ")4 ")4 ")4 ")4 ")4 ")4 ")4 " )4 ")4 ")4 " )4 ")4 " )4 ")4 ,3" 6 6 n n6 6 6 ?& ? & ?& ?& ? & ? & ? & ?& ?& ?& ?& ? & n 6 n6 6 6 n6 n 6 k k ! .!, /' ' 2 / 5.$ $ ) ' )4!, ' 2 /5 .$ #/ -0")4 3 62%& / 5 4 5 .)0 / ,!2 & or "ip o l a r # onnectfo r 5 nipolar-ode l ton6 & )& / 2%!$ 6$) ' )4! , / && 3 % 4 !$ *534 ' !). ! $ *534 6!.!, /' 3 4!24 #/ .6%24 ! .!, /' ).05 4 %.!",% & )& / $) 2 &3 4!4 &3 4!4
-??? x ? ? page 6 of 8 w ww.cd4 p ower.com thermal requirements a ll datel samplin g a/d converters are full y characterized a nd specified over operatin g temperature (case) ran g es of 0 to +70c and C55 to +125c. all room-tem p erature (t a = +25c) a production testing is per f ormed without the use o f heat sinks or f orced-air cooling. thermal impedance f igures f or each device a re listed in their respective speci f ication tables. th ese d ev i ces d o not norma ll y requ i re h eat s i n k s, h owever, s tan d ar d precaut i onary d es i gn an d l ayout proce d ures s h ou ld b e use d to ensure d ev i ces d o not over h eat. th e g roun d an d power planes beneath the packa g e, as well as all pcb si g nal r uns to and from the device, should be as heav y as possible to help conduct heat awa y from the packa g e. electricall y insulatin g , thermall y -conductive "pads" ma y be installed un d erneat h t h e pac k age. d ev i ces s h ou ld b e so ld ere d to boards rather than "socketed", and o f course, minimal air f low over the sur f ace can greatly help reduce the package t empera t ure. in more severe ambient conditions, the package/junction t emperature of a g iven device can be reduced dramaticall y (t y picall y 35%) b y usin g one of datel's hs series heat sinks. see orderin g information for the assi g ned part number. see pa g e 1-183 of the datel data acquisition c omponents c atalog for more information on the h s s eries. request datel application note an-8, "heat s inks for dip d ata c onverters," or contact datel directly, for additional i n f ormation. figure 3. ads-935 timing diagra m n o te s : 1. s cale is approximatel y 20ns per didsion.fs = 5mhz 2 . this device has three pipeline dela y s. four start convert pulses (clock c y cles) must be applied f or valid data f rom the first conversion to a pp ear at the out p ut of the a/d. 1111 1111 1111 1111 lsb "1" to "0" 1110 0000 0000 0000 1100 0000 0000 0000 1000 0000 0000 0000 0111 1111 1111 1111 0100 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0001 lsb "0" to "1" 0000 0000 0000 0000 + f s C1 l sb + f s C1 1 / 2 l sb +3 / 4 f s +1 / 2 f s 0 C 1 l sb C 1 / 2 f s C 3 / 4 f s C f s +1 l sb C f s + 1 / 2 l s b Cf s input r an g e 2.75 v + 2 .74 9916 + 2 .74 98 74 + 2 . 062 5 00 + 1 . 3 75 000 0 . 000000 C0 . 00008 4 C1 . 3 75 000 C2 . 062 5 00 C2 .74 9916 C2 .74 99 5 8 C2 .75 0000 0000 0000 0000 0000 lsb "0" to "1" 0001 1111 1111 1111 0 0011 1111 1111 1111 0 0111 1111 1111 1111 0 1000 000 000 0000 1 1011 1111 1111 1111 0 1101 1111 1111 1111 0 1111 1111 1111 1110 1 l sb "1" to "0" 1111 1111 1111 1111 0 0111 1111 1111 1111 l s b "1" to "0 " 0110 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 111 0 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0001 0 lsb "0" to "1 " 1000 0000 0000 0000 1000 0000 0000 0000 1 ls b "0" to "1" 1001 1111 1111 1111 0 1011 1111 1111 1111 0 1111 1111 1111 1111 0 0000 0000 0000 0000 1 0011 1111 1111 1111 0 0101 1111 1111 1111 0 0111 1111 1111 1110 1 l sb "1" to "0" 0111 1111 1111 1111 0 b ip o la r scale table 2b. o utput c odin g 0 C1 l s b 0 C1 1 / 2 l s b 0 C 1 / 8 f s 0 C 1 / 4 f s C1 / 2 f s C 1 / 2l sb C 1 / 2 l s b C3 / 4 f s C7 / 8 f s Cf s +1 l sb C f s + 1 / 2 l s b Cf s input ran g e 0 to C 5 . 5v C0.000084 C0.000126 C0.687500 C1.375000 C2.749958 C2.750000 C4.125000 C4.812500 C5.499916 C5.499958 C5.500000 u nip o la r scale msb lsb msb lsb msb lsb msb lsb offset binary comp. off. bin. two's comp. comp. two's comp. comp. binary binary comp. two's comp. two's comp. star t conver t i nternal s/ h n n + 1 eoc ou tp ut data da t a n-4 v a li d conversion time o v r o t m hold o d n + 2 n + 3 acquisition time a q s e da t a n-1 v a li d i nv alid da t a i nv alid da t a da t a n-2 v a li d data n- 3 vali d 20ns typ. 0 s y 125ns typ. p 110ns typ. p 75ns typ. 5 s y 50ns typ. 0 s y 20ns typ. 2 n t p 20ns typ. 0 s y . 5 0ns typ . 150ns typ. 1 0 s y
-??? x p age 7 of 8 ? ? www.cd4 p ower.com figure 4. ads-935 evaluation board schematic. 20 k r4 1 2 3 u2 9 8 7 6 5 4 3 2 11 1 19 1 8 17 16 1 5 14 13 12 10 20 7 4h c t573 uut b 6 b 7 b 8 b 9 b 10 b11 + 5vd d gnd m sb b2 b 3 b4 b5 b12 b 13 b 1 4 b 1 5 l s b s tar t ad s - 935 f stat 2 fs tat1 + 12 / +15 v C 12 / C15v + 5va - 5va ag n d co m p enable of e oc read f if o/ d i r dg n d g a i n o ff s e t ag n d ana in +3 .2vref u 6 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 13 1 4 1 5 1 6 17 18 1 9 2 0 2 1 22 23 24 25 26 27 28 29 30 31 3 2 33 3 4 35 36 37 38 39 40 u 1 1 2 1 1 13 8 9 10 7 4h c t7 4 2 .2 f c 1 3 33 3 1 29 27 25 23 2 1 19 17 15 13 1 1 9 7 5 3 1 3 4 3 2 30 2 8 2 6 24 22 2 0 18 1 6 14 1 2 10 8 6 4 2 p 1 f s t 2 s tar t f s t 1 b 16 fif / di r b 15 rea d b 14 n . c. b 1 3 co mpli m b 12 enabl e b 11 d g nd b10 d g nd b 9 dg nd b8 dg nd b 7 dg nd b6 dg nd b5 dg nd b4 e oc b3 o vrfl w b2 b1b m sb b 1(msb) 2.2 f c 11 0.1 f c 20 u 4 9 8 7 6 5 4 3 2 1 1 1 19 18 1 7 16 15 14 13 12 10 2 0 74h c t 5 7 3 0.1 f c 1 5 3 3pf c 10 1 2 0.1 f c 18 0 .1f c3 2 .2 f c1 2 .2f c 1 4 2.2 f c2 2 . 2f c9 s g 8 sg 7 2 .2f c 12 2 .2f c 21 r2 r 1 3 .3k r 3 1 2 u 1 2 3 1 6 5 4 7 4hct7 4 sg 9 sg6 2 . 2 f c 4 20 m h l4 ar1 2 3 4 6 7 0 .1 f c 5 20 mh l3 u3 9 8 7 6 5 4 3 2 1 1 1 19 18 17 16 1 5 14 13 12 10 2 0 7 4h c t 5 7 3 sg4 sg3 x 1 1 7 8 14 5 mhz sg2 74h c86 c6 2 . 2 f 20m h l2 0 .1f c 19 j 5 p 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 24 25 26 50 r 6 sg 5 12 13 7 4h c86 u 5 4 5 6 j2 2 0 m h l 1 74h c 86 b2 2 3 1 f c 1 1f c1 2 2f c b1 1 1f c s 1 b 3 co p nab 5a 5 a 5 a 5a 5 a 5a 5a 5 f 5f 5f 5 f 5 f 5f 5 f fi f fi f d d s ta t co n t b2 a b 9 a b 9 15 1 5 oc a b a b a b 1 a b 1 a b 2 a b2 a b 3 ab3 a b a b a b 5 a b 5 a b a b a b ab a b 1 a b1 a b 15 a b1 5 ab1 a b1 a b1 3 a b1 3 a b 12 a b12 a b 11 a b1 1 a b 1 ab1 a b1 fif o di ad c opi b1 5 b1 fs t 2 of b 1 5 d 5 d 5 d 5 d 5d 5d b b 5 b b b1b s b b13 b1 b b12 b11 b 1 b9 1 5 1 5 a n d a nd a nd a n d a n d an d a n d a n d a nd a nd a nd a n d a n d 5a 5 a 5 a 5 a 5 a 5a 5a d nd d nd d nd d n d d nd d nd d n d d nd d n d d nd d nd a d nd d nd d nd d n d d n d d nd d nd d n d d nd d nd s tat co nt ana o inpu t o pti on apifi 3 2 1 1 sb ainad ust o ffst a du s t 3 3 2 2 1 1 1 sb sb 1 5 f 5 f co p 2 5 1 2 3 5a 5 a 2 3 1 9 1 c fst 1 3 2 3 3 2 2 3 2 1 d nd 1 f 1f a n d s b u5 3 u5 u5 p re li m i nar y e va l uat i on b oar d - modified ads-b933 to include 12v or 15v supplies to u6
page 8 of 8 - ??? x ds -0367 05 / 05 me c hani c al dimen s i o n s inches (mm ) o rdering informatio n o peratin g m o del temp. ran ge ad s - 9 35mc 0 to +70 c ad s - 9 35 mm C55 to +125 c r eceptacles for p c board mountin g can be ordered throu g h amp, inc., part # 3-331272-8 ( c omponent lead s ocket), 40 required. for mil- s td-883 product, or surface mount packa g in g , contact datel. a cc e sso rie s ad s -b 9 35 evaluation board (without ad s -935) hs-4 0 heat s ink for all ad s -935 models 0).).$%8 /.4/0 ? 490 3%!4).' 0,!.% -!8 -!8 ? $imension4olerances unlessotherwiseindicated placedecima l88 ?? placedecima l 888 ?? ,ead-aterial +ovarallo y ,ead&inish microi nchesminimum goldplating overmi croinchesnominal nickelplating ? ? ? w ww.cd4 p ower.com c &d technologies (datel), inc . 11 c abot boulevard, mansfield, ma 02048-1151 t el: ( 508 ) 339-3000 ( 800 ) 233-2765 fax: ( 508 ) 339-6356 www.cd4 p ower.com e-mail: sales @ cdtechno.com c &d technolo g ies (datel) makes no representation that the use of its products in the circuits described herein, or the use of other technica l information contained herein, will not infrin g e upon existin g or future patent ri g hts. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. specifications are subj ect to change without notice. the datel logo is a registered c & d technologies, inc. trademark. c &d technologies ltd. milton ke y nes, united kin g dom t el: 44-(0)-1908-615232 e-mail: p ed.ltd@cdtechno.com c&d technolo g ies s .a.r.l. montigny le bretonneux, france t el: 33-(0)1-34-60-01-01 e-mail: ped.sarl@cdtechno.com c &d technologies g mbh mnchen, g erman y t el: 49-(0)-89-544334-0 e-mail: ped.gmbh@cdtechno.com c&d technolo g ies k k tokyo and osaka, japan k t el: 81-3-3779-1031, 6-6354-2025 e-mail: sales_tokyo@cdtechno.com, sales_osaka@cdtechno.com c &d technologies c hina , s hanghai, c hina t el: 011-86-21-50273678 e-mail: shan g hai @ cdtechno.com i so 9001:2000 registere d

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