integrated circuit systems, inc. icssstv16857c third party brands and names are the property of their respective owners. 16857c rev c 11/21/01 pin configuration recommended application: ddr memory modules product features: ? differential clock signal meets sstl_2 signal data supports sstl_2 class i & ii specifications low-voltage operation vdd = 2.3v to 2.7v 48 pin tssop package ddr 14-bit registered buffer truth table 1 block diagram q1 q2 gnd vddq q3 q4 q5 gnd vddq q6 q7 vddq gnd q8 q9 vddq gnd q10 q11 q12 vddq gnd q13 q14 d1 d2 gnd vdd d3 d4 d5 d6 d7 clk# clk vdd gnd vref reset# d8 d9 d10 d11 d12 vdd gnd d13 d14 icssstv16857c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 clk clk# 38 39 48 35 34 d1 vref reset# to 13 other channels q1 1 clk r d1 notes: 1. h = high signal level l = low signal level = transition low-to-high = transition high -to low x = irrelevant 2. output level before the indicated steady state input conditions were established. s t u p n is t u p t u o q # t e s e rk l c# k l cdq l r o x g n i t a o l f r o x g n i t a o l f r o x g n i t a o l f l h hh h ll hh r o lh r o lxq 0 ) 2 ( 48-pin tssop & tvsop 6.10 mm. body, 0.50 mm. pitch = tssop 4.40 mm. body, 0.40 mm. pitch = tssop (tvsop) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 icssstv16857c third party brands and names are the property of their respective owners. general description pin configuration the 14-bit icsstv16857 is a universal bus driver designed for 2.3v to 2.7v vdd operation and sstl_2 i/o levels except for the reset# input which is lvcmos. data flow from d to q is controlled by the differential clock, clk, clk# and reset#. data is triggered on the positive edge of clk. clk# must be used to maintain noise margins. reset# must be supported with lvcmos levels as vref may not be stable during power-up. reset# is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the low state, q outputs are low, and all input receivers, data and clock are switched off. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 8 1 , 9 1 , 0 2 , 3 2 , 4 2 , 6 , 7 , 0 1 , 1 1 , 4 1 , 5 1 1 , 2 , 5 ) 1 : 4 1 ( qt u p t u ot u p t u o a t a d , 2 2 , 3 1 , 8 , 3 6 4 , 6 3 , 7 2 d n gr w pd n u o r g 1 2 , 6 1 , 2 1 , 9 , 4q d d vr w pe g a t l o v y l p p u s t u p t u o , 1 3 , 0 3 , 9 2 , 6 2 , 5 2 , 2 4 , 1 4 , 0 4 , 3 3 , 2 3 8 4 , 7 4 , 4 4 , 3 4 ) 1 : 4 1 ( dt u p n it u p n i a t a d 8 3k l ct u p n it u p n i k c o l c e v i t i s o p 9 3# k l ct u p n it u p n i k c o l c e v i t a g e n 5 4 , 7 3 , 8 2d d vr w pe g a t l o v y l p p u s e r o c 4 3# t e s e rt u p n i) w o l e v i t c a ( t e s e r 5 3f e r vt u p n ie g a t l o v e c n e r e f e r t u p n i
3 icssstv16857c third party brands and names are the property of their respective owners. absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6v input voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to vdd +0.5 output voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to vddq +0.5 input clamp current . . . . . . . . . . . . . . . . . . . . . . . 50 ma output clamp current . . . . . . . . . . . . . . . . . . . . . 50ma continuous output current . . . . . . . . . . . . . . . . . 50ma vdd, vddq or gnd current/pin . . . . . . . . . . . . 100ma package thermal impedance 3 . . . . . . . . . . . . . . . . . . . . 55c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. notes: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this current will flow only whtn the output is in the high state level v 0 >v ddq . 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions parameter min typ max units v dd 2.3 2.5 2.7 v ddq 2.3 2.5 2.7 v ref 1.15 1.25 1.35 v tt v ref -0.04 v ref v ref -0.04 v i input voltage 0 v dd v ih dc input high voltage v ref +0.15 v ih ac input high voltage v ref +0.31 v il dc input low voltage v ref -0.15 v il ac input low voltage v ref -0.31 v ih input high voltage level 1.7 v il input low voltage level 0.7 v icr common mode input range 0.97 1.53 v id differential input voltage 0.36 v ix (v ddq /2) -0.2 (v ddq /2) +0.2 i oh -20 i ol 20 t a 070c 1 guarenteed b y desi g n, not 100% tested in p roduction. description supply voltage i/o supply voltage reference voltage v ref = 0.5x v ddq operating free-air temperature reset# clk, clk# v termination voltage cross point voltage of differential clock pair high-level output current low-level output current data inputs ma
4 icssstv16857c third party brands and names are the property of their respective owners. electrical characteristics - dc t a =0-70oc;v dd = 2.5 v +/-200mv, v ddq =2.5v 200mv; (unless otherwise stated) symbol parameters conditions vdd min typ max units v ik i i = -18ma 2.3v -1.2 i oh = -100a 2.3v-2.7 vdd -0.2 i oh = -16ma 2.3v 1.95 i ol = 100a 2.3-2.7v 0.2 v i ol = 16ma 2.3v 0.35 i i all inputs v i = v dd or gnd 2.7v 5 a standby (static) reset# = gnd 0.01 a i dd v i = v ih (ac#) or v il (ac) , operating (static) reset# = v dd 55 ma reset# = v dd , v i = v ih(ac) dynamic operating or v il (ac ) , ck and ck# clock only switching 50% duty cycle. 75 a/clock mhz reset# = v dd , v i = v ih(ac ) io = 0 2.7v i ddd or v il (ac ) , ck and ck# 15 a/ clock dynamic operating switching 50% duty cycle. mhz/data per each data input one data input switching at half clock frequency, 50% duty cycle r oh output high i oh = -20ma 2.3-2.7v 7 20 w r ol output low i ol = 20ma 2.3-2.7v 7 20 w [r oh - r ol ] each r o(d) separate bit i o = 20ma, t a = 25 c 2.5v 4 w data inputs v i = v ref 310mv 2.5 3.5 c i ck and ck# v ic r = 1.25v, v i(pp) = 360mv 2.5v 2.5 3.5 pf notes: 1 - guaranteed by design, not 100% tested in production. v oh v ol
5 icssstv16857c third party brands and names are the property of their respective owners. timing requirements (over recom mended operating free-air tem perature range, unless otherwise noted) symbol parameters vdd=2.50.2v units min typ max f clock clock frequency 133 200 mhz t pd clock to output time 1.6 2 2.6 ns t rst reset to output tim e 2.5 2.7 3.3 ns t sl output slew rate 1 1.5 4 v/ns setup time, fast slew rate 2, 4 data before ck ! ,ck# " 0.75 0.018 ns t su setup tim e, slow slew rate 3, 4 0.9 ns hold time, fast slew rate 2,4 data after ck ! ,ck# " 0.75 0.145 ns t h hold tim e, slow s lew rate 3 , 4 0.9 ns notes: 1 - guaranteed by design, not 100% tested in production. 2 - for data signal input slew rate ?1v/ns. 4 - clk, clk# signals input slew rates are ?1v/ns. 3 - for data signal input slew rate ?0.5v/ns and < 1v/ns. switching characteristics (over recom mended operating free-air tem perature range, unless otherwise noted) symbol from to vdd=2.50.2v units (input) (output) min typ max f clock 133 200 mhz t pd clk, clk# q 1.6 2 2.6 ns t ph1 reset q 2.5 2.7 3.3 ns
6 icssstv16857c third party brands and names are the property of their respective owners. notes: 1. cl incluces probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma. 3. all input pulses are supplied by generators having the following chareacteristics: prr 10 mhz, zo=50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v ddq /2 6. v ih = v ref + 310mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref -310mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. t plh and t phl are the same as t pd test point load circuit from output under test c = 30 pf (see note 1) l v tt r = l lvcmos reset# input lvcmos reset# input v/2 dd t inact t act i (see note 2) dd i ddh i ddl 10% 90% voltage and current waveforms inputs active and inactive times voltage waveforms - propagation delay times voltage waveforms - propagation delay times parameter measurement information (v = 2.5v 0.2v) dd voltage waveforms - pulse duration voltage waveforms - setup and hold times v/2 dd v dd 0v t w t su t h v ih v ih v oh v tt v tt v tt v oh v ih v il v il v ol v ol v i(pp) v i(pp) v il v ref v ref v ref v ref v icr v icr t phl t phl t phl v/2 dd v icr input input timing input timing input output output
7 icssstv16857c third party brands and names are the property of their respective owners. ordering information icssstv16857c y g-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type g=tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y g - ppp - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 v ariations min max min max 48 12.40 12.60 .488 .496 10-0039 symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
8 icssstv16857c third party brands and names are the property of their respective owners. index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.08 -- .003 variations min max min max 48 9.60 9.80 .378 .386 10-0037 symbol in millimeters in inches common dimensions common dimensions see variations see variations 6.40 basic 0.252 basic 0.40 basic 0.016 basic see variations see variations n dmm. d(inch) reference doc.: jedec publication 95, mo-153 4.40 mm. body, 0.40 mm. pitch tssop (173 mil) (16 mil) ordering information icssstv16857c y l-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type l=tssop (tvsop) revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y l - ppp - t ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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