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| preliminary fme-mb96340 rev 5 mb96340 specification fme/emdc- 2007-9-12mb96340_ds_cover.fm 16-bit proprietary microcontroller cmos f 2 mc-16fx mb96340 series description mb96340 series is based on fujitsu s advanced 16fx architecture (16-bit with instruction pipeline for risc-like performance). the cpu uses the same instruction set as the established 16lx series - thus allowing for easy migration of 16lx software to the new 16fx products. 16fx improvements compared to the previous generation include signi?antly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. for highest processing speed at optimized power consumption an internal pll can be selected to supply the cpu with up to 56mhz operation frequency from an external 4mhz resonator. the result is a minimum instruction cycle time of 17.8ns going together with excellent emi behavior. an on-chip clock modulation circuit signi?antly reduces emission peaks in the frequency spectrum. the emitted power is minimised by the on-chip voltage regulator that reduces the internal cpu voltage. a exible clock tree allows to select suitable operation frequencies for peripheral resources independent of the cpu speed.
mb96340 series speci?ation 2 fme/emdc- 2007-9-12 mb96340_ds_cover.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_features.fm 3 preliminary preliminary preliminary features feature description technology 0.18 m cmos cpu f2mc-16fx cpu up to 56 mhz internal, 17.8 ns instruction cycle time optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 8-byte instruction execution queue signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available system clock on-chip pll clock multiplier (x1..25, x1 when pll stop) 3-16 mhz external quartz clock, up to 4mhz external clock 32-100 khz subsystem quartz clock 100khz/2mhz internal rc clock for quick and save startup, oscillator stop detection, watchdog clock source selectable from main- and subclock oscillator (partnumber suffix ?? on-chip rc oscillator, independently for cpu and 2 clock domains of peripherals. low power consumption - 13 operating modes : (different run, sleep, timer modes, stop mode) clock modulator on-chip voltage regula- tor internal voltage regulator supports reduced internal mcu voltage, offering low emi and low power consumption figures low voltage reset reset is generated when supply voltage is below minimum. code security protects rom content from unintended read-out memory patch function replaces rom content can also be used to implement embedded debug support dma automatic transfer function independent of cpu, can be assigned freely to resources interrupts fast interrupt processing 8 programmable priority levels non-maskable interrupt (nmi) timers two independent clock timers (23-bit rc clock timer, 23-bit main clock timer, 17-bit sub clock timer) watchdog timer mb96340 series speci?ation 4 fme/emdc- 2007-9-12 mb96300_ds_features.fm preliminary can supports can protocol version 2.0 part a and b iso16845 certified bit rates up to 1 mbit/s 32 message objects each message object has its own identifier mask programmable fifo mode (concatenation of message objects) maskable interrupt disabled automatic retransmission mode for time triggered can applications programmable loop-back mode for self-test operation usart full duplex usarts (sci/lin) wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i2c up to 400 kbit/s master and slave functionality, 8-bit and 10-bit addressing a/d converter sar-type 10bit resolution signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer a/d converter refer- ence voltage switch 2 independant positive a/d converter reference voltages available reload timers 16-bit wide prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency event count function free running timers signals an interrupt on overflow, supports timer clear upon match with output compare (0, 4), prescaler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 ,1/2 8 of peripheral clock frequency input capture units 16-bit wide signals an interrupt upon external event rising edge, falling edge or rising & falling edge sensitive output compare units 16-bit wide signals an interrupt when a match with 16-bit i/o timer occurs a pair of compare registers can be used to generate an output signal. feature description speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_features.fm 5 preliminary preliminary preliminary programmable pulse generator 16-bit down counter, cycle and duty setting registers interrupt at trigger, counter borrow and/or duty match pwm operation and one-shot operation internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and reload timer overflow as clock input can be triggered by software or reload timer real time clock can be clocked either from sub oscillator (devices with partnumber suffix ??,main oscillator or from the rc oscillator facility to correct oscillation deviation of sub clock or rc oscillator clock (clock calibration) read/write accessible second/minute/hour registers can signal interrupts every halfsecond/second/minute/hour/day internal clock divider and prescaler provide exact 1s clock based on a 4 mhz or a 32 khz clock input (devices with partnumber suffix ?? clock input external interrupts edge sensitive or level sensitive interrupt mask and pending bit per channel each available can channel rx has an external interrupt for wake-up selected usart channels sin have an external interrupt for wake-up non maskable interrupt disabled after reset once enabled, can not be disabled other than by reset. level high or level low sensitive pin shared with external interrupt 0. external bus interface 8-bit or 16-bit bidirectional data up to 24-bit addresses 6 chip select signals multiplexed address/data lines wait state request external bus master possible timing programmable alarm comparators monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds threshold voltages defined externally or generated internally status is readable, interrupts can be masked separately feature description mb96340 series speci?ation 6 fme/emdc- 2007-9-12 mb96300_ds_features.fm preliminary i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs (except when used as i2c sda/scl line) bit-wise programmable as input/output or peripheral signal bit-wise programmable input enable bit-wise programmable input levels (automotive / cmos-schmitt trigger / ttl) bit-wise programmable pull-up resistor bit-wise programmable output driving strength for emi optimization package 100-pin plastic qfp and lqfp flash memory supports automatic programming, embedded algorithm tm*1 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10,000 times data retention time : 20 years erase can be performed on each sector individually sector protection flash security feature to protect the content of the flash low voltage detection during flash erase *1 : embedded algorithm is a trade mark of advanced micro devices inc. feature description speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_lineup.fm 7 preliminary preliminary preliminary product lineup features mb96v300 mb9634x product type evaluation sample flash product: mb96f34x mask rom product: mb9634x product options ys na lvd persistently on / single clock devices rs lvd can be disabled / single clock devices yw lvd persistently on / dual clock devices rw lvd can be disabled / dual clock devices ts satellite flash / lvd persistently on / single clock devices hs satellite flash / lvd can be disabled / single clock devices tw satellite flash / lvd persistently on / dual clock devices hw satellite flash / lvd can be disabled / dual clock devices as no can / no satellite flash / lvd persistently on / single clock devices cs no can / /satellite flash / lvd can be disabled / single clock devices aw no can / no satellite flash / lvd persistently on / dual clock devices cw no can / satellite flash / lvd can be disabled / dual clock devices flash/ rom ram 128kb 6kb rom/flash memory emulation by external ram, 92kb internal ram mb96344r, mb96344y 288kb 16kb mb96f346r, mb96346r, mb96f346y, mb96346y, mb96f346a 416kb 16kb mb96f347r, mb96347r, mb96f347y, mb96347y, mb96f347a 544kb 24kb mb96f348r, mb96f348y, mb96f348a main: 544kb, sat.: 32kb 24kb mb96f348c, mb96f348h, mb96f348t package bga416 fpt-100p-m20 fpt-100p-m22 dma 16 channels 6 channels usart 10 channels 7 channels mb96f348 tsa/hsa/twa/hwa: 4 channels i2c 2 channels 2 channel a/d converter 40 channels 24 channels mb96340 series speci?ation 8 fme/emdc- 2007-9-12 mb96340_ds_lineup.fm preliminary a/d converter reference voltage switch yes yes 16-bit reload timer 6 channels 4 channels 16-bit free- running timer 4 channels 2 channels 16-bit output compare 12 channels 8 channels 16-bit input capture 12 channels 8 channels 16-bit programmable pulse generator 20 channels 16 channels can interface (not available on mb963xxa, mb963xxc) 5 channels 2 channels external interrupts 16 channels non-maskable interrupt 1 channel real time clock 1 mb96f348tsa/hsa/twa/hwa: not available i/o ports 136 80 for part number with suf? "w", 82 for part number with suf? "s" alarm comparator 2 channels external bus interface ye s multiplexed chip select 6 signal clock output function 2 channels low voltage reset reset is generated when supply voltage is below minimum. on-chip rc- oscillator ye s features mb96v300 mb9634x speci?ation mb96340 fme/emdc- 2007-9-11 mb96340_ds_block_diagram.fm 9 preliminary preliminary preliminary block diagram satellite flash memory 1) i2c 2 ch. sda0 ... sda1 scl0 ... scl1 dma controller boot rom peripheral bus bridge peripheral bus bridge 16fx core bus (clkb) usart 7 ch. 10-bit adc 24 ch. alarm comparator 2 ch. 16-bit reload timer 4 ch. i/o timer 0 icu 0/1/2/3 ocu 0/1/2/3 16-bit ppg 16 ch. can interface 2 ch. external interrupt real time clock 2) clock output function 2 ch. watchdog ram voltage regulator sin0...sin3, sin7 2) ...sin9 2) sot0...sot3, sot7 2) ...sot9 2) sck0...sck3, sck7 2) ...sck9 2) alarm0 alarm1 wot ckot0, ckot1 ckotx0, ckotx1 avcc avss avrh avrl an0 ... an23 adtg tin0 ... tin3 tot0 ... tot3 frck0 in0 ... in3 out0 ... out3 int0 ... int15 tx0, tx1 rx0, rx1 peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) vcc vss c ppg0 ... ppg15 ttg0 ... ttg15 i/o timer 1 icu 4/5/6/7 ocu 4/5/6/7 frck1 in4 ... in7 out4 ... out7 16fx cpu interrupt controller clock & mode controller main flash memory memory patch unit x0, x1 x0a, x1a rstx ad00 ... ad15 a16 ... a23 ale rdx wrlx, wrhx hrq hakx rdy eclk external bus interface md0...md2 lbx, ubx cs0 ... cs5 nmi 1) available only on devices with suffix , ?? ??or suffix ? 2) not available on mb96f348 hsa/hwa/tsa/twa mb96340 series speci?ation 10 fme/emdc- 2007-9-11 mb96340_ds_block_diagram.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_pin_assignement.fm 11 preliminary preliminary preliminary pin assignments pin assignment (fpt-100p-m22) remark: mb96(f)34x products are pin-compatible to f 2 mc-16lx family mb90340 series. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 234 567 9 8 qfp - 100 package code (mold) fpt-100p-m22 (fpt-100p-m22) md1 md2 p00_0/ad00/int8/sck7_r 2) p10_1/tx0 p10_0/rx0/int8_r p09_7/out3/cs0 p09_6/out2/cs1 p09_5/out1/cs2 p09_4/out0/cs3 p09_3/ppg11/cs4 p09_2/ppg10/cs5 p09_1/ppg9/lbx p09_0/ppg8/ubx vss vcc p08_7/sck1 p08_6/sot1 p08_5/sin1/int1_r p08_4/sck0/int15_r p08_3/sot0/tot2 p08_2/sin0/tin2/int14_r p08_1/tot0/ckot0/int13_r p08_0/tin0/ckotx0/adtg/int12_r p07_7/an23/int7/sin9_r 2) p07_6/an22/int6/sot9_r 2) rstx md0 p00_1/ad01/int9/sot7_r 2) p00_2/ad02/int10/sin7_r 2) p00_3/ad03/int11/sck8_r 2) p00_4/ad04/int12/sot8_r 2) p00_5/ad05/int13/sin8_r 2) p00_6/ad06/int14 p00_7/ad07/int15 p01_0/ad08/ckot1/tin1 p01_1/ad09/ckotx1/tot1 p01_2/ad10/int11_r/sin3 p01_3/ad11/sot3 p01_4/ad12/sck3 p01_5/ad13/int7_r/sin2_r p01_6/ad14/sot2_r p01_7/ad15/sck2_r p02_0/a16/ppg12 p02_1/a17/ppg13 p02_2/a18/ppg14 p02_3/a19/ppg15 vcc vss x1 x0 p02_4/a20/ttg8/ttg0/in0 p02_6/a22/in2/ttg2/ttg10 p02_7/a23/in3/ttg3/ttg11 p03_0/ale/in4/ttg4/ttg12 p03_1/rdx/in5/ttg5/ttg13 p03_2/wrlx/wrx/int10_r p03_3/wrhx p03_4/hrq/out4 p03_5/hakx/out5 p03_6/rdy/out6 p03_7/eclk/out7 x0a 1) /p04_0 1) x1a 1) /p04_1 1) vcc vss c p04_2/in6/rx1/int9_r/ttg6/ttg14 p04_3/in7/tx1/ttg7/ttg15 p04_4/sda0/frck0 p04_5/scl0/frck1 p04_6/sda1 p04_7/scl1 p05_1/an9/alarm1/sot2 p05_2/an10/sck2 p05_3/an11/tin3/wot 2) p07_5/an21/int5/sck9_r 2) p07_4/an20/int4 p07_3/an19/int3 p07_2/an18/int2 p07_1/an17/int1 p07_0/an16/int0/nmi vss p06_7/an7/ppg7 p06_6/an6/ppg6 p06_5/an5/ppg5 p06_4/an4/ppg4 p06_3/an3/ppg3 p06_2/an2/ppg2 p06_1/an1/ppg1 p06_0/an0/ppg0 avss avrl avrh avcc p02_5/a21/ttg9/ttg1/in1/adtg_r p05_7/an15/int5_r p05_6/an14/int4_r p05_5/an13/int0_r/nmi_r p05_4/an12/tot3/int2_r p05_0/an8/alarm0/sin2/int3_r1 devices with suf? w: x0a/x1a devices with suf? s: p04_0, p04_1 1) 2) sin7_r, sot7_r, sck7_r, sin8_r, sot8_r, sck8_r, sin9_r, sot9_r, sck9_r not available on mb96f348tsb/hsb/twb/hwb mb96340 series speci?ation 12 fme/emdc- 2007-9-12 mb96340_ds_pin_assignement.fm preliminary pin assignment (fpt-100p-m20) remark: mb96(f)34x products are pin-compatible to f 2 mc-16lx family mb90340 series. 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 12 345 7 6 99 100 28 27 26 49 50 78 77 76 lqfp - 100 package code (mold) fpt-100p-m20 (fpt-100p-m20) p00_1ad01/int9/sot7_r 2) p00_2/ad02/int10/sin7_r 2) p00_3/ad03/int11/sck8_r 2) p00_4/ad04/int12/sot8_r 2) p00_5/ad05/int13/sin8_r 2) p00_6/ad06/int14 p00_7/ad07/int15 p01_0/ad08/ckot1/tin1 p01_1/ad09/ckotx1/tot1 p01_2/ad10/int11_r/sin3 p01_3/ad11/sot3 p01_4/ad12/sck3 p01_5/ad13/int7_r/sin2_r p01_6/ad14/sot2_r p01_7/ad15/sck2_r p02_0/a16/ppg12 p02_1/a17/ppg13 p02_2/a18/ppg14 p02_3/a19/ppg15 p02_4/a20/ttg8/ttg0/in0 p02_5/a21/ttg9/ttg1/in1/adtg_r vcc vss x1 x0 md1 md2 p07_5/an21/int5/sck9_r 2) p07_4/an20/int4 p07_3/an19/int3 p07_2/an18/int2 p07_1/an17/int1 p07_0/an16/int0/nmi vss p06_7/an7/ppg7 p06_6/an6/ppg6 p06_5/an5/ppg5 p06_4/an4/ppg4 p06_3/an3/ppg3 p06_2/an2/ppg2 p06_1/an1/ppg1 p06_0/an0/ppg0 avss avrl avrh avcc p05_7/an15/int5_r p05_6/an14/int4_r p05_5/an13/int0_r/nmi_r p05_4/an12/tot3/int2_r p00_0/ad00/int8/sck7_r 2) p10_1/tx0 p10_0/rx0/int8_r p09_7/out3/cs0 p09_6/out2/cs1 p09_5/out1/cs2 p09_4/out0/cs3 p09_3/ppg11/cs4 p09_2/ppg10/cs5 p09_1/ppg9/lbx p09_0/ppg8/ubx vss vcc p08_7/sck1 p08_6/sot1 p08_5/sin1/int1_r p08_4/sck0/int15_r p08_3/sot0/tot2 p08_2/sin0/tin2/int14_r p08_1/tot0/ckot0/int13_r p08_0/tin0/ckotx0/adtg/int12_r p07_7/an23/int7/ain3/sin9_r 2) p07_6/an22/int6/ain2/sot9_r 2) rstx md0 p02_6/a22/in2/ttg2/ttg10 p02_7/a23/in3/ttg3/ttg11 p03_0/ale/in4/ttg4/ttg12 p03_1/rdx/in5/ttg5/ttg13 p03_2/wrlx/wrx/int10_r p03_3/wrhx p03_4/hrq/out4 p03_5/hakx/out5 p03_6/rdy/out6 p03_7/eclk/out7 x0a 1) /p04_0 1) x1a 1) /p04_1 1) vcc vss c p04_2/in6/rx1/int9_r/ttg6/ttg14 p04_3/in7/tx1/ttg7/ttg15 p04_4/sda0/frck0 p04_5/scl0/frck1 p04_6/sda1 p04_7/scl1 p05_0/an8/alarm0/sin2/int3_r1 p05_1/an9/alarm1/sot2 p05_2/an10/sck2 p05_3/an11/tin3/wot 2) devices with suf? w: x0a/x1a devices with suf? s: p04_0, p04_1 1) 2) sin7_r, sot7_r, sck7_r, sin8_r, sot8_r, sck8_r, sin9_r, sot9_r, sck9_r not available on mb96f348tsb/hsb/twb/hwb speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_pin_circuit_type.fm 13 preliminary preliminary preliminary pin circuit type fpt-100p-m20 fpt-100p-m22 pin no. circuit type pin no. circuit type 1-10 h 1-12 h 11,12 b 1) 13, 14 b 1) 11,12 h 2) 13, 14 h 2) 13,14 supply 15,16 supply 15 c-pin 17 c-pin 16,17 h 18,19 h 18-21 n 20-23 n 22-29 i 24-31 i 30 f 32 f 31 g 33 g 32-33 f 34-35 f 34 to 41 i 36 to 43 i 42 supply 44 supply 43 to 48 i 45 to 50 i 49 to 51 c 51 to 53 c 52 e 54 e 53 to 54 i 55 to 56 i 55 to 62 h 57 to 64 h 63, 64 supply 65, 66 supply 65 to 87 h 67 to 89 h 88,89 supply 90, 91 supply 90, 91 a 92, 93 a 92-100 h 94 to 100 h 1) devices with suf?x w 2) devices without suf?x w mb96340 series speci?ation 14 fme/emdc- 2007-9-12 mb96340_ds_pin_circuit_type.fm preliminary i/o circuit type type circuit remarks a oscillation circuit high-speed oscillation feedback resistor = approx. 1 m ? b oscillation circuit low-speed oscillation feedback resistor = approx. 10 m ? c mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin e cmos hysteresis input pin pull-up resistor value: approx. 50 k ? f power supply input protection circuit x1 x0 xout standby control signal x1a x0a xout standby control signal r hysteresis inputs r pull-up resistor hysteresis inputs speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_pin_circuit_type.fm 15 preliminary preliminary preliminary g a/d converter ref+ (avrh) power supply input pin, with the protection circuit flash devices do not have a protection circuit against vcc for pin avrh h cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up registor:50k ? approx. type circuit remarks ane avr ane pout pull-up control nout r hysteresis input automotive inputs ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown mb96340 series speci?ation 16 fme/emdc- 2007-9-12 mb96340_ds_pin_circuit_type.fm preliminary i cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function) ttl input with input shutdown function programmable pull-up registor: 50k ? approx. analogue input n cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up registor:50k ? approx. type circuit remarks pout pull-up control nout r hysteresis input automotive inputs ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown analog input pout pull-up control nout r hysteresis input automotive inputs ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_pin_function_desc.fm 17 preliminary preliminary preliminary pin function description pin function description (1 / 2) pin name feature description adn external bus external bus interface (multiplexed mode) address/data input/ output adtg adc a/d converter trigger input adtg_r adc relocated a/d converter trigger input alarmn alarm comparator alarm comparator n input ale external bus external bus address latch enable output ann adc a/d converter channel n input avcc supply analogue circuits power supply avrh adc a/d converter high reference voltage input avrl adc a/d converter low reference voltage input avss supply analogue circuits power supply c voltage regulator internally regulated power supply stabilization capacitor pin. ckotn clock output function clock output function n output ckotxn clock output function clock output function n inverted output eclk external bus external bus clock output csn external bus external bus chip select n output frckn free running timer free running timer n input hakx external bus external bus hold acknowlegde hrq external bus external bus hold request inn icu input capture unit n input intn external interrupt external interrupt n input intn_r external interrupt relocated external interrupt n input lbx external bus external bus interface lower byte select strobe output mdn core input pins for specifying the operating mode. nmi external interrupt non-maskable interrupt input nmi_r external interrupt relocated non-maskable interrupt input outn ocu output compare unit n waveform output ppgn ppg programmable pulse generator n output ppgn_r ppg relocated programmable pulse generator n output mb96340 series speci?ation 18 fme/emdc- 2007-9-12 mb96300_ds_pin_function_desc.fm preliminary rdx external bus external bus interface read strobe output rdy external bus external bus interface external wait state request input rstx core reset input rxn can can interface n rx input sckn usart usart n serial clock input/output sckn_r usart relocated usart n serial clock input/output scln i2c i2c interface n clock i/o input/output sdan i2c i2c interface n serial data i/o input/output sinn usart usart n serial data input sinn_r usart relocated usart n serial data input sotn usart usart n serial data output sotn_r usart relocated usart n serial data output tinn reload timer reload timer n event input totn reload timer reload timer n output ttgn ppg programmable pulse generator n trigger input ttgn_r ppg relocated programmable pulse generator n trigger input txn can can interface n tx output ubx external bus external bus interface upper byte select strobe output vcc supply power supply vss supply power supply wot rtc real timer clock output wrhx external bus external bus high byte write strobe output wrlx external bus external bus low byte write strobe output x0 clock oscillator input x0a clock "subclock oscillator input (only for devices with suf?x ""w"")" x1 clock oscillator output x1a clock "subclock oscillator output (only for devices with suf?x ""w"")" pin function description (2 / 2) pin name feature description speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 19 preliminary preliminary preliminary memory map internal ram peripheral ext. bus dma gpr* peripheral ext. bus internal rom/ram -mirror internal ram ram external ram dsu area external bus emulation rom mb96v300 00.0000 00.00f0 00.0100 00.0180 00.0380 00.0c00 00.1200 00.8000 01.0000 02.0000 0e.0000 0f.0000 10.0000 de.0000 ff.ffff peripheral ext. bus dma gpr* peripheral ext. bus rom/ram -mirror internal ram external bus user rom mb96(f)34x the external bus area dma area are only available if the device contains the corresponding resource. satellite flash small sectors df.0000 boot-rom 0f.e000 start address of user rom area and (available on devices with suf x t , h , c ) the available ram and rom area depends on the device con guration. main flash number of small sector depends on the device * unused gpr banks can be used as ram area. ramstart** ** please refer to the table ramstart for different ram sizes on the next page sat rcb *** main rcb *** *** rom con guration block (rcb) must not be used for other purposes than described in the manual df.007f de.0000 de.002f ram availability and mapping depending on device not used for current available devices ext. bus ramstart** external bus end address ** reserved mb96340 series speci?ation 20 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary ramstart and external bus end address for different ram sizes devices ram size ramstart end address of exter- nal bus area mb96344 6 kb 6a40 69ff mb96(f)346, mb96(f)347 16 kb 4240 41ff mb96f348 24 kb 2240 21ff speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 21 preliminary preliminary preliminary flash sector configuration ff:ffffh ff:0000h fe:ffffh fe:0000h fd:ffffh fd:0000h fc:ffffh fc:0000h fb:ffffh fb:0000h fa:ffffh fa:0000h f9:ffffh f9:0000h f8:ffffh f8:0000h f7:ffffh f7:0000h e0:ffffh e0:0000h df:ffffh df:e000h df:dfffh df:c000h df:bfffh df:a000h df:9fffh df:8000h df:7fffh df:6000h df:5fffh df:4000h df:3fffh df:2000h df:1fffh df:0000h de:ffffh de:e000h de:dfffh de:c000h de:bfffh de:a000h de:9fffh de:8000h de:7fffh de:6000h de:5fffh de:4000h de:3fffh de:2000h de:1fffh de:0000h alternative mode 3f:ffffh 3f:0000h 3e:ffffh 3e:0000h 3d:ffffh 3d:0000h 3c:ffffh 3c:0000h 3b:ffffh 3b:0000h 3a:ffffh 3a:0000h 39:ffffh 39:0000h 38:ffffh 38:0000h 37:ffffh 37:0000h 20:ffffh 20:0000h 1f:ffffh 1f:e000h 1f:dfffh 1f:c000h 1f:bfffh 1f:a000h 1f:9fffh 1f:8000h 1f:7fffh 1f:6000h 1f:5fffh 1f:4000h 1f:3fffh 1f:2000h 1f:1fffh 1f:0000h 1e:ffffh 1e:e000h 1e:dfffh 1e:c000h 1e:bfffh 1e:a000h 1e:9fffh 1e:8000h 1e:7fffh 1e:6000h 1e:5fffh 1e:4000h 1e:3fffh 1e:2000h 1e:1fffh 1e:0000h flash memory mode address sa0 - 8k sa1 - 8k sa2 - 8k sa3 - 8k sa36 - 64k sa37 - 64k sa38 - 64k sa39 - 64k main flash size 288kbyte sa0 - 8k sa1 - 8k sa2 - 8k sa3 - 8k sa32 - 64k sa33 - 64k sa34 - 64k sa35 - 64k sa36 - 64k sa37 - 64k sa38 - 64k sa39 - 64k main flash size 544kbyte sb0 - 8k sb1 - 8k sb2 - 8k sb3 - 8k sa0 - 8k sa1 - 8k sa2 - 8k sa3 - 8k sa32 - 64k sa33 - 64k sa34 - 64k sa35 - 64k sa36 - 64k sa37 - 64k sa38 - 64k sa39 - 64k main flash size 544kbyte satellite flash size 32kbyte cpu address . . . . . . . . . . . . . . . . . . . . sa0 - 8k sa1 - 8k sa2 - 8k sa3 - 8k sa34 - 64k sa35 - 64k sa36 - 64k sa37 - 64k sa38 - 64k sa39 - 64k main flash size 416kbyte . . . . mb96f346y mb96f347y mb96f348y mb96f348r mb96f348c mb96f348h mb96f348t mb96f347r mb96f346r mb96f346a mb96f347a mb96f348a mb96340 series speci?ation 22 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary parallel programming flash memory control signals flash memory control signals (md[2:0] = 111) mb96f34x mbm29lv200 pin number normal function flash memory mode lqfp qfp 3 5 p03_0 aq16 a15 4 6 p03_1 ce ce 5 7 p03_2 oe oe 6 8 p03_3 we we 7 9 p03_4 aq17 a16 8 10 p03_5 aq18 9 11 p03_6 byte byte 10 12 p03_7 ry/ by ry/ by 16 to 19 18 to 21 p04_2 to p04_5 aq8 to aq11 a7 to a10 20 to 21 22 to 23 p04_6 to p04_7 aq12 to aq13 a11 to a12 22 to 23 24 to 25 p05_0 to p05_1 aq14 to aq15 a13 to a14 27 to 29 29 to 31 p05_5 to p05_7 aq19 to aq21 49 51 md2 md2 oe 50 52 md1 md1 reset 51 53 md0 mdo a9 52 54 rst reset reset 75 to 82 77 to 84 p00_0 to p00_7 dq0 to dq7 dq0 to dq7 83 to 86 85 to 88 p01_0 to p01_3 dq8 to dq11 dq8 to dq11 87, 92 to 94 89, 94 to 96 p01_4 to p01_7 dq12 to dq15 dq12 to dq15 99 to 2, 95 to 98 1 to 4, 97 to 100 p02_0 to p02_7 aq0 to aq7 a-1, a0 to a6 speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 23 preliminary preliminary preliminary serial programming communication interface note: for handshaking pin, please use for this device the default pin p00_1. if any other pin is required, please contact the flash programmer device vendor. usart pins for flash serial programming (md[2:0] = 010) mb96f34x pin number pin number usart number normal function lqfp-100 qfp-100 57 59 usart0 sin0 58 60 sot0 59 61 sck0 60 62 usart1 sin1 61 63 sot1 62 64 sck1 22 24 usart2 sin2 23 25 sot2 24 26 sck2 92 94 usart2 sin2_r 93 95 sot2_r 94 96 sck2_r 85 87 usart3 sin3 86 88 sot3 87 89 sck3 77 79 usart7 sin7_r 76 78 sot7_r 75 77 sck7_r 80 82 usart8 sin8_r 79 81 sot8_r 78 80 sck8_r 54 56 usart9 sin9_r 53 55 sot9_r 48 50 sck9_r mb96340 series speci?ation 24 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary i/o map i/o map (1 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess 000000h p00 - i/o port port data register pdr00 rw 000001h p01 - i/o port port data register pdr01 rw 000002h p02 - i/o port port data register pdr02 rw 000003h p03 - i/o port port data register pdr03 rw 000004h p04 - i/o port port data register pdr04 rw 000005h p05 - i/o port port data register pdr05 rw 000006h p06 - i/o port port data register pdr06 rw 000007h p07 - i/o port port data register pdr07 rw 000008h p08 - i/o port port data register pdr08 rw 000009h p09 - i/o port port data register pdr09 rw 00000ah p10 - i/o port port data register pdr10 rw 00000bh - 000017h reserved 000018h adc - control status register 0 low adcsl adcs rw 000019h adc - control status register 0 high adcsh rw 00001ah adc - data register 0 low adcrl adcr r 00001bh adc - data register 0 high adcrh r 00001ch adc - setting register low 0 adsr rw 00001dh adc - setting register high 0 00001eh adc - extended con?guration register adecr rw 000020h frt0 - data register of free-running timer tcdt0 rw 000021h frt0 - data register of free-running timer rw 000022h frt0 - control status register of free- running timer tccsl0 tccs0 rw 000023h frt0 - control status register of free- running timer tccsh0 rw 000024h frt1 - data register of free-running timer tcdt1 rw speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 25 preliminary preliminary preliminary 000025h frt1 - data register of free-running timer rw 000026h frt1 - control status register of free- running timer tccsl1 tccs1 rw 000027h frt1 - control status register of free- running timer tccsh1 rw 000028h ocu0 - output compare control status ocs0 rw 000029h ocu1 - output compare control status ocs1 rw 00002ah ocu0 - compare register occp0 rw 00002bh ocu0 - compare register rw 00002ch ocu1 - compare register occp1 rw 00002dh ocu1 - compare register rw 00002eh ocu2 - output compare control status ocs2 rw 00002fh ocu3 - output compare control status ocs3 rw 000030h ocu2 - compare register occp2 rw 000031h ocu2 - compare register rw 000032h ocu3 - compare register occp3 rw 000033h ocu3 - compare register rw 000034h ocu4 - output compare control status ocs4 rw 000035h ocu5 - output compare control status ocs5 rw 000036h ocu4 - compare register occp4 rw 000037h ocu4 - compare register rw 000038h ocu5 - compare register occp5 rw 000039h ocu5 - compare register rw 00003ah ocu6 - output compare control status ocs6 rw 00003bh ocu7 - output compare control status ocs7 rw i/o map (2 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 26 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 00003ch ocu6 - compare register occp6 rw 00003dh ocu6 - compare register rw 00003eh ocu7 - compare register occp7 rw 00003fh ocu7 - compare register rw 000040h icu0/icu1 - control status register ics01 rw 000041h icu0/icu1 - edge register ice01 rw 000042h icu0 - capture register ipcpl0 ipcp0 r 000043h icu0 - capture register ipcph0 r 000044h icu1 - capture register ipcpl1 ipcp1 r 000045h icu1 - capture register ipcph1 r 000046h icu2/icu3 - control status register ics23 rw 000047h icu2/3 - edge register ice23 rw 000048h icu2 - capture register ipcpl2 ipcp2 r 000049h icu2 - capture register ipcph2 r 00004ah icu3 - capture register ipcpl3 ipcp3 r 00004bh icu3 - capture register ipcph3 r 00004ch icu4/icu5 - control status register ics45 rw 00004dh icu4/icu5 - edge register ice45 rw 00004eh icu4 - capture register ipcpl4 ipcp4 r 00004fh icu4 - capture register ipcph4 r 000050h icu5 - capture register ipcpl5 ipcp5 r 000051h icu5 - capture register ipcph5 r 000052h icu6/icu7 - control status register ics67 rw 000053h icu6/icu7 - edge register ice67 rw 000054h icu6 - capture register ipcpl6 ipcp6 r 000055h icu6 - capture register ipcph6 r 000056h icu7 - capture register ipcpl7 ipcp7 r 000057h icu7 - capture register ipcph7 r 000058h extint0 - external interrupt enable register enir0 rw i/o map (3 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 27 preliminary preliminary preliminary 000059h extint0 - external interrupt interrupt request register eirr0 rw 00005ah extint0 - external interrupt level select elvrl0 elvr0 rw 00005bh extint0 - external interrupt level select elvrh0 rw 00005ch extint1 - external interrupt enable register enir1 rw 00005dh extint1 - external interrupt interrupt request register eirr1 rw 00005eh extint1 - external interrupt level select elvrl1 elvr1 rw 00005fh extint1 - external interrupt level select elvrh1 rw 000060h rlt0 - timer control status register low tmcsrl0 tmcsr0 rw 000061h rlt0 - timer control status register high tmcsrh0 rw 000062h rlt0 - reload register low tmrlr0 tmr0 rw 000063h rlt0 - reload register high tmrhr0 rw 000064h rlt1 - timer control status register low tmcsrl1 tmcsr1 rw 000065h rlt1 - timer control status register high tmcsrh1 rw 000066h rlt1 - reload register low tmrlr1 tmr1 rw 000067h rlt1 - reload register high tmrhr1 rw 000068h rlt2 - timer control status register low tmcsrl2 tmcsr2 rw 000069h rlt2 - timer control status register high tmcsrh2 rw 00006ah rlt2 - reload register low tmrlr2 tmr2 rw 00006bh rlt2 - reload register high tmrhr2 rw 00006ch rlt3 - timer control status register low tmcsrl3 tmcsr3 rw 00006dh rlt3 - timer control status register high tmcsrh3 rw i/o map (4 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 28 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 00006eh rlt3 - reload register low tmrlr3 tmr3 rw 00006fh rlt3 - reload register high tmrhr3 rw 000070h rlt6 - timer control status register low (dedic. rlt for ppg) tmcsrl6 tmcsr6 rw 000071h rlt6 - timer control status register high (dedic. rlt for ppg) tmcsrh6 rw 000072h rlt6 - reload register low (dedic. rlt for ppg) - for writing tmrlr6 rw 000072h rlt6 - reload register low (dedic. rlt for ppg) - for reading tmr6 rw 000073h rlt6 - reload register high (dedic. rlt for ppg) - for writing rw 000073h rlt6 - reload register high (dedic. rlt for ppg) - for reading rw 000074h ppg3-ppg0 - general control register 1 low gcn1l0 gcn10 rw 000075h ppg3-ppg0 - general control register 1 high gcn1h0 rw 000076h ppg3-ppg0 - general control register 2 low gcn2l0 gcn20 rw 000077h ppg3-ppg0 - general control register 2 high gcn2h0 rw 000078h ppg0 - timer register ptmr0 r 000079h ppg0 - timer register r 00007ah ppg0 - period setting register pcsr0 w 00007bh ppg0 - period setting register w 00007ch ppg0 - duty cycle register pdut0 w 00007dh ppg0 - duty cycle register w 00007eh ppg0 - control status register pcnl0 pcn0 rw 00007fh ppg0 - control status register pcnh0 rw 000080h ppg1 - timer register ptmr1 r 000081h ppg1 - timer register r 000082h ppg1 - period setting register pcsr1 w 000083h ppg1 - period setting register w i/o map (5 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 29 preliminary preliminary preliminary 000084h ppg1 - duty cycle register pdut1 w 000085h ppg1 - duty cycle register w 000086h ppg1 - control status register pcnl1 pcn1 rw 000087h ppg1 - control status register pcnh1 rw 000088h ppg2 - timer register ptmr2 r 000089h ppg2 - timer register r 00008ah ppg2 - period setting register pcsr2 w 00008bh ppg2 - period setting register w 00008ch ppg2 - duty cycle register pdut2 w 00008dh ppg2 - duty cycle register w 00008eh ppg2 - control status register pcnl2 pcn2 rw 00008fh ppg2 - control status register pcnh2 rw 000090h ppg3 - timer register ptmr3 r 000091h ppg3 - timer register r 000092h ppg3 - period setting register pcsr3 w 000093h ppg3 - period setting register w 000094h ppg3 - duty cycle register pdut3 w 000095h ppg3 - duty cycle register w 000096h ppg3 - control status register pcnl3 pcn3 rw 000097h ppg3 - control status register pcnh3 rw 000098h ppg7-ppg4 - general control register 1 low gcn1l1 gcn11 rw 000099h ppg7-ppg4 - general control register 1 high gcn1h1 rw 00009ah ppg7-ppg4 - general control register 2 low gcn2l1 gcn21 rw 00009bh ppg7-ppg4 - general control register 2 high gcn2h1 rw 00009ch ppg4 - timer register ptmr4 r 00009dh ppg4 - timer register r 00009eh ppg4 - period setting register pcsr4 w i/o map (6 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 30 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 00009fh ppg4 - period setting register w 0000a0h ppg4 - duty cycle register pdut4 w 0000a1h ppg4 - duty cycle register w 0000a2h ppg4 - control status register pcnl4 pcn4 rw 0000a3h ppg4 - control status register pcnh4 rw 0000a4h ppg5 - timer register ptmr5 r 0000a5h ppg5 - timer register r 0000a6h ppg5 - period setting register pcsr5 w 0000a7h ppg5 - period setting register w 0000a8h ppg5 - duty cycle register pdut5 w 0000a9h ppg5 - duty cycle register w 0000aah ppg5 - control status register pcnl5 pcn5 rw 0000abh ppg5 - control status register pcnh5 rw 0000ach i2c0 - bus status register ibsr0 r 0000adh i2c0 - bus control register ibcr0 rw 0000aeh i2c0 - ten bit slave address register low itbal0 itba0 rw 0000afh i2c0 - ten bit slave address register high itbah0 rw 0000b0h i2c0 - ten bit address mask register low itmkl0 itmk0 rw 0000b1h i2c0 - ten bit address mask register high itmkh0 rw 0000b2h i2c0 - seven bit slave address register isba0 rw 0000b3h i2c0 - seven bit address mask register ismk0 rw 0000b4h i2c0 - data register idar0 rw 0000b5h i2c0 - clock control register iccr0 rw 0000b6h i2c1 - bus status register ibsr1 r 0000b7h i2c1 - bus control register ibcr1 rw 0000b8h i2c1 - ten bit slave address register low itbal1 itba1 rw i/o map (7 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 31 preliminary preliminary preliminary 0000b9h i2c1 - ten bit slave address register high itbah1 rw 0000bah i2c1 - ten bit address mask register low itmkl1 itmk1 rw 0000bbh i2c1 - ten bit address mask register high itmkh1 rw 0000bch i2c1 - seven bit slave address register isba1 rw 0000bdh i2c1 - seven bit address mask register ismk1 rw 0000beh i2c1 - data register idar1 rw 0000bfh i2c1 - clock control register iccr1 rw 0000c0h usart0 usart - serial mode register smr0 rw 0000c1h usart0 - serial control register scr0 rw 0000c2h usart0 - tx register tdr0 w 0000c2h usart0 - rx register rdr0 r 0000c3h usart0 - serial status ssr0 rw 0000c4h usart0 - control/com. register eccr0 rw 0000c5h usart0 - ext. status register escr0 rw 0000c6h usart0 - baud rate generator register low bgrl0 bgr0 rw 0000c7h usart0 - baud rate generator register high bgrh0 rw 0000c8h usart0 - extended serial interrupt register esir0 rw 0000c9h reserved 0000cah usart1 - serial mode register smr1 rw 0000cbh usart1 - serial control register scr1 rw 0000cch usart1 - tx register tdr1 w 0000cch usart1 - rx register rdr1 r 0000cdh usart1 - serial status ssr1 rw 0000ceh usart1 - control/com. register eccr1 rw i/o map (8 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 32 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 0000cfh usart1 - ext. status register escr1 rw 0000d0h usart1 - baud rate generator register low bgrl1 bgr1 rw 0000d1h usart1 - baud rate generator register high bgrh1 rw 0000d2h usart1 - extended serial interrupt register esir1 rw 0000d3h reserved 0000d4h usart2 - serial mode register smr2 rw 0000d5h usart2 - serial control register scr2 rw 0000d6h usart2 - tx register tdr2 w 0000d6h usart2 - rx register rdr2 r 0000d7h usart2 - serial status ssr2 rw 0000d8h usart2 - control/com. register eccr2 rw 0000d9h usart2 - ext. status register escr2 rw 0000dah usart2 - baud rate generator register low bgrl2 bgr2 rw 0000dbh usart2 - baud rate generator register high bgrh2 rw 0000dch usart2 - extended serial interrupt register esir2 rw 0000ddh reserved 0000deh usart3 - serial mode register smr3 rw 0000dfh usart3 - serial control register scr3 rw 0000e0h usart3 - tx register tdr3 w 0000e0h usart3 - rx register rdr3 r 0000e1h usart3 - serial status ssr3 rw 0000e2h usart3 - control/com. register eccr3 rw 0000e3h usart3 - ext. status register escr3 rw 0000e4h usart3 - baud rate generator register low bgrl3 bgr3 rw 0000e5h usart3 - baud rate generator register high bgrh3 rw i/o map (9 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 33 preliminary preliminary preliminary 0000e6h usart3 - extended serial interrupt register esir3 rw 0000f0h external bus extbus0 rw 000100h dma0 -buffer address pointer low byte bapl0 rw 000101h dma0 - buffer address pointer middle byte bapm0 rw 000102h dma0 - buffer address pointer high byte baph0 rw 000103h dma0 - dma control register dmacs0 rw 000104h dma0 - i/o register address pointer low byte ioal0 ioa0 rw 000105h dma0 - i/o register address pointer high byte ioah0 rw 000106h dma0 - data counter low byte dctl0 dct0 rw 000107h dma0 - data counter high byte dcth0 rw 000108h dma1 -buffer address pointer low byte bapl1 rw 000109h dma1 - buffer address pointer middle byte bapm1 rw 00010ah dma1 - buffer address pointer high byte baph1 rw 00010bh dma1 - dma control register dmacs1 rw 00010ch dma1 - i/o register address pointer low byte ioal1 ioa1 rw 00010dh dma1 - i/o register address pointer high byte ioah1 rw 00010eh dma1 - data counter low byte dctl1 dct1 rw 00010fh dma1 - data counter high byte dcth1 rw 000110h dma2 -buffer address pointer low byte bapl2 rw 000111h dma2 - buffer address pointer middle byte bapm2 rw 000112h dma2 - buffer address pointer high byte baph2 rw 000113h dma2 - dma control register dmacs2 rw 000114h dma2 - i/o register address pointer low byte ioal2 ioa2 rw i/o map (10 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 34 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 000115h dma2 - i/o register address pointer high byte ioah2 rw 000116h dma2 - data counter low byte dctl2 dct2 rw 000117h dma2 - data counter high byte dcth2 rw 000118h dma3 -buffer address pointer low byte bapl3 rw 000119h dma3 - buffer address pointer middle byte bapm3 rw 00011ah dma3 - buffer address pointer high byte baph3 rw 00011bh dma3 - dma control register dmacs3 rw 00011ch dma3 - i/o register address pointer low byte ioal3 ioa3 rw 00011dh dma3 - i/o register address pointer high byte ioah3 rw 00011eh dma3 - data counter low byte dctl3 dct3 rw 00011fh dma3 - data counter high byte dcth3 rw 000120h dma4 -buffer address pointer low byte bapl4 rw 000121h dma4 - buffer address pointer middle byte bapm4 rw 000122h dma4 - buffer address pointer high byte baph4 rw 000123h dma4 - dma control register dmacs4 rw 000124h dma4 - i/o register address pointer low byte ioal4 ioa4 rw 000125h dma4 - i/o register address pointer high byte ioah4 rw 000126h dma4 - data counter low byte dctl4 dct4 rw 000127h dma4 - data counter high byte dcth4 rw 000128h dma5 -buffer address pointer low byte bapl5 rw 000129h dma5 - buffer address pointer middle byte bapm5 rw 00012ah dma5 - buffer address pointer high byte baph5 rw 00012bh dma5 - dma control register dmacs5 rw i/o map (11 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 35 preliminary preliminary preliminary 00012ch dma5 - i/o register address pointer low byte ioal5 ioa5 rw 00012dh dma5 - i/o register address pointer high byte ioah5 rw 00012eh dma5 - data counter low byte dctl5 dct5 rw 00012fh dma5 - data counter high byte dcth5 rw 000180h cpu - general purpose registers (ram access) gpr_ram rw 000380h dma0 - interrupt select disel0 rw 000381h dma1 - interrupt select disel1 rw 000382h dma2 - interrupt select disel2 rw 000383h dma3 - interrupt select disel3 rw 000384h dma4 - interrupt select disel4 rw 000385h dma5 - interrupt select disel5 rw 000386h - 00038fh reserved 000390h dma7-dma0 - status register dsrl dsr rw 000391h reserved 000392h dma7-dma0 - stop status register dssrl dssr rw 000393h reserved 000394h dma7-dma0 - enable register derl der rw 000395h - 000398h reserved 000399h unused 0003a0h interrupt level register ilr icr rw 0003a1h interrupt index register idx rw 0003a2h interrupt vector table base register tbrl tbr rw 0003a3h interrupt vector table base register tbrh rw 0003a4h delayed interrupt register dirr rw 0003a5h non maskable interrupt register nmi rw i/o map (12 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 36 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 0003a6h - 0003adh reserved 0003aeh rom mirror control register romm rw 0003afh edsu con?guration register edsu rw 0003b0h memory patch control/status register ch 0/1 pfcs0 rw 0003b1h memory patch control/status register ch 0/1 rw 0003b2h memory patch control/status register ch 2/3 pfcs1 rw 0003b3h memory patch control/status register ch 2/3 rw 0003b4h memory patch control/status register ch 4/5 pfcs2 rw 0003b5h memory patch control/status register ch 4/5 rw 0003b6h memory patch control/status register ch 6/7 pfcs3 rw 0003b7h memory patch control/status register ch 6/7 rw 0003b8h memory patch function - patch address 0 low pfal0 rw 0003b9h memory patch function - patch address 0 middle pfam0 rw 0003bah memory patch function - patch address 0 high pfah0 rw 0003bbh memory patch function - patch address 1 low pfal1 rw 0003bch memory patch function - patch address 1 middle pfam1 rw 0003bdh memory patch function - patch address 1 high pfah1 rw 0003beh memory patch function - patch address 2 low pfal2 rw 0003bfh memory patch function - patch address 2 middle pfam2 rw i/o map (13 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 37 preliminary preliminary preliminary 0003c0h memory patch function - patch address 2 high pfah2 rw 0003c1h memory patch function - patch address 3 low pfal3 rw 0003c2h memory patch function - patch address 3 middle pfam3 rw 0003c3h memory patch function - patch address 3 high pfah3 rw 0003c4h memory patch function - patch address 4 low pfal4 rw 0003c5h memory patch function - patch address 4 middle pfam4 rw 0003c6h memory patch function - patch address 4 high pfah4 rw 0003c7h memory patch function - patch address 5 low pfal5 rw 0003c8h memory patch function - patch address 5 middle pfam5 rw 0003c9h memory patch function - patch address 5 high pfah5 rw 0003cah memory patch function - patch address 6 low pfal6 rw 0003cbh memory patch function - patch address 6 middle pfam6 rw 0003cch memory patch function - patch address 6 high pfah6 rw 0003cdh memory patch function - patch address 7 low pfal7 rw 0003ceh memory patch function - patch address 7 middle pfam7 rw 0003cfh memory patch function - patch address 7 high pfah7 rw 0003d0h memory patch function - patch data 0 pfdl0 pfd0 rw 0003d1h memory patch function - patch data 0 pfdh0 rw 0003d2h memory patch function - patch data 1 pfdl1 pfd1 rw 0003d3h memory patch function - patch data 1 pfdh1 rw i/o map (14 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 38 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 0003d4h memory patch function - patch data 2 pfdl2 pfd2 rw 0003d5h memory patch function - patch data 2 pfdh2 rw 0003d6h memory patch function - patch data 3 pfdl3 pfd3 rw 0003d7h memory patch function - patch data 3 pfdh3 rw 0003d8h memory patch function - patch data 4 pfdl4 pfd4 rw 0003d9h memory patch function - patch data 4 pfdh4 rw 0003dah memory patch function - patch data 5 pfdl5 pfd5 rw 0003dbh memory patch function - patch data 5 pfdh5 rw 0003dch memory patch function - patch data 6 pfdl6 pfd6 rw 0003ddh memory patch function - patch data 6 pfdh6 rw 0003deh memory patch function - patch data 7 pfdl7 pfd7 rw 0003dfh memory patch function - patch data 7 pfdh7 rw 0003e0h - 0003efh reserved 0003f0h - 0003f2h reserved 0003f3h flash memory timing con?guration register 1 (main flash) mfmtch rw 0003f7h flash memory timing con?guration register 1 (sat flash) sfmtch rw 0003f8h flash memory write control register 0 fmwc0 rw 0003f9h flash memory write control register 1 fmwc1 rw 0003fdh flash memory write control register 5 fmwc5 rw 000401h clock select register cksr rw 000402h clock stabilisation select register ckssr rw 000403h clock monitor register ckmr r 000404h clock frequency control register low ckfcrl ckfcr rw 000405h clock frequency control register high ckfcrh rw 000406h pll control register low pllcrl pllcr rw 000408h rc clock timer control register rctcr rw i/o map (15 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 39 preliminary preliminary preliminary 000409h main clock timer control register mctcr rw 00040ah sub clock timer control register sctcr rw 00040bh reset cause and clock status register with clear function rccsrc r 00040ch reset con?guration register rcr rw 00040dh reset cause and clock status register rccsr r 00040eh watch dog timer con?guration register wdtc rw 00040fh watch dog timer clear pattern register wdtcp w 000410h - 000414h reserved 000415h clock output activation register coar rw 000416h clock output con?guration register 0 cocr0 rw 000417h clock output con?guration register 1 cocr1 rw 000418h clock modulator control register cmcr rw 000419h unused 00041ah clock modulator parameter register low cmprl cmpr rw 00041bh clock modulator parameter register high cmprh rw 00041ch - 00042bh reserved 00042ch voltage regulator control register vrcr rw 00042dh - 00042fh reserved 000430h p00 - i/o port data direction register ddr00 rw 000431h p01 - i/o port data direction register ddr01 rw 000432h p02 - i/o port data direction register ddr02 rw 000433h p03 - i/o port data direction register ddr03 rw 000434h p04 - i/o port data direction register ddr04 rw 000435h p05 - i/o port data direction register ddr05 rw i/o map (16 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 40 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 000436h p06 - i/o port data direction register ddr06 rw 000437h p07 - i/o port data direction register ddr07 rw 000438h p08 - i/o port data direction register ddr08 rw 000439h p09 - i/o port data direction register ddr09 rw 00043ah p10 - i/o port data direction register ddr10 rw 00043bh - 000443h reserved 000444h p00 - i/o port port input enable register pier00 rw 000445h p01 - i/o port port input enable register pier01 rw 000446h p02 - i/o port port input enable register pier02 rw 000447h p03 - i/o port port input enable register pier03 rw 000448h p04 - i/o port port input enable register pier04 rw 000449h p05 - i/o port port input enable register pier05 rw 00044ah p06 - i/o port port input enable register pier06 rw 00044bh p07 - i/o port port input enable register pier07 rw 00044ch p08 - i/o port port input enable register pier08 rw 00044dh p09 - i/o port port input enable register pier09 rw 00044eh p10 - i/o port port input enable register pier10 rw 00044fh - 000457h reserved 000458h p00 -i/o port port input level register pilr00 rw 000459h p01 -i/o port port input level register pilr01 rw 00045ah p02 -i/o port port input level register pilr02 rw i/o map (17 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 41 preliminary preliminary preliminary 00045bh p03 -i/o port port input level register pilr03 rw 00045ch p04 -i/o port port input level register pilr04 rw 00045dh p05 -i/o port port input level register pilr05 rw 00045eh p06 -i/o port port input level register pilr06 rw 00045fh p07 -i/o port port input level register pilr07 rw 000460h p08 -i/o port port input level register pilr08 rw 000461h p09 -i/o port port input level register pilr09 rw 000462h p10 -i/o port port input level register pilr10 rw 000463h - 00046bh reserved 00046ch p00 - i/o port extended port input level register epilr00 rw 00046dh p01 - i/o port extended port input level register epilr01 rw 00046eh p02 - i/o port extended port input level register epilr02 rw 00046fh p03 - i/o port extended port input level register epilr03 rw 000470h p04 - i/o port extended port input level register epilr04 rw 000471h p05 - i/o port extended port input level register epilr05 rw 000472h p06 - i/o port extended port input level register epilr06 rw 000473h p07 - i/o port extended port input level register epilr07 rw 000474h p08 - i/o port extended port input level register epilr08 rw 000475h p09 - i/o port extended port input level register epilr09 rw 000476h p10 - i/o port extended port input level register epilr10 rw 000477h - 00047fh reserved i/o map (18 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 42 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 000480h p00 - i/o port port output drive register podr00 rw 000481h p01 - i/o port port output drive register podr01 rw 000482h p02 - i/o port port output drive register podr02 rw 000483h p03 - i/o port port output drive register podr03 rw 000484h p04 - i/o port port output drive register podr04 rw 000485h p05 - i/o port port output drive register podr05 rw 000486h p06 - i/o port port output drive register podr06 rw 000487h p07 - i/o port port output drive register podr07 rw 000488h p08 - i/o port port output drive register podr08 rw 000489h p09 - i/o port port output drive register podr09 rw 00048ah p10 - i/o port port output drive register podr10 rw 00049ch - 0004a7h reserved 0004a8h p00 - i/o port pull-up resistor control register pucr00 rw 0004a9h p01 - i/o port pull-up resistor control register pucr01 rw 0004aah p02 - i/o port pull-up resistor control register pucr02 rw 0004abh p03 - i/o port pull-up resistor control register pucr03 rw 0004ach p04 - i/o port pull-up resistor control register pucr04 rw 0004adh p05 - i/o port pull-up resistor control register pucr05 rw i/o map (19 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 43 preliminary preliminary preliminary 0004aeh p06 - i/o port pull-up resistor control register pucr06 rw 0004afh p07 - i/o port pull-up resistor control register pucr07 rw 0004b0h p08 - i/o port pull-up resistor control register pucr08 rw 0004b1h p09 - i/o port pull-up resistor control register pucr09 rw 0004b2h p10 - i/o port pull-up resistor control register pucr10 rw 0004b3h - 0004bbh reserved 0004bch p00 - i/o port external pin state register epsr00 r 0004bdh p01 - i/o port external pin state register epsr01 r 0004beh p02 - i/o port external pin state register epsr02 r 0004bfh p03 - i/o port external pin state register epsr03 r 0004c0h p04 - i/o port external pin state register epsr04 r 0004c1h p05 - i/o port external pin state register epsr05 r 0004c2h p06 - i/o port external pin state register epsr06 r 0004c3h p07 - i/o port external pin state register epsr07 r 0004c4h p08 - i/o port external pin state register epsr08 r 0004c5h p09 - i/o port external pin state register epsr09 r 0004c6h p10 - i/o port external pin state register epsr10 r 0004c7h - 0004cfh reserved i/o map (20 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 44 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 0004d0h adc analog input enable register 0 ader0 rw 0004d1h adc analog input enable register 1 ader1 rw 0004d2h adc analog input enable register 2 ader2 rw 0004d3h - 0004d4h reserved 0004d5h reserved 0004d6h peripheral resource relocation register 0 prrr0 rw 0004d7h peripheral resource relocation register 1 prrr1 rw 0004d8h - 0004dbh reserved 0004dch peripheral resource relocation register 6 prrr6 rw 0004ddh peripheral resource relocation register 7 prrr7 rw 0004deh peripheral resource relocation register 8 prrr8 rw 0004dfh peripheral resource relocation register 9 prrr9 rw 0004e0h rtc - sub second register l wtbrl0 wtbr0 rw 0004e1h rtc - sub second register m wtbrh0 rw 0004e2h rtc - sub-second register h wtbr1 rw 0004e3h rtc - second register wtsr rw 0004e4h rtc - minutes wtmr rw 0004e5h rtc - hour wthr rw 0004e6h rtc - timer control extended register wtcer rw 0004e7h rtc - clock select register wtcksr rw 0004e8h reserved 0004e9h rtc - timer control register h wtcrh rw 0004eah cal - calibration unit control register cucr rw i/o map (21 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 45 preliminary preliminary preliminary 0004ebh reserved 0004ech cal -sub/rc-clock timer data register l cutdl cutd rw 0004edh cal -sub/rc-clock timer data register h cutdh rw 0004eeh cal - main clock timer data register 2 l cutr2l cutr2 r 0004efh cal - main clock timer data register 2 h cutr2h r 0004f0h cal - main clock timer data register 1 l cutr1l cutr1 r 0004f1h cal - main clock timer data register 1 h cutr1h r 0004f2h - 0004f9h reserved 0004fah rlt - timer input select (for cascading) tmisr rw 0004fbh - 00053dh reserved 00053eh usart7 - serial mode register smr7 rw 00053fh usart7 - serial control register scr7 rw 000540h usart7 - serial tx register tdr7 w 000540h usart7 - serial rx register rdr7 r 000541h usart7 - serial status register ssr7 rw 000542h usart7 - ext. control/com. register eccr7 rw 000543h usart7 - ext. status com. register escr7 rw 000544h usart7 - baud rate generator register bgrl7 bgr7 rw 000545h usart7 - baud rate generator register bgrh7 rw 000546h usart7 - extended serial interrupt register esir7 rw 000548h usart8 - serial mode register smr8 rw i/o map (22 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 46 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 000549h usart8 - serial control register scr8 rw 00054ah usart8 - serial tx register tdr8 w 00054ah usart8 - serial rx register rdr8 r 00054bh usart8 - serial status register ssr8 rw 00054ch usart8 - ext. control/com. register eccr8 rw 00054dh usart8 - ext. status com. register escr8 rw 00054eh usart8 - baud rate generator register bgrl8 bgr8 rw 00054fh usart8 - baud rate generator register bgrh8 rw 000550h usart8 - extended serial interrupt register esir8 rw 000552h usart9 - serial mode register smr9 rw 000553h usart9 - serial control register scr9 rw 000554h usart9 - serial tx register tdr9 w 000554h usart9 - serial rx register rdr9 r 000555h usart9 - serial status register ssr9 rw 000556h usart9 - ext. control/com. register eccr9 rw 000557h usart9 - ext. status com. register escr9 rw 000558h usart9 - baud rate generator register bgrl9 bgr9 rw 000559h usart9 - baud rate generator register bgrh9 rw 00055ah usart9 - extended serial interrupt register esir9 rw 000560h alarm0 - control status register acsr0 rw 000561h alarm0 - extended control status register aecsr0 rw 000562h alarm1 - control status register acsr1 rw 000563h alarm1 - extended control status register aecsr1 rw 000564h ppg6 - timer register ptmr6 r 000565h ppg6 - timer register r i/o map (23 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 47 preliminary preliminary preliminary 000566h ppg6 - period setting register pcsr6 w 000567h ppg6 - period setting register w 000568h ppg6 - duty cycle register pdut6 w 000569h ppg6 - duty cycle register w 00056ah ppg6 - control status register pcnl6 pcn6 rw 00056bh ppg6 - control status register pcnh6 rw 00056ch ppg7 - timer register ptmr7 r 00056dh ppg7 - timer register r 00056eh ppg7 - period setting register pcsr7 w 00056fh ppg7 - period setting register w 000570h ppg7 - duty cycle register pdut7 w 000571h ppg7 - duty cycle register w 000572h ppg7 - control status register pcnl7 pcn7 rw 000573h ppg7 - control status register pcnh7 rw 000574h ppg11-ppg8 - general control register 1 low gcn1l2 gcn12 rw 000575h ppg11-ppg8 - general control register 1 high gcn1h2 rw 000576h ppg11-ppg8 - general control register 2 low gcn2l2 gcn22 rw 000577h ppg11-ppg8 - general control register 2 high gcn2h2 rw 000578h ppg8 - timer register ptmr8 r 000579h ppg8 - timer register r 00057ah ppg8 - period setting register pcsr8 w 00057bh ppg8 - period setting register w 00057ch ppg8 - duty cycle register pdut8 w 00057dh ppg8 - duty cycle register w 00057eh ppg8 - control status register pcnl8 pcn8 rw 00057fh ppg8 - control status register pcnh8 rw 000580h ppg9 - timer register ptmr9 r i/o map (24 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 48 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 000581h ppg9 - timer register r 000582h ppg9 - period setting register pcsr9 w 000583h ppg9 - period setting register w 000584h ppg9 - duty cycle register pdut9 w 000585h ppg9 - duty cycle register w 000586h ppg9 - control status register pcnl9 pcn9 rw 000587h ppg9 - control status register pcnh9 rw 000588h ppg10 - timer register ptmr10 r 000589h ppg10 - timer register r 00058ah ppg10 - period setting register pcsr10 w 00058bh ppg10 - period setting register w 00058ch ppg10 - duty cycle register pdut10 w 00058dh ppg10 - duty cycle register w 00058eh ppg10 - control status register pcnl10 pcn10 rw 00058fh ppg10 - control status register pcnh10 rw 000590h ppg11 - timer register ptmr11 r 000591h ppg11 - timer register r 000592h ppg11 - period setting register pcsr11 w 000593h ppg11 - period setting register w 000594h ppg11 - duty cycle register pdut11 w 000595h ppg11 - duty cycle register w 000596h ppg11 - control status register pcnl11 pcn11 rw 000597h ppg11 - control status register pcnh11 rw 000598h ppg15-ppg12 - general control register 1 low gcn1l3 gcn13 rw 000599h ppg15-ppg12 - general control register 1 high gcn1h3 rw 00059ah ppg15-ppg12 - general control register 2 low gcn2l3 gcn23 rw 00059bh ppg15-ppg12 - general control register 2 high gcn2h3 rw i/o map (25 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 49 preliminary preliminary preliminary 00059ch ppg12 - timer register ptmr12 r 00059dh ppg12 - timer register r 00059eh ppg12 - period setting register pcsr12 w 00059fh ppg12 - period setting register w 0005a0h ppg12 - duty cycle register pdut12 w 0005a1h ppg12 - duty cycle register w 0005a2h ppg12 - control status register pcnl12 pcn12 rw 0005a3h ppg12 - control status register pcnh12 rw 0005a4h ppg13 - timer register ptmr13 r 0005a5h ppg13 - timer register r 0005a6h ppg13 - period setting register pcsr13 w 0005a7h ppg13 - period setting register w 0005a8h ppg13 - duty cycle register pdut13 w 0005a9h ppg13 - duty cycle register w 0005aah ppg13 - control status register pcnl13 pcn13 rw 0005abh ppg13 - control status register pcnh13 rw 0005ach ppg14 - timer register ptmr14 r 0005adh ppg14 - timer register r 0005aeh ppg14 - period setting register pcsr14 w 0005afh ppg14 - period setting register w 0005b0h ppg14 - duty cycle register pdut14 w 0005b1h ppg14 - duty cycle register w 0005b2h ppg14 - control status register pcnl14 pcn14 rw 0005b3h ppg14 - control status register pcnh14 rw 0005b4h ppg15 - timer register ptmr15 r 0005b5h ppg15 - timer register r 0005b6h ppg15 - period setting register pcsr15 w 0005b7h ppg15 - period setting register w 0005b8h ppg15 - duty cycle register pdut15 w 0005b9h ppg15 - duty cycle register w i/o map (26 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 50 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 0005bah ppg15 - control status register pcnl15 pcn15 rw 0005bbh ppg15 - control status register pcnh15 rw 0005bch - 0006dfh reserved 0006e0h external bus area con?guration register 0 eacl0 eac0 rw 0006e1h external bus area con?guration register 0 each0 rw 0006e2h external bus area con?guration register 1 eacl1 eac1 rw 0006e3h external bus area con?guration register 1 each1 rw 0006e4h external bus area con?guration register 2 eacl2 eac2 rw 0006e5h external bus area con?guration register 2 each2 rw 0006e6h external bus area con?guration register 3 eacl3 eac3 rw 0006e7h external bus area con?guration register 3 each3 rw 0006e8h external bus area con?guration register 4 eacl4 eac4 rw 0006e9h external bus area con?guration register 4 each4 rw 0006eah external bus area con?guration register 5 eacl5 eac5 rw 0006ebh external bus area con?guration register 5 each5 rw 0006ech external bus area select register 2 eas2 rw 0006edh external bus area select register 3 eas3 rw 0006eeh external bus area select register 4 eas4 rw 0006efh external bus area select register 5 eas5 rw 0006f0h external bus mode register ebm rw 0006f1h external bus clock and function register ebcf rw i/o map (27 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 51 preliminary preliminary preliminary 0006f2h external bus address output enable register 0 ebae0 rw 0006f3h external bus address output enable register 1 ebae1 rw 0006f4h external bus address output enable register 2 ebae2 rw 0006f5h external bus control signal register ebcs rw 0006f6h - 0006ffh reserved 000700h can0 - control register ctrlrl0 ctrlr0 rw 000701h can0 - control register ctrlrh0 r 000702h can0 - status register statrl0 statr0 rw 000703h can0 - status register statrh0 r 000704h can0 - error counter (transmit) errcntl0 errcnt0 r 000705h can0 - error counter (receive) errcnth0 r 000706h can0 - bit timing register btrl0 btr0 rw 000707h can0 - bit timing register btrh0 rw 000708h can0 - interrupt register intrl0 intr0 r 000709h can0 - interrupt register intrh0 r 00070ah can0 - test register testrl0 testr0 rw 00070bh can0 - test register testrh0 r 00070ch can0 - brp extension register brperl0 brper0 rw 00070dh can0 - brp extension register brperh0 r 00070eh - 00070fh reserved 000710h can0 - if1 command request register if1creql0 if1creq0 rw 000711h can0 - if1 command request register if1creqh0 rw 000712h can0 - if1 command mask register if1cmskl0 if1cmsk0 rw 000713h can0 - if1 command mask register if1cmskh0 r 000714h can0 - if1 mask register if1msk1l0 if1msk10 if1msk0 rw 000715h can0 - if1 mask register if1msk1h0 rw i/o map (28 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 52 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 000716h can0 - if1 mask register if1msk2l0 if1msk20 rw 000717h can0 - if1 mask register if1msk2h0 rw 000718h can0 - if1 arbitration register if1arb1l0 if1arb10 1f1arb0 rw 000719h can0 - if1 arbitration register if1arb1h0 rw 00071ah can0 - if1 arbitration register if1arb2l0 if1arb20 rw 00071bh can0 - if1 arbitration register if1arb2h0 rw 00071ch can0 - if1 message control register if1mctrl0 if1mctr0 rw 00071dh can0 - if1 message control register if1mctrh0 rw 00071eh can0 - if1 data a1 if1dta1l0 if1dta10 if1dta0 rw 00071fh can0 - if1 data a1 if1dta1h0 rw 000720h can0 - if1 data a2 if1dta2l0 if1dta20 rw 000721h can0 - if1 data a2 if1dta2h0 rw 000722h can0 - if1 data b1 if1dtb1l0 if1dtb10 if1dtb0 rw 000723h can0 - if1 data b1 if1dtb1h0 rw 000724h can0 - if1 data b2 if1dtb2l0 if1dtb20 rw 000725h can0 - if1 data b2 if1dtb2h0 rw 000726h - 00073fh reserved 000740h can0 - if2 command request register if2creql0 if2creq0 rw 000741h can0 - if2 command request register if2creqh0 rw 000742h can0 - if2 command mask register if2cmskl0 if2cmsk0 rw 000743h can0 - if2 command mask register if2cmskh0 r 000744h can0 - if2 mask register if2msk1l0 if2msk10 if2msk0 rw 000745h can0 - if2 mask register if2msk1h0 rw 000746h can0 - if2 mask register if2msk2l0 if2msk20 rw 000747h can0 - if2 mask register if2msk2h0 rw 000748h can0 - if2 arbitration register if2arb1l0 if2arb10 if2arb0 rw 000749h can0 - if2 arbitration register if2arb1h0 rw 00074ah can0 - if2 arbitration register if2arb2l0 if2arb20 rw 00074bh can0 - if2 arbitration register if2arb2h0 rw i/o map (29 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 53 preliminary preliminary preliminary 00074ch can0 - if2 message control register if2mctrl0 if2mctr0 rw 00074dh can0 - if2 message control register if2mctrh0 rw 00074eh can0 - if2 data a1 if2dta1l0 if2dta10 if2dta0 rw 00074fh can0 - if2 data a1 if2dta1h0 rw 000750h can0 - if2 data a2 if2dta2l0 if2dta20 rw 000751h can0 - if2 data a2 if2dta2h0 rw 000752h can0 - if2 data b1 if2dtb1l0 if2dtb10 if2dtb0 rw 000753h can0 - if2 data b1 if2dtb1h0 rw 000754h can0 - if2 data b2 if2dtb2l0 if2dtb20 rw 000755h can0 - if2 data b2 if2dtb2h0 rw 000756h - 000779h reserved 000780h can0 - transmission request register treqr1l0 treqr10 treqr0 r 000781h can0 - transmission request register treqr1h0 r 000782h can0 - transmission request register treqr2l0 treqr20 r 000783h can0 - transmission request register treqr2h0 r 000784h - 00078fh reserved 000790h can0 - new data register newdt1l0 newdt10 newdt0 r 000791h can0 - new data register newdt1h0 r 000792h can0 - new data register newdt2l0 newdt20 r 000793h can0 - new data register newdt2h0 r 000794h - 00079fh reserved 0007a0h can0 - interrupt pending register intpnd1l0 intpnd10 intpnd0 r 0007a1h can0 - interrupt pending register intpnd1h0 r 0007a2h can0 - interrupt pending register intpnd2l0 intpnd20 r i/o map (30 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 54 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 0007a3h can0 - interrupt pending register intpnd2h0 r 0007a4h - 0007afh reserved 0007b0h can0 - message valid register msgval1l0 msgval10 msgval0 r 0007b1h can0 - message valid register msgval1h0 r 0007b2h can0 - message valid register msgval2l0 msgval20 r 0007b3h can0 - message valid register msgval2h0 r 0007b4h - 0007cdh reserved 0007ceh can0 - output enable register coer0 rw 0007cfh - 0007ffh reserved 000800h can1 - control register ctrlrl1 ctrlr1 rw 000801h can1 - control register ctrlrh1 r 000802h can1 - status register statrl1 statr1 rw 000803h can1 - status register statrh1 r 000804h can1 - error counter (transmit) errcntl1 errcnt1 r 000805h can1 - error counter (receive) errcnth1 r 000806h can1 - bit timing register btrl1 btr1 rw 000807h can1 - bit timing register btrh1 rw 000808h can1 - interrupt register intrl1 intr1 r 000809h can1 - interrupt register intrh1 r 00080ah can1 - test register testrl1 testr1 rw 00080bh can1 - test register testrh1 r 00080ch can1 - brp extension register brperl1 brper1 rw 00080dh can1 - brp extension register brperh1 r 00080eh - 00080fh reserved 000810h can1 - if1 command request register if1creql1 if1creq1 rw i/o map (31 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 55 preliminary preliminary preliminary 000811h can1 - if1 command request register if1creqh1 rw 000812h can1 - if1 command mask register if1cmskl1 if1cmsk1 rw 000813h can1 - if1 command mask register if1cmskh1 r 000814h can1 - if1 mask register if1msk1l1 if1msk11 rw 000815h can1 - if1 mask register if1msk1h1 rw 000816h can1 - if1 mask register if1msk2l1 if1msk21 rw 000817h can1 - if1 mask register if1msk2h1 rw 000818h can1 - if1 arbitration register if1arb1l1 if1arb11 rw 000819h can1 - if1 arbitration register if1arb1h1 rw 00081ah can1 - if1 arbitration register if1arb2l1 if1arb21 rw 00081bh can1 - if1 arbitration register if1arb2h1 rw 00081ch can1 - if1 message control register if1mctrl1 if1mctr1 rw 00081dh can1 - if1 message control register if1mctrh1 rw 00081eh can1 - if1 data a1 if1dta1l1 if1dta11 rw 00081fh can1 - if1 data a1 if1dta1h1 rw 000820h can1 - if1 data a2 if1dta2l1 if1dta21 rw 000821h can1 - if1 data a2 if1dta2h1 rw 000822h can1 - if1 data b1 if1dtb1l1 if1dtb11 rw 000823h can1 - if1 data b1 if1dtb1h1 rw 000824h can1 - if1 data b2 if1dtb2l1 if1dtb21 rw 000825h can1 - if1 data b2 if1dtb2h1 rw 000826h - 00083fh reserved 000840h can1 - if2 command request register if2creql1 if2creq1 rw 000841h can1 - if2 command request register if2creqh1 rw 000842h can1 - if2 command mask register if2cmskl1 if2cmsk1 rw 000843h can1 - if2 command mask register if2cmskh1 r 000844h can1 - if2 mask register if2msk1l1 if2msk11 rw 000845h can1 - if2 mask register if2msk1h1 rw 000846h can1 - if2 mask register if2msk2l1 if2msk21 rw i/o map (32 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 56 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 000847h can1 - if2 mask register if2msk2h1 rw 000848h can1 - if2 arbitration register if2arb1l1 if2arb11 rw 000849h can1 - if2 arbitration register if2arb1h1 rw 00084ah can1 - if2 arbitration register if2arb2l1 if2arb21 rw 00084bh can1 - if2 arbitration register if2arb2h1 rw 00084ch can1 - if2 message control register if2mctrl1 if2mctr1 rw 00084dh can1 - if2 message control register if2mctrh1 rw 00084eh can1 - if2 data a1 if2dta1l1 if2dta11 rw 00084fh can1 - if2 data a1 if2dta1h1 rw 000850h can1 - if2 data a2 if2dta2l1 if2dta21 rw 000851h can1 - if2 data a2 if2dta2h1 rw 000852h can1 - if2 data b1 if2dtb1l1 if2dtb11 rw 000853h can1 - if2 data b1 if2dtb1h1 rw 000854h can1 - if2 data b2 if2dtb2l1 if2dtb21 rw 000855h can1 - if2 data b2 if2dtb2h1 rw 000856h - 00087fh reserved 000880h can1 - transmission request register treqr1l1 treqr11 r 000881h can1 - transmission request register treqr1h1 r 000882h can1 - transmission request register treqr2l1 treqr21 r 000883h can1 - transmission request register treqr2h1 r 000890h can1 - new data register newdt1l1 newdt11 r 000891h can1 - new data register newdt1h1 r 000892h can1 - new data register newdt2l1 newdt21 r 000893h can1 - new data register newdt2h1 r 000894h - 00089fh reserved i/o map (33 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 57 preliminary preliminary preliminary 0008a0h can1 - interrupt pending register intpnd1l1 intpnd11 r 0008a1h can1 - interrupt pending register intpnd1h1 r 0008a2h can1 - interrupt pending register intpnd2l1 intpnd21 r 0008a3h can1 - interrupt pending register intpnd2h1 r 0008b0h can1 - message valid register msgval1l1 msgval11 r 0008b1h can1 - message valid register msgval1h1 r 0008b2h can1 - message valid register msgval2l1 msgval21 r 0008b3h can1 - message valid register msgval2h1 r 0008ceh can1 - output enable register coer1 rw 000c00h external bus area (16-bit address up to 000fffh) extbus1 rw 001000h external bus area (remaining ram area) extbus1 rw i/o map (34 / 34) address register abbreviation 8-bit access abbreviation 16-bit access abbreviation 32-bit access ac- cess mb96340 series speci?ation 58 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary interrupt vector table interrupt vector table (1 / 4) vector number offset in vector ta- ble vector name cleared by dma index in icr to program description 0 3fc callv0 no - 1 3f8 callv1 no - 2 3f4 callv2 no - 3 3f0 callv3 no - 4 3ec callv4 no - 5 3e8 callv5 no - 6 3e4 callv6 no - 7 3e0 callv7 no - 8 3dc reset no - 9 3d8 int9 no - 10 3d4 exception no - 11 3d0 nmi no - non-maskable interrupt 12 3cc dly no 12 delayed interrupt 13 3c8 rc_timer no 13 rc timer 14 3c4 mc_timer no 14 main clock timer 15 3c0 sc_timer no 15 sub clock timer 16 3bc reserved no 16 reserved 17 3b8 extint0 yes 17 external interrupt 0 18 3b4 extint1 yes 18 external interrupt 1 19 3b0 extint2 yes 19 external interrupt 2 20 3ac extint3 yes 20 external interrupt 3 21 3a8 extint4 yes 21 external interrupt 4 22 3a4 extint5 yes 22 external interrupt 5 23 3a0 extint6 yes 23 external interrupt 6 24 39c extint7 yes 24 external interrupt 7 25 398 extint8 yes 25 external interrupt 8 26 394 extint9 yes 26 external interrupt 9 speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 59 preliminary preliminary preliminary 27 390 extint10 yes 27 external interrupt 10 28 38c extint11 yes 28 external interrupt 11 29 388 extint12 yes 29 external interrupt 12 30 384 extint13 yes 30 external interrupt 13 31 380 extint14 yes 31 external interrupt 14 32 37c extint15 yes 32 external interrupt 15 33 378 can0 no 33 can controller 0 34 374 can1 no 34 can controller 1 35 370 ppg0 yes 35 programmable pulse generator 0 36 36c ppg1 yes 36 programmable pulse generator 1 37 368 ppg2 yes 37 programmable pulse generator 2 38 364 ppg3 yes 38 programmable pulse generator 3 39 360 ppg4 yes 39 programmable pulse generator 4 40 35c ppg5 yes 40 programmable pulse generator 5 41 358 ppg6 yes 41 programmable pulse generator 6 42 354 ppg7 yes 42 programmable pulse generator 7 43 350 ppg8 yes 43 programmable pulse generator 8 44 34c ppg9 yes 44 programmable pulse generator 9 45 348 ppg10 yes 45 programmable pulse generator 10 46 344 ppg11 yes 46 programmable pulse generator 11 47 340 ppg12 yes 47 programmable pulse generator 12 48 33c ppg13 yes 48 programmable pulse generator 13 49 338 ppg14 yes 49 programmable pulse generator 14 50 334 ppg15 yes 50 programmable pulse generator 15 51 330 rlt0 yes 51 reload timer 0 52 32c rlt1 yes 52 reload timer 1 53 328 rlt2 yes 53 reload timer 2 54 324 rlt3 yes 54 reload timer 3 55 320 ppgrlt yes 55 reload timer 6 - dedicated for ppg interrupt vector table (2 / 4) vector number offset in vector ta- ble vector name cleared by dma index in icr to program description mb96340 series speci?ation 60 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary 56 31c icu0 yes 56 input capture unit 0 57 318 icu1 yes 57 input capture unit 1 58 314 icu2 yes 58 input capture unit 2 59 310 icu3 yes 59 input capture unit 3 60 30c icu4 yes 60 input capture unit 4 61 308 icu5 yes 61 input capture unit 5 62 304 icu6 yes 62 input capture unit 6 63 300 icu7 yes 63 input capture unit 7 64 2fc ocu0 yes 64 output compare unit 0 65 2f8 ocu1 yes 65 output compare unit 1 66 2f4 ocu2 yes 66 output compare unit 2 67 2f0 ocu3 yes 67 output compare unit 3 68 2ec ocu4 yes 68 output compare unit 4 69 2e8 ocu5 yes 69 output compare unit 5 70 2e4 ocu6 yes 70 output compare unit 6 71 2e0 ocu7 yes 71 output compare unit 7 72 2dc frt0 yes 72 free running timer 0 73 2d8 frt1 yes 73 free running timer 1 74 2d4 iic0 yes 74 i2c interface 75 2d0 iic1 yes 75 i2c interface 76 2cc adc0 yes 76 a/d converter 77 2c8 alarm0 no 77 alarm comparator 0 78 2c4 alarm1 no 78 alarm comparator 1 79 2c0 linr0 yes 79 lin usart 0 rx 80 2bc lint0 yes 80 lin usart 0 tx 81 2b8 linr1 yes 81 lin usart 1 rx 82 2b4 lint1 yes 82 lin usart 1 tx 83 2b0 linr2 yes 83 lin usart 2 rx 84 2ac lint2 yes 84 lin usart 2 tx interrupt vector table (3 / 4) vector number offset in vector ta- ble vector name cleared by dma index in icr to program description speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_memory.fm 61 preliminary preliminary preliminary 85 2a8 linr3 yes 85 lin usart 3 rx 86 2a4 lint3 yes 86 lin usart 3 tx 87 2a0 main_flash no 87 main flash memory 88 29c sat_flash no 88 satellite flash memory (only mb96f348h/t) 89 298 linr7 yes 89 lin usart 7 rx (not available on mb96f348tsa/hsa/ twa/hwa) 90 294 lint7 yes 90 lin usart 7 tx (not available on mb96f348tsa/hsa/ twa/hwa) 91 290 linr8 yes 91 lin usart 8 rx (not available on mb96f348tsa/hsa/ twa/hwa) 92 28c lint8 yes 92 lin usart 8 tx (not available on mb96f348tsa/hsa/ twa/hwa) 93 288 linr9 yes 93 lin usart 9 rx (not available on mb96f348tsa/hsa/ twa/hwa) 94 284 lint9 yes 94 lin usart 9 tx (not available on mb96f348tsa/hsa/ twa/hwa) 95 280 rtc0 no 95 real timer clock (not available on mb96f348tsa/hsa/ twa/hwa) 96 27c cal0 no 96 clock calibration unit (not available on mb96f348tsa/hsa/ twa/hwa) interrupt vector table (4 / 4) vector number offset in vector ta- ble vector name cleared by dma index in icr to program description mb96340 series speci?ation 62 fme/emdc- 2007-9-12 mb96340_ds_memory.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_handling.fm 51 preliminary preliminary preliminary handling devices special care is required for the following when handling the device: latch-up prevention treatment of unused pins external clock precautions for when not using a sub clock signal notes on pll clock mode operation power supply pins (vcc/vss) crystal oscillator circuit turn on sequence of power supply to a/d converter and analog inputs connection of unused pins of a/d converter notes on energization stabilization of power supply voltage 1. preventing latch-up cmos ic chips may suffer latch-up under the following conditions: a voltage higher than vcc or lower than vss is applied to an input or output pin. a voltage higher than the rated voltage is applied between vcc and vss. the avcc power supply is applied before the vcc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. for the same reason, also be careful not to let the analog power-supply voltage (avcc, avrh) exceed the digital power-supply voltage. 2. treatment of unused pins unused input pins may be left open when the input is disabled (corresponding bit of port input enable register pier = 0). leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. therefore they must be pulled up or pulled down through resistors. to prevent latch- up, those resistors should be more than 2 k ? . unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. external clock usage to use external clock, drive the x0 pin and leave x1 pin open. 4. precautions for when not using a sub clock signal if you do not connect pins x0a and x1a to an oscillator, use a pull-down resistor on the x0a pin, and leave the x1a pin open. 5. notes on pll clock mode operation if the pll clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the freely oscillating pll. performance of this operation, however, cannot be guaranteed. 6. power supply pins (vcc/vss) ensure that all vcc-level power supply pins are at the same potential. in addition, ensure the same for all vss-level power supply pins. if there are more than one vcc or vss systems, the device may operate incorrectly even within the guaranteed operating range. connect vcc and vss to the device from the power supply with lowest possible impedance. mb96340 series speci?ation 52 fme/emdc- 2007-9-12 mb96300_ds_handling.fm preliminary as a measure against power supply noise, connect a capacitor of about 0.1 f as a bypass capacitor between vcc and vss as close as possible to vcc and vss pins. 7. crystal oscillator circuit noise at x0 or x1 pins may possibly cause abnormal operation. make sure to provide bypass capacitors with shortest distance to x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with a ground area for stabilizing the operation. it is highly recommended to evaluate the quartz/mcu system at the quartz manufacturer. 8. turn on sequence of power supply to a/d converter and analog inputs make sure to turn the a/d converter power supply (avcc, avrh, avrl) and analog inputs (ann) on after turning the digital power supply (vcc) on. turn the digital power off after turning the a/d converter supply and analog inputs off. in this case, make sure that the voltage does not exceed avrh or avcc (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. connection of unused pins of a/d converter connect unused pins of a/d converter as avcc = vcc, avss = avrh = avrl = vss. 10. notes on energization to prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50 s from 0.2 v to 2.7 v. 11. stabilization of power supply voltage if the power supply voltage varies acutely even within the operation assurance range of the vcc power supply voltage, a malfunction may occur. the vcc power supply voltage must therefore be stabilized. as stabilization guidelines, stabilize the power supply voltage so that vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 hz) fall within 10% of the standard vcc power supply voltage and the transient fluctuation rate becomes 0.1v/ s or less in instantaneous fluctuation for power supply switching. speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_abs_max_rat.fm 53 preliminary preliminary preliminary electrical characteristics 1. absolute maximum ratings *1: set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc neither when the power is switched on. *2: v i and v o should not exceed v cc + 0.3 v. v i should not exceed the speci ed ratings. however if the maximum current to/from a input is limited by some means with external components, the i clamp rating supercedes the v i rating. input/output voltages of standard ports depend on v cc. parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc *1 avrh, avrl v ss - 0.3 v ss + 6.0 v av cc avrh, av cc avrl, avrh > avrl, avrl av ss input voltage v i v ss - 0.3 v ss + 6.0 v v i v cc + 0.3v *2 output voltage v o v ss - 0.3 v ss + 6.0 v v o v cc + 0.3v *2 maximum clamp current i clamp -4.0 +4.0 ma applicable to general purpose i/o pins *3 total maximum clamp current |i clamp |- 40ma applicable to general purpose i/o pins *3 l level maximum output current i ol1 -15ma normal outputs for normal drive output port setting l level average output current i olav1 -5ma normal outputs for normal drive output port setting l level maximum overall output current i ol1 - 100 ma normal outputs for normal drive output port setting l level average overall output current i olav1 -50ma normal outputs for normal drive output port setting h level maximum output current i oh1 - -15 ma normal outputs for normal drive output port setting h level average output current i ohav1 --5ma normal outputs for normal drive output port setting h level maximum overall output current i oh1 - -100 ma normal outputs for normal drive output port setting h level average overall output current i ohav1 - -50 ma normal outputs for normal drive output port setting power consumption p d - 600 mw operating temperature t a 0 +70 o c mb96v300b -40 +125 *4 others operating temperature at flash erase/ write t af -40 +105 o c storage temperature t stg -55 +150 o c mb96340 series speci?ation 54 fme/emdc- 2007-9-12 mb96300_ds_el_abs_max_rat.fm preliminary *3: ? applicable to all general purpose i/o pins (pnn_m) ? use within recommended operating conditions. ? use at dc voltage (current) ? the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not xed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suf cient to operate the power reset (except devices with persistant low voltage reset in internal vector mode). ? sample recommended circuits: warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. *4 if used exceeding t a = +105 ? c, be sure to contact fujitsu for reliability limitations. * p-ch n-ch v cc r protective diode limiting resistance +b input (0v to 16v) speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_rec_cond.fm 55 preliminary preliminary preliminary 2. recommended conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu repre- sentatives beforehand. *1: if used exceeding t a = +105 ? c, be sure to contact fujitsu for reliability limitations. parameter symbol value unit remarks min typ max power supply voltage vcc, dvcc 3.0 - 5.5 v smoothing capacitor at c pin c s 4.7 - 10 f use a x7r ceramic capacitor operating temperature t a 0 - +70 o c mb96v300b -40 - +125 *1 others mb96340 series speci?ation 56 fme/emdc- 2007-9-12 mb96300_ds_el_rec_cond.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_dc_char.fm 57 preliminary preliminary preliminary 3. dc characteristics (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin condition value unit remarks min typ max input h voltage v ih - port inputs if cmos hysteresis 0.8/0.2 input is selected 0.8 v cc - v cc + 0.3 v - port inputs if cmos hysteresis 0.7/0.3 input is selected 0.7 v cc - v cc + 0.3 v - port inputs if au- tomotive hys- teresis input is se- lected 0.8 v cc - v cc + 0.3 v - port inputs if ttl input is selected 2.0 - v cc + 0.3 v v ihr rstx - 0.8 v cc - v cc + 0.3 v rstx input pin (cmos hysteresis) v ihm md2-md0 - v cc - 0.3 - v cc + 0.3 v mdx input pins v ihx0s x0,x0a - 2.5 - v cc + 0.3 v external clock in os- cillation mode input h voltage v ihx0f x0 - 0.8 v cc - v cc + 0.3 v external clock in fast clock input mode (not available in mb96v300, mb96f34xy/r/a) input l voltage v il - port inputs if cmos hysteresis 0.8/0.2 input is selected v ss - 0.3 - 0.2 v cc v - port inputs if cmos hysteresis 0.7/0.3 input is selected v ss - 0.3 - 0.3 v cc v - port inputs if au- tomotive hys- teresis input is se- lected v ss - 0.3 - 0.5 v cc v - port inputs if ttl input is selected v ss - 0.3 - 0.8 v v ilr rstx - v ss - 0.3 - 0.2 v cc v rstx input pin (cmos hysteresis) v ilm md2-md0 - v ss - 0.3 - v ss + 0.3 v mdx input pins v ilx0s x0, x0a - v ss - 0.3 - 0.5 v external clock in os- cillation mode mb96340 series speci?ation 58 fme/emdc- 2007-9-12 mb96300_ds_el_dc_char.fm preliminary note: input/output voltages of ports depend on v cc. v ilx0f x0 - v ss - 0.3 - 0.2 v cc v external clock in fast clock input mode (not available in mb96v300, mb96f34xy/r/a) output h voltage v oh2 normal outputs 4.5v v cc 5.5v i oh = -2ma v cc - 0.5 --v driving strength set to 2ma 3.0v v cc < 4.5v i oh = -1.6ma v oh5 normal outputs 4.5v v cc 5.5v i oh = -5ma v cc - 0.5 --v driving strength set to 5ma 3.0v v cc < 4.5v i oh = -3ma output h voltage v oh3 i 2 c outputs 4.5v v cc 5.5v i oh = -3ma v cc - 0.5 --v 3.0v v cc < 4.5v i oh = -2ma output l voltage v ol2 normal outputs 4.5v v cc 5.5v i ol = +2ma - - 0.4 v driving strength set to 2ma 3.0v v cc < 4.5v i ol = +1.6ma v ol5 normal outputs 4.5v v cc 5.5v i ol = +5ma - - 0.4 v driving strength set to 5ma 3.0v v cc < 4.5v i ol = +3ma output l voltage v ol3 i 2 c outputs 4.5v v cc 5.5v i ol = +3ma - - 0.4 v 3.0v v cc < 4.5v i ol = +2ma input leak current i il pnn_m v cc = 5.5v v ss < v i < v cc -1 - +1 a pull-up resistance r up pnn_m, rstx - 25 50 100 k ? (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin condition value unit remarks min typ max speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_dc_char.fm 59 preliminary preliminary preliminary (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition value temp remarks typ max unit power supply cur- rent in run modes* i ccpll pll run mode with clks1/2 = 56mhz = clkb = clkp1, clkp2 = 28mhz 44 57 ma 25 ? c clkrc and clksc stopped. core voltage at 1.9v 45 60 125 ? c pll run mode with clks1/2 = 48mhz, clkb = clkp1/2 = 24mhz 25 34 ma 25 ? c clkrc and clksc stopped. core voltage at 1.9v 26 37 125 ? c i ccmain main run mode with clks1/2=clkb = clkp1/2 = 4mhz 4.5 5.5 ma 25 ? c clkpll, clksc and clkrc stopped 5.1 8.5 125 ? c i ccrch rc run mode with clks1=clks2=clkb = clkp1/2 = 2mhz 2.9 4 ma 25 ? c clkmc, clkpll and clksc stopped 3.5 6.5 125 ? c i ccrcl rc run mode with clks1/2 = clkb = clkp1 /2 = 100khz, sm- cr:lpms=0 0.4 0.6 ma 25 ? c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.9 3.5 125 ? c rc run mode with clks1/2 = clkb = clkp1 /2 = 100khz, sm- cr:lpms=1 0.15 0.25 ma 25 ? c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode, no flash pro- gramming/erasing allowed. 0.65 3.2 125 ? c power supply cur- rent in run modes* i ccsub sub run mode with clks1/2 = clkb = clkp1/2 = 32khz 0.1 0.2 ma 25 ? c clkmc, clkpll and clkrc stopped, no flash programming/ erasing allowed. 0.6 3 125 ? c mb96340 series speci?ation 60 fme/emdc- 2007-9-12 mb96300_ds_el_dc_char.fm preliminary power supply cur- rent in sleep modes* i ccspll pll sleep mode with clks1/2 = 48mhz, clkp1/2 = 24mhz 9 10.5 ma 25 ? c clkrc and clksc stopped. 9.7 13 125 ? c pll sleep mode with clks1/2 = clkp1 = 56mhz, clkp2 = 28mhz 14 15.5 ma 25 ? c clkrc and clksc stopped. 14.8 18 125 ? c i ccsmain main sleep mode with clks1/2 = clkp1/2 = 4mhz 1.5 1.8 ma 25 ? c clkpll clkrc and clksc stopped 2 4.5 125 ? c i ccsrch rc sleep mode with clks1/2 = clkp1/2 = 2mhz 0.8 1.3 ma 25 ? c clkmc, clkpll and clksc stopped 1.4 4 125 ? c i ccsrcl rc sleep mode with clks1/2 = clkp1/2 = 100khz, sm- cr:lpmss=0 0.3 0.5 ma 25 ? c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.8 3.4 125 ? c rc sleep mode with clks1/2 = clkp1/2 = 100khz, sm- cr:lpmss=1 0.06 0.15 ma 25 ? c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode 0.56 3 125 ? c power supply cur- rent in sleep modes* i ccssub sub sleep mode with clks1/2 = clkp1/2 = 32khz 0.04 0.12 ma 25 ? c clkmc, clkpll and clkrc stopped 0.54 2.9 125 ? c parameter symbol condition value temp remarks typ max unit speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_dc_char.fm 61 preliminary preliminary preliminary power supply cur- rent in timer modes* i cctpll pll timer mode with clkmc = 4mhz, clk- pll = 56mhz 1.6 2 ma 25 ? c clkrc and clksc stopped. core voltage at 1.9v 2.1 4.8 125 ? c i cctmain main timer mode with clkmc = 4mhz, sm- cr:lpmss=0 0.35 0.5 ma 25 ? c clkpll, clkrc and clksc stopped. volt- age regulator in high power mode 0.85 3.3 125 ? c main timer mode with clkmc = 4mhz, sm- cr:lpmss=1 0.1 0.15 ma 25 ? c clkpll, clkrc and clksc stopped. volt- age regulator in low pow- er mode 0.6 2.9 125 ? c i cctrch rc timer mode with clkrc = 2mhz, sm- cr:lpmss=0 0.35 0.5 ma 25 ? c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.85 3.3 125 ? c rc timer mode with clkrc = 2mhz, sm- cr:lpmss=1 0.1 0.15 ma 25 ? c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode 0.6 2.9 125 ? c i cctrcl rc timer mode with clkrc = 100khz, sm- cr:lpmss=0 0.3 0.45 ma 25 ? c clkmc, clkpll and clksc stopped. volt- age in high power mode 0.8 3.2 125 ? c rc timer mode with clkrc = 100khz, sm- cr:lpmss=1 0.05 0.1 ma 25 ? c clkmc, clkpll and clksc stopped. volt- age in low power mode 0.55 2.8 125 ? c parameter symbol condition value temp remarks typ max unit mb96340 series speci?ation 62 fme/emdc- 2007-9-12 mb96300_ds_el_dc_char.fm preliminary * the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter 10 of the harware manual for further details about voltage regulator control. power supply cur- rent in timer modes* i cctsub sub timer mode with clksc = 32khz 0.03 0.1 ma 25 ? c clkmc, clkpll and clkrc stopped 0.53 2.8 125 ? c stop mode i cch vrcr:lpmb[2:0] = 110 0.02 0.08 ma 25 ? c core voltage at 1.8v 0.52 2.8 125 ? c vrcr:lpmb[2:0] = 000 0.015 0.06 ma 25 ? c core voltage at 1.2v 0.4 2.3 125 ? c power supply cur- rent for active low voltage detector i cclvd low voltage detector en- abled (rcr:lvde= 1 ) 70 100 a 25 ? c this current must be added to all power sup- ply currents above 70 100 125 ? c clock modulator current i ccclomo clock modulator en- abled (cmcr:pdx = 1 ) 34 ma 25 ? c must be added to all cur- rent above 3 4 125 ? c flash write/erase current i ccflash 15 40 ma 25 ? c must be added to all cur- rent above 15 40 125 ? c input capacitance c in - 5 15 pf parameter symbol condition value temp remarks typ max unit speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_src_clk.fm 63 preliminary preliminary preliminary 4. ac characteristics source clock timing (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 - 16 mhz when using an oscillation circuit, pll off 3.5 - 16 mhz when using an oscillation circuit, pll on 0 - 4 mhz when using an external clock, pll off 3.5 - 4 mhz when using an external clock, pll on clock frequency f fci x0 0 - 56 mhz when using an external clock in fast clock input mode (not available in mb96v300, mb96f34xy/r/a) clock frequency f cl x0a, x1a 32 32.768 100 khz when using an oscillation circuit 0 - 100 khz when using an external clock clock frequency f cr - 50 100 200 khz when using slow frequency of rc oscil- lator 124mhz when using fast frequency of rc oscil- lator clock frequency f clkvco - 50 - 200 mhz vco output frequency of pll (clkvco) input clock pulse width p wh , p wl x0 8 - - ns duty ratio is about 30% to 70% input clock pulse width p whl , p wll x0a 5 - - s input clock rise and fall time t cr , t cf x0 - - 5 ns when using external clock x0 t cyl p wh t cf t cr p wl v il v ih x0a t cyll p whl t cf t cr p wll v il v ih mb96340 series speci?ation 64 fme/emdc- 2007-9-12 mb96300_ds_el_ac_src_clk.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_int_clk.fm 65 preliminary preliminary preliminary internal clock timing (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol core voltage settings unit remarks 1.8v 1.9v min max min max internal system clock fre- quency (clks1 and clks2) f clks1 , f clks2 092096mhz 0 68 0 74 mhz mb96f34xy/r internal cpu clock frequen- cy (clkb), internal periph- eral clock frequency (clkp1) f clkb , f clkp1 052056mhz internal peripheral clock fre- quency (clock clkp2) f clkp2 028032mhz mb96340 series speci?ation 66 fme/emdc- 2007-9-12 mb96300_ds_el_ac_int_clk.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_rst.fm 67 preliminary preliminary preliminary external reset timing (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max reset input time t rstl rstx 500 - - ns 0.2 v cc rstx t rstl 0.2 v cc mb96340 series speci?ation 68 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_rst.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_pon_rst.fm 69 preliminary preliminary preliminary power on reset timing (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max power on rise time t r vcc 0.05 - 30 ms power off time t off vcc 1 - - ms due to repetitive operation 0.2 v t r 2.7v t off 0.2 v 0.2 v if you change the power supply too rapidly, a power-on reset may occur. we recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the gure below. perform while not using the pll clock. however if voltage drops are below 1 v/s, you can operate while using the pll clock. 3 v v cc v cc rising edge of 50 mv/ms maximum is allowed mb96340 series speci?ation 70 fme/emdc- 2007-9-12 mb96300_ds_el_ac_pon_rst.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_inpt.fm 71 preliminary preliminary preliminary external input timing (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) note : relocated resource inputs have same characteristics parameter symbol pin condition value unit used pin input func- tion min max input pulse width t inh t inl intn ? 200 ? ns external interrupt nmi nmi pnn_m t clkp1 + 200 (t clkp1 =1/f clkp1 ) ? ns general purpose io tinn reload timer ttgn ppg trigger input adtg ad converter trigger frckn free running timer external clock inn input capture v il v ih t inh v il v ih t inl external pin input mb96340 series speci?ation 72 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_inpt.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm 81 preliminary preliminary preliminary external bus timing basic timing (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive =5ma,c l =50pf) (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l =50pf) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 25 ? ns t chcl ? t cyc /2-5 t cyc /2+5 ns if clkb duty cy- cle is 50% t clch ? t cyc /2-5 t cyc /2+5 ns eclk ubx/ lbx / csn time t chcbh csn, ubx, lbx,eclk ? -20 20 ns t chcbl ? -20 20 ns t clcbh ? -20 20 ns t clcbl ? -20 20 ns eclk ale time t chlh ale, eclk ? -10 10 ns t chll ? -10 10 ns t cllh ? -10 10 ns t clll ? -10 10 ns eclk address valid time t chav a[23:16],eclk ? -15 15 ns t clav ? -15 15 ns eclk address valid time t cladv ad[15:0],eclk ? -15 15 ns t chadv ? -15 15 ns eclk rdx /wrx time t chrwh rdx, wrx, wrlx,wrhx, eclk ? -10 10 ns t chrwl ? -10 10 ns t clrwh ? -10 10 ns t clrwl ? -10 10 ns parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 30 ? ns t chcl ? t cyc /2-8 t cyc /2+8 ns if clkb duty cy- cle is 50% t clch ? t cyc /2-8 t cyc /2+8 ns eclk ubx/ lbx / csn time t chcbh csn, ubx, lbx,eclk ? -25 25 ns t chcbl ? -25 25 ns t clcbh ? -25 25 ns t clcbl ? -25 25 ns mb96340 series speci?ation 82 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm preliminary refer to the hardware manual for detailed timing charts. eclk ale time t chlh ale, eclk ? -15 15 ns t chll ? -15 15 ns t cllh ? -15 15 ns t clll ? -15 15 ns eclk address valid time t chav a[23:16],eclk ? -20 20 ns t clav ? -20 20 ns eclk address valid time t cladv ad[15:0],eclk ? -20 20 ns t chadv ? -20 20 ns eclk rdx /wrx time t chrwh rdx, wrx, wrlx, wrhx, eclk ? -15 15 ns t chrwl ? -15 15 ns t clrwh ? -15 15 ns t clrwl ? -15 15 ns parameter symbol pin condition value unit remarks min max eclk t cyc csn ale a[23:16] 0.2*vcc t chcl t chav t chcbl t chcbh lbx ubx t cllh t chll t chlh t clll t cladv ad[15:0] address t clav t chadv t clcbh t clcbl t chrwh t clrwh t clrwl t chrwl rdx wrx (wrlx, wrhx) 0.8*vcc t clch speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm 83 preliminary preliminary preliminary bus timing (read) (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive =5ma,c l =50pf parameter sym- bol pin conditions value unit remarks min max ale pulse width t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 5 ? ns eacl:sts=1 t cyc ? 5 ? ns eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 5 ? ns valid address ? ale time t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 15 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 15 ? ns eacl:sts=0 and eacl:ace=1 2t cyc ? 15 ? ns eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 15 ? ns t advll ale,ad[15 :0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 15 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 15 ? ns eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 15 ? ns eacl:sts=1 and eacl:ace=1 2t cyc ? 15 ? ns ale ? address valid time t llax ale, ad[15 :0] eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 -15 ? ns valid address ? rdx time t avrl rdx, a[23:16] eacl:ace=0 3t cyc /2 ? 15 ? ns eacl:ace=1 5t cyc /2 ? 15 ? ns valid address ? rdx time t advrl rdx,ad[15 :0] eacl:ace=0 t cyc ? 15 ? ns eacl:ace=1 2t cyc ? 15 ? ns valid address ? valid data input t avdv a[23:16], ad[15;0] eacl:ace=0 ? 3t cyc ? 55 ns w/o cycle extension eacl:ace=1 ? 4t cyc ? 55 ns valid address ? valid data input t advdv ad[15 :0] eacl:ace=0 ? 5t cyc /2 ? 55 ns w/o cycle extension; eacl:ace=1 ? 7t cyc /2 ? 55 ns rdx pulse width t rlrh rdx ? 3 t cyc /2 ? 5 ? ns w/o cycle extension rdx ? valid data input t rldv rdx, ad[15:0] ?? 3t cyc /2 ? 50 ns w/o cycle extension rdx ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns address valid ? data hold time t axdx a[23:16], ad[15:0] ? 0 ? ns rdx ? ale time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 10 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 10 ? ns mb96340 series speci?ation 84 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm preliminary (t a =? 40 c to + 125 c, v cc = , v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l =50pf) valid address ? eclk time t avch a[23:16], eclk ? t cyc ? 15 ? ns t advch ad[15:0], eclk ? t cyc /2 ? 15 ? ns rdx ? eclk time t rlch rdx, clk ? t cyc /2 ? 10 ? ns ale ? rdx time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 10 ? ns eacl:sts=1 ? 10 ? ns eclk ? valid data input t chdv ad[15:0], eclk ?? t cyc ? 50 ns parameter sym- bol pin conditions value unit remarks min max ale pulse width t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 8 ? ns eacl:sts=1 t cyc ? 8 ? ns eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 8 ? ns valid address ? ale time t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 20 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 20 ? ns eacl:sts=0 and eacl:ace=1 2t cyc ? 20 ? ns eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 20 ? ns t advll ale,ad[15 :0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 20 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 20 ? ns eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 20 ? ns eacl:sts=1 and eacl:ace=1 2t cyc ? 20 ? ns ale ? address valid time t llax ale, ad[15 :0] eacl:sts=0 t cyc /2 ? 20 ? ns eacl:sts=1 -20 ? ns valid address ? rdx time t avrl rdx, a[23:16] eacl:ace=0 3t cyc /2 ? 20 ? ns eacl:ace=1 5t cyc /2 ? 20 ? ns valid address ? rdx time t advrl rdx,ad[15 :0] eacl:ace=0 t cyc ? 20 ? ns eacl:ace=1 2t cyc ? 20 ? ns valid address ? valid data input t avdv a[23:16], ad[15;0] eacl:ace=0 ? 3t cyc ? 60 ns w/o cycle extension eacl:ace=1 ? 4t cyc ? 60 ns valid address ? valid data input t advdv ad[15 :0] eacl:ace=0 ? 5t cyc /2 ? 60 ns w/o cycle extension; eacl:ace=1 ? 7t cyc /2 ? 60 ns rdx pulse width t rlrh rdx ? 3t cyc /2 ? 8 ? ns w/o cycle extension parameter sym- bol pin conditions value unit remarks min max speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm 85 preliminary preliminary preliminary refer to the hardware manual for detailed timing charts. rdx ? valid data input t rldv rdx, ad[15:0] ?? 3t cyc /2 ? 55 ns w/o cycle extension rdx ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns address valid ? data hold time t axdx a[23:16] ? 0 ? ns rdx ? ale time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 15 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 15 ? ns valid address ? eclk time t avch a[23:16], eclk ? t cyc ? 20 ? ns t advch ad[15:0], eclk ? t cyc /2 ? 20 ? ns rdx ? eclk time t rlch rdx, clk ? t cyc /2 ? 15 ? ns ale ? rdx time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 ? 15 ? ns eclk ? valid data input t chdv ad[15:0], eclk ?? t cyc ? 55 ns parameter sym- bol pin conditions value unit remarks min max a[23:16] ad[15:0] address vil vih vih vil read data t rhdx t rldv t advdv eclk t advch 0.8*vcc t rlch ale t lhll t rhlh 0.2*vcc t llax t advll rdx t llrl t rlrh t advrl t avch t avll t avdv t avrl t chdv t axdx mb96340 series speci?ation 86 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm preliminary bus timing (write) (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive =5ma,c l =50pf) (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l =50pf) parameter symbol pin condition value unit remarks min max valid address ? wrx time t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 3t cyc /2 ? 15 ? ns eacl:ace=1 5t cyc /2 ? 15 ? ns valid address ? wrx time t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 t cyc ? 15 ns eacl:ace=1 2t cyc ? 15 ns wrx pulse width t wlwh wrx, wrxl, wrhx ? t cyc ? 5 ? ns w/o cycle extension valid data output ? wrx time t dvwh wrx, wrlx, wrhx, ad[15:0] ? t cyc ? 20 ? ns w/o cycle extension wrx ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ? t cyc /2 ? 15 ? ns wrx ? address valid time t whax wrx, wrlx, wrhx, a[23:16] eacl:sts=0 t cyc /2 ? 15 ? ns wrx ? ale time t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 10 ? ns other ebm:ace and eacl:sts setting t cyc ? 10 ? ns wrx ? eclk time t wlch wrx, wrlx, wrhx, eclk ? t cyc /2 ? 10 ? ns wrx ? csn time t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ? 3t cyc /2 ? 15 ns eacl:ace=1 ? 5t cyc /2 ? 15 ns wrx ? csn time t whcsh wrx, wrlx, wrhx, csn eacl:sts=0 t cyc /2 ? 15 ? ns parameter symbol pin condition value unit remarks min max valid address ? wrx time t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 3t cyc /2 ? 20 ? ns eacl:ace=1 5t cyc /2 ? 20 ? ns valid address ? wrx time t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 t cyc ? 20 eacl:ace=1 2t cyc ? 20 speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm 87 preliminary preliminary preliminary wrx pulse width t wlwh wrx, wrlx, wrhx ? t cyc ? 8 ? ns w/o cycle extension valid data output ? wrx time t dvwh wrx, wrlx, wrhx, ad[15:0] ? t cyc ? 25 ? ns w/o cycle extension wrx ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ? t cyc /2 ? 20 ? ns wrx ? address valid time t whax wrx, wrlx, wrhx, a[23:16] eacl:sts=0 t cyc /2 ? 20 ? ns wrx ? ale time t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 15 ? ns other ebm:ace and eacl:sts setting t cyc ? 15 ? ns wrx ? eclk time t wlch wrx, wrlx, wrhx, eclk ? t cyc /2 ? 15 ? ns csn ? wrx time t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ? 3t cyc /2 ? 20 ns eacl:ace=1 ? 5t cyc /2 ? 20 ns wrx ? csn time t whcsh wrx, wrlx, wrhx, csn eacl:sts=0 t cyc /2 ? 20 ? ns parameter symbol pin condition value unit remarks min max mb96340 series speci?ation 88 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm preliminary refer to the hardware manual for detailed timing charts. ready input timing (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive =5ma,c l =50pf) (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l =50pf) note : if the rdy setup time is insuf cient, use the auto-ready function. parameter sym- bol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 35 ? ns rdy hold time t ryhh rdy 0 ? ns parameter sym- bol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns rdy hold time t ryhh rdy 0 ? ns eclk t wlch 0.8*vcc ale t whlh wrx (wrlx, wrhx) t wlwh t advwl a[23:16] t whax ad[15:0] address write data t dvwh t whdx csn t whcsh t avwl t cslwl 0.2*vcc speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm 89 preliminary preliminary preliminary refer to the hardware manual for detailed timing charts. hold timing (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive =5ma,c l =50pf) (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l =50pf) refer to the hardware manual for detailed timing charts. parameter symbol pin condition value units remarks min max pin floating ? hakx time t xhal hakx ? t cyc ? 20 t cyc + 20 ns hakx time ? pin valid time t hahv hakx t cyc ? 20 t cyc +20 ns parameter symbol pin condition value units remarks min max pin floating ? hakx time t xhal hakx ? t cyc ? 25 t cyc +25 ns hakx time ? pin valid time t hahv hakx t cyc ? 25 t cyc +25 ns eclk rdy when wait is not used. vih vih t ryhh rdy when wait is used. t ryhs vil 0.8*vcc hakx each pin high-z t hahv t xhal 0.8*vcc 0.2*vcc 0.8*vcc 0.2*vcc mb96340 series speci?ation 90 fme/emdc- 2007-9-12 mb96300_ds_el_ac_ext_bus.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_usart.fm 73 preliminary preliminary preliminary usart timing (t a = -40 ? c to 125 ? c, v cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v, io drive =5ma, c l =50pf) notes: ? ac characteristic in clk synchronized mode. ? c l is load capacity value of pins when testing. ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in mb96300 super series hardware manual ? t clkp1 is the cycle time of the peripheral clock 1 (clkp1), unit : ns *1: parameter n depends on t scyci and can be calculated as: if t scyci = 2*k*t clkp1 , then n = k, where k is an integer > 2 if t scyci = (2*k+1)*t clkp1 , then n = k+1, where k is an integer > 1 examples: parameter symbol pin condition v cc =av cc = 4.5v to 5.5v v cc =av cc = 3.0v to 4.5v unit min max min max serial clock cycle time t scyci sckn internal shift clock mode 4 t clkp1 ? 4 t clkp1 ? ns sck sot delay time t slovi sckn, sotn -20 + 20 -30 + 30 ns sot sck delay time t ovshi sckn, sotn n*t clkp1 - 20 *1 ? n*t clkp1 - 30 *1 ? valid sin sck t ivshi sckn, sinn t clkp1 + 45 ? t clkp1 + 55 ? ns sck valid sin hold time t shixi sckn, sinn 0 ? 0 ? ns serial clock l pulse width t slshe sckn external shift clock mode t clkp1 + 10 ? t clkp1 + 10 ? ns serial clock h pulse width t shsle sckn t clkp1 + 10 ? t clkp1 + 10 ? ns sck sot delay time t slove sckn, sotn ? 2 t clkp1 + 45 ? 2 t clkp1 + 55 ns valid sin sck t ivshe sckn, sinn t clkp1 /2 + 10 ? t clkp1 /2 + 10 ? ns sck valid sin hold time t shixe sckn, sinn t clkp1 + 10 ? t clkp1 + 10 ? ns sck fall time t fe sckn ? 20 ? 20 ns sck rise time t re sckn ? 20 ? 20 ns t scyci n 4*t clkp1 2 5*t clkp1, 6*t clkp1 3 7*t clkp1, 8*t clkp1 4 ... ... mb96340 series speci?ation 74 fme/emdc- 2007-9-12 mb96300_ds_el_ac_usart.fm preliminary internal shift clock mode sot t slovi sin vil vih t ivshi vil vih t shixi t ovshi sck for escr:sces = 0 0.8*vcc t scyci sck for escr:sces = 1 0.8*vcc 0.8*vcc 0.2*vcc 0.2*vcc 0.2*vcc 0.8*vcc 0.2*vcc external shift clock mode t fe vil vil vil vil sot t slove sin vil vih t ivshe vil vih t shixe vih t re vih t slshe vil vih t shsle vih vih sck for escr:sces = 0 sck for escr:sces = 1 0.8*vcc 0.2*vcc speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_i2c.fm 95 preliminary preliminary preliminary i 2 c timing (t a = -40 ? c to 125 ? c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) *1 : r,c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hddat have only to be met if the device does not stretch the l width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. *4 : for use at over 100 khz, set the peripheral clock 1 to at least 6 mhz. parameter symbol condition standard-mode fast-mode* 4 unit min max min max scl clock frequency f scl r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? s l width of the scl clock t low 4.7 ? 1.3 ? s h width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45* 2 0 0.9* 3 s data set-up time sda scl t sudat 250 ? 100 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between a stop and start condition t bus 4.7 ? 1.3 ? s sda scl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto mb96340 series speci?ation 96 fme/emdc- 2007-9-12 mb96300_ds_el_ac_i2c.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_adc.fm 75 preliminary preliminary preliminary 5. analogue digital converter (t a = -40 ? c to +125 ? c, 3.0 v avrh - avrl, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) *1: if a/d converter is not operating, a current when cpu is stopped is applicable (vcc = avcc = avrh = 5.0 v) . note : the accuracy gets worse as avrh - avrl becomes smaller. de?ition of a/d converter terms resolution: analog variation that is recognized by an a/d converter. non linear ity error : deviation between a line across zero-transition line ( 00 0000 0000 <--> 00 0000 0001 ) and full-scale transition line ( 11 1111 1110 <--> 11 1111 1111 ) and actual conversion characteristics. parameter symbol pin value unit remarks min typ max resolution - - - - 10 bit total error - - -3 - +3 lsb nonlinearity error - - -2.5 - +2.5 lsb differential nonlineari- ty error - - -1.9 - +1.9 lsb zero reading voltage v ot ann avrl - 1.5 avrl+ 0.5 avrl + 2.5 lsb full scale reading voltage v fst ann avrh - 3.5 avrh - 1.5 avrh + 0.5 lsb compare time - - 1.0 - 16,500 s 4.5v v cc 5.5v 2.0 - - s 3.0v v cc < 4.5v sampling time - - 0.5 - - s 4.5v v cc 5.5v 1.2 - - s 3.0v v cc < 4.5v analog port input cur- rent i ain ann -1 - +1 at a = 25 ? c -3 - +3 at a = 125 ? c analog input voltage range v ain ann avrl - avrh v reference voltage range avrh avrh/ avrh2 0.75 avcc - avcc v avrl avrl av ss - 0.25 av cc v power supply current i a avcc - 2.5 5 ma ac converter active i ah avcc - - 5 a ad converter not operated *1 reference voltage cur- rent i r avrh/ avrl - 0.7 1 ma ac converter active i rh avrh/ avrl --5 a ad converter not operated offset between input channels - ann - - tbd lsb mb96340 series speci?ation 76 fme/emdc- 2007-9-12 mb96300_ds_el_adc.fm preliminary diff erential linear ity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. t otal error : difference between an actual value and an ideal value. a total error includes zero transition error, full-scale transition error, and linear error. zero reading v oltage: input voltage which results in the minimum conversion value. full scale reading v oltage: input voltage which results in the maximum conversion value. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error of digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avrh ? avrl 1024 [v] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh ? 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n ? 1) to n. total error speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_adc.fm 77 preliminary preliminary preliminary notes on a/d converter section about the e xternal impedance of the analog input and its sampling time a/d converter with sample and hold circuit. if the external impedance is too high to keep suf cient sampling time, the analog voltage charged to the internal sample and hold capacitor is insuf cient, adversely affecting a/ d conversion precision. 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) non linearity error differential linearity error non linearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at which digital output transits from 000 h to 001 h . v fst : voltage at which digital output transits from 3fe h to 3ff h . mb96340 series speci?ation 78 fme/emdc- 2007-9-12 mb96300_ds_el_adc.fm preliminary to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time (t samp ) is longer than the minimum value. usually, this value is set to 7 , where = rc. if you include the external input resistance (r ext ) connected to the analog input, the sampling time is expressed: t samp [min] = 7.(r ext + r).c if the sampling time cannot be suf cient, connect a capacitor of about 0.1 mf to the analog input pin. about the error the accuracy gets worse as |avrh - avrl| becomes smaller. analog input circuit model: comparator sampling switch r c analog input reference values: r = 2.6 k ? (max) c = 8.5 pf (max) speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_alarm.fm 101 preliminary preliminary preliminary 6. alarm comparator (t a = -40 ? c to +125 ? c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max power supply current i a5almf av cc -2540 a alarm comparator enabled in fast mode (one channel) i a5alms -710 a alarm comparator enabled in slow mode (one channel) i a5almh --5 a alarm comparator disabled alarm pin input cur- rent i alin alarm0, alarm1 -1 - +1 at a = 25 ? c -3 - +3 at a = 125 ? c alarm pin input volt- age range v alin 0-av cc v external low threshold v evtl 0.36 * av cc -5% 0.36 * av cc 0.36 * av cc +5% v intref=0 external high threshold v evth 0.78 * av cc -3% 0.78 * av cc 0.78 * av cc +3% v intref=0 internal low threshold v ivtl 1.15 1.25 1.35 v intref=1 internal high threshold v ivth 2.45 2.55 2.65 v intref=1 switching hysteresis v hys 50 - 250 mv comparison time t compf - 0.1 - s cmd=1 (fast) t comps - - 100 s cmd=0 (slow) comparator output v evtl, v evth v ivtl, v ivth v hys v alin h l mb96340 series speci?ation 102 fme/emdc- 2007-9-12 mb96300_ds_el_alarm.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_lvd_char.fm 105 preliminary preliminary preliminary 7. low voltage detector characteristics (t a = -40 ? c to +125 ? c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max power consumptiont i cclvd v cc - 75 100 a level 0 v dl0 2.7 - 2.95 v level 1 v dl1 2.9 - 3.2 v level 2 v dl2 3.1 - 3.4 v level 3 v dl3 3.5 - 3.85 v level 4 v dl4 3.6 - 3.95 v level 5 v dl5 3.7 - 4.05 v level 6 v dl6 3.8 - 4.15 v level 7 v dl7 3.9 - 4.3 v level 8 v dl8 4.0 - 4.4 v level 9 v dl9 4.1 - 4.5 v level 10 v dl10 not supported for this device level 11 v dl11 level 12 v dl12 level 13 v dl13 level 14 v dl14 level 15 v dl15 speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_lvd_char.fm 106 preliminary preliminary preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_ac_flash.fm 107 preliminary preliminary preliminary 8. flash memory program/erase characteristics ( t a = 25 o c , vcc = 5.0v) *1: this value was converted from the results of evaluating the reliability of the technology (using arrhenius equation to convert high temperature measurements into into normalized value at 85 o c)) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s erasure programming time not included chip erase time - n*0.9 n*3.6 s n is the number of flash sector of the device word (16-bit width) pro- gramming time - 23 370 us system overhead time not in- cluded programme/erase cycle 10 000 cycle 100 000 cycles for t j < 105 o c flash data retention time 20 year *1 mb96340 series speci?ation 108 fme/emdc- 2007-9-12 mb96300_ds_el_ac_flash.fm preliminary speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_example_char.fm 109 preliminary preliminary preliminary example characteristics the diagrams below show the characteristics of one measured sample of mb96f348hsb with typical process parameters. run mode 0.01 0.10 1.00 10.00 100.00 -50.00 0.00 50.00 100.00 150.00 ta [oc] icc [ma] main osc. (4 mhz) rc clock (2 mhz) rc clock (100 khz) sub osc.(32 khz) pll clock (56 mhz) sleep mode 0.01 0.10 1.00 10.00 100.00 -50.00 0.00 50.00 100.00 150.00 ta [oc] icc [ma] main osc. (4 mhz) rc clock (100 khz) sub osc.(32 khz) rc clock (2 mhz) pll clock (56 mhz) speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_example_char.fm 110 preliminary preliminary preliminary timer mode 0.01 0.10 1.00 10.00 -50.00 0.00 50.00 100.00 150.00 ta [oc] icc [ma] main osc. (4 mhz) rc clock (100 khz) sub osc. (32 khz) pll clock (56 mhz) rc clock (2 mhz) stop mode 0.00 0.01 0.10 1.00 -50.00 0.00 50.00 100.00 150.00 ta [oc] icc [ma] speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_example_char.fm 111 preliminary preliminary preliminary used settings mode selected source clock clock/regulator settings run mode pll clks1 = clks2 = clkb = clkp1 = 56 mhz clkp2 = 28 mhz regulator in high power mode core voltage = 1.9 v main osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 4 mhz regulator in high power mode core voltage = 1.8 v rc clock fast clks1 = clks2 = clkb = clkp1 = clkp2 = 2 mhz regulator in high power mode core voltage = 1.8 v rc clock slow clks1 = clks2 = clkb = clkp1 = clkp2 = 100 khz regulator in high power mode core voltage = 1.8 v sub osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 32 khz regulator in low power mode a core voltage = 1.8 v sleep mode pll clks1 = clks2 = clkp1 = 56 mhz clkp2 = 28 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.9 v main osc. clks1 = clks2 = clkp1 = clkp2 = 4 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v rc clock fast clks1 = clks2 = clkp1 = clkp2 = 2 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v rc clock slow clks1 = clks2 = clkp1 = clkp2 = 100 khz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v sub osc. clks1 = clks2 = clkp1 = clkp2 = 32 khz (clkb is stopped in this mode) regulator in low power mode a core voltage = 1.8 v speci?ation mb96340 fme/emdc- 2007-9-12 mb96300_ds_el_example_char.fm 112 preliminary preliminary preliminary timer mode pll clkmc = 4 mhz, clkpll = 56 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.9 v main osc. clkmc = 4 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v rc clock fast clkrc = 2 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v rc clock slow clkrc = 100 khz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v sub osc. clksc = 100 khz (system clocks are stopped in this mode) regulator in low power mode a, core voltage = 1.8 v stop mode stopped (all clocks are stopped in this mode) regulator in low power mode b used settings mode selected source clock clock/regulator settings speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_package.fm 113 preliminary preliminary preliminary package dimension mb96(f)34x lqfp 100p 100-pin plastic lqfp lead pitch 0.50 mm package width package length 14.0 mm 14.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin plastic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 fujitsu limited f100031s-c-2-1 14.00 0.10(.551 .004)sq 16.000.20(.630.008)sq 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.008 .002) m 0.08(.003) 0.145 0.055 (.0057 .0022) 0.08(.003) "a" index .059 .004 +.008 0.10 +0.20 1.50 (mounting height) 0 ? ~8 ? (0.50(.020)) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) details of "a" part (stand off) * dimensions in mm (inches). note: the values in parentheses are reference values mb96340 series speci?ation 114 fme/emdc- 2007-9-12 mb96340_ds_package.fm preliminary package dimension mb96(f)34x qfp 100p 100-pin plastic qfp lead pitch 0.65 mm package width package length 14.00 20.00 mm lead shape gullwing sealing method plastic mold mounting height 3.35 mm max code (reference) p-qfp100-14 20-0.65 100-pin plastic qfp (fpt-100p-m22) ( fpt-100p-m06 ) (fpt-100p-m22) c 2002 fujitsu limited f100008s-c-5-5 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 0.20 +.014 .008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 ? * * dimensions in mm (inches). note: the values in parentheses are reference values. speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_order.fm 115 preliminary preliminary preliminary ordering information mcu with can controller part number satellite ?sh memory subclock persistant low volt- age reset package remarks mb96f346ysa pqc-gse2 no no yes 100 pin plastic qfp (fpt-100p-m22) mb96f346rsa pqc-gse2 no mb96f346ywa pqc-gse2 yes yes mb96f346rwa pqc-gse2 no mb96f346ysa pmc-gse2 no yes 100 pin plastic lqfp (fpt-100p-m20) mb96f346rsa pmc-gse2 no mb96f346ywa pmc-gse2 yes yes mb96f346rwa pmc-gse2 no mb96f347ysa pqc-gse2 no no yes 100 pin plastic qfp (fpt-100p-m22) mb96f347rsa pqc-gse2 no mb96f347ywa pqc-gse2 yes yes mb96f347rwa pqc-gse2 no mb96f347ysa pmc-gse2 no yes 100 pin plastic lqfp (fpt-100p-m20) mb96f347rsa pmc-gse2 no mb96f347ywa pmc-gse2 yes yes mb96f347rwa pmc-gse2 no mb96f348tsb pqc-gse2 yes no yes 100 pin plastic qfp (fpt-100p-m22) mb96f348hsb pqc-gse2 no mb96f348twb pqc-gse2 yes yes mb96f348hwb pqc-gse2 no mb96f348tsb pmc-gse2 no yes 100 pin plastic lqfp (fpt-100p-m20) mb96f348hsb pmc-gse2 no mb96f348twb pmc-gse2 yes yes mb96f348hwb pmc-gse2 no mb96v300brb-es emulated by ext. ram yes no 416 pin plastic bga (bga416-m02) for evalua- tion mb96340 series speci?ation 116 fme/emdc- 2007-9-12 mb96340_ds_order.fm preliminary mcu without can controller part number satellite ?sh memory subclock package remarks mb96f346asa pqc-gse2 no no 100 pin plastic qfp (fpt-100p-m22) mb96f346awa pqc-gse2 yes mb96f346asa pmc-gse2 no 100 pin plastic lqfp (fpt-100p-m20) mb96f346awa pmc-gse2 yes mb96f347asa pqc-gse2 no no 100 pin plastic qfp (fpt-100p-m22) mb96f347awa pqc-gse2 yes mb96f347asa pmc-gse2 no 100 pin plastic lqfp (fpt-100p-m20) mb96f347awa pmc-gse2 yes mb96f348asa pqc-gse2 no no 100 pin plastic qfp (fpt-100p-m22) mb96f348awa pqc-gse2 yes mb96f348asa pmc-gse2 no 100 pin plastic lqfp (fpt-100p-m20) mb96f348awa pmc-gse2 yes mb96f348csb pqc-gse2 yes no 100 pin plastic qfp (fpt-100p-m22) mb96f348cwb pqc-gse2 yes mb96f348csb pmc-gse2 no 100 pin plastic lqfp (fpt-100p-m20) mb96f348cwb pmc-gse2 yes speci?ation mb96340 fme/emdc- 2007-9-12 mb96340_ds_revisions.fm 117 preliminary preliminary preliminary revision history revision date modi cation 1 2007-05-07 creation 2 2007-05-10 external bus hold timing update 3 2007-05-23 electrical characteristics updates 4 2007-08-02 electrical characteristics updates, product lineup, changes and ordering information 5 2007-09-12 addition of the electrical charcateristic examples and the lvd characteristics speci cations, updates of the dc charcateristics. pin circuit type drawing modi cations. mb96340 series speci?ation 118 fme/emdc- 2007-9-12 mb96340_ds_revisions.fm preliminary |
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