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3.3 v dual-loop 50 mbps to 1.25 gbps laser diode driver adn2848 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 50 mbps to 1.25 gbps operation single 3.3 v operation bias current range: 2 to 100 ma modulation current range: 5 to 80 ma monitor photo diode curr ent: 50 a to 1200 a 50 ma supply current at 3.3 v closed-loop control of power and extinction ratio full current parameter monitoring laser fail and laser degrade alarms automatic laser shutdown (als) optional clocked data supports fec rates 32-lead, 5 mm 5 mm lfcsp_vq package applications sonet oc-1/3/12/24 sdh stm-0/1/4 fibre channel gigabit ethernet general description the adn2848 uses a unique control algorithm to control both the average power and the extinction ratio of the laser diode (ld) after initial factory setup. external component count and pcb area are low because both power and extinction ratio control are fully integrated. programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail). functional block diagram v cc gnd gnd v cc ld gnd datap datan clkp clkn imodp i bias aset adn2848 i bias i mod gnd gnd control impd pset erset lbwset ercap pavcap gnd v cc clksel imodn v cc degrade fail als impdmon immon ibmon mpd 02746-001 v cc r z figure 1.
adn2848 rev. a | page 2 of 12 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 theory of operation ........................................................................ 7 control........................................................................................... 7 loop bandwidth selection .......................................................... 7 alarms.............................................................................................7 monitor currents ..........................................................................8 data and clock inputs..................................................................8 ccbias...........................................................................................8 i bias ...................................................................................................8 automatic laser shutdown..........................................................8 alarm interfaces ............................................................................8 power consumption .....................................................................9 laser diode interfacing................................................................9 optical supervisor.........................................................................9 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 8/06rev. 0 to rev. a updated format..................................................................universal changes to figure 1.......................................................................... 1 changes to specifications ................................................................ 3 changes to figure 8........................................................................ 10 changes to figure 9 to figure11................................................... 11 updated outline dimensions ....................................................... 12 changes to ordering guide .......................................................... 12 1/03revision 0: initial version
adn2848 rev. a | page 3 of 12 specifications v cc = 3.0 v to 3.6 v. all specifications t min to t max , unless otherwise noted. 1 typical values are specified at 25c. table 1. parameter min typ max unit conditions/comments laser bias current (i bias , als) output current i bias 2 100 ma compliance voltage 1.2 v cc v i bias i bias 0.1 ma when als asserted als response time 5 s i bias < 10% of nominal ccbias compliance voltage 1.2 v cc v modulation current (imodp, imodn) output current i mod 5 80 ma compliance voltage 1.5 v cc v i mod 0.1 ma when als asserted rise time 2 80 170 ps fall time 2 80 170 ps random jitter 2 1 1.5 ps rms pulse width distortion 2 15 ps i mod = 40 ma monitor pd (mpd) current 50 1200 a average current compliance voltage 1.65 v power set input (pset) capacitance 80 pf monitor photodiode current into rpset resistor 50 1200 a average current voltage 1.1 1.2 1.3 v extinction ratio set input (erset) allowable resistance range 1.2 25 k voltage 1.1 1.2 1.3 v alarm set (aset) allowable resistance range 1.2 25 k voltage 1.1 1.2 1.3 v hysteresis 5 % control loop low loop bandwidth selection time constant 0.22 sec lbwset = gnd 2.25 sec lbwset = v cc data inputs (datap, datan, clkp, clkn) 3 v p-p (single-ended, peak-to-peak) 100 500 mv data and clock inputs are input impedance (single-ended) 50 ac-coupled t setup 4 50 ps see figure 2 t hold 4 100 ps see figure 2 logic inputs (als, lbwset, clksel) v ih 2.4 v v il 0.8 v alarm outputs (fail, degrade) internal 30 k pull-up v oh 2.4 v v ol 0.8 v ibmon, immon, impdmon immon division ratio 100 a/a impdmon 1 a/a compliance voltage 0 v cc ? 1.2 v
adn2848 rev. a | page 4 of 12 parameter min typ max unit conditions/comments supply i cc 5 50 ma i bias = i mod = 0 v cc 6 3.0 3.3 3.6 v 1 temperature range is ?40c to +85c. 2 measured into a 25 load us ing a 0-1 pattern at 622 mbps. 3 when the voltage on datap is greater than the voltage on datan, the modulation current flows in the imodp pin. 4 guaranteed by design and characterization. not production tested. 5 i ccmin for power calculation on page 9 is the typical i cc given. 6 all v cc pins should be shorted together. t s t h setup hold datap/datan clkp 02746-002 figure 2. setup and hold time
adn2848 rev. a | page 5 of 12 absolute maximum ratings table 2. parameter rating v cc to gnd 4.2 v digital inputs (als, lbwset, clksel) ?0.3 v to v cc + 0.3 v imodn, imodp v cc + 1.2 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c 32-lead lfcsp_vq package power dissipation 1 (t j max C t a )/ ja w ja thermal impedance 2 32c/w lead temperature (soldering for 10 sec) 300c 1 power consumption formulas are provided on page 9. 2 ja is defined when device is soldered in a 4-layer board. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adn2848 rev. a | page 6 of 12 pin configuration and fu nction descriptions pin 1 indicator top view (not to scale) 24 ibmon 23 immon 22 gnd3 21 v cc 3 lbwset 1 aset 2 erset 3 32 ccbias 20 als 19 fail 18 degrade 17 clksel 9 10 11 12 13 14 15 16 pset 4 impd 5 impdmon 6 gnd4 7 v cc 48 31 i bias 30 gnd2 29 gnd2 28 imodp 27 gnd2 26 imodn 25 v cc 2 adn2848 ercap pavcap v cc 1 datan datap gnd1 clkp clkn 02746-003 figure 3. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 lbwset loop bandwidth select. 2 aset alarm threshold set pin. 3 erset extinction ratio set pin. 4 pset average optical power set pin. 5 impd monitor photodiode input. 6 impdmon mirrored current from monitor photodiodecurrent source. 7 gnd4 supply ground. 8 v cc 4 supply voltage. 9 ercap extinction ratio loop capacitor. 10 pavcap average power loop capacitor. 11 v cc 1 supply voltage. 12 datan data negative differential terminal. 13 datap data positive differential terminal. 14 gnd1 supply ground. 15 clkp data clock positive differential terminal. this pin is used if clksel = v cc . 16 clkn data clock negative differential terminal. this pin is used if clksel = v cc . 17 clksel clock select (active = v cc ). this pin is used if data is clocked into chip. 18 degrade degrade alarm output. 19 fail fail alarm output. 20 als automatic laser shutdown. 21 v cc 3 supply voltage. 22 gnd3 supply ground. 23 immon modulation current mirror outputcurrent source. 24 ibmon bias current mirr or outputcurrent source. 25 v cc 2 supply voltage. 26 imodn modulation current negative output. connect this pin via a matching resistor to v cc . 27 gnd2 supply ground. 28 imodp modulation current positive output. connect this pin to the laser diode. 29, 30 gnd2 supply ground. 31 i bias laser diode bias currentcurrent sink. 32 ccbias connected to vcc when dc-coupled to laser diode; connected to i bias when ac-coupled to laser diodecurrent sink.
adn2848 rev. a | page 7 of 12 theory of operation a laser diode (ld) has current-in to light-out transfer functions, as shown in figure 4. two key characteristics of this transfer function are the threshold current, i th , and slope in the linear region beyond the threshold current, referred to as slope efficiency, or li. p1 p av p0 optical power i th p i current li = p i er = p1 p0 p av = p1 + p0 2 0 2746-004 figure 4. laser transfer function control a monitor photodiode, mpd, is required to control the ld. the mpd current is fed into the adn2848 to control the power and extinction ratio, continuously adjusting the bias current and modulation current in response to the lasers changing threshold current and light-to-current slope efficiency. the adn2848 uses automatic power control, apc, to maintain a constant average power over time and temperature. the adn2848 uses closed-loop extinction ratio control to allow optimum setting of extinction ratio for every device. thus, sonet/sdh interface standards can be met over device variation, temperature, and laser aging. closed-loop modulation control eliminates the need to either overmodulate the ld or include external components for temperature compensation. this reduces research and development time and second sourcing issues caused by characterizing lds. average power and extinction ratio are set using the pset and erset pins, respectively. potentiometers are connected between these pins and ground. the potentiometer r pset is used to change the average power. the potentiometer r erset is used to adjust the extinction ratio. both pset and erset are kept 1.2 v above gnd. for an initial setup, r pset and r erset potentiometers can be calculated using the following formulas: () = av pset i r v2.1 () + ? = av cw cwmpd erset p er er p i r 1 1 v2.1 _ where: i av is the average mpd current. p cw is the dc optical power specified on the laser data sheet. i mpd_cw is the mpd current at that specified p cw . p av is the average power required. er is the desired extinction ratio (er = p1/p0). note that i erset and i pset change from device to device; however, the control loops determine the actual values. it is not required to know the exact values for li or mpd optical coupling. loop bandwidth selection for continuous operation, the user hardwires the lbwset pin high and uses 1 f capacitors to set the actual loop bandwidth. these capacitors are placed between the pavcap and ercap pins and ground. it is important that these capacitors are low leakage multilayer ceramics with an insulation resistance greater than 100 g or a time constant of 1000 seconds, whichever is less. setting lbset low and using 47 nf capacitors results in a shorter loop time constant (a 10 reduction over using 1 f capacitors and keeping lbwset high). table 4. operation mode lbwset recommended pavcap recommended ercap continuous 50 mbps to 1.25 gbps high 1 f 1 f optimized for 1.25 gbps low 47 nf 47 nf alarms the adn2848 is designed to allow interface compliance to itu-t-g958 (11/94), section 10.3.1.1.2 (transmitter fail) and section 10.3.1.1.3 (transmitter degrade). the adn2848 has two active high alarms, degrade and fail. a resistor between ground and the aset pin is used to set the current at which these alarms are raised. the current through the aset resistor is a ratio of 100:1 to the fail alarm threshold. the degrade alarm is raised at 90% of this level.
adn2848 rev. a | page 8 of 12 example: ma45 ma50 = = degrade fail iso i a500 100 ma50 100 === fail aset i i k ? 4.2 a500 2.1v2.1 * === aset aset i r *the smallest valid value for r aset is 1.2 k, because this corresponds to the i bias maximum of 100 a. the laser degrade alarm, degrade, is provided to give a warning of imminent laser failure if the laser diode degrades further or if environmental conditions such as increasing temperature continue to stress the ld. the laser fail alarm, fail, is activated when the transmitter can no longer be guaranteed to be sonet/sdh compliant. this occurs when one of the following conditions arise: ? the aset threshold is reached. ? the als pin is set high. this shuts off the modulation and bias currents to the ld, resulting in the mpd current dropping to zero. this gives closed-loop feedback to the system that als has been enabled. degrade is raised only when the bias current exceeds 90% of aset current. monitor currents ibmon, immon, and impdmon are current controlled current sources from v cc . they mirror the bias, modulation, and mpd current for increased monitoring functionality. an external resistor to gnd gives a voltage proportional to the current monitored. if the monitoring function impdmon is not required, the impd pin must be grounded and the monitor photodiode output must be connected directly to the pset pin. data and clock inputs data and clock inputs are ac-coupled (10 nf capacitors recommended) and terminated via a 100 internal resistor between datap and datan and also between the clkp and clkn pins. there is a high impedance circuit to set the common-mode voltage, which is designed to allow for maximum input voltage headroom over temperature. it is necessary that ac coupling be used to eliminate the need for matching between common-mode voltages. adn2848 to flip-flops 50 50 v reg r r = 2.5k , data r = 3k , clk 400a tp datap datan 02746-005 figure 5. ac coupling of data inputs for input signals that exceed 500 mv p-p single-ended, it is necessary to insert an attenuation circuit as shown in figure 6. 02746-006 datap/clkp datan/clkn r3 r1 r2 r in adn2848 note that r in = 100 ? = the differential input impedance of the adn2848. figure 6. attenuation circuit ccbias when the laser is used in ac-coupled mode, the ccbias pin and the i bias pin are tied together (see figure 9). in dc-coupled mode, ccbias is tied to v cc . i bias to achieve optimum optical eye quality, a pull-up resistor r z , as shown in figure 8 and figure 9, is required. the recommended r z value is approximately 200 ~ 500 . automatic laser shutdown the adn2848 als allows compliance to itu-t-g958 (11/94), section 9.7. when als is logic high, both the bias and the modulation currents are turned off. correct operation of als is confirmed by the fail alarm being raised when als is asserted. note that this is the only time that degrade is low while fail is high. alarm interfaces the fail and degrade outputs have an internal 30 k pull- up resistor that is used to pull the digital high value to v cc . however, the alarm output can be overdriven with an external resistor, allowing alarm interfacing to non-v cc levels. non-v cc alarm output levels must be below the v cc used for the adn2848.
adn2848 rev. a | page 9 of 12 power consumption the adn2848 die temperature must be kept below 125c. the lfcsp_vq package has an exposed paddle. the exposed paddle should be connected in such a manner that it is at the same potential as the adn2848 ground pins. the ja for the package is shown under the absolute maximum ratings. power consumption can be calculated using i cc = i ccmin + 0.3 i mod p = v cc i cc + (i bias v bias_pin ) + i mod (v modp_pin + v modn_pin )/2 t die = t ambient + ja p thus, the maximum combination of i bias + i mod must be calculated where: i ccmin = 50 ma, the typical value of i cc provided on page 3 with i bias = i mod = 0. t die = die temperature. t ambient = ambient temperature. v bias_pin = voltage at i bias pin. v modp_pin = average voltage at imodp pin. v modn_pin = average voltage at imodn pin. laser diode interfacing many laser diodes designed for 1.25 gbps operation are packaged with an internal resistor to bring the effective impedance up to 25 in order to minimize transmission line effects. in high current applications, the voltage drop across this resistor, combined with the laser diode forward voltage, makes direct connection between the laser and the driver impractical in a 3 v system. ac coupling the driver to the laser diode removes this headroom constraint. caution must be used when choosing component values for ac coupling to ensure that the time constants (l/r and rc, see figure 9) are sufficiently long for the data rate and the expected number of cids (consecutive identical digits). failure to do this could lead to pattern dependent jitter and vertical eye closure. for designs with low series resistance, or where external components become impractical, the adn2848 supports direct connection to the laser diode (see figure 8). in this case, care must be taken to ensure that the voltage drop across the laser diode does not violate the minimum compliance voltage on the imodp pin. optical supervisor the pset and erset potentiometers can be replaced with a dual digital potentiometer, the adn2850 (see figure 7). the adn2850 provides an accurate digital control for the average optical power and extinction ratio and ensures excellent stability over temperature. v cc v cc adn2848 impd pset erset datap datan idtone imodp i bias datap datan idtone sdi sdo clk cs dac1 dac2 adn2850 v cc tx rx clk cs 02746-007 figure 7. application using the adn2850 dual 10-bit digital potentiometer with extremely low temperature coefficient as an optical supervisor
adn2848 rev. a | page 10 of 12 v cc 2 imodn gnd2 imodp gnd2 gnd2 i bias ccbias clkn clkp gnd1 datap datan v cc 1 pavcap ercap lbwset aset ibmon immon fail degrade erset pset impd impdmon gnd4 v cc 4 gnd3 v cc 3 als fail degrade clksel a ls 1k? 1.5k ? 15k ? 17 24 25 32 v c c v c c v c c 10h ld mpd * * * * ** ** 18 1.5k ? 9 16 1f 1f 10nf 10nf 10nf 10nf clkn clkp datap datan 10nf 10nf 10nf 10nf 10f v c c gnd each v cc should have bypass capacitors as close as possible to the actual supply pins on the adn2848 and the laser diode used. conservative decoupling would include 100pf capacitors in parallel with 10nf capacitors. ld = laser diode mpd = monitor photodiode notes designates components that need to be optimized for the type of laser used. for digital programming. the adn2850 or the adn2860 optical supervisor can be used. * ** adn2848 02746-008 + v cc r z figure 8. dc-coupled 50 mbps to 1.25 gbps test circuit, data not clocked
adn2848 rev. a | page 11 of 12 v cc 2 imodn gnd2 imodp gnd2 gnd2 i bias ccbias clkn clkp gnd1 datap datan v cc 1 pavcap ercap lbwset aset ibmon immon fail degrade erset pset impd impdmon gnd4 v cc 4 gnd3 v cc 3 als fail degrade clksel als 1k? 1.5k ? 15k ? 17 24 25 32 v cc v c c v c c 10h ld v cc mpd * * * ** ** 18 1.5k ? 9 16 1f 1f 10nf 10nf 10nf 10nf clkn clkp datap datan 10nf 10nf 10nf 10nf 10f v c c gnd each v cc should have bypass capacitors as close as possible to the actual supply pins on the adn2848 and the laser diode used. conservative decoupling would include 100pf capacitors in parallel with 10nf capacitors. ld = laser diode mpd = monitor photodiode notes designates components that need to be optimized for the type of laser used. for digital programming. the adn2850 or the adn2860 optical supervisor can be used. * ** adn2848 * * * * * * 02746-009 + r z figure 9. ac-coupled 50 mbps to 1.25 gbps test circuit, data not clocked 02746-010 figure 10. a 1.244 mbps optical eye. temperature at 25c. average power = 0 dbm, extinction ratio = 10 db, prbs 31 pattern, 1 gb ethernet mask. eye ob tained using a dfb laser. 02746-011 figure 11. a 1.244 mbps optical eye. temperature at 85c. average power = 0 dbm, extinction ratio = 10 dbm, prbs 31 pattern, 1 gb ethernet mask. eye obtained using a dfb laser.
adn2848 rev. a | page 12 of 12 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 12. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model temperature range package description package option adn2848acp-32 C40c to +85c 32-lead lfcsp_vq cp-32-2 adn2848acp-32-rl C40c to +85c 32-lead lfcsp_vq cp-32-2 adn2848acp-32-rl7 C40c to +85c 32-lead lfcsp_vq cp-32-2 adn2848acpz-32 1 C40c to +85c 32-lead lfcsp_vq cp-32-2 ADN2848ACPZ-32-RL 1 C40c to +85c 32-lead lfcsp_vq cp-32-2 ADN2848ACPZ-32-RL7 1 C40c to +85c 32-lead lfcsp_vq cp-32-2 1 z = pb-free part. ?2006 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. c02746-0-10/06(a)

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