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rev. a a adp3330 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. high accuracy ultralow i q , 200 ma, sot-23, anycap ? low dropout regulator functional block diagram thermal protection cc in adp3330 out r1 r2 gnd q1 sd bandgap ref driver g m err features high accuracy over line and load: 6 0.7% @ +25 8 c, 6 1.4% over temperature ultralow dropout voltage: 140 mv (typ) @ 200 ma requires only c o = 0.47 m f for stability anycap = stable with any type of capacitor (including mlcc) current and thermal limiting low noise low shutdown current: <2 m a 2.9 v to 12 v supply range C40 8 c to +85 8 c ambient temperature range ultrasmall thermally enhanced chip-on-lead? sot-23-6 6-lead package applications cellular telephones notebook, palmtop computers battery powered systems pcmcia regulator bar code scanners camcorders, cameras general description the adp3330 is a member of the adp330x family of precision low dropout anycap voltage regulators. the adp3330 operates with an input voltage range of 2.9 v to 12 v and delivers a load current up to 200 ma. the adp3330 stands out from the con- ventional ldos with a novel architecture and an enhanced process that enables it to offer performance advantages and higher output current than its competition. its patented design requires only a 0.47 m f output capacitor for stability. this device is insensitive to output capacitor equivalent series resistance (esr), and is stable with any good quality capaci- tor, including ceramic (mlcc) types for space-restricted applica tions. the adp3330 achieves exceptional accuracy of 0.7% at room temperature and 1.4% over temperature, line and load variations. the dropout voltage of the adp3330 is only 140 mv (typical) at 200 ma. this device also includes a safety current limit, thermal overload protection and a shutdown feature. in shutdown mode, the ground current is reduced to less than 2 m a. the adp3330 has ultralow quiescent current 34 m a (typ) in light load situations. anycap and chip-on-lead are trademarks of analog devices, inc. v out v in + C adp3330 nr out err on off sd gnd in c out 0.47 m f c in 0.47 m f + C figure 1. typical application circuit the sot-23-6 package has been thermally enhanced using analog devices proprietary chip-on-lead feature to maximize power dissipation.
C2C rev. a adp3330-xxCspecifications parameter symbol conditions min typ max units output voltage accuracy v out v in = v outnom +0.25 v to +12 v i l = 0.1 ma to 200 ma t a = +25 c C0.7 +0.7 % v in = v outnom +0.25 v to +12 v i l = 0.1 ma to 150 ma t a = C40 c to +85 c C1.4 +1.4 % v in = v outnom +0.25 v to +12 v i l = 0.1 ma to 200 ma t a = C20 c to +85 c C1.4 +1.4 % line regulation v in = v outnom +0.25 v to +12 v t a = +25 c 0.04 mv/v load regulation i l = 0.1 ma to 200 ma t a = +25 c 0.04 mv/ma ground current i gnd i l = 200 ma, t a = C20 c to +85 c 1.6 4.0 ma i l = 150 ma 1.2 3.1 ma i l = 50 ma 0.4 1.1 ma i l = 0.1 ma 34 50 m a ground current in dropout i gnd v in = v outnom C 100 mv i l = 0.1 ma 37 55 m a dropout voltage v drop v out = 98% of v outnom i l = 200 ma, t a = C20 c to +85 c 0.14 0.23 v i l = 150 ma 0.11 0.17 v i l = 10 ma 0.042 0.06 v i l = 1 ma 0.025 0.05 2 v peak load current i ldpk v in = v outnom + 1 v 300 ma output noise 3 v noise f = 10 hzC100 khz, c l = 10 m f i l = 200 ma, c nr = 10 nf, v out = 3 v 47 m v rms f = 10 hzC100 khz, c l = 10 m f i l = 200 ma, c nr = 0 nf, v out = 3 v 95 m v rms shutdown threshold v thsd on 2.0 v off 0.4 v shutdown pin input current i sd v in = 12 v, 0 < sd , 12 v 1.9 9 m a 0 < sd , 5 v 1.4 6 m a ground current in shutdown mode i gndsd sd = 0 v, v in = 12 v 0.01 2 m a output current in shutdown i osd t a = +25 c @ v in = 12 v 1 m a mode t a = +85 c @ v in = 12 v 2 m a error pin output leakage i el v eo = 5 v 1 m a error pin output low voltage v eol i sink = 400 m a 0.19 0.40 v notes 1 ambient temperature of +85 c corresponds to a junction temperature of +125 c under typical full load test conditions. 2 application stable with no load. 3 see detail in figure 19 and application section of data sheet. specifications subject to change without notice. (@ t a = C40 8 c to +85 8 c, v in = +7 v, c in = 0.47 m f, c out = 0.47 m f, unless otherwise noted). 1, 2 the following specifications apply to all voltage options except C2.5. d v o d v in d d v i o l
C3C rev. a adp3330 adp3330-2.5Cspecifications parameter symbol conditions min typ max units output voltage accuracy v out v in = +2.9 v to +12 v i l = 0.1 ma to 200 ma t a = +25 c C0.7 +0.7 % v in = +2.9 v to +12 v i l = 0.1 ma to 150 ma t a = C40 c to +85 c C1.4 +1.4 % v in = +2.9 v to +12 v i l = 0.1 ma to 200 ma t a = C20 c to +85 c C1.4 +1.4 % line regulation v in = +2.9 v to +12 v t a = +25 c 0.04 mv/v load regulation i l = 0.1 ma to 200 ma t a = +25 c 0.04 mv/ma ground current i gnd i l = 200 ma, t a = C20 c to +85 c 1.6 4.0 ma i l = 150 ma 1.2 3.1 ma i l = 50 ma 0.4 1.1 ma i l = 0.1 ma 34 50 m a ground current in dropout i gnd v in = v outnom C 100 mv i l = 0.1 ma 37 55 m a dropout voltage v drop v out = 98% of v outnom i l = 200 ma, t a = C20 c to +85 c 0.14 0.4 v i l = 150 ma 0.11 0.3 v i l = 10 ma 0.042 0.06 v i l = 1 ma 0.025 0.05 2 v peak load current i ldpk v in = v outnom + 1 v 300 ma output noise 3 v noise f = 10 hzC100 khz, c l = 10 m f i l = 200 ma, c nr = 10 nf, v out = 3 v 47 m v rms f = 10 hzC100 khz, c l = 10 m f i l = 200 ma, c nr = 0 nf, v out = 3 v 95 m v rms shutdown threshold v thsd on 2.0 v off 0.4 v shutdown pin input current i sd v in = 12 v, 0 < sd , 12 v 1.9 9 m a 0 < sd , 5 v 1.4 6 m a ground current in shutdown mode i gndsd sd = 0 v, v in = 12 v 0.01 2 m a output current in shutdown i osd t a = +25 c @ v in = 12 v 1 m a mode t a = +85 c @ v in = 12 v 2 m a error pin output leakage i el v eo = 5 v 1 m a error pin output low voltage v eol i sink = 400 m a 0.19 0.40 v notes 1 ambient temperature of +85 c corresponds to a junction temperature of +125 c under typical full load test conditions. 2 application stable with no load. 3 see detail in figure 19 and application section of data sheet. specifications subject to change without notice. (@ t a = C40 8 c to +85 8 c, v in = +7 v ,c in = 0.47 m f, c out = 0.47 m f, unless otherwise noted). 1, 2 d v o d v in d d v i o l
adp3330 C4C rev. a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp3330 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* input supply voltage . . . . . . . . . . . . . . . . . . . . C0.3 v to +16 v shutdown input voltage . . . . . . . . . . . . . . . . . C0.3 v to +16 v power dissipation . . . . . . . . . . . . . . . . . . . . internally limited operating ambient temperature range . . . . . C40 c to +85 c operating junction temperature range . . . . C40 c to +125 c q ja (4-layer board) . . . . . . . . . . . . . . . . . . . . . . . +165 c/w q ja (2-layer board) . . . . . . . . . . . . . . . . . . . . . . . +190 c/w storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *this is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ordering guide voltage package marking model output option* code adp3330art-2.5 2.5 v rt-6 (sot-23-6) l1b adp3330art-2.75 2.75 v rt-6 (sot-23-6) l2b adp3330art-2.85 2.85 v rt-6 (sot-23-6) l3b adp3330art-3 3.0 v rt-6 (sot-23-6) l4b adp3330art-3.3 3.3 v rt-6 (sot-23-6) l5b adp3330art-3.6 3.6 v rt-6 (sot-23-6) l6b adp3330art-5 5.0 v rt-6 (sot-23-6) l8b *contact the factory for the availability of other output voltage options. pin function descriptions pin name function 1 out output of the regulator. bypass to g round with a 0.47 m f or larger capacitor. 2 in regulator input. 3 err open collector output that goes low to indicate that the output is about to go out of regulation. 4 gnd ground pin. 5 nr noise reduction pin. used for further reduction of output noise (see text for detail). no connection if not used. 6 sd active low shutdown pin. connect to ground to disable the regulator output. when shutdown is not used, this pin should be connected to the input pin. pin configuration top view (not to scale) 6 5 4 1 2 3 gnd nr sd err in out adp3330 warning! esd sensitive device
adp3330 C5C rev. a typical performance characteristicsC input voltage C volts output voltage C volts 3.010 3.002 2.996 3.25 456789101112 3.008 3.006 3.000 2.998 3.004 2.994 2.992 2.990 v out = 3.0v i l = 0ma i l = 10ma i l = 100ma i l = 50ma i l = 150ma i l = 200ma figure 2. line regulation output voltage vs. supply voltage output load C ma ground current C ma 1.6 1.4 0.6 0 50 200 100 150 1.2 1.0 0.8 v in = 7v 0.4 0.2 0 figure 5. ground current vs. load current output load C ma input/output voltage C mv 250 200 0 0 25 100 50 75 150 100 50 125 150 175 200 figure 8. dropout voltage vs. output current output load C ma output voltage C volts 3.005 2.998 0 25 50 75 100 125 150 175 200 3.004 3.003 3.002 3.001 3.000 2.999 v out = 3.0v v in = 7v 2.997 2.996 2.995 2.994 figure 3. output voltage vs. load current 0.2 0.4 C45 C25 135 C5 15 35 75 95 115 55 0.1 0.0 C0.1 0.3 junction temperature C 8 c output voltage C % i l = 50ma i l = 0ma i l = 150ma i l = 200ma figure 6. output voltage variation % vs. junction temperature 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1.0 2.0 3.0 4.0 5.0 input/output voltage C volts time C sec v out = 3v sd = v in r l = 15 v figure 9. power-up/power-down input voltage C volts ground current C m a 45 40 20 0 2 4 6 8 10 12 35 30 25 v out = 3v 15 10 5 0 i l = 100 m a i l = 0 m a figure 4. ground current vs. supply voltage junction temperature C 8 c ground current C ma 3.0 2.8 0 C45 C25 115 C5 15 35 55 75 95 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 135 v in = 7v i l = 0ma i l = 100ma i l = 50ma i l = 150ma i l = 200ma figure 7. gro und current vs. jun ction temperature 3 2 1 0 10 5 0 0 100 200 300 400 500 v out C volts v in C volts time C m s v in = 7v v out = 3v sd = v in r l = 15 v c l = 10 m f c l = 0.47 m f figure 10. power-up response
adp3330 C6C rev. a 3.020 3.000 2.980 2.960 2.940 7.5 7.0 0 100 200 300 400 500 time C m s v out C volts v in C volts v out = 3v r l = 15 v c l = 0.47 m f figure 11. line transient response 3.100 3.050 3.000 2.950 2.900 200 100 0 0 200 400 600 800 1000 volts ma time C m s v in = 7v v out = 3v c l = 10 m f 20ma figure 14. load transient r esponse frequency C hz ripple rejection C db 0 10 100 1k 10k 100k 1m 10m C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 c l = 0.47 m f i l = 0.1ma c l = 0.47 m f i l = 200ma c l = 10 m f i l = 200ma c l = 10 m f i l = 0.1ma v out = 3.0v figure 17. power supply ripple rejection 3.020 3.000 2.980 2.960 2.940 7.5 7.0 0 100 200 300 400 500 time C m s v out C volts v in C volts v out = 3v r l = 15 v c l = 10 m f figure 12. line transient response 3 0 500 400 300 200 100 0 volts ma 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time C sec v out i out v in = 7v figure 15. short circuit current 120 160 050 10 20 30 40 100 80 60 140 c l C m f rms noise C m v 40 20 0 i l = 0ma with noise reduction i l = 200ma i l = 200ma with noise reduction i l = 0ma figure 18. rms noise vs. c l (10 hzC100 khz) 3.100 3.050 3.000 2.950 2.900 200 100 0 0 200 400 600 800 1000 volts ma time C m s v in = 7v v out = 3v c l = 0.47 m f 20ma figure 13. load transient response 3 2 1 0 0 2 0 3 volts v out v err v sd 0 200 400 600 800 1000 time C m s v in = 7v v out = 3v c l = 10 m f r l = 15 v figure 16. turn onCturn off response frequency C hz voltage noise spectral density C m v/ hz 1 0.01 10 100 1m 0.1 1k 10k 100k v out = 3.0v i l = 200ma c l = 0.47 m f c nr = 0 c l = 10 m f c nr = 0 c l = 0.47 m f c nr = 10nf c l = 10 m f c nr = 10nf figure 19. output noise density
adp3330 C7C rev. a theory of operation the new anycap ldo adp3330 uses a single control loop for regulation and reference functions. the output voltage is sensed by a resistive voltage divider consisting of r1 and r2 which is varied to provide the available output voltage options. feedback is taken from this network by way of a series diode (d1) and a second resistor divider (r3 and r4) to the input of an amplifier. ptat v os g m noninverting wideband driver input q1 adp3330 compensation capacitor attenuation (v bandgap /v out ) r1 d1 r2 r3 r4 output ptat current r load c load (a) gnd figure 20. functional block diagram a very high gain error amplifier is used to control this loop. the amplifier is constructed in such a way that at equilibrium it produces a large, temperature-proportional input offset voltage that is repeatable and very well controlled. the tempera ture- proportional offset voltage is combined with the com plementary diode voltage to form a virtual bandgap voltage, implicit in the network, although it never appears explicitly in the circuit. ultimately, this patented design makes it possible to control the loop with only one amplifier. this technique also improves the noise characteristics of the amplifier by providing more flexibil- ity on the tradeoff of noise sources that leads to a low noise design. the r1, r2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. although the r1, r2 resistor divider is loaded by the diode d1, and a s econd divider consist- ing of r3 and r4, the values are chosen to produce a tempera- ture stable output. this unique arrangement specifically corrects for the loading of the divider so that the error resulting from base current loading in conventional circuits is avoided. the patented amplifier controls a new and unique noninverting driver that drives the pass transistor, q1. the use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type and esr of the load capacitance. most ldos place strict requirements on the range of esr values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resis- tance. moreover, the esr value, required to keep conventional ldos stable, changes depending on load and temperature. these esr limitations make designing with ldos more difficult because of their unclear specifications and extreme variations over temperature. with the adp3330 anycap ldo, this is no longer true. it can be used with virtually any good quality capacitor, with no constraint on the minimum esr. the innovative design allows the circuit to be stable with just a small 0.47 m f capacitor on the output. additional advantages of the pole splitting scheme include superior line noise rejection and very high regulator gain which leads to excellent line and load regulation. an impressive 1.4% accuracy is guaranteed over line, load and temperature. additional features of the circuit include current limit, thermal shutdown and noise reduction. compared to standard solutions that give warning after the output has lost regulation, the adp3330 provides improved system performance by enabling the err pin to give warning just before the device loses regulation. as the chips temperature rises above +165 c, the circuit activates a soft thermal shutdown, indicated by a signal low on the err pin, to reduce the current to a safe level.
adp3330 C8C rev. a application information capacitor selection output capacitors: as with any micropower device, output transient response is a function of the output capacitance. the adp3330 is stable with a wide range of capacitor values, types and esr (anycap). a capacitor as low as 0.47 m f is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. the adp3330 is stable with extremely low esr capacitors (esr ? 0), such as multilayer ceramic capacitors (mlcc) or oscon. note that the effective capacitance of some capacitor types may fall below the minimum at cold temperature. ensure that the capacitor provides more than 0.47 m f at minimum temperature. input bypass capacitor: an input bypass capacitor is not strictly required but it is advisable in any application involving long input wires or high source impedance. connecting a 0.47 m f capacitor from in to ground reduces the circuits sensitivity to pc board layout. if a larger value output capacitor is used, then a larger value input capacitor is also recommended. noise reduction a noise reduction capacitor (c nr ) can be used to further reduce the noise by 6 dbC10 db (figure 21). low leakage capacitors in 10 pfC500 pf range provide the best performance. since the noise reduction pin (nr) is internally connected to a high imped- ance node, any connection to this node should be carefully done to avoid noise pickup from external sources. the pad connected to this pin should be as small as possible and long pc board traces are not recommended. when adding a noise reduction capacitor, use the following guidelines: ? maintain a minimum load current of 1 ma when not in shutdown. ? for cnr values greater than 500 pf, add a 100 k w series resistor (rnr). it is important to note that as cnr increases, the turn-on time will be delayed. with cnr values greater than 1 nf, this delay may be on the order of several milliseconds. + C v in + c1 0.47 m f in C adp3330-3 sd gnd v out = +3.3v out 330k v c2 0.47 m f r1 cnr nr err rnr figure 21. noise reduction circuit chip-on-lead package the adp3330 uses a patented chip-on-lead package design to ensure the best thermal performance in an sot-23 footprint. in a standard sot-23, the majority of the heat flows out of the ground pin. this new package uses an electrically isolated die attach that allows all pins to contribute to heat con duction. this technique reduces the thermal resistance to 190 c/w on a 2-layer board as compared to >230 c/w for a standard sot-23 leadframe. figure 22 shows the difference between the standard sot-23 and the chip-on-lead leadframes. silicon die a. normal sot-23-6 package silicon die with electrically isolated die attach b. thermally enhanced chip-on-lead package figure 22. thermal overload protection the adp3330 is protected against damage due to excessive power dissipation by its thermal overload protection circuit which limits the die temperature to a maximum of +165 c. under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above +165 c, the output current is reduced until the die temperature has dropped to a safe level. the output current is restored when the die temperature is reduced. current and thermal limit protections are intended to protect the device against accidental overload conditions. for normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +125 c. calculating junction temperature device power dissipation is calculated as follows: p d = ( v in C v out ) i load +( v in ) i gnd where i load and i gnd are load current and ground current, v in and v out are input and output voltages respectively. assuming i load = 200 ma, i gnd = 4 ma, v in = 4.2 v and v out = 3.0 v, device power dissipation is: p d = (4.2 C 3) 200 ma + 4.2 (4 ma ) = 257 mw the proprietary package used in the adp3330 has a thermal resistance of 165 c/w, significantly lower than a standard 6-lead sot-23 package. assuming a 4-layer board, the junction temperature rise above ambient temperature will be approxi- mately equal to: d t j a = 0.257 w 165 c/w = 42.4 c to limit the maximum junction temperature to +125 c, maximum allowable ambient temperature will be: t a max = 125 c C 42.4 c = 82.6 c
adp3330 C9C rev. a printed circuit board layout considerations all surface mount packages rely on the traces of the pc board to conduct heat away from the package. in standard packages the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. in typical thermally enhanced packages one or more of the leads are fused to the die attach pad, significantly decreasing this component. to make the improvement mean- ingful, however, a significant copper area on the pcb must be attached to these fused pins. the patented chip-on-lead frame design of the adp3330 uniformly minimizes the value of the dominant portion of the thermal resistance. it ensures that heat is conducted away by all pins of the package. this yields a very low 165 c/w thermal resistance for an sot-23-6 package, without any special board layout requirements, just relying on the normal traces con- nected to the leads. this yields a 17% improvement in heat dissipation capability as compared to a standard sot-23-6 package. the thermal resistance can be decreased by, ap proxi- mately, an additional 10% by attaching a few square cm of copper area to the v in pin of the adp3303 package. it is not recommended to use solder mask or silkscreen on the pcb traces adjacent to the adp3330s pins since it will increase the junction to ambient thermal resistance of the package. error flag dropout detector the adp3330 will maintain its output voltage over a wide range of load, input voltage and temperature conditions. if the output is about to lose regulation by reducing the supply voltage below the combined regulated output and dropout voltages, the err flag will be activated. the err output is an open collector, which will be driven low. once set, the err flags hysteresis will keep the output low until a small margin of operating range is restored either by raising the supply voltage or reducing the load. shutdown mode applying a ttl high signal to the shutdown ( sd ) pin, or tying it to the input pin, will turn the output on. pulling sd down to 0.4 v or below, or tying it to ground, will turn the output off. in shutdown mode, quiescent current is reduced to much less than 1 m a. low power, low dropout applications adp3330 is well suited for applications such as cellular phone handsets that require low quiescent current and low dropout voltage features. adp3330 draws 34 m a typical under light load situations (i.e., load current = 100 m a), which results in low power consumption when the cell phone is in standby mode. figure 23 shows an application in which the adp3330 is used in a handset to provide 2.75 v nominal output voltage. the cell phone is powered from 3 cell nicd or 1 cell li-ion battery. adp3330 guarantees an accuracy of 1.4%, even when the input/ output differential is merely 250 mv (worst case). this implies that the output is regulated and within specification even when the battery voltage has reached its end-of-discharge voltage of 3 v. the output voltage never falls below 2.7 v, even under worst case load and temperature conditions. the low dropout feature coupled with the high accuracy of the adp3330 ensures that the system is reliably powered until the end of the life of the battery, which results in increased system talk time. minimum battery voltage 3.0v nominal output voltage 2.75v 2.712v absolute minimum output voltage 2.700v end of discharge voltage of 3 cell nicd or 1 cell li-ion battery 250mv maximum input-output overhead for 200ma output current C1.4% output voltage accuracy 12mv transient, line and load respective margin figure 23. ldo budgeting for a 3 cell nicd/1 cell li-ion supply
adp3330 C10C rev. a application circuits crossover switch the circuit in figure 24 shows how two adp3330s can be used to form a mixed supply voltage system. the output switches between two different levels selected by an external digital input. output voltages can be any combination of voltages from the ordering guide of the data sheet. adp3330-3.6 adp3330-2.5 + out in sd gnd + in out sd gnd c1 1.0 m f c2 0.47 m f v out = 3.6v/2.5v v in = 3.85v to 12v output select 3v 0v logic supply figure 24. crossover switch higher output current the adp3330 can source up to 200 ma at room temperature without any heatsink or pass transistor. if higher current is needed, an appropriate pass transistor can be used, as in figure 25, to increase the output current to 1 a. adp3330-3 out in sd gnd + v in = 4.5v to 8v mje253* v out = 3v@1a c1 100 m f c2 100 m f *aavid531002 heat sink is used err r1 50 v figure 25. high output current linear regulator
adp3330 C11C rev. a 6-lead surface mount rt-6 (sot-23-6) 0.122 (3.10) 0.106 (2.70) pin 1 0.071 (1.80) 0.059 (1.50) 0.118 (3.00) 0.098 (2.50) 0.075 (1.90) bsc 0.037 (0.95) bsc 1 3 4 5 6 2 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 0 0.020 (0.50) 0.010 (0.25) 0.059 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90) outline dimensions dimensions shown in inches and (mm). c3455aC0C8/99 printed in u.s.a.
C12C c3455aC0C8/99 printed in u.s.a.
package/price information high accuracy ultralow i(q), 200 ma, sot - 23, anycap ? low dropout regulator * this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit in the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability for further information. model status package description pin count temperature range price* (100 - 499) adp3330art - 2.5 - rl production sot - 23, sot - 143 or sot - 223 6 industrial - adp3330art - 2.5 - rl7 production sot - 23, sot - 143 or sot - 223 6 industrial - adp3330art - 2.75 - r7 production sot - 23, sot - 143 or sot - 223 6 industrial - adp3330art - 2.75 - rl production sot - 23, sot - 143 or sot - 223 6 industrial - adp3330art - 2.85 - r7 production sot - 23, sot - 143 or sot - 223 6 industrial - adp3330art-2.85-rl production sot-23, sot-143 or sot-223 6 industrial - adp3330art-3-reel production sot-23, sot-143 or sot-223 6 industrial - adp3330art-3-reel7 production sot-23, sot-143 or sot-223 6 industrial - adp3330art-3.3-rl production sot-23, sot-143 or sot-223 6 industrial - adp3330art-3.3-rl7 production sot-23, sot-143 or sot-223 6 industrial - adp3330art-3.6-rl production sot-23, sot-143 or sot-223 6 industrial - adp3330art-3.6-rl7 production sot-23, sot-143 or sot-223 6 industrial - adp3330art-5-reel production sot-23, sot-143 or sot-223 6 industrial - adp3330art-5-reel7 production sot-23, sot-143 or sot-223 6 industrial -

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