View AIF04ZPFC-01_3781145.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

model : aif - pfc series december, 2004 revision 07 sh 1 of 30 technical reference note aif - pfc power factor correction series aif - pfc 1600w ac-dc converter module the pfc power factor correction module is part of astec?s family of advanced high density modular power supply components. featuring high reliability and convenient control and monitoring functions, these modules are designed to reduce product development time and enhance system performance. the pfc is designed to work over all typical line voltages used worldwide, and provide unity power factor with very low levels of harmonic distortion in line current. the pfc includes active start-up current control. power line disturbance (pld) circuitry copes with a wide range of input voltage fluctuations. . environmental specifications ? operating temperature: -20c to +100c ( baseplate) ? storage temperature: -40c to +110c ? meet power line disturbance immunity specification per iec 61000-4-11 ? generic immunity standards against voltage dips, interruptions? electrical parameters input input range 85 ? 264 vac 120 - 370vdc (configurable) input surge 290vac / 1s efficiency 95%@ 230vac, 1600w (typical) total harmonic 10% distortion control enable ttl compatible (positive & negative enable options) output output voltage io =4.2a / vi > 180vac 380v typ io = 0 393v typ maximum output power 85vac vin 120vac 1000w 120vac < vin < 220vac see p. 16 vin 3 220vac 1600w output voltage adjust range 76% - 100% of nominal output overvoltage protection 430v special features ? unity power factor ? dc input (configurable) ? high efficiency - up to 95% ? universal input voltage and frequency range ? up to 1600w output power ? parallelable with current sharing within 10% ? < 10% harmonic distortion conforming to iec 1000- 3-2 compliance ? 100c baseplate operating temperature. ? high reliability - over 1 million hours mtbf @ baseplate temperature 50 c ? programmable power fail warning signal ? eeprom data storage via i 2 c interface ? power density up to 290w/in 3 ? switching frequency 125khz safety ul, cul 60950 recognized tuv en60950 licensed
model : aif - pfc series december, 2004 revision 07 sh 2 of 30 technical reference note aif - pfc power factor correction series aif - pfc series this specification covers the requirements for a new full brick 1600w ac/dc converter model name sis code vout,iout serial no. prefix AIF04ZPFC-01 AIF04ZPFC-01n aif04zpfc-02 aif04zpfc-02n AIF04ZPFC-01nt AIF04ZPFC-01nnt aif04zpfc-02nt aif04zpfc-02nnt AIF04ZPFC-01 AIF04ZPFC-01n aif04zpfc-02 aif04zpfc-02n AIF04ZPFC-01nt AIF04ZPFC-01nnt aif04zpfc-02nt aif04zpfc-02nnt 380v, 4.2a 380v, 4.2a 380v, 4.2a 380v, 4.2a 380v, 4.2a 380v, 4.2a 380v, 4.2a 380v, 4.2a a648 b796 a826 b797 d943 d945 d944 d946 * 1600w max suffix option n negative logic enable no suffix positive logic enable nt non-thread hole
model : aif - pfc series december, 2004 revision 07 sh 3 of 30 technical reference note aif - pfc power factor correction series electrical specifications unless otherwise indicated, specifications apply over all operating input voltage and temperature conditions. standard test condition on a single unit. tambient: 25 c l1: 115vac, 220vac l 2 : return pin for l1 enable: open +vout1: connect to load - vout1: connect to load (return) trim(vadj): connect to s gnd output cap: 470uf x 2 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the specs. exposure to absolute maximum ratings for extended periods can adversely affect device reliability . parameter device symbol min typ max unit input voltage: continuous: surge voltage (1 sec) all all v i v i 85 - 264 290 vac vac operating case temperature start up case temperature all all tc -20 -40 - 100 100 oc oc storage temperature all t stg -40 - 110 oc operating humidity all - - - 95 % isolation input to baseplate output to baseplate baseplate capacitance all - - - - - - - - 2700 2700 1300 vdc vdc pf
model : aif - pfc series december, 2004 revision 07 sh 4 of 30 technical reference note aif - pfc power factor correction series control signals control function conditions parameter min typ max units temp mon - temperature v temp mon sensitivity 9.8 10 10.2 mv/c monitor signal source impedence 16 k w v adj - voltage adjust adjust using external resistor vo 76 100 % vo nom c mon - current monitor io = 4.2a i c mon 0.9 1 1.1 ma signal io = 20 to 100% iorated i o /i c mon 4.2 a/ma c share - current share c share pins of modules in c share accuracy 3% 10 %io rated function** parallel connected max no. of units 10 clk out - clock output v clk out 5 vp-p clk in open clock freq. 0.97 1 1.03 mhz max fan out 2 clk in - clock input vclk in 4.5 6 vp-p clock freq 0.95 1 1.05 mhz pfw adj - power fail pfw adj=0 to 2.80 vdc pfw set point 265 280 295 vdc warning adjust pfw adj=3.2 vdc pfw set point 305 320 335 vdc pfw adj = 3.40vdc pfw set point 325 340 355 vdc pfw adj current source 1 ma pfw - power fail warning*** input power ok, i pfw = 0 v pfw 12 13.7 15 v input power fail, i pfw = 15ma v pfw 0 0.2 0.4 v (pfw short to s_gnd) pfw current source ? 2.9 - ma ld enable - load enable load enabled, (i ld enable = 0) v ld enable 12 13.7 15 v load disabled, (i ld enable = 15ma) v ld enable 0 0.2 0.4 v ld enable short to s_gnd ld enable current source ? 2.9 - ma pf enable - module negative enable: enable*** module enabled v pf enable 0 0.8 v module disabled v pf enable 2.2 5 v positive enable: module enabled v pf enable 2.2 5 v module disabled v pf enable 0 0.8 v v enable = 0.8v pf enable current source 400 a pv_aux*** i pv_aux = 0a pv_aux voltage 11 v i pv_aux = 20ma pv_aux voltage 8 9 v ** for AIF04ZPFC-01, total input current of all the modules must not exceed 16a rms *** only apply on primary side
model : aif - pfc series december, 2004 revision 07 sh 5 of 30 technical reference note aif - pfc power factor correction series input specifications parameter device symbol min typ max unit operating input voltage all v i 85 264 v ac input current (v i = 115vac, load = 1000w) i i,m ax - - 10 a inrush transient (need external inrush limiting circuit) - 20 apk power factor po 3 500w po 3 1000w 0.96 0.98 0.97 0.99 no load input power (v i = v i,nom ) all - - - 3.8 w total harmonic distortion (iec1000-3-2) all - - - 10 % note: 1) half cycle surge current due to input transient surge must be limited to 20a peak or less 2) need external inrush limiting circuit 3) for AIF04ZPFC-01, total input current for modules connected in parallel must not exceed 16a 4) for aif04zpfc-02, negative rail input rectifiers must be provided by external circuitry. see p.24 5) total harmonic distortion ? input harmonics meet the requirements of iec 1000-3-2 6) the pfc?s ld enable signal is recommended to be used to enable the load in case of initial surge load condition
model : aif - pfc series december, 2004 revision 07 sh 6 of 30 technical reference note aif - pfc power factor correction series output specifications parameter device symbol min typ max unit output voltage io = 4.2a / v i > 180v io = 0 370 380 393 400 v v maximum output power for 85vac vi 120vac for vi > 220 vac for 120vac < vi < 220vac 1000 1600 see p.16 w w efficiency vi = 115vac, (1000w) vi = 230vac, (1000w) vi = 230vac, (1600w) 90 92 92 92 94 95 % % % turn-on time vi = 115vac vi = 230vac 0.5 0.5 2.5 2.5 4.0 3.5 sec sec external output capacitor 470 3000 m f general specifications parameter device symbol min typ max unit calculated mtbf ( io = 2.6a ; t b = 40 c, mil-217fn2) all - - 450k - hours weight all - - 300 (9.6) g(oz.)
model : aif - pfc series december, 2004 revision 07 sh 7 of 30 technical reference note aif - pfc power factor correction series feature specifications parameter device symbol min typ max unit pf enable interface : positive logic ? no suffix low logic ? module off high logic ? module on negative logic ? suffix ?n? low logic ? module on high logic ? module off enable current source (venable = 0.8v) all all all all all v enable v enable v enable v enable 0 2 0 2 0.8 5 0.8 5 400 v v v v m a output voltage adjustment range - 76 - 100 %vo output overvoltage shutdown (latch off) all 420 430 v output ripple vin = 115vac, vo = 380v, io = 2.6a 11 vp-p undervoltage lockout turn-on point turn-off point all all - - 79 57 84.5 62 v v overtemperature shutdown (baseplate temperature) all 105 120 c
model : aif - pfc series december, 2004 revision 07 sh 8 of 30 technical reference note aif - pfc power factor correction series function description this section explains how to implement the functions found on the aif - pfc series . all signals are on primary side. pfc enable input (pf enable) the enable pin is a ttl compatible input used to turn the output of the module on or off. for module with no suffix, the output is enabled when the pf enable (pin 16) is open or driven to a logic high > 2.2v. the output is disabled when the pf enable is connected to s gnd (pin 13) or driven to a logic low of < 0.8v (but not negative). for module with suffix ?n?, the output is enabled when the pf enable is connected to s gnd or driven to a logic low < 0.8v (but not negative). the output is disabled when the pf enable is open or driven to a logic high > 2.2v. s gnd (signal ground) the s gnd pin is connected to the internal common ground of the module. it is also internally connected to the ?o/p terminals. note: when connecting s gnd to external circuitry care must be taken to ensure that the current flowing through this pin is kept below 25ma.
model : aif - pfc series december, 2004 revision 07 sh 9 of 30 technical reference note aif - pfc power factor correction series dc-dc converter module enable output (ld enable) after the pfc power up sequence, the power to the load can be enabled. this can be performed manually or the pfc can automatically enable the load using the ld enable signal. initially the load is disabled and the ld enable (pin 15) is at 0.4v (low). when the pfc power up sequence has completed, the ld enable voltage goes high. and the ld enable will stay high as long as vin is above 175vac or vout is above 250v, even if pf_enable is in disable mode . (please see the application example section at p.24 for the external circuit to interlock the ld-enable from pf_enable) the ld enable pin is capable of delivering 2.7ma at 1.5v when high. see electrical specifications for exact figures. power fail warning if output voltage can not be maintained at the pre-programmed pfw threshold voltage, the pfw (pin 14) will go from high to low.
model : aif - pfc series december, 2004 revision 07 sh 10 of 30 technical reference note aif - pfc power factor correction series the output of the pfw signal can drive an opto-coupler to provide an isolated signal from primary side to the secondary side. the nominal factory set pfw threshold is set at 340v. power fail warning adjust the level at which a power fail warning occurs can be programmed using the pfw adjust input (pin 12). if the pin is left unconnected then the pfw operates at the default factory set value. the output from the pfw adj pin is a 1ma current source. to adjust the pfw threshold, a voltage source (0 ? 4volts) or a programming resistance (0 ? 4kohm) referenced to s s gnd (pin 13) should be connected. this allows adjustment of the pfw threshold from 280v up to 340v. the value of resistance or voltage required can be read from the graph above. clock signals (clk in, clk out) the pfc?s internal clock is accurate and stable over its full operating range and synchronization is not normally required, but it can reduce noise in paralleled systems. clock signals can be wired in series (the clk out pin of one module to the clk in pin of the next etc) in which case all the modules will be synchronized with the first module in the chain. alternatively, an external clock signal of ttl level at 1mhz 10% can be connected to the clk in pins of all the modules.
model : aif - pfc series december, 2004 revision 07 sh 11 of 30 technical reference note aif - pfc power factor correction series if the clock input to any module fails, the module will automatically switch back to its internal clock and will continue to operate at full power even in current sharing systems .. the clk in and clk out signals are ac coupled. temperature monitoring (temp mon) the temp mon pin provides an indication of the module?s internal temperature. the voltage at the temp mon pin is proportional to the temperature of the module baseplate at 10mv per c, where: module temperature ( c) = (vtemp mon x 100) - 273 the temperature monitor signal can be used by thermal management systems (e.g. to control a variable speed fan). it can also be used for overtemperature warning circuits and for thermal design verification of prototype power supplies and heatsink.
model : aif - pfc series december, 2004 revision 07 sh 12 of 30 technical reference note aif - pfc power factor correction series current monitoring (c mon) the c mon pin provides an indication of the amount of current supplied by the module. the output of the c mon pin is a current source proportional to the output current of the module, where i o / i cmon = 4.2a/1ma if a 4.2k ohm resistor is connected then the voltage in volts on the c mon pin is directly equivalent to the current supplied by the module in amps. maximum voltage on c mon is 6v
model : aif - pfc series december, 2004 revision 07 sh 13 of 30 technical reference note aif - pfc power factor correction series current sharing (c share) to ensure that all modules in a parallel system accurately share current, the c share pins on each module should be connected together. the voltage on the c share pins represents the average load current per module. each module compares this average with its own current and adjusts its output voltage to correct the error. in this way the module maintains accurate current sharing even under variable or light load conditions. note: 1) the s gnd pins of each module must also be connected together to ensure accurate current sharing. 2) current flow to s gnd must less than 25ma
model : aif - pfc series december, 2004 revision 07 sh 14 of 30 technical reference note aif - pfc power factor correction series output voltage adjust (v adj) the output voltage of the module may be accurately adjusted from 76% to 100% of the nominal output voltage. adjustment can be made using a resistor connected as below. v-adj value chart 300 310 320 330 340 350 360 370 380 390 400 1.0 2.3 5.1 11.4 25.6 57.7 129.7 291.9 656.8 k-ohm v-out vout = vr * (1 + rh * ( 1 / ( rj + r) + 1 / rw)) + 10.94 where r is the resistor connected between the vadj pin to s_gnd (units in kohm) vr = 5.029 rh = 1084 rw = 19.2 rj = 58.5
model : aif - pfc series december, 2004 revision 07 sh 15 of 30 technical reference note aif - pfc power factor correction series dc enable for using dc input, connect the dc enable pin to s gnd sda / scl eeprom communication data storage is provided for compliance with intel / hewlett-packard / nec / dell platform management fru (field replacement unit*) information storage definition. * contact factory for more information
model : aif - pfc series december, 2004 revision 07 sh 16 of 30 technical reference note aif - pfc power factor correction series design considerations maximum output power vs input voltage the maximum output power available varies with the input voltage as shown below. efficiency vs input voltage and output power efficiency vs. load current 75 80 85 90 95 100 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% load [a] efficiency [%] 85vin 110vin 230vin 264vin
model : aif - pfc series december, 2004 revision 07 sh 17 of 30 technical reference note aif - pfc power factor correction series input undervoltage protection an input undervoltage protection circuit protects the module under low input voltage conditions. hysteresis is built into the pfc series module to allow for high levels of variation on the input supply voltage without causing the module to cycle on and off. pfc modules will operate when the input exceeds 85vac and turn off below 63vac. input fusing astec modules do not have an in-line fuse fitted internally. in order to comply with csa, vde and ul safety regulations it is recommended that a fuse of 250vac, 15a be fitted at the module?s input. output capacitor the pfc requires an output hold-up capacitor of between 470uf and 3000uf to prevent the module from disabling due to fluctuations in output voltage. ideally the capacitor should be connected directly to the pfc output pins. if this is not possible the connection must be less than 50mm from the pins. selecting an external output capacitor the output capacitor value is determined by the following factors : 1. rms ripple current. 2. peak-to-peak output ripple voltage. 3. hold-up time. 4. expected lifetime of the capacitor.
model : aif - pfc series december, 2004 revision 07 sh 18 of 30 technical reference note aif - pfc power factor correction series rms ripple current the maximum permissible rms ripple current for the output capacitor should be greater than the rms ripple current for the application. the ripple current for the pfc module can be approximated as i rms = (p o /eff) x 1/ ? (v o x v rms ) where : p o = output power (w) eff = efficiency v o = output voltage (v) v rms = input rms voltage (v) this gives the ripple current at 125khz. the maximum ripple current for capacitors is usually specified at 120hz. to convert from 125khz to 120hz the irms figure should be divided by 1.3 . peak to peak output ripple voltage the ac input causes a ripple on the output voltage. the size of the ripple is inversely proportional to the size of the capacitor. therefore the maximum allowable ripple voltage should be decided in order to calculate the size of capacitor required. this may be calculated using the following equation: c o = p o / (2 p f x eff x v o x v ripple ) where : c o = output capacitance (f) eff = efficiency f = input voltage frequency (hz) v o = output voltage (v) v ripple = output ripple voltage (v) hold-up time requirement the output capacitor value is different for different hold-up time requirements. the minimum capacitance corresponding to the required hold-up time of a system comprised of astec dc/dc power modules and an pfc module can be calculated as follows: c o min = (2 x p o x t hold )/[(v o -v ripple ) 2 - (v min ) 2 ] where : c o min = output capacitance (f) p o = output power (w) t hold = hold up time (sec) v o = output voltage (v) v ripple = output ripple voltage (v) v min = minimum input voltage for dc/dc module
model : aif - pfc series december, 2004 revision 07 sh 19 of 30 technical reference note aif - pfc power factor correction series for example: a pfc module driving 3 aif80a300 400w modules @ 5v. efficiency of the aif80a300 module is 88%, the minimum input voltage is 250v, the output voltage of the pfc is 380v, the required hold-up time is 20ms and the peak-to-peak voltage v ripple is chosen to be 16v. c o min = 2 x (3 x 400/0.88) x 0.02 = 390f (470 f 20%) [(380-16) 2 -250 2 ] this figure is the minimum capacitance. to allow for capacitor tolerances and aging effects the actual value should generally be around 1.5 times greater. pf & load enable connections and timing the pfc module must be supplied with a pf enable signal to initiate the start-up sequence. the output of the ld enable pin goes high (on) once the pfc has completed the start-up sequence. it is recommended that the ld enable signals is always used to enable the load, however, if the load is to be enabled manually it is essential that the ton time has expired before enabling occurs.
model : aif - pfc series december, 2004 revision 07 sh 20 of 30 technical reference note aif - pfc power factor correction series connections to enable astec dc-dc converters. the output from the pfc?s ld enable (pin 13) can directly drive an opto-coupler to provide an isolated signal to enable the power output of one or more astec dc-dc converter modules. general connections to enable a load for enabling loads other than astec dc-dc converters the following circuit can be used. the ld enable pin can directly drive a mosfet with a 15v zener clamping the gate voltage. conducted emi the pfc modules will require additional emi filtering to enable the system to meet relevant emi standards. pfc modules have an effective input to ground (baseplate) capacitance of 1600pf. this should be accounted for when calculating the maximum emi ?y? capacitance to meet ground leakage current specifications. an example filter circuit is shown below.
model : aif - pfc series december, 2004 revision 07 sh 21 of 30 technical reference note aif - pfc power factor correction series
model : aif - pfc series december, 2004 revision 07 sh 22 of 30 technical reference note aif - pfc power factor correction series
model : aif - pfc series december, 2004 revision 07 sh 23 of 30 technical reference note aif - pfc power factor correction series application example pfc module input connection example: model aif04zpfc-02 parallel operation the aif04zpfc-02 has been specifically designed for paralleling applications where the total input current exceeds 16arms. for stand-alone applications or those where the total input current does not exceed 16arms the AIF04ZPFC-01 is recommended. the aif04zpfc-02 requires external negative rail rectifiers to be implemented at the input to the system. it is possible to operate the aif04zpfc-02 as a stand-alone configuration although the external negative rail rectifiers must still be provided. current sharing in multi-module paralleled systems, all modules will share current to within 10% of the average load current per module when the c-share pins of each module are connected together.
model : aif - pfc series december, 2004 revision 07 sh 24 of 30 technical reference note aif - pfc power factor correction series interlock circuit between ld enable and pf enable (continues from p.9, ld enable) initially the load is disabled and the ld enable (pin 15) is at 0.4v (low). when the pfc power up sequence has completed, the ld enable voltage goes high. and the ld enable will stay high as long as vin is above 175vac or vout is above 250v, even if pf_enable is in disable mode. if the application needs the ld_en goes low when the pf_en is disable, please use the following interlock circuitry. ld_en goes low when pf_en is set low (AIF04ZPFC-01) ld_en goes low when pf_en is set high (AIF04ZPFC-01n)
model : aif - pfc series december, 2004 revision 07 sh 25 of 30 technical reference note aif - pfc power factor correction series synchronization modules are synchronized by connecting the clk out pin of one module to the clk in of the next module in an open daisy chain configuration. if the clock input to a module fails it will automatically revert to its internal clock and continue to operate at full power. * the current rate requirement of external rectifier for each line is 20a x number of units in parallel. for example, if there are 3 pieces of aif04zpfc-02 in parallel, customer will need to put 60a (20a x 3) external rectifier for each line.
model : aif - pfc series december, 2004 revision 07 sh 26 of 30 technical reference note aif - pfc power factor correction series recommend external inrush current limit circuit
model : aif - pfc series december, 2004 revision 07 sh 27 of 30 technical reference note aif - pfc power factor correction series brown out ride through brown out conditions occurs when there is a transient break in input current. during this period the external output bulk capacitor holds up the voltage to the load until input current is restored. when the input voltage is restored the pfc module will continue delivering power to the load after a brown out condition where the output voltage has not dropped below 250vdc, the module will recover when input power is restored. the pfw signal can be used to monitor input power loss.
model : aif - pfc series december, 2004 revision 07 sh 28 of 30 technical reference note aif - pfc power factor correction series thermal data natural convection thermal impedance of the pfc package without a heatsink is approximately 4c/w. a standard horizontal fin heatsink available from astec (part number apa501-80-006) with 37mm fins and 8.8mm pitch, will reduce module thermal impedance to 0.4c /w with a forced air flow of 2.5 m/s (500 lfm) when mounted with a thermal pad (astec p/n apa502-80-001) between heatsink and module. overtemperature protection if the module's internal temperature exceeds 105c (typical), the module will protect itself by latching off heatsink thermal resistance 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 500 1000 1500 air velocity (lfm) thermal resistance heatsink to ambient ( c/w) apa501-80-005 apa501-80-006
model : aif - pfc series december, 2004 revision 07 sh 29 of 30 technical reference note aif - pfc power factor correction series outline drawing case thickness can meet ul-v0 flammability standard. aif04zpfc-xxxnt aif04zpfc-xxx
model : aif - pfc series december, 2004 revision 07 sh 30 of 30 technical reference note aif - pfc power factor correction series comparison between aif - pfc and apa100 series AIF04ZPFC-01 aif04zpfc-02 apa100-101 apa100-101m apa100-102 apa100-103 apa100-104 input voltage max output power 85vac vin 120vac 550w 750w vin 3 220vac 950w 1200w vac under-voltage / power interrupt power line interrupt protection floating pv_aux supply v-aux frequency operating temperature remote on/off eeprom data storage inrush current limit circuit internal external internal external external parallel application input current total i in < 16arms no limit no limit external diode pair no need yes yes full load vo ld_enable trigger point minimum setting for pfw_adj encapsulated internal fuse yes (10a) no fully smt design qav control pins power pins mounting kits module colour 205vdc non-fixed frequency fixed at 250khz 1200w fast-recovery full recycle yes no not rated no need -20c - 100c various yes external yes yes 16 pins ? 2.06mm 280vdc no 85 - 264vac 380vdc yes no 1000w 1600w meet power line disturbance immunity specification per iec61000-4-11 250vdc output 14 pins ? 1.52mm emerson blue 85 - 265vac -20c - 85c negative logic only no 750w 377vdc partial 180vdc output need black total i in < 16arms no need total i in < 16arms no need no no

▲Up To Search▲

Price & Availability of AIF04ZPFC-01

	To Download AIF04ZPFC-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .