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| mos integrated circuit m m m m pd703100-33, 703100-40, 703101-33, 703102-33 v850e/ms1 tm 32-/16-bit single-chip microcontrollers document no. u13995ej2v0ds00 (2nd edition) date published november 2000 n cp(k) the mark shows major revised points. printed in japan data sheet 1999 the m pd703101-33 and m pd703102-33 are members of the v850 family tm of 32-bit single-chip microcontrollers designed for real-time control operations. these microcontrollers provide on-chip features, including a 32-bit cpu core, rom, ram, interrupt controller, real-time pulse unit, serial interface, a/d converter, and dma controller. the m pd703100-33 and m pd703100-40 are romless versions of the m pd703101-33 and m pd703102-33 products. the m pd703100a-33, m pd703100a-40, m pd703101a-33, and m pd703102a-33 are also available as products having a 3.3 v power supply for external pins. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. v850e/ms1 users manual hardware: u12688e v850e/ms1 users manual architecture: u12197e features ? number of instructions: 81 ? minimum instruction execution time 25 ns (@ 40 mhz operation) m pd703100-40 30 ns (@ 33 mhz operation) m pd703100-33, 703101-33, 703102-33 ? general-purpose registers 32 bits 32 ? instruction set optimized for control applications ? internal memory rom : none ( m pd703100-33, 703100-40), 96 kb ( m pd703101-33), 128 kb ( m pd703102-33) ram : 4 kb ? advanced on-chip interrupt controller ? real-time pulse unit suitable for control operations ? powerful serial interface (on-chip dedicated baud rate generator) ? on-chip clock generator ? 10-bit resolution a/d converter: 8 channels ? dma controller: 4 channels ? power saving functions applications ? office automation equipment: printers, facsimile machines, ppcs, etc. ? multimedia equipment: digital still cameras, video printers, etc. ? consumer equipment: single-lens reflex cameras, etc. ? industrial equipment: motor controllers, nc machine tools, etc. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet u13995ej2v0ds00 2 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 ordering information part number package maximum operating frequency internal rom m pd703100gj-33-uen 144-pin plastic lqfp (fine pitch) (20 20) 33 mhz none m pd703100gj-40-uen 144-pin plastic lqfp (fine pitch) (20 20) 40 mhz none m pd703101gj-33- xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) 33 mhz 96 kb m pd703102gj-33- xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) 33 mhz 128 kb remark xxx indicates rom code suffix. pin configuration (top view) 144-pin plastic lqfp (fine pitch) (20 20) ? m pd703100gj-33-uen ? m pd703101gj-33-xxx-uen ? m pd703100gj-40-uen ? m pd703102gj-33-xxx-uen intp103/ dmarq3/ p07 1 intp102/ dmarq2/ p06 2 intp101/ dmarq1/ p05 3 intp100/ dmarq0/ p04 4 ti10/ p03 5 tclr10/ p02 6 to101/ p01 7 to100/ p00 8 v ss 9 intp113/ dm aak3/ p17 10 intp112/ dm aak2/ p16 11 intp111/ dm aak1/ p15 12 intp110/ dm aak0/ p14 13 ti11/ p13 14 tclr11/ p12 15 to111/ p11 16 to110/ p10 17 intp123/ tc3/ p107 18 intp122/ tc2/ p106 19 intp121/ tc1/ p105 20 intp120/ tc0/ p104 21 ti12/ p103 22 tclr12/ p102 23 to121/ p101 24 to120/ p100 25 ani7/ p77 26 ani6/ p76 27 ani5/ p75 28 ani4/ p74 29 ani3/ p73 30 ani2/ p72 31 ani1/ p71 32 ani0/ p70 33 av dd 34 av ss 35 av ref 36 a16/ p60 108 a17/ p61 107 a18/ p62 106 a19/ p63 105 a20/ p64 104 a21/ p65 103 a22/ p66 102 a23/ p67 101 hv dd 100 cs0/ ras0/ p80 99 cs1/ ras1/ p81 98 cs2/ ras2/ p82 97 cs3/ ras3/ p83 96 cs4/ ras4/ iowr/ p84 95 cs5/ ras5/ iord/ p85 94 cs6/ ras6/ p86 93 cs7/ ras7/ p87 92 lcas/ lwr/ p90 91 ucas/ uwr/ p91 90 rd/ p9 2 89 we/ p9 3 88 bcyst/ p94 87 oe/ p9 5 86 hldak/ p96 85 hldrq/ p97 84 v ss 83 refrq/ px5 82 wai t/ px6 81 clkout/ px7 80 to150/ p120 79 to151/ p121 78 tclr15/ p122 77 ti15/ p123 76 intp150/ p124 75 intp151/ p125 74 intp152/ p126 73 v dd 144 d0/ p40 143 d1/ p41 142 d2/ p42 141 d3/ p43 140 d4/ p44 139 d5/ p45 138 d6/ p46 137 d7/ p47 136 v ss 135 d8/ p50 134 d9/ p51 133 d10/ p52 132 d11/ p53 131 d12/ p54 130 d13/ p55 129 d14/ p56 128 d15/ p57 127 hv dd 126 a0/ pa0 125 a1/ pa1 124 a2/ pa2 123 a3/ pa3 122 a4/ pa4 121 a5/ pa5 120 a6/ pa6 119 a7/ pa7 118 v ss 117 a8/ pb0 116 a9/ pb1 115 a10/ pb2 114 a11/ pb3 113 a12/ pb4 112 a13/ pb5 111 a14/ pb6 110 a15/ pb7 109 nmi/ p20 37 p21 38 txd0/so0/p22 39 rxd0/si0/p23 40 sck0/ p24 41 txd1/so1/p25 42 rxd1/si1/p26 43 sck1/ p27 44 v dd 45 intp133/ sck2/ p37 46 intp132/ si2/ p36 47 intp131/ so2/ p35 48 intp130/ p34 49 ti13/ p33 50 tclr13/ p32 51 to131/ p31 52 to130/ p30 53 intp143/ sck3/ p117 54 intp142/ si3/ p116 55 intp141/ so3/ p115 56 intp140/ p114 57 ti14/ p113 58 tclr14/ p112 59 to141/ p111 60 to140/ p110 61 cv dd 62 x2 63 x1 64 cv ss 65 cksel 66 mode0 67 mode1 68 mode2 69 mode3 70 reset 71 intp153/ adtrg/ p127 72 data sheet u13995ej2v0ds00 3 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 pin names a0 to a23: address bus p50 to p57: port 5 adtrg: ad trigger input p60 to p67: port 6 ani0 to ani7: analog input p70 to p77: port 7 av dd : analog power supply p80 to p87: port 8 av ref : analog reference voltage p90 to p97: port 9 av ss : analog ground p100 to p107: port 10 bcyst: bus cycle start timing p110 to p117: port 11 cksel : clock generator operating mode select p120 to p127: port 12 clkout: clock output pa0 to pa7: port a cs0 to cs7: chip select pb0 to pb7: port b cv dd : clock generator power supply px5 to px7: port x cv ss : clock generator ground ras0 to ras7: row address strobe d0 to d15: data bus rd: read dmaak0 to dmaak3 : dma acknowledge refrq: refresh request dmarq0 to dmarq3 : dma request reset: reset hldak: hold acknowledge rxd0, rxd1: receive data hldrq: hold request sck0 to sck3: serial clock hv dd : power supply for external pins si0 to si3: serial input intp100 to intp103, : interrupt request from peripherals so0 to so3: serial output intp110 to intp113, tc0 to tc3: terminal count signal intp120 to intp123, tclr10 to tclr15: timer clear intp130 to intp133, ti10 to ti15: timer input intp140 to intp143, to100, to101, : timer output intp150 to intp153 to110, to111, iord: i/o read strobe to120, to121, iowr: i/o write strobe to130, to131, lcas: lower column address strobe to140, to141, lwr: lower write strobe to150, to151 mode0 to mode3: mode txd0, txd1: transmit data nmi: non-maskable interrupt request ucas: upper column address strobe oe: output enable uwr: upper write strobe p00 to p07: port 0 v dd : power supply for internal unit p10 to p17: port 1 v ss : ground p20 to p27: port 2 wait: wait p30 to p37: port 3 we: write enable p40 to p47: port 4 x1, x2: crystal data sheet u13995ej2v0ds00 4 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 internal block diagram note m pd703100-33, 703100-40: none m pd703101-33: 96 kb (mask rom) m pd703102-33: 128 kb (mask rom) tclr10 to tclr15 ti10 to ti15 to100, to101, to110, to111, to120, to121, to130, to131, to140, to141, to150, to151 intp100 to intp103, intp110 to intp113, intp120 to intp123, intp130 to intp133, intp140 to intp143, intp150 to intp153 nmi intc rpu uart0/csi0 sio sck0 si0/rxd0 so0/txd0 brg0 uart1/csi1 sck1 si1/rxd1 so1/txd1 brg1 csi2 sck2 si2 so2 brg2 csi3 sck3 si3 so3 av ref adc av ss av dd adtrg ani0 to ani7 port px5 to px7 pb0 to pb7 pa0 to pa7 p120 to p127 p110 to p117 p100 to p107 p90 to p97 p80 to p87 p70 to p77 p60 to p67 p50 to p57 p40 to p47 p30 to p37 p21 to p27 p20 p10 to p17 p00 to p07 hv dd note rom 4 kb ram instruction queue pc system registers general-purpose registers (32 bits 32) multiplier (32 32 ? 64) barrel shifter alu dramc page rom controller dmac bcu cpu tc0 to tc3 lwr/lcas dmaak0 to dmarq3 dmarq0 to dmarq3 d0 to d15 a0 to a23 wait cs0 to cs7/ras0 to ras7 uwr/ucas oe rd we bcyst refrq iord iowr hldak hldrq cg cksel clkout x1 x2 cv dd cv ss system controller reset v dd v ss mode0 to mode3 data sheet u13995ej2v0ds00 5 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 contents 1. differences among products........................................................................................... 6 2. pin functions ............................................................................................................... .............. 7 2.1 port pins ................................................................................................................... .............. 7 2.2 non-port pins ............................................................................................................... .......... 10 2.3 pin i/o circuits and recommended connection of unused pins..................................... 14 3. electrical specifications ................................................................................................... 17 4. package drawing............................................................................................................. ........ 74 5. recommended soldering conditions ............................................................................. 75 data sheet u13995ej2v0ds00 6 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 1. differences among products product name m pd703100 m pd703101 m pd703102 m pd70f3102 item -33 -40 a-33 a-40 -33 a-33 -33 a-33 -33 a-33 internal rom none 96 kb (mask rom) 128 kb (mask rom) 128 kb (flash memory) maximum operating frequency 33 mhz 40 mhz 33 mhz 40 mhz 33 mhz hv dd 4.5 to 5.5 v 3.0 to 3.6 v 4.5 to 5.5 v 3.0 to 3.6 v 4.5 to 5.5 v 3.0 to 3.6 v 4.5 to 5.5 v 3.0 to 3.6 v operation mode single-chip mode 0, 1 none provided flash memory programming mode none provided flash memory programming pin none provided (v pp ) electrical specifications power consumptions differ (refer to the data sheet of each product). package 144lqfp 144lqfp 157fbga 144lqfp 144lqfp 157fbga 144lqfp 144lqfp 157fbga 144lqfp 144lqfp 157fbga others noise tolerance and noise radiation will differ due to the differences in circuit scale and mask layout. remark 144lqfp: 144-pin plastic lqfp (fine pitch) (20 20) 157fbga: 157-pin plastic fbga (14 14) data sheet u13995ej2v0ds00 7 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 2. pin functions 2.1 port pins (1/3) pin name i/o function alternate function p00 to100 p01 to101 p02 tclr10 p03 ti10 p04 intp100/dmarq0 p05 intp101/dmarq1 p06 intp102/dmarq2 p07 i/o port 0 8-bit i/o port input/output can be specified in 1-bit units intp103/dmarq3 p10 to110 p11 to111 p12 tclr11 p13 ti11 p14 intp110/dmaak0 p15 intp111/dmaak1 p16 intp112/dmaak2 p17 i/o port 1 8-bit i/o port input/output can be specified in 1-bit units intp113/dmaak3 p20 input nmi p21 C p22 txd0/so0 p23 rxd0/si0 p24 sck0 p25 txd1/so1 p26 rxd1/si1 p27 i/o port 2 p20 is an input only port. when a valid edge is input, this pin operates as nmi input. also, bit 0 of the p2 register indicates the nmi input status. p21 to p27 are 7-bit i/o port. input/output can be specified in 1-bit units sck1 p30 to130 p31 to131 p32 tclr13 p33 ti13 p34 intp130 p35 intp131/so2 p36 intp132/si2 p37 i/o port 3 8-bit i/o port input/output can be specified in 1-bit units intp133/sck2 p40 to p47 i/o port 4 8-bit i/o port input/output can be specified in 1-bit units d0 to d7 data sheet u13995ej2v0ds00 8 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (2/3) pin name i/o function alternate function p50 to p57 i/o port 5 8-bit i/o port input/output can be specified in 1-bit units d8 to d15 p60 to p67 i/o port 6 8-bit i/o port input/output can be specified in 1-bit units a16 to a23 p70 to p77 input port 7 8-bit input only port ani0 to ani7 p80 cs0/ras0 p81 cs1/ras1 p82 cs2/ras2 p83 cs3/ras3 p84 cs4/ras4/iowr p85 cs5/ras5/iord p86 cs6/ras6 p87 i/o port 8 8-bit i/o port input/output can be specified in 1-bit units cs7/ras7 p90 lcas/lwr p91 ucas/uwr p92 rd p93 we p94 bcyst p95 oe p96 hldak p97 i/o port 9 8-bit i/o port input/output can be specified in 1-bit units hldrq p100 to120 p101 to121 p102 tclr12 p103 ti12 p104 intp120/tc0 p105 intp121/tc1 p106 intp122/tc2 p107 i/o port 10 8-bit i/o port input/output can be specified in 1-bit units intp123/tc3 p110 to140 p111 to141 p112 tclr14 p113 ti14 p114 intp140 p115 intp141/so3 p116 intp142/si3 p117 i/o port 11 8-bit i/o port input/output can be specified in 1-bit units intp143/sck3 data sheet u13995ej2v0ds00 9 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (3/3) pin name i/o function alternate function p120 to150 p121 to151 p122 tclr15 p123 ti15 p124 intp150 p125 intp151 p126 intp152 p127 i/o port 12 8-bit i/o port input/output can be specified in 1-bit units intp153/adtrg pa0 a0 pa1 a1 pa2 a2 pa3 a3 pa4 a4 pa5 a5 pa6 a6 pa7 i/o port a 8-bit i/o port input/output can be specified in 1-bit units a7 pb0 a8 pb1 a9 pb2 a10 pb3 a11 pb4 a12 pb5 a13 pb6 a14 pb7 i/o port b 8-bit i/o port input/output can be specified in 1-bit units a15 px5 refrq px6 wait px7 i/o port x 3-bit i/o port input/output can be specified in 1-bit units clkout data sheet u13995ej2v0ds00 10 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 2.2 non-port pins (1/4) pin name i/o function alternate function to100 p00 to101 p01 to110 p10 to111 p11 to120 p100 to121 p101 to130 p30 to131 p31 to140 p110 to141 p111 to150 p120 to151 output pulse signal output for timers 10 to 15 p121 tclr10 p02 tclr11 p12 tclr12 p102 tclr13 p32 tclr14 p112 tclr15 input external clear signal input for timers 10 to 15 p122 ti10 p03 ti11 p13 ti12 p103 ti13 p33 ti14 p113 ti15 input external count clock input for timers 10 to 15 p123 intp100 p04/dmarq0 intp101 p05/dmarq1 intp102 p06/dmarq2 intp103 input external maskable interrupt request input, shared as external capture trigger input for timer 10 p07/dmarq3 intp110 p14/dmaak0 intp111 p15/dmaak1 intp112 p16/dmaak2 intp113 input external maskable interrupt request input, shared as external capture trigger input for timer 11 p17/dmaak3 intp120 p104/tc0 intp121 p105/tc1 intp122 p106/tc2 intp123 input external maskable interrupt request input, shared as external capture trigger input for timer 12 p107/tc3 data sheet u13995ej2v0ds00 11 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (2/4) pin name i/o function alternate function intp130 p34 intp131 p35/so2 intp132 p36/si2 intp133 input external maskable interrupt request input, shared as external capture trigger input for timer 13 p37/sck2 intp140 p114 intp141 p115/so3 intp142 p116/si3 intp143 input external maskable interrupt request input, shared as external capture trigger input for timer 14 p117/sck3 intp150 p124 intp151 p125 intp152 p126 intp153 input external maskable interrupt request input, shared as external capture trigger input for timer 15 p127/adtrg so0 p22/txd0 so1 p25/txd1 so2 p35/intp131 so3 output serial transmit data output (3-wire) for csi0 to csi3 p115/intp141 si0 p23/rxd0 si1 p26/rxd1 si2 p36/intp132 si3 input serial receive data input (3-wire) for csi0 to csi3 p116/intp142 sck0 p24 sck1 p27 sck2 p37/intp133 sck3 i/o serial clock i/o (3-wire) for csi0 to csi3 p117/intp143 txd0 p22/so0 txd1 output serial transmit data output for uart0 and uart1 p25/so1 rxd0 p23/si0 rxd1 input serial receive data input for uart0 and uart1 p26/si1 d0 to d7 p40 to p47 d8 to d15 i/o 16-bit data bus for external memory p50 to p57 a0 to a7 pa0 to pa7 a8 to a15 pb0 to pb7 a16 to a23 output 24-bit address bus for external memory p60 to p67 lwr output lower byte write-enable signal output for external data bus p90/lcas uwr output higher byte write-enable signal output for external data bus p91/ucas rd output read strobe signal output for external data bus p92 we output write enable signal output for dram p93 oe output output enable signal output for dram p95 data sheet u13995ej2v0ds00 12 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (3/4) pin name i/o function alternate function lcas output column address strobe signal output for drams lower data p90/lwr ucas output column address strobe signal output for drams higher data p91/uwr ras0 to ras3 p80/cs0 to p83/cs3 ras4 p84/cs4/iowr ras5 p85/cs5/iord ras6 p86/cs6 ras7 output low address strobe signal output for dram p87/cs7 bcyst output strobe signal output indicating start of bus cycle p94 cs0 to cs3 p80/ras0 to p83/ras3 cs4 p84/ras4/iowr cs5 p85/ras5/iord cs6 p86/ras6 cs7 output chip select signal output p87/ras7 wait input control signal input for inserting waits in bus cycle px6 refrq output refresh request signal output for dram px5 iowr output dma write strobe signal output p84/ras4/cs4 iord output dma read strobe signal output p85/ras5/cs5 dmarq0 to dmarq3 input dma request signal input p04/intp100 to p07/intp103 dmaak0 to dmaak3 output dma acknowledge signal output p14/intp110 to p17/intp113 tc0 to tc3 output dma end (terminal count) signal output p104/intp120 to p107/intp123 hldak output bus hold acknowledge output p96 hldrq input bus hold request input p97 ani0 to ani7 input analog input to a/d converter p70 to p77 nmi input non-maskable interrupt request input p20 clkout output system clock output px7 cksel input input for specifying clock generators operation mode C mode0 to mode3 input specify operation modes C reset input system reset input C x1 input C x2 C oscillator connection for system clock. i nput is via x1 when using an external clock. C adtrg input a/d converter external trigger input p127/intp153 av ref input reference voltage input for a/d converter C av dd C positive power supply for a/d converter C av ss C ground potential for a/d converter C data sheet u13995ej2v0ds00 13 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (4/4) pin name i/o function alternate function cv dd C positive power supply for dedicated clock generator C cv ss C ground potential for dedicated clock generator C v dd C positive power supply (power supply for internal units) C hv dd C positive power supply (power supply for external pins) C v ss C ground potential C data sheet u13995ej2v0ds00 14 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the i/o circuit type of each pin and recommended connection of unused pins. figure 2-1 shows the various circuit types using partially abridged diagrams. when connecting to v dd or v ss via a resistor, a resistance value in the range of 1 to 10 k w is recommended. table 2-1. i/o circuit type of each pin and recommended connection of unused pins (1/2) pin i/o circuit type recommended connection of unused pins p00/to100, p01/to101 5 p02/tclr10, p03/ti10 p04/intp100/dmarq0 to p07/intp103/dmarq3 5-k p10/to110, p11/to111 5 p12/tclr11, p13/ti11 p14/intp110/dmaak0 to p17/intp113/dmaak3 5-k input: independently connect to hv dd or v ss via a resistor output: leave open p20/nmi 2 connect directly to v ss p21 p22/txd0/so0 5 p23/rxd0/si0 p24/sck0 5-k p25/txd1/so1 5 p26/rxd1/si1 p27/sck1 5-k p30/to130, p31/to131 5 p32/tclr13, p33/ti13 p34/intp130 p35/intp131/so2 p36/intp132/si2 p37/intp133/sck2 5-k p40/d0 to p47/d7 p50/d8 to p57/d15 p60/a16 to p67/a23 5 input: independently connect to hv dd or v ss via a resistor output: leave open p70/ani0 to p77/ani7 9 connect directly to v ss p80/cs0/ras0 to p83/cs3/ras3 p84/cs4/ras4/iowr, p85/cs5/ras5/iord p86/cs6/ras6, p87/cs7/ras7 p90/lcas/lwr p91/ucas/uwr 5 input: independently connect to hv dd or v ss via a resistor output: leave open data sheet u13995ej2v0ds00 15 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 table 2-1. i/o circuit type of each pin and recommended connection of unused pins (2/2) pin i/o circuit type recommended connection of unused pins p92/rd p93/we p94/bcyst p95/oe p96/hldak p97/hldrq p100/to120, p101/to121 5 p102/tclr12, p103/ti12 p104/intp120/tc0 to p107/intp123/tc3 5-k p110/to140, p111/to141 5 p112/tclr14, p113/ti14 p114/intp140 p115/intp141/so3 p116/intp142/si3 p117/intp143/sck3 5-k p120/to150, p121/to151 5 p122/tclr15, p123/ti15 p124/intp150 to p126/intp152 p127/intp153/adtrg 5-k pa0/a0 to pa7/a7 pb0/a8 to pb7/a15 px5/refrq px6/wait px7/clkout 5 input: independently connect to hv dd or v ss via a resistor output: leave open cksel 1 connect directly to hv dd reset mode0 to mode2 C mode3 2 connect to v ss via a resistor (r vpp ) av ref , av ss C connect directly to v ss av dd C connect directly to hv dd data sheet u13995ej2v0ds00 16 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 figure 2-1. pin i/o circuits caution replace v dd by hv dd when referencing the circuit diagrams shown above. in p-ch v dd n-ch in data p-ch v dd n-ch in/out output disable input enable data p-ch v dd n-ch in/out output disable input enable in + C input enable p-ch n-ch v ref (threshold voltage) type 1 type 2 type 5 type 5-k type 9 comparator schmitt-triggered input with hysteresis characteristics data sheet u13995ej2v0ds00 17 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 3. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit v dd v dd pin - 0.5 to +4.6 v hv dd hv dd pin, hv dd 3 v dd - 0.5 to +7.0 v cv dd cv dd pin - 0.5 to +4.6 v cv ss cv ss pin - 0.5 to +0.5 v av dd av dd pin - 0.5 to hv dd + 0.5 v power supply voltage av ss av ss pin - 0.5 to +0.5 v x1 pin, except mode3 pin - 0.5 to hv dd + 0.5 v input voltage v i mode3 pin - 0.5 to v dd + 0.5 v clock input voltage v k x1, v dd = 3.0 to 3.6 v - 0.5 to v dd + 1.0 v 1 pin 4.0 ma output current, low i ol total of all pins 100 ma 1 pin - 4.0 ma output current, high i oh total of all pins - 100 ma output voltage v o hv dd = 5.0 v 10 % - 0.5 to hv dd + 0.5 v av dd > hv dd - 0.5 to hv dd + 0.5 v analog input voltage v ian p70/ani0 to p77/ani7 pins hv dd 3 av dd - 0.5 to av dd + 0.5 v av dd > hv dd - 0.5 to hv dd + 0.5 v a/d converter reference input voltage av ref hv dd 3 av dd - 0.5 to av dd + 0.5 v operating ambient temperature t a m pd703100-40 - 40 to +70 c m pd703100-33, 703101-33, 703102-33 - 40 to +85 c storage temperature t stg - 60 to +150 c cautions 1. do not make direct connections of the output (or input/output) pins of the ic product with each other, and also avoid direct connections to v dd , v cc , or gnd. however, the open drain pins or the open collector pins can be directly connected with each other. a direct connection can also be made for an external circuit designed with timing specifications that prevent conflicting output from pins subject to high-impedance state. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance. data sheet u13995ej2v0ds00 18 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 capacitance (t a = 25 c, v dd = hv dd = cv dd = v ss = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v. 15 pf operating conditions operation mode internal operating clock frequency ( f ) operating ambient temperature (t a ) power supply voltage (v dd , hv dd ) m pd703100-40 2 to 40 mhz - 40 to +70 c direct mode m pd703100-33, 703101-33, 703102-33 2 to 33 mhz - 40 to +85 c m pd703100-40 note 2 20 to 40 mhz - 40 to +70 c pll mode note 1 m pd703100-33, 703101-33, 703102-33 note 3 20 to 33 mhz - 40 to +85 c v dd = 3.0 to 3.6 v, hv dd = 5.0 v 10% notes 1. the internal operating clock frequency in pll mode is the value for 5 operation. when used for 1 or 1/2 operation as set by the ckdivn (n = 0, 1) bit of the ckc register, operation at a frequency of 20 mhz or less is possible. 2. set the input clock frequency used in pll mode to 4.0 to 8.0 mhz. 3. set the input clock frequency used in pll mode to 4.0 to 6.6 mhz. data sheet u13995ej2v0ds00 19 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 recommended oscillator (a) ceramic resonator (t a = - - - - 40 to +70 c ? m m m m pd703100-40, t a = - - - - 40 to +85 c ? m m m m pd703100-33, 703101-33, 703102-33) (i) murata mfg. co., ltd. (t a = - - - - 40 to +85 c) recommended circuit constant oscillation voltage range type part number oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k w ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) csac4.00mgc040 4.0 100 100 0 3.0 3.6 0.5 cstcc4.00mg0h6 4.0 on-chip on-chip 0 3.0 3.6 0.3 csac5.00mgc040 5.0 100 100 0 3.0 3.6 0.4 cstcc5.00mg0h6 5.0 on-chip on-chip 0 3.0 3.6 0.2 csac6.60mt 6.6 30 30 0 3.0 3.6 0.2 cstcc6.60mg0h6 6.6 on-chip on-chip 0 3.0 3.6 0.1 csac8.00mt 8.0 30 30 0 3.0 3.6 0.2 surface mounting cstcc8.00mg0h6 8.0 on-chip on-chip 0 3.0 3.6 0.3 csa4.00mg040 4.0 100 100 0 3.0 3.6 0.5 cst4.00mgw040 4.0 on-chip on-chip 0 3.0 3.6 0.5 csa5.00mg040 5.0 100 100 0 3.0 3.6 0.5 cst5.00mgw040 5.0 on-chip on-chip 0 3.0 3.6 0.5 csa6.60mtz 6.6 30 30 0 3.0 3.6 0.1 cst6.60mtw 6.6 on-chip on-chip 0 3.0 3.6 0.1 csa8.00mtz 8.0 30 30 0 3.0 3.6 0.1 lead cst8.00mtw 8.0 on-chip on-chip 0 3.0 3.6 0.1 cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area enclosed by broken lines. 3. sufficiently evaluate the matching between the m m m m pd703100-33, 703100-40, 703101-33, 703102-33 and the resonator. x1 c1 x2 c2 r d data sheet u13995ej2v0ds00 20 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (ii) tdk (t a = - - - - 40 to +85 c) recommended circuit constant oscillation voltage range manufac- turer part number oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k w ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) ccr4.0mc3 4.0 on-chip on-chip 0 3.0 3.6 0.17 ccr5.0mc3 5.0 on-chip on-chip 0 3.0 3.6 0.15 tdk ccr8.0mc5 8.0 on-chip on-chip 0 3.0 3.6 0.11 cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area enclosed by broken lines. 3. sufficiently evaluate the matching between the m m m m pd703100-33, 703100-40, 703101-33, 703102-33 and the resonator. (iii) kyocera corporation (t a = - - - - 20 to +80 c) recommended circuit constant oscillation voltage range manufac- turer part number oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k w ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) pbrc5.00br-a 5.0 on-chip on-chip 0 3.0 3.6 0.06 pbrc6.00br-a 6.0 on-chip on-chip 0 3.0 3.6 0.06 kyocera pbrc6.60br-a 6.6 on-chip on-chip 0 3.0 3.6 0.06 cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area enclosed by broken lines. 3. sufficiently evaluate the matching between the m m m m pd703100-33, 703100-40, 703101-33, 703102-33 and the resonator. x1 c1 x2 c2 r d x1 c1 x2 c2 r d data sheet u13995ej2v0ds00 21 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (b) external clock input (t a = ?40 to +70 c ... m m m m pd703100-40, t a = ?40 to +85 c ... m m m m pd703100-33, m m m m pd703101-33, m m m m pd703102-33) x1 x2 open external clock caution input cmos-level voltage to the x1 pin. data sheet u13995ej2v0ds00 22 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 dc characteristics (t a = ?40 to +70 c ... m m m m pd703100-40, t a = ?40 to +85 c ... m m m m pd703100-33, m m m m pd703101-33, m m m m pd703102-33, v dd = cv dd = 3.0 to 3.6 v, hv dd = 5.0 10%, v ss = 0 v) parameter symbol condition min. typ. max. unit except note 1 2.2 hv dd + 0.3 v input voltage, high v ih note 1 0.8hv dd hv dd + 0.3 v except note 1 and note 2 - 0.5 +0.8 v input voltage, low v il note 1 - 0.5 0.2hv dd v x1 pin direct mode 0.8v dd v dd + 0.3 v clock input voltage, high v xh pll mode 0.8v dd v dd + 0.3 v x1 pin direct mode - 0.3 0.15v dd v clock input voltage, low v xl pll mode - 0.3 0.15v dd v hv t + note 1 , rising edge 3.0 v schmitt-triggered input threshold voltage hv t - note 1 , falling edge 2.0 v schmitt-triggered input hysteresis width hv t + Chv t - note 1 0.5 v i oh = - 2.5 ma 0.7hv dd v output voltage, high v oh i oh = - 100 m ahv dd - 0.4 v output voltage, low v ol i ol = 2.5 ma 0.45 v input leakage current, high i lih except v i = h vdd or note 2 10 m a input leakage current, low i lil except v i = 0 v or note 2 - 10 m a output leakage current, high i loh v o = hv dd 10 m a output leakage current, low i lol v o = 0 v - 10 m a notes 1. p04/intp100/dmarq0 to p07/intp103/dmarq3, p14/intp110/dmaak0 to p17/intp113/dmaak3, p34/intp130, p35/intp131/so2, p36/intp132/si2, p37/intp133/sck2, p104/intp120/tc0 to p107/intp123/tc3, p114/intp140, p115/intp141/so3, p116/intp142/si3, p117/intp143/sck3, p124/intp150 to p126/intp152, p127/intp153/adtrg, p02/tclr10, p12/tclr11, p32/tclr13, p102/tclr12, p112/tclr14, p122/tclr15, p03/ti10, p13/ti11, p33/ti13, p103/ti12, p113/ti14, p123/ti15, p20/nmi, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, mode0 to mode2, reset 2. when the p70/ani0 to p77/ani7 pins are used as analog input. remark typ. values are reference values for when t a = 25 c, v dd = cv dd = 3.3 v, and hv dd = 5.0 v. data sheet u13995ej2v0ds00 23 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 dc characteristics (t a = ?40 to +70 c ... m m m m pd703100-40, t a = ?40 to +85 c ... m m m m pd703100-33, m m m m pd703101-33, m m m m pd703102-33, v dd = cv dd = 3.0 to 3.6 v, hv dd = 5.0 10%, v ss = 0 v) parameter symbol condition min. typ. max. unit v dd + cv dd 2.0 fx 3.6 fx ma normal mode i dd1 hv dd 1.8 fx 3.0 fx ma v dd + cv dd 1.4 fx 2.5 fx ma halt mode i dd2 hv dd 0.8 fx 1.6 fx ma v dd + cv dd 1.5 3.0 ma idle mode i dd3 hv dd 10 50 m a v dd + cv dd 1.0 3.0 ma m pd703100-40 hv dd 10 50 m a v dd + cv dd 20 100 m a power supply current stop mode i dd4 m pd703100-33, 703101-33, 703102-33 hv dd 10 50 m a remarks 1. typ. values are reference values for when t a = 25c, v dd = cv dd = 3.3 v, and hv dd = 5.0 v. 2. direct mode: f x = 2 to 40 mhz ( m pd703100-40) f x = 2 to 33 mhz ( m pd703100-33, m pd703101-33, m pd703102-33) pll mode: f x = 20 to 40 mhz ( m pd703100-40) f x = 20 to 33 mhz ( m pd703100-33, m pd703101-33, m pd703102-33) 3. the unit for f x is mhz. data sheet u13995ej2v0ds00 24 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 data hold characteristics (t a = ?40 to +70 c ... m m m m pd703100-40, t a = ?40 to +85 c ... m m m m pd703100-33, m m m m pd703101- 33, m m m m pd703102-33) parameter symbol condition min. typ. max. unit v dddr stop mode, v dd = v dddr 1.5 3.6 v data hold voltage hv dddr stop mode, hv dd = hv dddr v dddr 5.5 v m pd703100-40 v dd = v dddr 1.0 3.0 ma data hold current i dddr m pd703100-33, 703101-33, 703102-33 v dd = v dddr 30 150 m a power supply voltage rise time t rvd 200 m s power supply voltage fall time t fvd 200 m s power supply voltage hold time (to stop mode setting) t hvd 0ms stop mode release signal input time t drel 0ns data hold high-level input voltage v ihdr note 0.8hv dddr hv dddr v data hold low-level input voltage v ildr note 00.2hv dddr v note p04/intp100/dmarq0 to p07/intp103/dmarq3, p14/intp110/dmaak0 to p17/intp113/dmaak3, p34/intp130, p35/intp131/so2, p36/intp132/si2, p37/intp133/sck2, p104/intp120/tc0 to p107/intp123/tc3, p114/intp140, p115/intp141/so3, pl16/intp142/si3, p117/intp143/sck3, p124/intp150 to p126/intp152, p127/intp153/adtrg, p02/tclr10, p12/tclr11, p32/tclr13, p102/tclr12, p112/tclr14, p122/tclr15, p03/ti10, p13/ti11, p33/ti13, p103/ti12, p113/ti14, p123/ti15, p20/nmi, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, mode0 to mode2, reset remark typ. values are reference values for when t a = 25 c. data sheet u13995ej2v0ds00 25 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 hv dd reset (input) v ihdr v ihdr v ildr v dd t hvd t fvd v dddr t rvd t drel stop mode setting nmi (input) (released by falling edge) nmi (input) (released by rising edge) data sheet u13995ej2v0ds00 26 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 ac characteristics (t a = ?40 to +70 c ... m m m m pd703100-40, t a = ?40 to +85 c ... m m m m pd703100-33, m m m m pd703101-33, m m m m pd703102-33, v dd = cv dd = 3.0 to 3.6 v, hv dd = 5.0 10%, v ss = 0 v, output pin load capacitance: c l = 50 pf) ac test input waveform (a) p04/intp100/dmarq0 to p07/intp103/dmarq3, p14/intp110/dmaak0 to p17/intp113/dmaak3, p34/ intp130, p35/intp131/so2, p36/intp132/si2, p37/intp133/sck2, p104/intp120/tc0 to p107/intp123/ tc3, p114/intp140, p115/intp141/so3, p116/intp142/si3, p117/intp143/sck3, p124/intp150 to p126/ intp152, p127/intp153/adtrg, p02/tclr10, p12/tclr11, p32/tclr13, p102/tclr12, p112/tclr14, p122/tclr15, p03/ti10, p13/ti11, p33/ti13, p103/ti12, p113/ti14, p123/ti15, p20/nmi, p23/rxd0/si0, p24/ sck0, p26/rxd1/si1, p27/sck1, mode0 to mode2, reset hv dd 0 v 0.8hv dd 0.2hv dd 0.8hv dd 0.2hv dd test points input signal (b) pins other than those listed in (a) above 2.4 v 0.4 v 2.2 v 0.8 v 2.2 v 0.8 v test points input signal ac test output test points 2.4 v 0.8 v 2.4 v 0.8 v test points output signal data sheet u13995ej2v0ds00 27 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 load condition caution in cases where the load capacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other element to reduce the device's load capacitance 50 pf. (1) clock timing parameter symbol condition min. max. unit m pd703100-40 12.5 250 ns direct mode m pd703100-33, 703101-33, 703102-33 15 250 ns m pd703100-40 125 250 ns x1 input cycle <1> t cyx pll mode m pd703100-33, 703101-33, 703102-33 150 250 ns direct mode 5 ns x1 input high-level width <2> t wxh pll mode 50 ns direct mode 5 ns x1 input low-level width <3> t wxl pll mode 50 ns direct mode 4 ns x1 input rise time <4> t xr pll mode 10 ns x1 input fall time <5> t xf direct mode 4 ns pll mode 10 ns m pd703100-40 25 500 ns clkout output cycle <6> t cyk m pd703100-33, 703101-33, 703102-33 30 500 ns clkout high-level width <7> t wkh 0.5t C 7 ns clkout low-level width <8> t wkl 0.5t C 4 ns clkout rise time <9> t kr 5ns clkout fall time <10> t kf 5ns remark t = t cyk c l = 50 pf dut (device under test) data sheet u13995ej2v0ds00 28 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (2) output waveform (other than x1, clkout) parameter symbol condition min. max. unit output rise time <12> t or 10 ns output fall time <13> t of 10 ns <13> signals other than x1, clkout <12> <4> <5> <2> <3> <1> x1 (pll mode) <1> <2> <3> <4> <5> <9> <10> <7> <8> <6> x1 (direct mode) clkout (output) data sheet u13995ej2v0ds00 29 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (3) reset timing parameter symbol condition min. max. unit reset high-level width <14> t wrsh 500 ns when power supply is on, and stop mode has been released 500 + t os ns reset low-level width <15> t wrsl other than when power supply is on, and stop mode has been released 500 ns remark t os : oscillation stabilization time <14> <15> reset (input) data sheet u13995ej2v0ds00 30 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (4) sram, external rom, or external i/o access timing (a) access timing (sram, external rom, or external i/o) (1/2) parameter symbol condition min. max. unit address, csn output delay time (from clkout ) <16> t dka 210ns address, csn output hold time (from clkout ) <17> t hka 210ns rd, iord delay time (from clkout - ) <18> t dkrdl 214ns rd, iord - delay time (from clkout - ) <19> t hkrdh 214ns uwr, lwr, iowr delay time (from clkout - ) <20> t dkwrl 210ns uwr, lwr, iowr - delay time (from clkout - ) <21> t hkwrh 210ns bcyst delay time (from clkout ) <22> t dkbsl 210ns bcyst - delay time (from clkout ) <23> t hkbsh 210ns wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout - ) <26> t skid 18 ns data input hold time (from clkout - ) <27> t hkid 2ns data output delay time (from clkout ) <28> t dkod 210ns data output hold time (from clkout ) <29> t hkod 210ns remarks 1. maintain at least one of the data input hold times t hkid and t hrdid . 2. n = 0 to 7 data sheet u13995ej2v0ds00 31 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (a) access timing (sram, external rom, or external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) a0 to a23 (output) csn (output) bcyst (output) rd, iord (output) [read time] uwr, lwr, iowr (output) [write time] d0 to d15 (i/o) [read time] d0 to d15 (i/o) [write time] wait (input) <16> <17> <22> <23> <18> <19> <20> <21> <26> <27> <28> <29> <24> <25> <24> <25> t1 tw t2 data sheet u13995ej2v0ds00 32 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (b) read timing (sram, external rom, or external i/o) (1/2) parameter symbol condition min. max. unit data input setup time (to address) <30> t said (1.5 + w d + w)t C 28 ns data input setup time (to rd) <31> t srdid (1 + w d + w)t C 32 ns rd, iord low-level width <32> t wrdl (1 + w d + w)t C 10 ns rd, iord high-level width <33> t wrdh t C 10 ns delay time from address, csn to rd, iord <34> t dard 0.5t C 10 ns delay time from rd, iord - to address <35> t drda (0.5 + i)t C 10 ns data input hold time (from rd, iord - ) <36> t hrdid 0ns delay time from rd, iord - to data output <37> t drdod (0.5 + i)t C 10 ns wait setup time (to address) <38> t saw note t C 25 ns wait setup time (to bcyst ) <39> t sbsw note t C 25 ns wait hold time (from bcyst - ) <40> t hbsw note 0ns note for first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. i: the number of idle states that are inserted when a write cycle follows a read cycle. 5. maintain at least one of the data input hold times t hkid and t hrdid . 6. n = 0 to 7 data sheet u13995ej2v0ds00 33 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (b) read timing (sram, external rom, or external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0 to 7 uwr, lwr, iowr (output) rd, iord (output) d0 to d15 (i/o) t1 tw t2 clkout (output) <33> <32> <35> <38> <34> <31> <30> <36> <37> <39> <40> a0 to a23 (output) csn (output) wait (input) bcyst (output) data sheet u13995ej2v0ds00 34 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (c) write timing (sram, external rom, or external i/o) (1/2) parameter symbol condition min. max. unit wait setup time (to address) <38> t saw note t C 25 ns wait setup time (to bcyst ) <39> t sbsw note t C 25 ns wait hold time (from bcyst - ) <40> t hbsw note 0ns delay time from address, csn to uwr, lwr, iowr <41> t dawr 0.5t C 10 ns address setup time (to uwr, lwr, iowr - ) <42> t sawr (1.5 + w d + w)t C 10 ns delay time from uwr, lwr, iowr - to address <43> t dwra 0.5t C 10 ns uwr, lwr, iowr high-level width <44> t wwrh t C 10 ns uwr, lwr, iowr low-level width <45> t wwrl (1 + w d + w)t C 10 ns data output setup time (to uwr, lwr, iowr - ) <46> t sodwr (1.5 + w d + w)t C 10 ns data output hold time (from uwr, lwr, iowr - ) <47> t hwrod 0.5t C 10 ns note for first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. n = 0 to 7 data sheet u13995ej2v0ds00 35 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (c) write timing (sram, external rom, or external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0 to 7 t1 tw t2 clkout (output) <44> <45> <43> <38> <46> <47> <39> <40> <41> <42> a0 to a23 (output) csn (output) rd, iord (output) uwr, lwr, iowr (output) d0 to d15 (i/o) wait (input) bcyst (output) data sheet u13995ej2v0ds00 36 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (d) dma flyby transfer timing (sram ? ? ? ? external i/o transfer) (1/2) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns rd low-level width <32> t wrdl (1 + w d + w f + w) t C 10 ns rd high-level width <33> t wrdh t C 10 ns delay time from address, csn to rd <34> t dard 0.5t C 10 ns delay time from rd - to address <35> t drda (0.5 + i)t C 10 ns delay time from rd - to data output <37> t drdod (0.5 + i)t C 10 ns wait setup time (to address) <38> t saw note t C 25 ns wait setup time (to bcyst ) <39> t sbsw note t C 25 ns wait hold time (from bcyst - ) <40> t hbsw note 0ns delay time from address to iowr <41> t dawr 0.5t C 10 ns address setup time (to iowr - ) <42> t sawr (1.5 + w d + w)t C 10 ns delay time from iowr - to address <43> t dwra 0.5t C 10 ns iowr high-level width <44> t wwrh t C 10 ns iowr low-level width <45> t wwrl (1 + w d + w)t C 10 ns w f = 0 0 ns delay time from iowr - to rd - <48> t dwrrd w f = 1 t C 10 ns delay time from dmaakm to iowr <49> t ddawr 0.5t C 10 ns delay time from iowr - to dmaakm - <50> t dwrda (0.5 + w f )t C 10 ns note for first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. n = 0 to 7, m = 0 to 3 data sheet u13995ej2v0ds00 37 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (d) dma flyby transfer timing (sram ? ? ? ? external i/o transfer) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero and w f = 0. 2. the broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 clkout (output) t1 tw t2 <33> <32> <35> <34> <48> <50> <49> <43> <42> <41> <44> <45> <37> <38> <24> <24> <25> <25> <40> <39> a0 to a23 (output) csn (output) rd (output) dmaakm (output) iord (output) iowr (output) uwr, lwr (output) d0 to d15 (i/o) wait (input) bcyst (output) data sheet u13995ej2v0ds00 38 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (e) dma flyby transfer timing (external i/o ? ? ? ? sram transfer) (1/2) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns iord low-level width <32> t wrdl (1 + w d + w f + w)t C 10 ns iord high-level width <33> t wrdh t C 10 ns delay time from address, csn to iord <34> t dard 0.5t C 10 ns delay time from iord - to address <35> t drda (0.5 + i)t C 10 ns delay time from iord - to data output <37> t drdod (0.5 + i)t C 10 ns wait setup time (to address) <38> t saw note t C 25 ns wait setup time (to bcyst ) <39> t sbsw note t C 25 ns wait hold time (from bcyst - ) <40> t hbsw note 0ns delay time from address to uwr, lwr <41> t dawr 0.5t C 10 ns address setup time (to uwr, lwr - ) <42> t sawr (1.5 + w d + w)t C 10 ns delay time from uwr, lwr to address <43> t dwra 0.5t C 10 ns uwr, lwr high-level width <44> t wwrh t C 10 ns uwr, lwr low-level width <45> t wwrl (1 + w d + w)t C 10 ns w f = 0 0 ns delay time from uwr, lwr - to iord - <48> t dwrrd w f = 1 t C 10 ns delay time from dmaakm to iord <51> t ddard 0.5t C 10 ns delay time from iord - to dmaakm - <52> t drdda 0.5t C 10 ns note for first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. n = 0 to 7, m = 0 to 3 data sheet u13995ej2v0ds00 39 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (e) dma flyby transfer timing (external i/o ? ? ? ? sram transfer) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero and w f = 0. 2. the broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 clkout (output) t1 tw t2 <44> <45> <48> <52> <33> <37> <38> <24> <24> <25> <25> <40> <39> <42> <41> <43> <51> <32> <35> <34> a0 to a23 (output) csn (output) uwr, lwr (output) rd (output) dmaakm (output) iowr (output) iord (output) d0 to d15 (i/o) wait (input) bcyst (output) data sheet u13995ej2v0ds00 40 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (5) page rom access timing (1/2) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout - ) <26> t skid 18 ns data input hold time (from clkout - ) <27> t hkid 2ns off-page data input setup time (to address) <30> t said (1.5 + w d + w)t C 28 ns off-page data input setup time (to rd) <31> t srdid (1 + w d + w)t C 32 ns off-page rd low-level width <32> t wrdl (1 + w d + w)t C 10 ns rd high-level width <33> t wrdh 0.5t C 10 ns data input hold time (from rd) <36> t hrdid 0ns delay time from rd - to data output <37> t drdod (0.5 + i)t C 10 ns on-page rd low-level width <53> t wordl (1.5 + w pr + w)t C 10 ns on-page data input setup time (to address) <54> t soaid (1.5 + w pr + w)t C 28 ns on-page data input setup time (to rd) <55> t sordid (1.5 + w pr + w)t C 32 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. w pr : the number of waits due to the prc register. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. maintain at least one of the data input hold times t hkid and t hrdid . data sheet u13995ej2v0ds00 41 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (5) page rom access timing (2/2) note on-page and off-page addresses are as follows. prc register ma5 ma4 ma3 on-page addresses off-page addresses 0 0 0 a0, a1 a2 to a23 0 0 1 a0 to a2 a3 to a23 0 1 1 a0 to a3 a4 to a23 1 1 1 a0 to a4 a5 to a23 remarks 1. this is the timing for the following case. number of waits due to the dwc1 and dwc2 registers (tdw): 1 number of waits due to the prc register (tprw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) on-page address note t1 tdw tw t2 to1 tprw tw to2 <24> <25> <24> <25> <24> <25> <24> <25> <26> <27> <36> <32> <31> <53> <55> <27> <26> <36> <37> <33> <30> <54> off-page address note csn (output) uwr, lwr (output) rd (output) d0 to d15 (i/o) wait (input) bcyst (output) data sheet u13995ej2v0ds00 42 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (6) dram access timing (a) read timing (high-speed page dram access, normal access: off-page) (1/3) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout - ) <26> t skid 18 ns data input hold time (from clkout - ) <27> t hkid 2ns delay time from oe - to data output <37> t drdod (0.5 + i)t C 10 ns row address setup time <56> t asr (0.5 + w rp )t C 10 ns row address hold time <57> t rah (0.5 + w rh )t C 10 ns column address setup time <58> t asc 0.5t C 10 ns column address hold time <59> t cah (1.5 + w da + w)t C 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w) t C 10 ns ras precharge time <61> t rp (0.5 + w rp )t C 10 ns ras pulse time <62> t ras (2.5 + w rh + w da + w)t C 10 ns ras hold time <63> t rsh (1.5 + w da + w)t C 10 ns column address read time for ras <64> t ral (2 + w da + w)t C 10 ns cas pulse width <65> t cas (1 + w da + w)t C 10 ns cas-ras precharge time <66> t crp (1 + w rp )t C 10 ns cas hold time <67> t csh (2 + w rh + w da + w)t C 10 ns we setup time <68> t rcs (2 + w rp + w rh )t C 10 ns we hold time (from ras - ) <69> t rrh 0.5t C 10 ns we hold time (from cas - ) <70> t rch t C 10 ns cas precharge time <71> t cpn (2 + w rp + w rh )t C 10 ns output enable access time <72> t oea (2 + w rp + w rh + w da + w) t C 28 ns ras access time <73> t rac (2 + w rh + w da + w) t C 28 ns access time from column address <74> t aa (1.5 + w da + w)t C 28 ns cas access time <75> t cac (1 + w da + w)t C 28 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: the number of idle states that are inserted when a write cycle follows a read cycle. data sheet u13995ej2v0ds00 43 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (a) read timing (high-speed page dram access, normal access: off-page) (2/3) parameter symbol condition min. max. unit ras column address delay time <76> t rad (0.5 + w rh )t C 10 ns ras-cas delay time <77> t rcd (1 + w rh )t C 10 ns output buffer turn-off delay time (from oe - ) <78> t oez 0ns output buffer turn-off delay time (from cas - ) <79> t off 0ns remarks 1. t = t cyk 2. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). data sheet u13995ej2v0ds00 44 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (a) read timing (high-speed page dram access, normal access: off-page) (3/3) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 trpw trhw t2 t1 tdaw tw t3 <56> <61> <57> <58> <59> <62> <76> <63> <64> <60> <77> <65> <67> <66> <71> <73> <68> <75> <74> <72> <70> <69> <79> <37> <27> <25> <26> <25> <24> <78> <24> clkout (output) a0 to a23 (output) rasn (output) we (output) oe (output) wait (input) d0 to d15 (i/o) ucas (output) lcas (output) row address column address data sheet u13995ej2v0ds00 45 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 [memo] data sheet u13995ej2v0ds00 46 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (b) read timing (high-speed page dram access: on-page) (1/2) parameter symbol condition min. max. unit data input setup time (to clkout - ) <26> t skid 18 ns data input hold time (from clkout - ) <27> t hkid 2ns delay time from oe - to data output <37> t drdod (0.5 + i)t C 10 ns column address setup time <58> t asc (0.5 + w cp )t C 10 ns column address hold time <59> t cah (1.5 + w da )t C 10 ns ras hold time <63> t rsh (1.5 + w da )t C 10 ns column address read time for ras <64> t ral (2 + w cp + w da )t C 10 ns cas pulse width <65> t cas (1 + w da )t C 10 ns we setup time (to cas ) <68> t rcs (1 + w cp )t C 10 ns we hold time (from ras - ) <69> t rrh 0.5t C 10 ns we hold time (from cas - ) <70> t rch t C 10 ns output enable access time <72> t oea (1 + w cp + w da )t C 28 ns access time from column address <74> t aa (1.5 + w cp + w da ) t C 28 ns cas access time <75> t cac (1 + w da )t C 28 ns output buffer turn-off delay time (from oe - ) <78> t oez 0ns output buffer turn-off delay time (from cas - ) <79> t off 0ns access time from cas precharge <80> t acp (2 + w cp + w da )t C 28 ns cas precharge time <81> t cp (1 + w cp )t C 10 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da )t C 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da ) t C 10 ns remarks 1. t = t cyk 2. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. i: the number of idle states that are inserted when a write cycle follows a read cycle. data sheet u13995ej2v0ds00 47 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (b) read timing (high-speed page dram access: on-page) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 tcpw to1 tdaw to2 <58> <59> <63> <64> <83> <65> <81> <82> <68> <75> <72> <26> <79> <37> <74> <80> <27> <78> <70> <69> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) wait (input) column address data sheet u13995ej2v0ds00 48 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (c) write timing (high-speed page dram access, normal access: off-page) (1/2) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns row address setup time <56> t asr (0.5 + w rp )t C 10 ns row address hold time <57> t rah (0.5 + w rh )t C 10 ns column address setup time <58> t asc 0.5t C 10 ns column address hold time <59> t cah (1.5 + w da + w)t C 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w)t C 10 ns ras precharge time <61> t rp (0.5 + w rp )t C 10 ns ras pulse time <62> t ras (2.5 + w rh + w da + w)t C 10 ns ras hold time <63> t rsh (1.5 + w da + w)t C 10 ns column address read time (from ras - ) <64> t ral (2 + w da + w)t C 10 ns cas pulse width <65> t cas (1 + w da + w)t C 10 ns cas-ras precharge time <66> t crp (1 + w rh )t C 10 ns cas hold time <67> t csh (2 + w rh + w da + w)t C 10 ns cas precharge time <71> t cpn (2 + w rp + w rh )t C 10 ns ras column address delay time <76> t rad (0.5 + w rh )t C 10 ns ras-cas delay time <77> t rcd (1 + w rh )t C 10 ns we setup time (to cas ) <84> t wcs (1 + w rp + w rh )t C 10 ns we hold time (from cas ) <85> t wch (1 + w da + w)t C 10 ns data setup time (to cas ) <86> t ds (1.5 + w rp + w rh ) t C 10 ns data hold time (from cas ) <87> t dh (1.5 + w da + w)t C 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). data sheet u13995ej2v0ds00 49 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (c) write timing (high-speed page dram access, normal access: off-page) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 trpw trhw t2 t1 tdaw tw t3 <56> <61> <57> <58> <59> <62> <76> <63> <64> <60> <77> <65> <67> <66> <71> <84> <25> <25> <24> <24> <85> <86> <87> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) wait (input) row address column address data sheet u13995ej2v0ds00 50 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (d) write timing (high-speed page dram access: on-page) (1/2) parameter symbol condition min. max. unit column address setup time <58> t asc (0.5 + w cp )t C 10 ns column address hold time <59> t cah (1.5 + w da )t C 10 ns ras hold time <63> t rsh (1.5 + w da )t C 10 ns column address read time (from ras - ) <64> t ral (2 + w cp + w da )t C 10 ns cas pulse width <65> t cas (1 + w da )t C 10 ns cas precharge time <81> t cp (1 + w cp )t C 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da )t C 10 ns we setup time (to cas ) <84> t wcs w cp 3 1w cp t C 10 ns we hold time (from cas ) <85> t wch (1 + w da )t C 10 ns data setup time (to cas ) <86> t ds (0.5 + w cp )t C 10 ns data hold time (from cas ) <87> t dh (1.5 + w da )t C 10 ns we read time (from ras - ) <88> t rwl w cp = 0 (1.5 + w da )t C 10 ns we read time (from cas - ) <89> t cwl w cp = 0 (1 + w da )t C 10 ns data setup time (to we ) <90> t dswe w cp = 0 0.5t C 10 ns data hold time (from we ) <91> t dhwe w cp = 0 (1.5 + w da )t C 10 ns we pulse width <92> t wp w cp = 0 (1 + w da )t C 10 ns remarks 1. t = t cyk 2. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). data sheet u13995ej2v0ds00 51 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (d) write timing (high-speed page dram access: on-page) (2/2) tcpw to1 tdaw to2 <58> <59> <63> <64> <83> <81> <65> <89> <88> <84> <85> <92> <91> <86> <87> <90> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) oe (output) we (output) d0 to d15 (i/o) wait (input) column address remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the cpcxx bit of the drcn register (tcpw ): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 data sheet u13995ej2v0ds00 52 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (e) read timing (edo dram) (1/3) parameter symbol condition min. max. unit data input setup time (to clkout - ) <26> t skid 18 ns data input hold time (from clkout - ) <27> t hkid 2ns delay time from oe - to data output <37> t drdod (0.5 + i)t C 10 ns row address setup time <56> t asr (0.5 + w rp )t C 10 ns row address hold time <57> t rah (0.5 + w rh )t C 10 ns column address setup time <58> t asc 0.5t C 10 ns column address hold time <59> t cah (0.5 + w da )t C 10 ns ras precharge time <61> t rp (0.5 + w rp )t C 10 ns column address read time (from ras - ) <64> t ral (2 + w cp + w da )t C 10 ns cas-ras precharge time <66> t crp (1 + w rp )t C 10 ns cas hold time <67> t csh (1.5 + w rh + w da ) t C 10 ns we setup time (to cas ) <68> t rcs (2 + w rp + w rh )t C 10 ns we hold time (from ras - ) <69> t rrh 0.5t C 10 ns we hold time (from cas - ) <70> t rch 1.5t C 10 ns ras access time <73> t rac (2 + w rh + w da ) t C 28 ns access time from column address <74> t aa (1.5 + w da )t C 28 ns cas access time <75> t cac (1 + w da )t C 28 ns delay time from ras to column address <76> t rad (0.5 + w rh )t C 10 ns ras-cas delay time <77> t rcd (1 + w rh )t C 10 ns output buffer turn-off delay time (from oe) <78> t oez 0ns access time from cas precharge <80> t acp (1.5 + w cp + w da ) t C 28 ns cas precharge time <81> t cp (0.5 + w cp )t C 10 ns ras hold time for cas precharge <83> t rhcp (2 + w cp + w da )t C 10 ns read cycle time <93> t hpc (1 + w da + w cp )t C 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da ) t C 10 ns cas pulse width <95> t hcas (0.5 + w da )t C 10 ns off-page <96> t och1 (2 + w rh + w da )t C 10 ns cas hold time from oe on-page <97> t och2 (0.5 + w da )t C 10 ns data input hold time (from cas ) <98> t dhc 0ns remarks 1. t = t cyk 2. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: the number of idle states that are inserted when a write cycle follows a read cycle. data sheet u13995ej2v0ds00 53 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (e) read timing (edo dram) (2/3) parameter symbol condition min. max. unit off-page <99> t oea1 (2 + w rp + w rh + w da )t C 28 ns output enable access time on-page <100> t oea2 (1 + w cp + w da ) t C 28 ns remarks 1. t = t cyk 2. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). data sheet u13995ej2v0ds00 54 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (e) read timing (edo dram) (3/3) note for on-page access from another cycle during the rasn low-level signal. remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 trpw t1 trhw t2 tdaw tcpw tb tdaw te <56> <57> <59> <58> <76> <64> <94> <61> <67> <83> <77> <95> <81> <75> <66> <93> <95> <80> <97> <74> <27> <78> data <74> data <70> <69> <68> <96> <100> <26> <37> <27> <98> <26> <75> <73> <99> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) bcyst (output) wait (input) row address column address column address note data sheet u13995ej2v0ds00 55 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 [memo] data sheet u13995ej2v0ds00 56 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (f) write timing (edo dram) (1/2) parameter symbol condition min. max. unit row address setup time <56> t asr (0.5 + w rp )t C 10 ns row address hold time <57> t rah (0.5 + w rh )t C 10 ns column address setup time <58> t asc 0.5t C 10 ns column address hold time <59> t cah (0.5 + w da )t C 10 ns ras precharge time <61> t rp (0.5 + w rp )t C 10 ns ras hold time <63> t rsh (1.5 + w da )t C 10 ns column address read time (from ras - ) <64> t ral (2 + w cp + w da )t C 10 ns cas-ras precharge time <66> t crp (1 + w rp )t C 10 ns cas hold time <67> t csh (1.5 + w rh + w da ) t C 10 ns delay time from ras to column address <76> t rad (0.5 + w rh )t C 10 ns ras-cas delay time <77> t rcd (1 + w rh )t C 10 ns cas precharge time <81> t cp (0.5 + w cp )t C 10 ns ras hold time for cas precharge <83> t rhcp (2 + w cp + w da )t C 10 ns we hold time (from cas ) <85> t wch (1 + w da )t C 10 ns data hold time (from cas ) <87> t dh (0.5 + w da )t C 10 ns we read time (from ras - ) on-page <88> t rwl w cp = 0 (1.5 + w da )t C 10 ns we read time (from cas - ) on-page <89> t cwl w cp = 0 (0.5 + w da )t C 10 ns we pulse width on-page <92> t wp w cp = 0 (1 + w da )t C 10 ns write cycle time <93> t hpc (1 + w da + w cp )t C 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da ) t C 10 ns cas pulse width <95> t hcas (0.5 + w da )t C 10 ns off-page <101> t wcs1 (1 + w rp + w rh ) t C 10 ns we setup time (to cas ) on-page <102> t wcs2 w cp 3 1w cp t C 10 ns off-page <103> t ds1 (1.5 + w rp + w rh ) t C 10 ns data setup time (to cas ) on-page <104> t ds2 (0.5 + w cp )t C 10 ns remarks 1. t = t cyk 2. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). data sheet u13995ej2v0ds00 57 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (f) write timing (edo dram) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 trpw t1 trhw t2 tdaw tcpw tb tdaw te <56> <57> <59> <58> <58> <59> <76> <64> <94> <61> <67> <83> <77> <95> <81> <63> <66> <93> <95> <89> <88> <102> <101> <92> <85> <85> <103> <87> <104> <87> data data clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) rd (output) oe (output) we (output) d0 to d15 (i/o) bcyst (output) wait (input) row address column address column address data sheet u13995ej2v0ds00 58 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (g) dma flyby transfer timing (dram (edo, high-speed page) ? ? ? ? external i/o transfer) (1/3) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns delay time from oe - to data output <37> t drdod (0.5 + i)t C 10 ns delay time from address to iowr <41> t dawr (0.5 + w rp )t C 10 ns address setup time (to iowr - ) <42> t sawr (2 + w rp + w rh + w da + w)t C 10 ns delay time from iowr - to address <43> t dwra 0.5t C 10 ns w f = 0 0 ns delay time from iowr - to rd - <48> t dwrrd w f = 1 t C 10 ns iowr low-level width <50> t wwrl (2 + w rh + w da + w)t C 10 ns row address setup time <56> t asr (0.5 + w rp )t C 10 ns row address hold time <57> t rah (0.5 + w rh )t C 10 ns column address setup time <58> t asc 0.5t C 10 ns column address hold time <59> t cah (1.5 + w da + w f + w)t C 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w f + w)t C 10 ns ras precharge time <61> t rp (0.5 + w rp )t C 10 ns ras hold time <63> t rsh (1.5 + w da + w f + w)t C 10 ns column address read time for ras <64> t ral (2 + w cp + w da + w f + w)t C 10 ns cas pulse width <65> t cas (1 + w da + w f + w)t C 10 ns cas-ras precharge time <66> t crp (1 + w rp )t C 10 ns cas hold time <67> t csh (2 + w rh + w da + w f + w) t C 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5 .w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 8. i: the number of idle states that are inserted when a write cycle follows a read cycle. data sheet u13995ej2v0ds00 59 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (g) dma flyby transfer timing (dram (edo, high-speed page) ? ? ? ? external i/o transfer) (2/3) parameter symbol condition min. max. unit we setup time (to cas ) <68> t rcs (2 + w rp + w rh )t C 10 ns we hold time (from ras - ) <69> t rrh 0.5t C 10 ns we hold time (from cas - ) <70> t rch 1.5t C 10 ns cas precharge time <71> t cpn (2 + w rp + w rh )t C 10 ns delay time from ras to column address <76> t rad (0.5 + w rh )t C 10 ns ras-cas delay time <77> t rcd (1 + w rh )t C 10 ns output buffer turn-off delay time (from oe - ) <78> t oez 0ns output buffer turn-off delay time (from cas - ) <79> t off 0ns cas precharge time <81> t cp (0.5 + w cp )t C 10 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da + w f + w) t C 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da + w f + w) t C 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da + w f + w)t C 10 ns off-page <96> t och1 (2.5 + w rp + w rh + w da + w f + w)t C 10 ns cas hold time from oe (from cas - ) on-page <97> t och2 (1.5 + w cp + w da + w f + w) t C 10 ns delay time from dmaakm to cas <105> t ddacs (1.5 + w rh )t C 10 ns delay time from iowr to cas <106> t drdcs (1 + w rh )t C 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 8. m = 0 to 3 data sheet u13995ej2v0ds00 60 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (g) dma flyby transfer timing (dram (edo, high-speed page) ? ? ? ? external i/o transfer) (3/3) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits that are inserted for a source-side access during a dma flyby transfer: 0 2. the broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 trpw t1 trhw t2 tdaw tw t3 tcpw to1 to2 tw tdaw <56> <57> <58> <59> <76> <61> <60> <94> <64> <77> <65> <83> <63> <81> <67> <66> <71> <82> <96> <105> <68> <69> <70> <79> <48> <97> <106> <42> <41> <50> <43> <78> <37> <24> <25> <24> <25> <25> <24> data data clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) rd (output) oe (output) dmaakm (output) we (output) iord (output) iowr (output) d0 to d15 (i/o) wait (input) bcyst (output) row address column address column address data sheet u13995ej2v0ds00 61 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (h) dma flyby transfer timing (external i/o ? ? ? ? dram (edo, high-speed page) transfer) (1/3) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns iord low-level width <32> t wrdl (2 + w rh + w da + w f + w)t C 10 ns iord high-level width <33> t wrdh t C 10 ns delay time from address to iord - <34> t dard 0.5t C 10 ns delay time from iord - to address <35> t drda (0.5 + i)t C 10 ns row address setup time <56> t asr (0.5 + w rp )t C 10 ns row address hold time <57> t rah (0.5 + w rh )t C 10 ns column address setup time <58> t asc 0.5t C 10 ns column address hold time <59> t cah (1.5 + w da + w f )t C 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w f + w)t C 10 ns ras precharge time <61> t rp (0.5 + w rp )t C 10 ns ras hold time <63> t rsh (1.5 + w da + w f )t C 10 ns column address read time for ras <64> t ral (2 + w cp + w da + w f + w)t C 10 ns cas pulse width <65> t cas (1 + w da + w f )t C 10 ns cas-ras precharge time <66> t crp (1 + w rp )t C 10 ns cas hold time <67> t csh (2 + w rh + w da + w f + w)t C 10 ns cas precharge time <71> t cpn (2 + w rp + w rh + w)t C 10 ns delay time from ras to column address <76> t rad (0.5 + w rh )t C 10 ns ras-cas delay time <77> t rcd (1 + w rh + w)t C 10 ns cas precharge time <81> t cp (0.5 + w cp + w)t C 10 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da + w f + w)t C 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da + w)t C 10 ns we hold time (from cas ) <85> t wch (1 + w da )t C 10 ns we read time (from ras - ) <88> t rwl w cp = 0 (1.5 + w da + w)t C 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 8. i: the number of idle states that are inserted when a write cycle follows a read cycle. 9. n = 0 to 7 data sheet u13995ej2v0ds00 62 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (h) dma flyby transfer timing (external i/o ? ? ? ? dram (edo, high-speed page) transfer) (2/3) parameter symbol condition min. max. unit we read time (from cas - ) <89> t cwl w cp = 0 (1 + w da + w)t C 10 ns we pulse width <92> t wp w cp = 0 (1 + w da + w)t C 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da + w f + w)t C 10 ns off-page <101> t wcs1 w cp = 0 (1 + w rh + w rp + w)t C 10 ns we setup time (to cas ) on-page <102> t wcs2 w cp 3 1w cp t C 10 ns delay time from dmaakm to cas <105> t ddacs (1.5 + w rh + w)t C 10 ns delay time from iord to cas <106> t drdcs (1 + w rh + w)t C 10 ns delay time from we - to iord - <107> t dwerd w f = 0 0 ns w f = 1 t C 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 8. m = 0 to 3 data sheet u13995ej2v0ds00 63 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (h) dma flyby transfer timing (external i/o ? ? ? ? dram (edo, high-speed page) transfer) (3/3) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits that are inserted for a source-side access during a dma flyby transfer: 0 2. the broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 trpw t1 trhw tw t2 tdaw t3 tcpw tw to2 tdaw to1 <56> <57> <58> <76> <61> <60> <94> <64> <77> <65> <63> <81> <67> <66> <71> <82> <101> <105> <83> <85> <89> <106> <34> <107> <33> <24> <25> <24> <25> <24> data data <59> <88> <102> <92> <35> <32> <25> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) rd (output) oe (output) dmaakm (output) we (output) iowr (output) iord (output) d0 to d15 (i/o) wait (input) bcyst (output) row address column address column address data sheet u13995ej2v0ds00 64 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (i) cbr refresh timing parameter symbol condition min. max. unit ras precharge time <61> t rp (1.5 + w rrw )t C 10 ns ras pulse width <62> t ras (1.5 + w rcw note )t C 10 ns cas hold time <108> t chr (1.5 + w rcw note )t C 10 ns refrq pulse width <109> t wrfl (3 + w rrw + w rcw note )t C 10 ns ras precharge cas hold time <110> t rpc (0.5 + w rrw )t C 10 ns refrq active delay time (from clkout ) <111> t dkrf 210ns refrq inactive delay time (from clkout ) <112> t hkrf 210ns cas setup time <113> t csr t C 10 ns note at least one clock cycle is inserted by default for w rcw regardless of the settings of the rcw0 to rcw2 bits of the rwc register. remarks 1. t = t cyk 2. w rrw : the number of waits due to the rrw0 and rrw1 bits of the rwc register. 3. w rcw : the number of waits due to the rcw0 to rcw2 bits of the rwc register. ti refrq (output) t3 trcw trcw note t2 t1 trrw <109> <111> <112> rasn (output) <62> ucas (output) <108> <110> <61> <113> <110> lcas (output) clkout (output) note this trcw is always inserted regardless of the settings of the rcw0 to rcw2 bits of the rwc register. remarks 1. this is the timing for the following case. number of waits due to the rrw0 and rrw1 bits of the rwc register (trrw): 1 number of waits due to the rcw0 to rcw2 bits of the rwc register (trcw): 2 2. n = 0 to 7 data sheet u13995ej2v0ds00 65 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (j) cbr self-refresh timing parameter symbol condition min. max. unit refrq active delay time (from clkout ) <111> t dkrf 210ns refrq inactive delay time (from clkout ) <112> t hkrf 210ns cas hold time <114> t chs - 5ns ras precharge time <115> t rps (1 + 2w srw )t C 10 ns remarks 1. t = t cyk 2. w srw : the number of waits due to the srw0 to srw2 bits of the rwc register. remarks 1. this is the timing for the following case. number of waits due to the rrw0 and rrw1 bits of the rwc register (trrw): 1 number of waits due to the rcw0 to rcw2 bits of the rwc register (trcw): 1 number of waits due to the srw0 to srw2 bits of the rwc register (tsrw): 2 2. the broken lines indicate high impedance. 3. n = 0 to 7 <111> th th th trrw tsrw ti th trcw tsrw output signals other than above <115> <112> <114> clkout (output) refrq (output) rasn (output) ucas (output) lcas (output) data sheet u13995ej2v0ds00 66 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (7) dmac timing parameter symbol condition min. max. unit dmarqn setup time (to clkout - ) <116> t sdrk 15 ns <117> t hkdr1 2ns dmarqn hold time (from clkout - ) <118> t hkdr2 until dmaakn ns dmaakn output delay time (from clkout ) <119> t dkda 210ns dmaakn output hold time (from clkout ) <120> t hkda 210ns tcn output delay time (from clkout ) <121> t dktc 210ns tcn output hold time (from clkout ) <122> t hktc 210ns remark n = 0 to 3 remark n = 0 to 3 <121> dmarqn (input) dmaakn (output) tcn (output) <122> <120> <119> <118> <117> <116> <116> clkout (output) data sheet u13995ej2v0ds00 67 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 [memo] data sheet u13995ej2v0ds00 68 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (8) bus hold timing (1/2) parameter symbol condition min. max. unit hldrq setup time (to clkout - ) <123> t shrk 15 ns hldrq hold time (from clkout - ) <124> t hkhr 2ns delay time from clkout to hldak <125> t dkha 210ns hldrq high-level width <126> t whqh t + 17 ns hldak low-level width <127> t whal t C 8 ns delay time from clkout to bus float <128> t dkcf 10 ns delay time from hldak - to bus output <129> t dhac 0ns delay time from hldrq to hldak <130> t dhqha1 2.5t ns delay time from hldrq - to hldak - <131> t dhqha2 0.5t 1.5t ns remark t = t cyk data sheet u13995ej2v0ds00 69 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (8) bus hold timing (2/2) remarks 1. the broken lines indicate high impedance. 2. n = 0 to 7 t1 t2 t3 ti th th th ti t1 a0 to a23 (output) d0 to d15 (i/o) <123> <124> <124> <123> <123> <123> <126> <130> <125> <127> <125> <128> <129> <131> address undefined data clkout (output) hldrq (input) hldak (output) csn/rasn (output) bcyst (output) rd (output) we (output) wait (input) ucas (output) lcas (output) data sheet u13995ej2v0ds00 70 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (9) interrupt timing parameter symbol condition min. max. unit nmi high-level width <132> t wnih 500 ns nmi low-level width <133> t wnil 500 ns intpn high-level width <134> t with 4t + 10 ns intpn low-level width <135> t witl 4t + 10 ns remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153 2. t = t cyk nmi (input) <132> <133> intpn (input) <134> <135> remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153 (10) rpu timing parameter symbol condition min. max. unit ti1n high-level width <136> t wtih 3t + 18 ns ti1n low-level width <137> t wtil 3t + 18 ns tclr1n high-level width <138> t wtch 3t + 18 ns tclr1n low-level width <139> t wtcl 3t + 18 ns remarks 1. n = 0 to 5 2. t = t cyk ti1n (input) <136> <137> tclr1n (input) <138> <139> remark n = 0 to 5 data sheet u13995ej2v0ds00 71 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (11) uart0, uart1 timing (clock-synchronized or master mode only) parameter symbol condition min. max. unit sckn cycle < 140> t cysk0 output 250 ns sckn high-level width <141> t wsk0h output 0.5t cysk0 C 20 ns sckn low-level width <142> t wsk0l output 0.5t cysk0 C 20 ns rxdn setup time (to sckn - ) <143> t srxsk 30 ns rxdn hold time (from sckn - ) <144> t hskrx 0ns txdn output delay time (from sckn ) <145> t dsktx 20 ns txdn output hold time (from sckn - ) <146> t hsktx 0.5t cysk0 C 5 ns remark n = 0, 1 sckn (i/o) <142> <140> <141> rxdn (input) <143> <144> input data txdn (output) <145> output data <146> remarks 1. the broken lines indicate high impedance. 2. n = 0, 1 data sheet u13995ej2v0ds00 72 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 (12) csi0 to csi3 timing (a) master mode parameter symbol condition min. max. unit sckn cycle < 147> t cysk1 output 100 ns sckn high-level width <148> t wsk1h output 0.5t cysk1 C 20 ns sckn low-level width <149> t wsk1l output 0.5t cysk1 C 20 ns sin setup time (to sckn - ) <150> t ssisk 30 ns sin hold time (from sckn - ) <151> t hsksi 0ns son output delay time (from sckn ) <152> t dskso 20 ns son output hold time (from sckn - ) <153> t hskso 0.5t cysk1 C 5 ns remark n = 0 to 3 (b) slave mode parameter symbol condition min. max. unit sckn cycle < 147> t cysk1 input 100 ns sckn high-level width <148> t wsk1h input 30 ns sckn low-level width <149> t wsk1l input 30 ns sin setup time (to sckn - ) <150> t ssisk 10 ns sin hold time (from sckn - ) <151> t hsksi 10 ns son output delay time (from sckn ) <152> t dskso 30 ns son output hold time (from sckn - ) <153> t hskso t wsk1h ns remark n = 0 to 3 sckn (i/o) <149> <147> <148> sln (input) <150> <151> input data son (output) <152> output data <153> remarks 1. the broken lines indicate high impedance. 2. n = 0 to 3 data sheet u13995ej2v0ds00 73 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 a/d converter characteristics (t a = ?40 to +70 c ... m m m m pd703100-40, t a = ?40 to +85 c ... m m m m pd703100-33, 703101-33, 703102-33, v dd = cv dd = 3.0 to 3.6 v, hv dd = 5.0 v 10%, v ss = 0 v, hv dd ? 0.5 v av dd hv dd , output pin load capacitance: c l = 50 pf) parameter symbol condition min. typ. max. unit resolution C 10 bit total error C 4lsb quantization error C 1/2 lsb conversion time t conv 510 m s sampling time t samp conversion clock note /6 ns zero scale error C 4lsb scale error C 4lsb linearity error C 3lsb analog input voltage v ian - 0.3 av ref + 0.3 v analog input resistance r an 2m w av ref input voltage av ref av ref = av dd 4.5 5.5 v av ref input current ai ref 2.0 ma av dd current ai dd 6ma note conversion clock is the number of clocks set by the adm1 register. data sheet u13995ej2v0ds00 74 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 4. package drawing 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 ? + 4 ? - 3 ? g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 - 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b data sheet u13995ej2v0ds00 75 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 5. recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 5-1. surface mounting type soldering conditions m m m m pd703100gj-40-uen: 144-pin plastic lqfp (fine pitch) (20 20) m m m m pd703100gj-33-uen: 144-pin plastic lqfp (fine pitch) (20 20) m m m m pd703101gj-33-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) m m m m pd703102gj-33-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 vps package peak temperature: 215 c, time: 25 to 40 sec. max. (at 200 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vp15-103-2 partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) C note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. data sheet u13995ej2v0ds00 76 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. related documents m pd70f3102-33 data sheet (u13844e) m pd703100a-33, 703100a-40, 703101a-33, 703102a-33 data sheet (u14168e) m pd70f3102a-33 data sheet (u13845e) reference materials electrical characteristics for microcomputer (u15170j note ) note this document number is that of japanese version. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850e/ms1 and v850 family are trademarks of nec corporation. data sheet u13995ej2v0ds00 77 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7 m m m m pd703100-33, 703100-40, 703101-33, 703102-33 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: m pd703100-33, 703100-40 the customer must judge the need for license: m pd703101-33, 703102-33 m8e 00. 4 the information in this document is current as of august, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). |
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