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sed1520 series epson 2C1 overview the sed1520 family of dot matrix lcd drivers are designed for the display of characters and graphics. the drivers generate lcd drive signals derived from bit mapped data stored in an internal ram. the drivers are available in two configurations the sed1520 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages. these features give the designer a flexible means of implementing small to medium size lcd displays for compact, low power systems. ? the sed1520 which is able to drive two lines of twelve characters each. ? the sed1521 which is able to drive 80 segments for extention. ? the sed1522 which is able to drive one line of thirteen characters each. line-up features ? fast 8-bit mpu interface compatible with 80- and 68- family microcomputers ? many command set ? total 80 (segment + common) drive sets ? low power 30 m w at 2 khz external clock ? wide range of supply voltages v dd C v ss : C2.4 to C7.0 v v dd C v5: C3.5 to C13.0 v ? low-power cmos ? package code (for example sed1520) sed1520t sed1520f ** : pkg sed1520f * a (qfp5-100pin) sed1520f * c (qfp15-100pin) sed1520d ** : chip sed1520d * a (al-pad) sed1520d * b (au-bump) product clock frequency number number name applicable driver of seg of cmos duty on-chip external drivers drivers sed1520 * 0 * 18 khz 18 khz sed1520 * 0 * , sed1521 * 0 * 61 16 1/16, 1/32 sed1521 * 0 * 18 khz sed1520 * 0 * , sed1522 * 0 * 80 0 1/8 to 1/32 sed1522 * 0 * 18 khz 18 khz sed1522 * 0 * , sed1521 * 0 * 69 8 1/8, 1/16 sed1520 * a * 2 khz sed1520 * a * , sed1521 * a * 61 16 1/16, 1/32 sed1521 * a * 2 khz sed1520 * a * , sed1522 * a * 80 0 1/8 to 1/32 sed1522 * a * 2 khz sed1522 * a * , sed1521 * a * 69 8 1/8, 1/16
sed1520 series 2C2 epson a 0 ,cs display data latch circuit lcd drive circuit common counter display start line register line counter line address decoder column address decoder column address counter column address register status command decoder display timing generator circuit mpu interface i/o buffer display data ram (2560-bit) low-address register bus holder cl fr d 0 ~d 7 (e,r/w) com 0 to com 15 v 1 ,v 2 ,v 3 ,v 4 ,v 5 seg 0 to seg 60 rd,wr v dd v ss res m/s block diagram an example of sed1520 * aa:
sed1520 series epson 2C3 package outline qfp5 qfp15 note: this is an example of sed1520f pin assignment. the modified pin names are given below. sed1520: common outputs com0 to com15 of the master lsi correspond to com31 to com16 of the slave lsi. sed1522: common outputs com0 to com15 of the master lsi correspond to com15 to com8 of the slave lsi. product pin/pad number name 74 75 96 to 100, 1 to 11 93 94 95 sed1520f 0a osc1 osc2 com0 to com15* m/s v4 v1 sed1521f 0a cs cl seg76 to seg61 seg79 seg78 seg77 sed1522f 0a osc1 osc2 com0 to 7, seg68 to 61 m/s v4 v1 sed1520f aa cs cl com0 to com15* m/s v4 v1 sed1521f aa cs cl seg76 to seg61 seg79 seg78 seg77 sed1522f aa cs cl com0 to 7, seg68 to 61 m/s v4 v1 seg45 seg19 com 7 r/w(wr) 46 46 seg20 v ss seg44 com 6 index com 8 e (rd) com 9 cl (osc2) com10 cs (osc1) com11 aq 1 5 75 70 65 60 55 10 15 20 25 80 50 45 40 35 30 85 90 95 com12 seg0 com13 seg1 com14 seg2 com15 seg3 seg60 seg4 seg59 seg5 seg58 seg6 seg57 seg7 seg56 seg8 seg55 seg9 seg54 seg10 seg53 seg11 seg52 seg12 seg51 seg13 seg50 seg14 seg49 seg15 seg48 seg16 seg47 seg17 seg46 seg18 seg21 d30 seg22 d31 seg23 d32 seg24 d33 seg25 d34 seg26 d35 seg27 d36 seg28 d37 seg29 v dd seg30 res seg31 f r seg32 v5 seg33 v3 seg34 v2 seg35 m/s seg36 v4 seg37 v1 seg38 com 0 seg39 com 1 seg40 com 2 seg41 com 3 seg42 com 4 seg43 com 5 cs2 cs3 cs4 cs5 cs6 cs7 v dd res f2 v5 v1 v2 m/s v4 v1 com0 com1 com2 com3 com4 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 a0 cs(osc1) cl(osc2) e(rd) r/w(wr) v ss cs0 cs1 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 index 85 35 40 45 55 60 65 70 75 5 10 15 20 25 90 95 100
sed1520 series 2C4 epson pad pad arrangement chip specifications of al pad package chip size: 4.80 7.04 0.400 mm pad pitch: 100 100 m m chip specifications of gold bump package chip size: 4.80 7.04 0.525 mm bump pitch: 199 m m (min.) bump height: 22.5 m m (typ.) bump size: 132 111 m m ( 20 m m) for mushroom model 116 92 m m ( 4 m m) for vertical model note: an example of sed1520d aa die numbers is given. these numbers are the same as the bump package. 100 95 90 85 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 d1520d * aa x y 4.80 mm 7.04 mm (0, 0)
sed1520 series epson 2C5 1 com5 159 6507 2 com6 159 6308 3 com7 159 6108 4 com8 159 5909 5 com9 159 5709 6 com10 159 5510 7 com11 159 5310 8 com12 159 5111 9 com13 159 4911 10 com14 159 4712 11 com15 159 4512 12 seg60 159 4169 13 seg59 159 3969 14 seg58 159 3770 15 seg57 159 3570 16 seg56 159 3371 17 seg55 159 3075 18 seg54 159 2876 19 seg53 159 2676 20 seg52 159 2477 21 seg51 159 2277 22 seg50 159 2078 23 seg49 159 1878 24 seg48 159 1679 25 seg47 159 1479 26 seg46 159 1280 27 seg45 159 1080 28 seg44 159 881 29 seg43 159 681 30 seg42 159 482 31 seg41 504 159 32 seg40 704 159 33 seg39 903 159 34 seg38 1103 159 the other sed1520 series packages have the different pin names as shown. pad arrangement an example of sed1520d a * pin names is given. the asterisk ( * ) can be a for al pad package or b for gold bump package. sed1520d ab pad center coordinates pad pin xy pad pin xy pad pin xy no. name no. name no. name 35 seg37 1302 159 36 seg36 1502 159 37 seg35 1701 159 38 seg34 1901 159 39 seg33 2100 159 40 seg32 2300 159 41 seg31 2499 159 42 seg30 2699 159 43 seg29 2898 159 44 seg28 3098 159 45 seg27 3297 159 46 seg26 3497 159 47 seg25 3696 159 48 seg24 3896 159 49 seg23 4095 159 50 seg22 4295 159 51 seg21 4641 482 52 seg20 4641 681 53 seg19 4641 881 54 seg18 4641 1080 55 seg17 4641 1280 56 seg16 4641 1479 57 seg15 4641 1679 58 seg14 4641 1878 59 seg13 4641 2078 60 seg12 4641 2277 61 seg11 4641 2477 62 seg10 4641 2676 63 seg9 4641 2876 64 seg8 4641 3075 65 seg7 4641 3275 66 seg6 4641 3474 67 seg5 4641 3674 68 seg4 4641 3948 69 seg3 4641 4148 70 seg2 4641 4347 71 seg1 4641 4547 72 seg0 4641 4789 73 a0 4641 5048 74 cs 4641 5247 75 cl 4641 5447 76 e (rd) 4641 5646 77 r/w (wr) 4641 5846 78 v ss 4641 6107 79 db0 4641 6307 80 db1 4641 6506 81 db2 4295 6884 82 db3 4095 6884 83 db4 3896 6884 84 db5 3696 6884 85 db6 3497 6884 86 db7 3297 6884 87 v dd 3098 6884 88 res 2898 6884 89 fr 2699 6884 90 v 5 2499 6884 91 v 3 2300 6884 92 v 2 2100 6884 93 m/s 1901 6884 94 v 4 1701 6884 95 v 1 1502 6884 96 com0 1302 6884 97 com1 1103 6884 98 com2 903 6884 99 com3 704 6884 100 com4 504 6884 package/pad no. 74 75 96 to 100, 1 to 11 93 94 95 sed1520d 0* osc1 osc2 com0 to com15 * m/s v 4 v 1 sed1522d 0* osc1 osc2 com0 to 7, seg68 to 61 m/s v 4 v 1 sed1522d a* osc1 osc2 com0 to 7, seg68 to 61 m/s v 4 v 1 sed1521d 0* cs cl seg76 to seg61 seg79 seg78 seg77 sed1521d a* cs cl seg76 to seg61 seg79 seg78 seg77
sed1520 series 2C6 epson pin description (1) power pins name description v dd connected to the +5vdc power. common to the v cc mpu power pin. v ss 0 vdc pin connected to the system ground. v 1 , v 2 , v 3 , v 4 , v 5 multi-level power supplies for lcd driving. the voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp, and supplied. these voltages must satisfy the following: v dd 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 (2) system bus connection pins d7 to d0 three-state i/o. the 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard mpu data buses. a0 input. usually connected to the low-order bit of the mpu address bus and used to identify the data or a command. a0=0: d0 to d7 are display control data. a0=1: d0 to d7 are display data. res input. when the res signal goes the 68-series mpu is initialized, and when it goes , the 80-series mpu is initialized. the system is reset during edge sense of the res signal. the interface type to the 68-series or 80-series mpu is selected by the level input as follows: high level: 68-series mpu interface low level: 80-series mpu interface cs input. active low. effective for an external clock operation model only. an address bus signal is usually decoded by use of chip select signal, and it is entered. if the system has a built-in oscillator, this is used as an input pin to the oscillator amp and an rf oscillator resistor is connected to it. in such case, the rd, wr and e signals must be ored with the cs signals and entered. e (rd) ? if the 68-series mpu is connected: input. active high. used as an enable clock input of the 68-series mpu. ? if the 80-series mpu is connected: input. active low. the rd signal of the 80-series mpu is entered in this pin. when this signal is kept low, the sed1520 data bus is in the output status. r/w (wr) ? if the 68-series mpu is connected: input. used as an input pin of read control signals (if r/w is high) or write control signals (if low). ? if the 80-series mpu is connected: input. active low. the wr signal of the 80-series mpu is entered in this pin. a signal on the data bus is fetched at the rising edge of wr signal.
sed1520 series epson 2C7 (3) lcd drive circuit signals name description cl input. effective for an external clock operation model only. this is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges. if the system has a built-in oscillator, this is used as an output pin of the oscillator amp and an rf oscillator resistor is con- nected to it. fr input/output. this is an i/p pin of lcd ac signals, and connected to the m terminal of common driver. i/o selection ? common oscillator built-in model: output if m/s is 1; input if m/s is 0. ? dedicate segment model: input segn output. the output pin for lcd column (segment) driving. a single level of v dd , v 2 , v 3 and v 5 is selected by the combination of display ram contents and rf signal. 10 1010 vv2v5v3 dd fr signal data output level comn output. the output pin for lcd common (low) driving. a single level of v dd , v 1 , v 4 and v 5 is selected by the combination of common counter output and rf signal. the slave lsi has the reverse common output scan sequence than the master lsi. 10 1010 v v1 v5 v4 dd fr signal counter output output level m/s input. the master or slave lsi operation select pin for the sed1520 or sed1522. connected to v dd (to select the master lsi operation mode) or v ss (to select the slave lsi operation mode). when this m/s pin is set, the functions of fr, com0 to com15, osc1 (cs), and osc2 (cl) pins are changed. * the slave driver has the reverse common output scan sequence than the master driver. m/s fr com output osc1 osc2 sed1520f 0a v dd output com0 to com15 input output v ss input com31 to com16 nc input sed1522f 0a v dd output com0 to com7 input output v ss input com15 to com8 nc input
sed1520 series 2C8 epson level after reset (see table 1). when the cs signal is high, the sed1520 series is disconnected from the mpu bus and set to stand by. however, the reset signal is entered regardless of the internal setup status. block description system bus mpu interface 1. selecting an interface type the sed1520 series transfers data via 8-bit bidirec- tional data buses (d0 to d7). as its reset pin has the mpu interface select function, the 80-series mpu or the 68-series mpu can directly be connected to the mpu bus by the selection of high or low res signal res signal input level mpu type a0 e r/w cs d0 to d7 active 68-series ----- active 80-series - rd wr -- table 1 data transfer the sed1520 and sed1521 drivers use the a0, e (or rd) and r/w (or wr) signals to transfer data between the system mpu and internal registers. the combina- tions used are given in the table blow. in order to match the timing requirements of the mpu with those of the display data ram and control registers all data is latched into and out of the driver. this introduces a one cycle delay between a read request for data and the data arriving. for example when the mpu executes a read cycle to access display ram the current contents of the latch are placed on the system data bus while the desired contents of the display ram are moved into the latch. this means that a dummy read cycle has to be executed at the start of every series of reads. see figure 1. no dummy cycle is required at the start of a series of writes as data is transferred automatically from the input latch to its destination. common 68 mpu 80 mpu function a0 r/w rd wr 1101 read display data 1010 write display data 0101 read status 0010 write to internal register (command)
sed1520 series epson 2C9 figure 1 bus buffer delay busy flag when the busy flag is logical 1, the sed1520 series is executing its internal operations. any command other than status read is rejected during this time. the busy flag is output at pin d7 by the status read command. if an appropriate cycle time (tcyc) is given, this flag needs not be checked at the beginning of each command and, therefore, the mpu processing capacity can greatly be enhanced. display start line and line count registers the contents of this register form a pointer to a line of data in display data ram corresponding to the first line of the display (com0), and are set by the display start line command. see section 3. the contents of the display start line register are copied into the line count register at the start of every frame, that is on each edge of fr. the line count register is incremented by the cl clock once for every display line, thus generating a pointer to the current line of data, in display data ram, being transferred to the segment driver circuits. column address counter the column address counter is a 7-bit presettable counter that supplies the column address for mpu access to the display data ram. see figure 2. the counter is incremented by one every time the driver receives a read or write display data command. addresses above 50h are invalid, and the counter will not increment past this value. the contents of the column address counter are set with the set column address command. page register the page resiter is a 2-bit register that supplies the page address for mpu access to the display data ram. see figure 2. the contents of the page register are set by the set page register command. display data ram the display data ram stores the lcd display data, on a 1-bit per pixel basis. the relation-ship between display data, display address and the display is shown in figure 2. n n + 1 n + 1 n + 2 n + 2 n + 3 n + 3 n n + 1 n + 2 n n n + 1 n + 2 n data bus hold wr mpu internal timing mpu internal timing read write wr wr data wr rd column address bus hold n n n + 1 n address set at n dummy read data read at n data read at n + 1 rd
sed1520 series 2C10 epson common timing generator circuit generates common timing signals and fr frame signals from the cl basic clock. the 1/16 or 1/32 duty (for sed1520) or 1/8 or 1/16 duty (for sed1522) can be selected by the duty select command. if the 1/32 duty is selected for the sed1520 and 1/16 duty is selected for the sed1522, the 1/32 and 1/16 duties are provided by two chips consisting of the master and slave chips in the common multi-chip mode. sed1520 012 1415 01 15 16 17 30 31 16 17 31 fr signal (master output) master common slave common sed1522 012 67 01 7 8 9 14 15 89 15 fr signal (master output) master common slave common display data latch circuit this latch stores one line of display data for use by the lcd driver interface circuitry. the output of this latch is controlled by the display on/off and static drive on/off commands. lcd driver circuit the lcd driver circuitry generates the 80 4-level signals used to drive the lcd panel, using output from the display data latch and the common timing generator circuitry. display timing generator this circuit generates the internal display timing signal using the basic clock, cl, and the frame signals, fr. fr is used to generate the dual frame ac-drive wave- form (type b drive) and to lock the line counter and common timing generator to the system frame rate. cl is used to lock the line counter to the system line scan rate. if a system uses both sed1520s or sed1522 and sed1521s they must have the same cl frequency rating.
sed1520 series epson 2C11 *1 if the parasitic capacitance of this section increases, the oscillation frequency may shift to the lower frequency. therefore, the rf oscillation frequency must be reduced below the specified level. *2 a cmos buffer is required if the oscillation circuit is connected to two or more slave mpu chips. oscillator circuit (sed1520 * 0a only) a low power-consumption cr oscillator for adjusting the oscillation frequency using rf oscillation resistor only. this circuit generates a display timing signal. some of sed1520 and sed1522 series models have a built-in oscillator and others use an external clock. this difference must be checked before use. connect the rf oscillation resistor as follows. to sup- press the built-in oscillator circuit and drive the mpu using an external clock, enter the clock having the same phase as the osc2 of mater chip into osc2 of the slave chip. ? mpu having a built-in oscillator ? mpu driven with an external clock reset circuit detects a rising or falling edge of an res input and initializes the mpu during power-on. ? initialization status 1. display is off. 2. display start line register is set to line 1. 3. static drive is turned off. 4. column address counter is set to address 0. 5. page address register is set to page 3. 6. 1/32 duty (sed1520) or 1/16 duty (sed1522) is selected. 7. forward adc is selected (adc command d0 is 1 and adc status flag is 1). 8. read-modify-write is turned off. the input signal level at res pin is sensed, and an mpu interface mode is selected as shown on table 1. for the 80-series mpu, the res input is passed through the inverter and the active high reset signal must be entered. for the 68-series mpu, the active low reset signal must be entered. as shown for the mpu interface (reference example), the res pin must be connected to the reset pin and reset at the same time as the mpu initialization. if the mpu is not initialized by the use of res pin during power-on, an unrecoverable mpu failure may occur. when the reset command is issued, initialization master chip slave chip m/s m/s osc1 osc2 osc1 osc2 v ss *2 *1 rf open v dd (cs) (cl) (cs) (cl) y driver cl2 sed1521f aa cl
sed1520 series 2C12 epson com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 com 17 com 18 com 19 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 com 30 com 31 start 1/16 line address common output 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f h column address adc d 0 = "1" d 0 = "0" seg pin seg 0 4f h 00 h 1 2 3 4 5 6 7 4e 4d 4c 4b 4a 49 48 01 02 03 04 05 06 07 77 78 79 02 01 00 4d 4e 4f d 0 d d d d d d d 1 2 3 4 5 6 7 data page address d 1 ,d 2 = 0,0 0,1 1,0 1,1 page 0 page 1 page 2 page 3 start line (example) response d 0 d d d d d d d 1 2 3 4 5 6 7 d 0 d d d d d d d 1 2 3 4 5 6 7 d 0 d d d d d d d 1 2 3 4 5 6 7 display area figure 2 display data ram addressing
sed1520 series epson 2C13 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg0 seg1 seg2 seg3 seg4 0123 150 0 012 3 1 1 2 2 3 3 31 15 31 fr com0 com1 com2 seg0 seg1 com0?eg0 com0?eg1 v v v v1 v2 v3 v4 v5 v1 v2 v3 v4 v5 v5 v4 v3 v2 v1 -v1 -v2 -v3 -v4 -v5 dd ss dd v dd v1 v2 v3 v4 v5 v dd v1 v2 v3 v4 v5 v dd v1 v2 v3 v4 v5 v dd v dd v5 v4 v3 v2 v1 -v1 -v2 -v3 -v4 -v5 v dd 1/5 bias, 1/16 duty 1/6 bias, 1/32 duty figure 4 lcd drive waveforms example
sed1520 series 2C14 epson code command a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display on/off 0 1 0 1 0 1 0 1 1 1 0/1 display start line 0 1 0 1 1 0 display start address (0 to 31) set page address 0 1 0 1 0 1 1 1 0 page (0 to 3) set column 0 1 0 0 column address (0 to 79) (segment) address read status 0 0 1 busy adc on/off reset 0 0 0 0 write display data 1 1 0 write data read display data 1 0 1 read data select adc 0 1 0 1 0 1 0 0 0 0 0/1 statis drive 010 1 0 1 0 01 0 0/1 on/off select duty 0 1 0 1 0 1 0 1 0 0 0/1 read-modify-write 0 1 0 1 1 1 0 0 0 0 0 end 010 1 1 1 0 11 1 0 reset 0 1 0 1 1 1 0 0 0 1 0 function turns display on or off. 1: on, 0: off specifies ram line corresponding to top line of display. sets display ram page in page address register. sets display ram column address in column address register. reads the following status: busy 1: busy 0: ready adc 1: cw output 0: ccw output on/off 1: display off 0: display on reset 1: being reset 0: normal writes data from data bus into display ram. reads data from display ram onto data bus. 0: cw output, 1: ccw output selects static driving operation. 1: static drive, 0: normal driving selets lcd duty cycle 1: 1/32, 0: 1/16 read-modify-write on read-modify-write off software reset commands summary
sed1520 series epson 2C15 command description table 3 is the command table. the sed1520 series identifies a data bus using a combination of a0 and r/w (rd or wr) signals. as the mpu translates a command in the internal timing only (independent from the external clock), its speed is very high. the busy check is usually not required. display on/off this command turns the display on and off. ? d=1: display on ? d=0: display off display start line this command specifies the line address shown in figure 3 and indicates the display line that corresponds to com0. the display area begins at the specified line address and continues in the line address increment direction. this area having the number of lines of the specified display duty is displayed. if the line address is changed dynamically by this command, the vertical smooth scrolling and paging can be used. this command loads the display start line register. see figure 2. set page address this command specifies the page address that corresponds to the low address of the display data ram when it is accessed by the mpu. any bit of the display data ram can be accessed when its page address and column address are specified. the display status is not changed even when the page address is changed. this command loads the page address register. see figure 2. r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 1 1 d aeh, afh r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 010110a 4 a 3 a 2 a 1 a 0 c0h to dfh a 4 a 3 a 2 a 1 a 0 line address 00000 0 00001 1 :: :: 11111 31 r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 010101110a 1 a 0 b8h to bbh a 1 a 0 page 00 0 01 1 10 2 11 3
sed1520 series 2C16 epson set column address this command specifies a column address of the display data ram. when the display data ram is accessed by the mpu continuously, the column address is incremented by 1 each time it is accessed from the set address. therefore, the mpu can access to data continuously. the column address stops to be incremented at address 80, and the page address is not changed continuously. this command loads the column address register. read status reading the command i/o register (a0=0) yields system status information. ? the busy bit indicates whether the driver will accept a command or not. busy=1: the driver is currently executing a command or is resetting. no new command will be accepted. busy=0: the driver will accept a new command. ? the adc bit indicates the way column addresses are assigned to segment drivers. adc=1: normal. column address n ? segment driver n. adc=0: inverted. column address 79-u ? segment driver u. ? the on/off bit indicates the current status of the display. it is the inverse of the polarity of the display on/off command. on/off=1: display off on/off=0: display on ? the reset bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode. reset=1: currently executing reset command. reset=0: normal operation write display data writes 8-bits of data into the display data ram, at a location specified by the contents of the column address and page address registers and then increments the column address register by one. r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 busy adc on/off reset 0000 r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 write data r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0100a 6 a 5 a 4 a 3 a 2 a 1 a 0 00h to 4fh a 6 a 5 a 4 a 3 a 2 a 1 a 0 column address 0000000 0 0000001 1 :: :: 1001111 79
sed1520 series epson 2C17 read display data reads 8-bits of data from the data i/o latch, updates the contents of the i/o latch with display data from the display data ram location specified by the contents of the column address and page address registers and then increments the column address register. after loading a new address into the column address register one dummy read is required before valid data is obtained. select adc this command selects the relationship between display data ram column addresses and segment drivers. d=1: seg0 ? column address 4fh, (inverted) d=0: seg0 ? column address 00h, (normal) this command is provided to reduce restrictions on the placement of driver ics and routing of traces during printed circuit board design. see figure 2 for a table of segments and column addresses for the two values of d. static drive on/off forces display on and all common outputs to be selected. d=1: static drive on d=0: static drive off select duty this command sets the duty cycle of the lcd drive and is only valid for the sed1520f and sed1522f. it is invalid for the sed1521f which performs passive operation. the duty cycle of the sed1521f is determined by the externally generated fr signal. sed1520 sed1522 d=1: 1/32 duty cycle 1/16 duty cycle d=0: 1/16 duty cycle 1/8 duty cycle when using the sed1520f 0a , sed1522f 0a (having a built-in oscillator) and the sed1521f 0a continuously, set the duty as follows: r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 read data r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 0 d a0h, a1h r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 0 d a4h, a5h r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 0 0 d a8h, a9h sed1521f 0a sed1520f 0a 1/32 1/32 1/16 1/16 sed1522f 0a 1/16 1/32 1/8 1/16
sed1520 series 2C18 epson read-modify-write this command defeats column address register auto-increment after data reads. the current conetents of the column address register are saved. this mode remains active until an end command is received. ? operation sequence during cursor display when the end command is entered, the column address is returned to the one used during input of read-modify-write command. this function can reduce the load of mpu when data change is repeated at a specific display area (such as cursor blinking). * any command other than data read or write can be used in the read-modify-write mode. however, the column address set command cannot be used. set page address set column address read-modify-write dummy read read data write data completed? end no yes end this command cancels read-modify-write mode and restores the contents of the column address register to their value prior to the receipt of the read-modify-write command. r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01011100000e0h r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01011101110eeh column address read-modify-write mode is selected. end return n n+1 n+2 n+3 n+m n
sed1520 series epson 2C19 reset this command clears ? the display start line register. ? and set page address register to 3 page. it does not affect the contents of the display data ram. when the power supply is turned on, a reset signal is entered in the res pin. the reset command cannot be used instead of this reset signal. power save (combination command) the power save mode is selected if the static drive is turned on when the display is off. the current consumption can be reduced to almost the static current level. in the power save mode: (a) the lcd drive is stopped, and the segment and common driver outputs are set to the v dd level. (b) the external oscillation clock input is inhibited, and the osc2 is set to the floating mode. (c) the display and operation modes are kept. the power save mode is released when the display is turned on or when the static drive is turned off. if the lcd drive voltage is supplied from an external resistance divider circuit, the current passing through this resistor must be cut by the power save signal. v dd v dd v sed1520 sed1522 power save signal 1 v 2 v 3 v 4 v 5 v ssh if the lcd drive power is generated by resistance division, the resistance and capacitance are determined by the lcd panel size. after the panel size has been determined, reduce the resistance to the level where the display quality is not affected and reduce the power consumption using the divider resistor. r/w a 0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01011100010e2h
sed1520 series 2C20 epson specifications absolute maximum ratings parameter symbol rating unit supply voltage (1) v ss C8.0 to +0.3 v supply voltage (2) v 5 C16.5 to +0.3 v supply voltage (3) v 1 , v 4 , v 2 , v 3 v5 to +0.3 v input voltage v in v ss C0.3 to +0.3 v output voltage v o v ss C0.3 to +0.3 v power dissipation p d 250 mw operating temperature t opr C40 to +85 deg. c storage temperature t stg C65 to +150 deg. c soldering temperature time at lead t sol 260, 10 deg. c, sec notes: 1. all voltages are specified relative to v dd = 0 v. 2. the following relation must be always hold v dd 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 3. exceeding the absolute maximum ratings may cause permanent damage to the device. functional operation under these conditions is not implied. 4. moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to avoid thermally stressing the package during board assembly. electrical specifications dc characteristics ta = C20 to 75 deg. c, v dd = 0 v unless stated otherwise rating parameter symbol condition unit applicable pin min. typ. max. operating recommended C5.5 C5.0 C4.5 voltage (1) v ss vv ss see note 1. allowable C7.0 C2.4 recommended C13.0 C3.5 v 5 v 5 v operating allowable C13.0 see note 10. voltage (2) allowable v 1 , v 2 0.6 v 5 v dd vv 1 , v 2 allowable v 3 , v 4 v 5 0.4 v 5 vv 3 , v 4 v iht v ss +2.0 v dd see note 2 & 3. v ihc 0.2 v ss v dd high-level input voltage v iht v ss = C3 v 0.2 v ss v dd see note 2 & 3. v ihc v ss = C3 v 0.2 v ss v dd v v ilt v ss v ss +0.8 see note 2 & 3. v ilc v ss 0.8 v ss low-level input voltage v ilt v ss = C3 v v ss 0.85 v ss see note 2 & 3. v ilc v ss = C3 v v ss 0.8 v ss v oht i oh = C3.0 ma v ss +2.4 osc2 v ohc1 i oh = C2.0 ma v ss +2.4 v see note 4 & 5. v ohc2 i oh = C120 m a 0.2 v ss high-level output voltage v oht v ss = C3 v i oh = C2 ma 0.2 v ss see note 4 & 5. v ohc1 v ss = C3 v i oh = C2 ma 0.2 v ss v osc2 v ohc2 v ss = C3 v i oh = C50 m a 0.2 v ss (continued)
sed1520 series epson 2C21 dc characteristics (contd) ta = C20 to 75 deg. c, v dd = 0 v unless stated otherwise rating parameter symbol condition unit applicable pin min. typ. max. v olt i ol = 3.0 ma v ss +0.4 osc2 v olc1 i ol = 2.0 ma v ss +0.4 v see note 4 & 5. v olc2 i ol = 120 m a 0.8 v ss low-level output voltage v olt v ss = C3 v i ol = 2 ma 0.8 v ss see note 4 & 5. v olc1 v ss = C3 v i ol = 2 ma 0.8 v ss v osc2 v olc2 v ss = C3 v i ol = 50 m a 0.8 v ss input leakage current i li C1.0 1.0 m a see note 6. output leakage current i lo C3.0 3.0 m a see note 7. v 5 = C5.0 v 5.0 7.5 seg0 to 79, lcd driver on resistance r on ta = 25 deg. c k w com0 to 15, v 5 = C3.5 v 10.0 50.0 see note 11 static current dissipation i ddq cs = cl = v dd 0.05 1.0 m av dd f cl = 2 khz 2.0 5.0 v dd during display r f = 1 m w 9.5 15.0 m a see note 12, v 5 = C5.0 v f cl = 18 khz 5.0 10.0 13 & 14. i dd (1) during display f cl = 2 khz 1.5 4.5 v dd dynamic current dissipation v 5 = C5 v m a see note 12 & 13. v ss = C3 v rf = 1 m w 6.0 12.0 during access t cyc = 200 khz 300 500 i dd (2) v ss = C3v, m a see note 8. 150 300 during access t cyc = 200 khz input pin capacitance c in ta = 25 deg. c, f = 1 mhz 5.0 8.0 pf all input pins r f = 1.0 m w 2%, 15 18 21 v ss = C5.0 v oscillation frequency f osc khz see note 9. r f = 1.0 m w 2%, 11 16 21 v ss = C3.0 v res reset time t r 1.0 m s see note 15. notes : 1. operation over the specified voltage range is guaranteed, except where the supply voltage changes suddenly during cpu access. 2. a0, d0 to d7, e (or rd), r/w (or wr) and cs 3. cl, fr, m/s and res 4. d0 to d7 5. fr 6. a0, e (or rd), r/w (or wr), cs, cl, m/s and res 7. when d0 to d7 and fr are high impedance. 8. during continual write acess at a frequency of t cyc . current consumption during access is effectively proportional to the access frequency. 9. see figure below for details 10. see figure below for details 11. for a voltage differential of 0.1 v between input (v 1 , , v 4 ) and output (com, seg) pins. all voltages within specified operating voltage range. 12. sed1520 * a * and sed1521 * a * and sed1522 * a * only. does not include transient currents due to stray and panel capacitances. 13. sed1520 * 0 * and sed1522 * 0 * only. does not include transient currents due to stray and panel capacitances. 14. sed1521 * 0 * only. does not include transient currents due to stray and panel capacitances. 15. t r (reset time) represents the time from the res signal edge to the completion of reset of the internal circuit. therefore, the sed1520 series enters the normal operation status after this t r .
sed1520 series 2C22 epson relationship between f osc , f fr and r f , and operating bounds on v ss and v5 *9 ? relationship between oscillation frequency, frames and rf (sed1520f 0a ), (sed1522f 0a ) 40 30 20 10 0 0.5 1.0 1.5 2.0 2.5 ta=25? v =-5v ss ta=25? v =-5v ss [khz] fosc v =-3v ss v =-5v ss 200 100 0 0.5 1.0 1.5 2.0 2.5 sed1520 sed1522 rf osc1 osc2 [hz] frame rf [m ] w [m ] w rf same for 1/16 and 1/32 duties figure 5 (a) figure 5 (b) ? relationship between external clocks (f cl ) and frames (sed1520f aa ) , (sed1522f aa ) 200 100 0123 f cl [khz] [hz] frame duty1/32 duty1/16 duty1/8 figure 5 (c) *10 ? operating voltage range of v ss and v5 systems ?5 ?0 ? 0 24 68 (v) v 5 v ss (v) operating voltage range figure 6
sed1520 series epson 2C23 ac characteristics ? mpu bus read/write i (80-family mpu) ta = C20 to 75 deg. c, v ss = C5.0 v 10% unless stated otherwise rating parameter symbol condition unit signal min. max. address hold time t ah8 10 ns a0, cs address setup time t aw8 20 ns system cycle time t cyc8 1000 ns wr, rd control pulsewidth t cc 200 ns data setup time t ds8 80 ns data hold time t dh8 10 ns d0 to d7 rd access time t acc8 90ns c l = 100 pf output disable time t ch8 10 60 ns rise and fall time t r , t f 15 ns (v ss = C2.7 to C4.5 v, ta = C20 to +75 c) rating parameter symbol condition unit signal min. max. address hold time t ah8 20 ns a0, cs address setup time t aw8 40 ns system cycle time t cyc8 2000 ns wr, rd control pulse width t cc 400 ns data setup time t ds8 160 ns data hold time t dh8 20 ns d0 to d7 rd access time t acc8 180 ns c l = 100 pf output disable time t ch8 20 120 ns rise and fall time t r , t f 15 ns t cc t cyc8 t aw8 a0,cs wr,rd d0 to d7 (write) d0 to d7 (read) t f t r t ds8 t ah8 t dh8 t oh8 t acc8
sed1520 series 2C24 epson ? mpu bus read/write ii (68-family mpu) ta = C20 to 75 deg. c, v ss = C5 v 10 unless stated otherwise rating parameter symbol condition unit signal min. max. system cycle time t cyc6 1000 ns address setup time t aw6 20 ns a0, cs, r/w address hold time t ah6 10 ns data setup time t ds6 80 ns data hold time t dh6 10 ns d0 to d7 output disable time t oh6 10 60 ns c l = 100 pf access time t acc6 90ns enable read 100 ns t ew e pulsewidth write 80 ns rise and fall time tr, tf 15 ns (v ss = C2.7 to C 4.5 v, ta = C20 to +75 c) rating parameter symbol condition unit signal min. max. system cycle time *1 t cyc6 2000 ns address setup time t aw6 40 ns a0, cs, r/w address hold time t ah6 20 ns data setup time t ds6 160 ns data hold time t dh6 20 ns d0 to d7 output disable time t oh6 20 120 ns c l = 100 pf access time t acc6 180 ns enable read 200 ns t ew e pulse width write 160 ns rise and fall time t r , t f 15 ns notes: 1. t cyc6 is the cycle time of cs. e = h, not the cycle time of e. t cyc6 t ew t ds6 t aw6 e d0 to d7 (write) t r t f t dh6 t oh6 t ah6 d0 to d7 (read) t acc6 r/w a0,cs
sed1520 series epson 2C25 ? display control signal timing input ta = C20 to 75 deg. c, v ss = C5.0 v 10% unless stated otherwise rating parameter symbol condition unit signal min. typ. max. low-level pulsewidth t wlcl 35 m s high-level pulsewidth t whcl 35 m s cl rise time t r 30 150 ns fall time t f 30 150 ns fr delay time t dfr C2.0 0.2 2.0 m sfr v ss = C2.7 to C4.5 v, ta = C20 to +75 c rating parameter symbol condition unit signal min. typ. max. low-level pulse width t wlcl 70 m s high-level pulse width t whcl 70 m s cl rise time t r 60 300 ns fall time t f 60 300 ns fr delay time t dfr C4.0 0.4 4.0 m sfr note: the listed input t dfr applies to the sed1520 and sed1521 and sed1522 in slave mode. output ta = C20 to 75 deg. c, v ss = C5.0 v 10% unless stated otherwise rating parameter symbol condition unit signal min. typ. max. fr delay time t dfr c l = 100 pf 0.2 0.4 m sfr v ss = C2.7 to C4.5 v, ta = C20 to +75 c rating parameter symbol condition unit signal min. typ. max. fr delay time t dfr c l = 100 pf 0.4 0.8 m sfr notes: 1. the listed output t dfr applies to the sed1520 and sed1522 in master mode. t wlcl t dfr cl fr t whcl t f t r
sed1520 series 2C26 epson application notes mpu interface configuration 80 family mpu reset v dd v cc v 5 v ss sed1520f aa gnd mpu decoder res wr rd d0 to d7 cs a0 res wr rd d0 to d7 a1 to a7 ioqr a0
sed1520 series epson 2C27 lcd drive interface configuration sed1520f 0a Csed1520f 0a sed1522f 0a Csed1522f 0a sed1520f aa Csed1520f aa sed1522f aa Csed1522f aa sed1520f 0a ) Csed1521f 0a (see note 1) sed1522f 0a to lcd seg to lcd com osc1 osc2 fr osc1 osc2 fr master slave sed1520f 0a sed1520f 0a m/s to lcd com v dd r f v ss to lcd seg m/s to lcd seg to lcd com cl fr cl fr master external clock slave sed1520f aa sed1520f aa m/s to lcd com v dd v ss to lcd seg m/s to lcd seg to lcd com osc1 osc2 fr osc1 osc2 fr master slave sed1520f 0a sed1521f 0a m/s v dd r f *2 to lcd seg
sed1520 series 2C28 epson sed1520f aa Csed1521f aa notes: 1. the duty cycle of the slave must be the same as that for the master. 2. if a system has two or more slave drivers a cmos buffer will be required. to lcd seg to lcd com cl fr cl fr external clock sed1520f aa sed1521f aa m/s v dd to lcd seg
sed1520 series epson 2C29 lcd panel wiring example (the full-dot lcd panel displays a character in 6 8 dots.) 1/16 duty: ? 10 characters 2 lines 1 16 161 lcd 16 61 sed1520f com seg 1/16 duty: ? 23 characters 2 lines lcd 16 141 1 16 161 62 141 seg seg sed1520f sed1521f com 1/32 duty: ? 33 characters 4 lines 1 16 161 62 141 142 202 17 32 com seg seg seg sed1520f sed1521f sed1520f * com lcd 32 202 * the sed1521f can be omitted (the 32 122-dot display mode is selected). note : a combination of ab or aa type chip (that uses internal clocks) and 0b or 0a type chip (that uses external clocks) is not allowed.
sed1520 series 2C30 epson package dimensions ? plastic qfp5C100 pin dimensions: inches (mm) ? plastic qfp15C100 pin 80 51 0.110 (2.8) 0~12 1 81 50 100 31 30 0.026 0.004 (0.65 0.1 ) 0.012 0.004 (0.30 0.1 ) 0.551 0.004 (14 0.1 ) 0.772 0.016 (19.6 0.4 ) index 1.008 0.016 (25.6 0.4 ) 0.787 0.004 (20 0.1 ) 0.059 0.012 (1.5 0.3 ) 0.006 0.002 (0.15 0.05 ) 0.106 0.004 (2.7 0.1 ) 1 0~12 75 50 76 25 51 26 100 index 0.007 0.004 (0.18 0.1 ) 0.020 0.004 (0.5 0.1 ) 0.005 0.002 (0.127 0.05 ) 0.055 0.004 (1.4 0.1 ) 0.630 0.016 (16.0 0.4 ) 0.551 0.004 (14.0 0.1 ) 0.020 0.004 (0.5 0.2 ) 0.039(1.0) 0.630 0.016 (16.0 0.4 ) 0.551 0.004 (14.0 0.1 )
sed1520 series epson 2C31 specifications ?base: u-rexs, 75 m ?copper foil: electrolytic copper foil, 35 m ?sn plating ?product pitch: 81p (28.5mm) ?solder resist positional tolerance: 0.3 output terminal pattern shape (mold, marking area) (mold, marking area) punching hole for good product

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