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description the cxp872p48a is a cmos 8-bit microcomputer which consists of a/d converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, pwm generator, pwm for tuner, viss/vass circuit, 32khz timer/event counter, remote control receiving circuit, general purpose prescaler, hsync counter, vcr vertical sync separation circuit and the measuring circuit which measure signals of capstan fg and drum fg/pg and other servo systems, as well as basic configurations like 8-bit cpu, prom, ram and i/o port. they are integrated into a single chip. also this ic provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32khz operation. the cxp872p48a is the on-chip prom version of the cxp87248a with on-chip mask rom, providing the function of being able to write directly into the program. it is suitable for evaluation use during system development and for small quantity production. features a wide instruction set (213 instructions) which covers various types of data ?16-bit arithmetic instruction/multiplication and division instruction/boolean bit operation instruction minimum instruction cycle during operation 333ns/12mhz (3.0 to 5.5v) during operation 250ns/16mhz (4.5 to 5.5v) during operation 122s/32khz incorporated prom capacity 48 kbytes incorporated ram capacity 1376 bytes peripheral functions ?a/d converter 8 bit, 12-channel, successive approximation system (conversion time 20.0s/16mhz) ?serial interface incorporated buffer ram (1 to 32 bytes auto transfer) 1-channel incorporated 8-bit and 8-stage fifo (1 to 8 bytes auto transfer) 1-channel ?timer 8-bit timer 8-bit timer/counter 19-bit time base timer 32khz timer/counter ?high precision timing pattern generator ppg 19-pin 32-stage programmable rtg 5-pin, 2-channel ?pwm/da gate output pwm 12-bit, 2-channel (repetitive frequency 62khz/16mhz) da gate pulse output 13-bit, 4-channel ?servo input control capstan fg, drum fg/pg, ctl input ?vsync separator ?frc capture unit incorporated 26-bit and 8-stage fifo ?pwm output 14-bit, 1-channel ?viss/vass circuit pulse duty auto detection circuit ?remote control receiving circuit 8-bit pulse measuring counter, 6-stage fifo ?general purpose prescaler 7-bit (sync1 input frequency divided, frc capture possible) ?hsync counter 12-bit event counter (counts sync1 input) interruption 22 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp/lqfp structure silicon gate cmos ic ?1 cxp872p48a e94813a1x-ps cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (plastic) 100 pin lqfp (plastic)
?2 cxp872p48a pi6/so1 a pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe1 pe2 to pe7 pf0 to pf3 pf4 to pf7 pg0 to pg7 pi1 to pi7 pj0 to pj7 clock generator/ system control ram 1376 bytes spc700 cpu core rom 48k bytes interrupt controller 2 2 32khz timer/counter fifo frc capture unit programmable pattern generator ram 2 5 19 avss av ref av dd 2 a/d converter serial interface unit (ch0) ram 8 bit timer/counter 0 8 bit timer 1 vsync separator 14 bit pwm generator 12 bit pwm generator ch0 servo input control capstan drum ctl 2 3 2 12 bit pwm generator ch1 4 pe7/dab1 pe5/daa1 pe3/pwm1 pe6/dab0 pe4/daa0 pe2/pwm0 pi2/pwm pi1/rmc pg3/pbctl pg2/dpg pg1/dfg pg0/cfg pg7/exi1 pg6/exi0 pg5/sync1 pg4/sync0 pi3/to/ddo pe1/ec pi5/sck1 pi7/si1 sck0 so0 si0 cs0 pf0/an4 to pf7/an11 an0 to an3 realtime pulse generator 12 8 port a 8 port b 8 port c 8 port d 6 2 port e 4 4 port f 8 port g 8 port h 7 port i ph0 to ph7 a nmi prescaler/ time base timer viss/vass remocon input fifo serial interface unit (ch1) ch0 ch 1 8 port j pa0/ppo0 to pc2/ppo18 pc3/rto3 to pc7/rto7 fifo pe0/ckout programmable prescaler hsync counter pe1/hcout 2 vss v dd mp rst xtal extal pe1/int2 pe0/int0 pi4/int1/nmi tx tex pi3/adj block diagram
3 cxp872p48a pin assignment 1 (top view) 100-pin qfp package pb5/ppo13 pb4/ppo12 pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pi6/so1 pi7/si1 pe0/int0/ckout pe1/ec/int2/hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref av ss pf4/an8 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 vpp v dd v ss tx tex pi1/rmc pi2/pwm pi3/to/ddo/adj pi4/int1/nmi pi5/sck1 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst v ss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 note) 1. vpp (pin 90) is always connected to v dd . 2. v ss (pins 41 and 88) are both connected to gnd.
4 cxp872p48a pin assignment 2 (top view) 100-pin lqfp package pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pe1/ec/int2/hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av re pb4/ppo12 pb5/ppo13 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 vpp v dd v ss tx tex pi1/rmc pi2/pwm pi3/to/ddo/adj pi4/int1/nmi pi5/sck1 pi6/so1 pi7/si1 pe0/int0/ckout pd2 pd1 pd0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst v ss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 pf4/an8 av ss 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 76 77 78 79 80 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 note) 1. vpp (pin 88) is always connected to v dd . 2. v ss (pins 39 and 86) are both connected to gnd.
5 cxp872p48a output/real time output output/real time output i/o/real time output i/o/real time output i/o input/input/output input/input/input/ output output/output output/output output/output output/output output/output output/output input input/input output/input i/o output input input (port a) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port b) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port c) 8-bit i/o port, enables to specify i/o by bit unit. data is gated with ppo or rto contents by or-gate and they are output. (8 pins) (port d) 8-bit i/o port. enables to specify i/o by 4-bit unit. enables to drive 12 ma sink current. (8 pins) (port e) 8-bit port. lower 2 bits are input port and upper 6 bits are output port. (8 pins) analog input pins to a/d converter. (12 pins) (port f) lower 4 bits are input port and upper 4 bits are output port. lower 4 bits also serve as standby release input pins. (8 pins) serial clock (ch0) i/o pin. serial data (ch0) output pin. serial data (ch0) input pin. serial chip select (ch0) input pin. external event input pin for timer/counter. input pin to request external interruption. active when falling edge. output pin for hsync counter matching signal. input pin to request external interruption. active when falling edge. system clock frequency division output. pwm output pins. (2 pins) da gate pulse output pins. (4 pins) programmable pattern generator (ppg) output. functions as high precision real time pulse output port. (19 pins) pb0 and pb2 can be 3-state controlled with ppg. real time pulse generator (rtg) output. functions as high precision real time pulse output port. (5 pins) pc3 can be 3-state controlled with rtg. symbol i/o description pa0/ppo0 to pa7/ppo7 pb0/ppo8 to pb7/ppo15 pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 pd0 to pd7 pe0/int0/ ckout pe1/ec/ int2/hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 an0 to an3 pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 sck0 so0 si0 cs0 pin description
6 cxp872p48a pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 ph0 to ph7 pi1/rmc pi2/pwm pi3/to/ ddo/adj pi4/int1/ nmi pi5/sck1 pi6/so1 pi7/si1 pj0 to pj7 extal xtal tex tx rst mp av dd av ref avss v dd vpp vss input/input input/input input/input input/input input/input input/input input/input input/input output i/o/input i/o/output i/o/output/output /output i/o/input/input i/o/i/o i/o/output i/o/input i/o input output input output input input input capstan fg input pin. drum fg input pin. drum pg input pin. playback ctl pulse input pin. external event input pin of timer/counter. composite sync signal input pin. external input pin to frc capture unit. (port g) 8-bit input port. (8 pins) (port h) 8-bit output port; medium withstand voltage (12v) and high current (12 ma), n-ch open drain output. (8 pins) remote control receiving circuit input pin. 14-bit pwm output pin. timer/counter, ctl duty detection, 32khz oscillation adjustment output pin. input pin to request external interruption and non-maskable interruption. active when falling edge. serial clock (ch1) i/o pin. serial data (ch1) output pin. serial data (ch1) input pin. (port i) 7-bit i/o port. enables to specify i/o by bit unit. (7 pins) (port j) 8-bit i/o port. function as standby release input can be specified by bit unit. enables to specify i/o by bit unit. connection pin of crystal oscillator for system clock. when supplying the external clock, input the external clock to extal pin and input opposite phase clock to xtal pin. connection pin of crystal oscillator for 32khz timer clock. when used as event counter, input to tex pin and leave tx pin open. (feedback resistor is not removed.) system reset pin of active "l" level. microprocessor mode input pin. always connect to gnd. positive power supply pin of a/d converter. reference voltage input pin of a/d converter. gnd pin of a/d converter. positive power supply pin. positive power supply pin used for writing incorporated prom. connect to v dd during normal operation. gnd pin. connect both v ss pins to gnd. symbol i/o description
7 cxp872p48a aaaa aaaa aa aa ppo8 or ppo10 data bus pb0 or pb2 data rd (port b) aaaa aaaa aa aa ppo9 or ppo11 data bus pb1 or pb3 data rd (port b) aaaaa a aaa a aaaaa ppg control status register bit 0 3-state control selection ppo9 or ppo11 output becomes active from high impedance by data writing to port register. output becomes active from high impedance by data writing to port register. 12 pins hi-z hi-z when reset pa0/ppo0 to pa7/ppo7 pb4/ppo12 to pb7/ppo15 pb0/ppo8 pb2/ppo10 hi-z pb1/ppo9 pb3/ppo11 aaaa aaaa aa aa ppo data data bus output becomes active from high impedance by data writing to port register. port a or port b rd (port a or port b) input/output circuit formats for pins port a port b pin circuit format 2 pins 2 pins
8 cxp872p48a rto3 data bus rd (port c) aaaa aaaa pc3 direction aaaa aaaa pc3 data aa aa rd (port c direction) rto4 aaaaa a aaa a aaaaa rtg interruption control register bit 7 3-state control selection rto4 aaaa aaaa pc4 direction aaaa pc4 data aa aa rto data is or-gate data of ch0 and ch1. data bus data bus data bus rd (port c) rd (port c direction) aa aa ip aa aa ip 6 pins hi-z hi-z when reset pc0/ppo16 to pc2/ppo18 pc5/rto5 to pc7/rto7 pc3/rto3 hi-z pc4/rto4 ppo, rto data data bus rd (port c) aaaa aa port c direction aaaa aaaa port c data input protection circuit ip (every bit) aa aa rd (port c direction) data bus port c pin circuit format 1 pin 1 pin
9 cxp872p48a data bus rd (port e) a input protection circuit ip a a aa aa mpx interruption circuit ps1 ps2 ps3 aaaa aaaa port e/pwm selection register bit 0, 1 8 pins hi-z hi-z when reset pd0 to pd7 pe0/int0 /ckout hi-z data bus rd (port d) aaaa aaaa a a port d direction aaaa port d data high current 12ma ip (every 4 bits) a a pd0 to 3 pd4 to 7 port d port e pin circuit format pe1/ec/int2 /hcout 1 pin 1 pin data bus rd (port e) a input protection circuit ip a a to interruption circuit/event counter from hsync counter hi-z control hcout port e
10 cxp872p48a rd (port f) data bus aa a ip input multiplexer a/d converter hi-z pin when reset circuit format pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 4 pins 2 pins 4 pins hi-z hi-z h level pe6/dab0 pe7/dab1 data bus rd (port e) aaaa a aa a aaaa aa aa aa aa aa aa da gate output hi-z control mpx aaaa aaaa port e data port/da output select data bus rd (port e) aaaa aaaa aa aa aa aa aa da gate output or pwm output hi-z control mpx aaaa port e data port/da output select port e an0 to an3 aa aa aa ip a/d converter input multiplexer 4 pins pf0/an4 to pf3/an7 port f port e
11 cxp872p48a 4 pins hi-z pin when reset circuit format pf4/an8 to pf7/an11 a/d converter data bus rd (port f) aaaa aaaa aa port/ad select ip aa aa aaaa aaaa port f data input multiplexer port f 8 pins hi-z pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 aa aa ip rd (port g) data bus schmitt input servo input note) for pg4/sync0, pg5/sync1, there are cmos schmitt input and ttl schmitt input. port g 8 pins hi-z ph0 to ph7 data bus rd (port h) aa aa aaaa aaaa port h data high current 12ma medium withstand voltage 12v port h 2 pins hi-z pi2/pwm pi3/to/ ddo/adj aa aa aa aa aa pi2: from 14-bit pwm from timer/counter, pi3: ctl duty detection circuit, 32khz timer mpx aaaa aaaa port i data aa ip data bus rd (port i) aaaa aaaa port i direction aaaa aaaa port i function select port i
12 cxp872p48a so0 output enable aa aa so0 from sio 3 pins hi-z hi-z pin when reset circuit format pi1/rmc pi4/int1/nmi pi7/si1 pi5/sck1 pi6/so1 2 pins 8 pins 1 pin hi-z hi-z hi-z pj0 to pj7 aa aa standby release aaaa port j data aa ip data bus rd (port j) aaaa aaaa port j direction a edge detection rd data bus aa aa aa aa aa mpx aaaa port i data aa ip data bus rd (port i) aaaa port i direction aaaa aaaa port i function select aa aa aa mpx to serial ch1 note) pi5 is schmitt input pi6 is inverter input from serial ch1 aa aa pi1: to remote control circuit pi4: to interruption circuit pi7: to serial ch1 aaaa aaaa port i data a a ip data bus rd (port i) aaaa aaaa port i direction schmitt input port j cs0 si0 aa aa aa aa ip schmitt input to sio 2 pins so0 port i port i
13 cxp872p48a 2 pins oscillation pin when reset circuit format extal xtal aa aa a ip aa aa extal xtal shows the circuit composition during oscillation. feedback resistor is removed during stop. 2 pins oscillation tex tx aa aa ip aa aa tex tx shows the circuit composition during oscillation. feedback resistor is removed during 32khz oscillation circuit stop by software. at this time tex pin outputs "l" level and tx pin outputs "h" level. to 32khz timer counter 1 pin hi-z sck0 sck0 output enable aa aa internal serial clock from sio aa aa ip schmitt input external serial clock to sio 1 pin hi-z mp aa aa aa ip cpu mode 1 pin l level rst aa aa aa aa ip schmitt input pull-up resistor mask option op
14 cxp872p48a ? 1 av dd and v dd should be set to a same voltage. ? 2 v in and v out should not exceed v dd + 0.3v. ? 3 the high current operation transistors are the n-ch transistors of the pd and ph ports. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium withstand output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd vpp av dd av ss v in v out v outp i oh i oh i ol i olc i ol topr tstg p d 0.3 to +7.0 0.3 to +13 avss to +7.0 ? 1 0.3 to +0.3 0.3 to +7.0 ? 2 0.3 to +7.0 ? 2 0.3 to +15.0 5 50 15 20 130 10 to +75 55 to +150 600 380 v v v v v v v ma ma ma ma ma c c mw unique to version with incorporated prom ph pin total of output pins other than high current output pins: per pin high current port output pin ? 3 : per pin total of output pins qfp package type lqfp package type item symbol rating unit remarks absolute maximum ratings (vss = 0v)
15 cxp872p48a analog supply voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 5.5 5.5 v dd v dd 5.5 5.5 v dd + 0.3 v dd + 0.2 0.3v dd 0.2v dd 0.2v dd 0.8 0.4 0.2 +75 3.0 2.7 2.7 2.5 3.0 0.7v dd 0.8v dd 2.2 v dd 0.4 v dd 0.2 0 0 0 0.3 0.3 10 supply voltage v v v v v v v v v v v v v v c item symbol min. max. unit remarks vpp av dd v ih v ihs v ihts v ihex v il v ils v ilts v ilex topr high-speed mode guaranteed operation range (1/2 dividing clock) low-speed mode guaranteed operation range (1/16 dividing clock) guaranteed operation range by tex clock guaranteed data hold range during stop ? 10 ? 1 ? 2 cmos schmitt input ? 3 and pe0/int0 pin cmos schmitt input ? 7 ttl schmitt input ? 4 extal pin ? 5 , ? 8 tex pin ? 6 , ? 8 extal pin ? 5 , ? 9 tex pin ? 6 , ? 9 ? 2 , ? 8 ? 2 , ? 9 cmos schmitt input ? 3 and pe0/int0 pin ttl schmitt input ? 4 extal pin ? 5 , ? 8 tex pin ? 6 , ? 8 extal pin ? 5 , ? 9 tex pin ? 6 , ? 9 v dd ? 1 av dd and v dd should be set to a same voltage. ? 2 normal input port (each pin of pc, pd, pf0 to pf3, pg, pi and pj), mp pin. ? 3 each pin of sck0, rst, pe1/ec/int2, pi1/rmc, pi4/int1/nmi, pi5/sck1 and pi7/si1. ? 4 each pin of pg4 and pg5 (when tll schmitt input is selected for the product) ? 5 it specifies only when the external clock is input. ? 6 it specifies only when the external event count is input. ? 7 each pin of cs0, si0, and pg ( when cmos schmitt input is selected for the product) ? 8 when the supply voltage (v dd ) is within a range from 4.5 to 5.5v. ? 9 when the supply voltage (v dd ) is within a range from 3.0 to 3.6v. ? 10 vpp should be the same voltage as v dd . recommended operating conditions (vss = 0v) vpp = v dd
16 cxp872p48a v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 0.5 0.1 0.1 1.5 v v v v v a a a a a a a pd, ph pa to pd, pe2 to pe7, pf4 to pf7, ph (v ol only) pi1 to pi7 pj, so0, sck0 extal tex rst ? 1 item symbol pins conditions min. other than v dd , vss, av dd , and avss clock 1mhz 0v other than the measured pins v dd i dd1 i iz i loh i dds1 i dd2 i dds2 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 40 10 10 400 10 50 max. unit supply voltage (v dd ) 4.5 to 5.5v dc characteristics (ta = 10 to +75 c, vss = 0v) ? 1 rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ? 2 when entire output pins are open. ? 3 when setting upper 2 bits (cpu clock selection) of clock control register clc (address: 00feh) to "00" and operating in high speed mode (1/2 dividing clock). v dd = 5v 0.5v ? 3 sleep mode v dd = 5v 0.5v v dd = 5v 0.5v supply current ? 2 input capacitance v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v v oh = 12v 16mhz crystal oscillation (c 1 = c 2 = 15pf) stop mode (extal and tex pins oscillation stop) i/o leakage current open drain output leakage current (n-ch tr off in state) pa to pg, pi, pj, mp an0 to an3, cs0, si0, so0 sck0, rst ? 1 ph 27 2 500 10 10 45 8 1000 30 30 20 ma ma a a a pf v dd = 3v 0.3v sleep mode v dd = 3v 0.3v 32khz crystal oscillation (c 1 = c 2 = 47pf)
17 cxp872p48a v dd = 3.0v, i oh = 0.15ma v dd = 3.0v, i oh = 0.5ma v dd = 3.0v, i ol = 1.2ma v dd = 3.0v, i ol = 1.6ma v dd = 3.0v, i ol = 5ma v dd = 3.6v, v ih = 3.6v v dd = 3.6v, v il = 0.3v v dd = 3.6v, v ih = 3.6v high level output voltage 2.7 2.3 0.3 0.3 0.1 0.1 0.9 v v v v v a a a a a a a pd, ph pa to pd, pe2 to pe7, pf4 to pf7, ph (v ol only) pi1 to pi7 pj, so0, sck0 extal tex rst ? 1 item symbol pins conditions min. other than v dd , vss, av dd , and avss clock 1mhz 0v other than the measured pins v dd i dd1 i iz i loh i dds1 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.3 0.5 1.0 20 20 10 10 200 10 50 max. unit supply voltage (v dd ) 3.0 to 3.6v (ta = 10 to +75 c, vss = 0v) v dd = 3.3v 0.3v ? 3 sleep mode v dd = 3.3v 0.3v v dd = 3.3v 0.3v supply current ? 2 input capacitance v dd = 3.6v, v il = 0.3v v dd = 3.6v, v i = 0, 3.6v v dd = 3.6v, v oh = 12v 12mhz crystal oscillation (c 1 = c 2 = 15pf) stop mode (extal and tex pins oscillation stop) i/o leakage current open drain output leakage current pa to pg, pi, pj, mp an0 to an3, cs0, si0, so0 sck0, rst ? 1 ph 12 0.8 10 25 2.5 30 20 ma ma a pf ? 1 rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ? 2 when entire output pins are open. ? 3 when setting upper 2 bits (cpu clock selection) of clock control register clc (address: 00feh) to "00" and operating in high speed mode (1/2 dividing clock).
18 cxp872p48a ? t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaaa a aaa a aaaaa external clock extal xtal 74hc04 aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal c 1 c 2 aaaaa a aaa a aaaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr ac characteristics (1) clock timing (ta = 10 to +75 c, v dd = 3.0 to 5.5v, v ss = 0v) system clock frequency system clock input pulse width system clock input rise and fall times event count clock input pulse width event count clock input rise and fall times system clock frequency event count clock input pulse width event count clock input rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal xtal extal xtal extal ec ec tex tx tex tex mhz ns ns ns ns khz s ms item symbol pins conditions unit fig. 1, fig. 2 fig. 1, fig. 2 (external clock drive) fig. 1, fig. 2 (external clock drive) fig. 3 fig. 3 fig. 2 v dd = 2.7 to 5.5v (32khz clock applied condition) fig. 3 fig. 3 min. 1 1 28 37.5 t sys 4 ? 32.768 10 max. 16 12 200 20 20 fig. 1. clock timing fig. 3. event count clock timing v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v fig. 2. clock applied condition
19 cxp872p48a input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) cs, sck, si and so mean each pin of cs cs0, sck sck0, si si0, and so so0 respectively. note 3) the load of sck output mode and so output delay time is 50pf + 1 ttl. (2) serial transfer (ch0) (ta = 10 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v) item cs sck delay time cs sck floating delay time cs so delay time cs so floating delay time cs high level width sck cycle time sck high and low level widths si input set-up time (against sck ) si input hold time (against sck ) sck so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pins min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 8000/fc t sys + 100 8000/fc 100 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 200 100 max. unit conditions
20 cxp872p48a input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) cs, sck, si and so mean each pin of cs cs0, sck sck0, si si0, and so so0 respectively. note 3) the load of sck output mode and so output delay time is 50pf. (2) serial transfer (ch0) (ta = 10 to +75 c, v dd = 3.0 to 3.6v, v ss = 0v) item cs sck delay time cs sck floating delay time cs so delay time cs so floating delay time cs high level width sck cycle time sck high and low level widths si input set-up time (against sck ) si input hold time (against sck ) sck so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pins min. t sys + 250 t sys + 200 t sys + 250 t sys + 200 t sys + 200 2 t sys + 200 8000/fc t sys + 100 8000/fc 150 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 250 125 max. unit conditions
21 cxp872p48a fig. 4. serial transfer timing (ch0) cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0
22 cxp872p48a serial transfer (ch1) (sio mode) (ta = 10 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v) note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck1 output mode and so1 output delay time is 50pf + 1 ttl. sck1 cycle time 2 t sys + 200 16000/fc t sys + 100 8000/fc 50 100 200 t sys + 200 100 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns item symbol pins conditions min. max. unit t kcy input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 sck1 high and low level widths t kh t kl sck1 si1 input set-up time (against sck1 ) t sik si1 t ksi si1 sck1 so1 delay time t kso so1 si1 input hold time (against sck1 ) serial transfer (ch1) (sio mode) (ta = 10 to +75 c, v dd = 3.0 to 3.6v, v ss = 0v) note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck1 output mode and so1 output delay time is 50pf. sck1 cycle time 2 t sys + 200 16000/fc t sys + 100 8000/fc 150 100 200 t sys + 200 100 t sys + 250 125 ns ns ns ns ns ns ns ns ns ns item symbol pins conditions min. max. unit t kcy input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 sck1 high and low level widths t kh t kl sck1 si1 input set-up time (against sck1 ) t sik si1 t ksi si1 sck1 so1 delay time t kso so1 si1 input hold time (against sck1 )
23 cxp872p48a sck1 si1 so1 t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd fig. 5. serial transfer ch1 timing (sio mode)
24 cxp872p48a serial transfer (ch1) (special mode) (ta = 10 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v) note 1) t lcy specifies only serial mode register (ch1) (siom1: address 01fa h ) lower 2 bits (so1 clock selection) has been set at 104s. note 2) the load of so1 pin is 50pf + 1 ttl. serial transfer (ch1) (special mode) (ta = 10 to +75 c, v dd = 3.0 to 3.6v, v ss = 0v) note 1) t lcy specifies only serial mode register (ch1) (siom1: address 01fa h ) lower 2 bits (so1 clock selection) has been set at 104s. note 2) the load of so1 pin is 50pf. fig. 6. serial transfer ch1 timing (special mode) so1 cycle time si1 data set-up time si1 data hold time t lcy t lsu t lhd so1 si1 si1 si1 note 1) 2 2 104 s s s item symbol pins conditions min. typ. max. unit so1 cycle time si1 data set-up time si1 data hold time t lcy t lsu t lhd so1 si1 si1 si1 note 1) 2 2 104 s s s item symbol pins conditions min. typ. max. unit so1 si1 t lcy start bit output data bit t lcy 0.5v dd 0.8v dd 0.2v dd t lcy/2 t lsu t lhd input data bit
25 cxp872p48a external clock input frequency external clock input pulse width external clock input rise and fall times f pck t wh , t wl t r t f sync1 sync1 sync1 33 12 200 mhz ns ns item symbol pins conditions min. typ. max. unit (3) general purpose prescaler (ta = 10 to +75 c, v dd = 3.0 to 5.5v, v ss = 0v) fig. 7. general purpose prescaler timing 1/f pck t f t wh 0.8v dd t r t wl 0.5v dd 0.2v dd sync1
26 cxp872p48a (4) hsync counter (ta = 10 to + 75 c, v dd = 3.0 to 5.5v, v ss = 0v) note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of hcout pin is 50pf. fig. 8. hsync counter timing external clock input frequency external clock input pulse width external clock input rise and fall times hcout output delay time (against sync1 ) hcout output rise and fall times f hck t wh , t wl t r t f t hlh t hhl t tlh t thl sync1 sync1 sync1 hcout hcout external clock input sync1 t r = t f = 6ns external clock input sync1 t r = t f = 6ns 33 t sys + 130 t sys + 90 100 30 12 200 t sys + 220 t sys + 150 280 70 mhz ns ns ns ns ns ns item symbol pins conditions min. typ. max. unit 1/f hck t f t wh 0.8v dd t r t wl 0.5v dd 0.2v dd t hlh 0.8v dd 0.5v dd 0.2v dd t tlh t thl t hhl sync1 hcout
27 cxp872p48a conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian i ref ta = 25 c v dd = av dd = av ref = 5.0v v ss = av ss = 0v operating mode sleep mode stop mode 32khz operating mode linearity error absolute error resolution av ref current av ref i refs s s v v av dd 1.0 ma 10 a 0.6 160/f adc ? 12/f adc ? av dd 0.5 0 item symbol pins conditions min. typ. max. unit bits (5) a/d converter characteristics (ta = 10 to +75 c, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v) 8 1 2 lsb lsb analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value fig. 9. definitions of a/d converter terms av ref an0 to an11 v dd = av dd = 4.5 to 5.5v ? the value of f adc is as follows by selecting adc operation clock (msc: address 01ff h bit 0). when ps2 is selected, f adc = fc/2 when ps1 is selected, f adc = fc conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian i ref ta = 25 c v dd = av dd = av ref = 5.0v v ss = av ss = 0v operating mode sleep mode stop mode 32khz operating mode linearity error absolute error resolution av ref current av ref i refs s s v v av dd 0.7 ma 10 a 0.4 160/f adc ? 12/f adc ? av dd 0.3 0 item symbol pins conditions min. typ. max. unit bits (ta = 10 to +75 c, v dd = av dd = 3.0 to 3.6v, av ref = 2.7 to av dd , vss = av ss = 0v) 8 1 2 lsb lsb av ref an0 to an11 v dd = av dd = 3.0 to 3.6v
28 cxp872p48a external interruption high and low level widths reset input low level width int0 int1 int2 nmi pj0 to pj7 rst 1 32/fc s s item symbol pins conditions min. max. unit t ih t il t rsl (6) interruption, reset input (ta = 10 to +75 c, v dd = 3.0 to 5.5v, vss = 0v) 0.2v dd 0.8v dd t ih t il int0 int1 int2 nmi pj0 to pj7 (during standby release input) (falling edge) fig. 10. interruption input timing t rsl 0.2v dd rst fig. 11. reset input timing (7) others (ta = 10 to +75 c, v dd = 3.0 to 5.5v, vss = 0v) item cfg input high and low level widths dfg input high and low level widths dpg minimum pulse width dpg minimum removal time pbctl input high and low level widths exi input high and low level widths t cfh t cfl t dfh t dfl t dpw t rem t cth t ctl t eih t eil cfg dfg dpg dpg pbctl exi0 exi1 ns ns ns ns ns ns symbol pins min. t frc 24 + 200 t frc 16 + 200 t frc 8 + 200 t frc 16 + 200 t frc 8 + 200 + t sys t frc 8 + 200 + t sys max. unit t sys = 2000/fc t sys = 2000/fc conditions note) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") t frc = 1000/fc [ns]
29 cxp872p48a 0.8v dd cfg t cfh t cfl 0.2v dd 0.8v dd dfg t dfh t dfl 0.2v dd 0.8v dd pbctl t cth t ctl 0.2v dd 0.8v dd exi0 exi1 t eih t eil 0.2v dd 0.8v dd t dpw t rem dpg t rem fig. 12. other timings
30 cxp872p48a appendix fig. 13. recommended oscillation circuit aaaa a aa a aaaa extal xtal c 1 c 2 rd (i) aaaa a aa a aaaa tex tx c 1 c 2 rd (ii) manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 8.00 10.00 12.00 8.00 10.00 12.00 12 12 12 12 0 16.00 30 18 470k (ii) 32.768khz 10 5 16 (12) 10 16.00 5 16 (12) 16 (12) 16 (12) 0 0 0 c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) (i) product list ? pg4/sync0 pin and pg5/sync1 pin only optional item package rom capacity reset pin pull- up resistor input circuit format ? 100-pin plastic qfp/lqfp 40k bytes /48k bytes existent /non-existent cmos schmitt /ttl schmitt 100-pin plastic qfp prom 48k bytes existent ttl schmitt 100-pin plastic lqfp prom 48k bytes existent ttl schmitt 100-pin plastic qfp prom 48k bytes existent cmos schmitt 100-pin plastic lqfp prom 48k bytes existent cmos schmitt mask product cxp872p48aq-1 - cxp872p48ar-1 - cxp872p48aq-2 - cxp872p48ar-2 -
31 cxp872p48a v dd [v] 34 56 0.1 1 10 i dd [ma] i dd vs. v dd (fc = 16mhz, ta = 25 c, typical) 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 32khz oscillation (instruction) sleep mode 32khz sleep mode i dd [ma] 2 0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode 4 6 8 10121416 5 10 15 20 25 system clock (mhz) i dd [ma] 2 0 4 6 8 10121416 5 10 15 20 25 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode v dd [v] 34 56 0.1 1 10 i dd [ma] 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode i dd vs. v dd (fc = 12mhz, ta = 25 c, typical) i dd vs. fc (v dd = 3.3v, ta = 25 c, typical) i dd vs. fc (v dd = 5.0v, ta = 25 c, typical) system clock (mhz) characteristics curve
32 cxp872p48a package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec.
33 cxp872p48a package outline unit: mm 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 ?0.1 + 0.2 0.5 0.2 (15.0) 0? to 10? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 ?0.03 ( 0.18 ) (0.127) + 0.08 0.127 ?0.02 + 0.05 detail b ? b 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 0.1 + 0.2 0.5 0.2 (15.0) 0 ? to 10 ? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b ? b lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. sony corporation

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