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1 features description applications tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 complete ddr, ddr2 and ddr3 memory power solution synchronous buck controller, 3-a ldo, buffered reference 2 synchronous buck controller (vddq) ? wide-input voltage range: 3.0-v to 28-v the tps51116 provides a complete power supply for ddr/sstl-2, ddr2/sstl-18, and ddr3 memory ? d ? cap? mode with 100-ns load step systems. it integrates a synchronous buck controller response with a 3-a sink/source tracking linear regulator and ? current mode option supports ceramic buffered low noise reference. the tps51116 offers output capacitors the lowest total solution cost in systems where space is at a premium. the tps51116 synchronous ? supports soft-off in s4/s5 states controller runs fixed 400khz pseudo-constant ? current sensing from r ds(on) or resistor frequency pwm with an adaptive on-time control that ? 2.5-v (ddr), 1.8-v (ddr2), adjustable to can be configured in d-cap? mode for ease of use 1.5-v (ddr3) or output range 0.75-v to and fastest transient response or in current mode to 3.0-v support ceramic output capacitors. the 3-a sink/source ldo maintains fast transient response ? equipped with powergood, overvoltage only requiring 20- m f (2 10 m f) of ceramic output protection and undervoltage protection capacitance. in addition, the ldo supply input is 3-a ldo (vtt), buffered reference (vref) available externally to significantly reduce the total ? capable to sink and source 3 a power losses. the tps51116 supports all of the sleep state controls placing vtt at high-z in s3 ? ldo input available to optimize power (suspend to ram) and discharging vddq, vtt and losses vttref (soft-off) in s4/s5 (suspend to disk). ? requires only 20- m f ceramic output tps51116 has all of the protection features including capacitor thermal shutdown and is offered in both a 20-pin htssop powerpad? package and 24-pin 4 ? qfn. ? buffered low noise 10-ma vref output ? accuracy 20 mv for both vref and vtt ? supports high-z in s3 and soft-off in s4/s5 ddr/ddr2/ddr3/lpddr3 memory power ? thermal shutdown supplies sstl-2 sstl-18 and hstl termination 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 d-cap, powerpad are trademarks of texas instruments. production data information is current as of publication date. copyright ? 2004 ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. s5 pgood vref 0.9 v 10 ma vtt 0.9 v 2 a tps51116rge 20 19 18 17 vbst drvh ll drvl v5filt vldoin vttgndvttsns 7 8 vtt cs_gnd 9 10 vddqset cs vddqsns 16 15 14 13 pgood 12 11 s5 s3 gndmode vttref comp nc nc v5in pgnd 22 21 24 23 1 2 3 4 5 6 c1 5v_in vddq1.8 v 10 a vin m1 m2 s3 l1 irf7832 irf7821 c4 c3 ceramic 2 10 m f ceramic0.033 m f ceramic 0.1 m f 1 m h c6sp?cap 2 150 m f c5ceramic 2 10 m f c2ceramic 1 m f c7ceramic 1 m f r2100 k w r15.1 k w r35.1 w udg?04153
absolute maximum ratings (1) dissipation ratings tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. ordering information (1) minimum orderable part output t a package pins order number supply quantity tps51116pwp tube 70 plastic htssop tps51116pwpr 20 tape-and-reel 2000 powerpad (pwp) tps51116pwprg4 tape-and-reel 2000 tps51116rge tube 90 -40 c to 85 c large plastic quad flat TPS51116RGER 3000 24 tape-and-reel pack (qfn) small tps51116rget 250 tape-and-reel (1) all packaging options have cu nipdau lead/ball finish. over operating free-air temperature range unless otherwise noted tps51116 units vbst -0.3 to 36 vbst wrt ll -0.3 to 6 v in input voltage range v cs, mode, s3, s5, vttsns, vddqsns, v5in, vldoin, vddqset, -0.3 to 6 v5filt pgnd, vttgnd, cs_gnd -0.3 to 0.3 drvh -1.0 to 36 v out output voltage range ll -1.0 to 30 v comp, drvl, pgood, vtt, vttref -0.3 to 6 t a operating ambient temperature range -40 to 85 c t stg storage temperature -55 to 150 (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to the network ground terminal unless otherwise noted. derating factor above t a = t a < 25 c power rating t a = 85 c power rating package 25 c (w) (w) (mw/ c) 20-pin pwp 2.53 25.3 1.01 24-pin rge 2.20 22.0 0.88 2 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
recommended operating conditions tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 min max unit supply voltage, v5in, v5filt 4.75 5.25 v vbst, drvh -0.1 34 ll -0.6 28 vldoin, vtt, vttsns, vddqsns -0.1 3.6 voltage range v vttref -0.1 1.8 pgnd, vttgnd, cs_gnd -0.1 0.1 s3, s5, mode, vddqset, cs, comp, pgood, -0.1 5.25 drvl operating free-air temperature, t a -40 85 c copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 3 product folder link(s): tps51116
electrical characteristics tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com over operating free-air temperature range, v v5in = 5 v (1) , vldoin is connected to vddq output (unless otherwise noted) parameter test conditions min typ max unit supply current t a = 25 c, no load, v s3 = v s5 = 5 v, i v5in1 supply current 1, v5in (1) 0.8 2 ma comp connected to capacitor t a = 25 c, no load, v s3 = 0 v, v s5 = 5 v, i v5in2 supply current 2, v5in (1) 300 600 comp connected to capacitor t a = 25 c, no load, v s3 = 0 v, v s5 = 5 v, i v5in3 supply current 3, v5in (1) 240 500 v comp = 5 v m a i v5insdn shutdown current, v5in (1) t a = 25 c, no load, v s3 = v s5 = 0 v 0.1 1.0 i vldoin1 supply current 1, vldoin t a = 25 c, no load, v s3 = v s5 = 5 v 1 10 i vldoin2 supply current 2, vldoin t a = 25 c, no load, v s3 = 5 v, v s5 = 0 v, 0.1 10 i vldoinsdn standby current, vldoin t a = 25 c, no load, v s3 = v s5 = 0 v 0.1 1.0 vttref output v vttref output voltage, vttref v vddqsns /2 v -10 ma < i vttref < 10 ma, v vddqsns = 2.5 v, -20 20 tolerance to v vddqsns /2 -10 ma < i vttref < 10 ma, v vddqsns = 1.8 v, -18 18 tolerance to v vddqsns /2 v vttreftol output voltage tolerance mv -10 ma < i vttref < 10 ma, v vddqsns = 1.5 v, -15 15 tolerance to v vddqsns /2 -10 ma < i vttref < 10 ma, v vddqsns = 1.2 v, ? 12 12 tolerance to v vddqsns /2 v vttrefsrc source current v vddqsns = 2.5 v, v vttref = 0 v -20 -40 -80 ma v vttrefsnk sink current v vddqsns = 2.5 v, v vttref = 2.5 v 20 40 80 vddq output t a = 25 c, v vddqset = 0 v, no load 2.465 2.500 2.535 0 c t a 85 c, v vddqset = 0 v, no load (2) 2.457 2.500 2.543 -40 c t a 85 c, v vddqset = 0 v, no load (2) 2.440 2.500 2.550 t a = 25 c, v vddqset = 5 v, no load (2) 1.776 1.800 1.824 v vddq output voltage, vddq v 0 c t a 85 c, v vddqset = 5v, no load (2) 1.769 1.800 1.831 -40 c t a 85 c, v vddqset = 5v, no load (2) 1.764 1.800 1.836 -40 c t a 85 c, adjustable mode, no 0.75 3.0 load (2) t a = 25 c, adjustable mode 742.5 750.0 757.5 mv v vddqset vddqset regulation voltage 0 c t a 85 c, adjustable mode 740.2 750.0 759.8 -40 c t a 85 c, adjustable mode 738.0 750.0 762.0 v vddqset = 0 v 215 k ? r vddqsns input impedance, vddqsns v vddqset = 5 v 180 adjustable mode 460 v vddqset = 0.78 v, comp = open -0.04 i vddqset input current, vddqset m a v vddqset = 0.78 v, comp = 5 v -0.06 v s3 = v s5 = 0 v, v vddqsns = 0.5 v, i vddqdisch discharge current, vddq 10 40 ma v mode = 0 v v s3 = v s5 = 0 v, v vddqsns = 0.5 v, i vldoindisch discharge current, vldoin 700 ma v mode = 0.5 v (1) v5in references to pwp packaged devices should be interpreted as v5filt references to rge packaged devices. (2) specified by design. 4 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 electrical characteristics (continued) over operating free-air temperature range, v v5in = 5 v , vldoin is connected to vddq output (unless otherwise noted) parameter test conditions min typ max unit vtt output v s3 = v s5 = 5 v, v vldoin = v vddqsns = 2.5 v 1.25 v vttsns output voltage, vtt v s3 = v s5 = 5 v, v vldoin = v vddqsns = 1.8 v 0.9 v v s3 = v s5 = 5 v, v vldoin = v vddqsns = 1.5 v 0.75 v vddqsns = v vldoin = 2.5 v, v s3 = v s5 = 5 v, -20 20 i vtt = 0 a vtt output voltage tolerance v vddqsns = v vldoin = 2.5 v, v s3 = v s5 = 5 v, v vtttol25 -30 30 mv to vttref |i vtt | < 1.5 a v vddqsns = v vldoin = 2.5 v, v s3 = v s5 = 5 v, -40 40 |i vtt | < 3 a v vddqsns = v vldoin = 1.8 v, v s3 = v s5 = 5 v, -20 20 i vtt = 0 a vtt output voltage tolerance v vddqsns = v vldoin = 1.8 v, v s3 = v s5 = 5 v, v vtttol18 -30 30 mv to vttref |i vtt | < 1 a v vddqsns = v vldoin = 1.8 v, v s3 = v s5 = 5 v, -40 40 |i vtt | < 2 a v vddqsns = v vldoin = 1.5 v, v s3 = v s5 = 5 v, -20 20 i vtt = 0 a vtt output voltage tolerance v vddqsns = v vldoin = 1.5 v, v s3 = v s5 = 5 v, v vtttol15 -30 30 mv to vttref |i vtt | < 1 a v vddqsns = v vldoin = 1.5 v, v s3 = v s5 = 5 v, -40 40 |i vtt | < 2 a v vddqsns = v vldoin = 1.2 v, v s3 = v s5 = 5 v, -20 20 i vtt = 0 a vtt output voltage tolerance v vddqsns = v vldoin = 1.2 v, v s3 = v s5 = 5 v, v vtttol12 -30 30 mv to vttref |i vtt | < 1 a v vddqsns = v vldoin = 1.2 v, v s3 = v s5 = 5 v, -40 40 |i vtt | < 1.5 a v vldoin = v vddqsns = 2.5 v, v vtt = v vttsns = 3.0 3.8 6.0 1.19 v, pgood = hi i vtttoclsrc source current limit, vtt v vldoin = v vddqsns = 2.5 v, v vtt = 0 v 1.5 2.2 3.0 a v vldoin = v vddqsns = 2.5 v, v vtt = v vttsns = 3.0 3.6 6.0 1.31 v, pgood = hi i vtttoclsnk sink current limit, vtt v vldoin = v vddqsns = 2.5 v, v vtt = v vddq 1.5 2.2 3.0 i vttlk leakage current, vtt v s3 = 0 v, v s5 = 5 v, v vtt = v vddqsns /2 -10 10 i vttbias input bias current, vttsns v s3 = 5 v, v vttsns = v vddqsns /2 -1 -0.1 1 m a i vttsnslk leakage current, vttsns v s3 = 0 v, v s5 = 5 v, v vtt = v vddqsns /2 -1 1 t a = 25 c, v s3 = v s5 = v vddqsns = 0 v, i vttdisch discharge current, vtt 10 17 ma v vtt = 0.5 v transconductance amplifier gm gain t a = 25 c 240 300 360 m s comp maximum sink v s3 = 0 v, v s5 = 5 v, v vddqset = 0 v, i compsnk 13 current v vddqsns = 2.7 v, v comp = 1.28 v m a comp maximum source v s3 = 0 v, v s5 = 5 v, v vddqset = 0 v, i compsrc -13 current v vddqsns = 2.3 v, v comp = 1.28 v v s3 = 0 v, v s5 = 5 v, v vddqset = 0 v, v comphi comp high clamp voltage 1.31 1.34 1.37 v vddqsns = 2.3 v, v cs = 0 v v v s3 = 0 v, v s5 = 5 v, v vddqset = 0 v, v complo comp low clamp voltage 1.18 1.21 1.24 v vddqsns = 2.7 v, v cs = 0 v copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 5 product folder link(s): tps51116
tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com electrical characteristics (continued) over operating free-air temperature range, v v5in = 5 v , vldoin is connected to vddq output (unless otherwise noted) parameter test conditions min typ max unit duty control t on operating on-time v in = 12 v, v vddqset = 0 v 520 t on0 startup on-time v in = 12 v, v vddqsns = 0 v 125 ns t on(min) minimum on-time t a = 25 c (3) 100 t off(min) minimum off-time t a = 25 c (3) 350 zero current comparator zero current comparator v zc -6 0 6 mv offset output drivers source, i drvh = -100 ma 3 6 r drvh drvh resistance sink, i drvh = 100 ma 0.9 3 ? source, i drvl = -100 ma 3 6 r drvl drvl resistance sink, i drvl = 100 ma 0.9 3 ll-low to drvl-on (3) 10 t d dead time ns drvl-off to drvh-on (3) 20 internal bst diode v fbst forward voltage v v5in-vbst , i f = 10 ma, t a = 25 c 0.7 0.8 0.9 v v vbst = 34 v, v ll = 28 v, v vddq = 2.6 v, i vbstlk vbst leakage current 0.1 1.0 m a t a = 25 c protections v pgnd-cs , pgood = hi, v cs < 0.5 v 50 60 70 v ocl current limit threshold mv v pgnd-cs , pgood = lo, v cs < 0.5 v 20 30 40 t a = 25 c, v cs > 4.5 v, pgood = hi 9 10 11 i trip current sense sink current m a t a = 25 c, v cs > 4.5 v, pgood = lo 4 5 6 trip current temperature r ds(on) sense scheme, on the basis tc itrip 4500 ppm/ c coefficient of t a = 25 c (3) overcurrent protection (v v5in-cs - v pgnd-ll ), v v5in-cs = 60 mv, v ocl(off) -5 0 5 comp offset v cs > 4.5 v (3) mv current limit threshold setting v r(trip) v v5in-cs (3) (4) 30 150 range powergood comparator pg in from lower 92.5% 95.0% 97.5% v tvddqpg vddq powergood threshold pg in from higher 102.5% 105.0% 107.5% pg hysteresis 5% i pg(max) pgood sink current v vtt = 0 v, v pgood = 0.5 v 2.5 7.5 ma t pg(del) pgood delay time delay for pg in 80 130 200 m s (3) specified by design. (4) v5in references to pwp packaged devices should be interpreted as v5filt references to rge packaged devices. 6 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 electrical characteristics (continued) over operating free-air temperature range, v v5in = 5 v , vldoin is connected to vddq output (unless otherwise noted) parameter test conditions min typ max unit undervoltage lockout/logic threshold wake up 3.7 4.0 4.3 v5in uvlo threshold v uvv5in voltage hysteresis 0.2 0.3 0.4 no discharge 4.7 v thmode mode threshold non-tracking discharge 0.1 2.5 v output 0.08 0.15 0.25 v v thvddqset vddqset threshold voltage 1.8 v output 3.5 4.0 4.5 v ih high-level input voltage s3, s5 2.2 v il low-level input voltage s3, s5 0.3 v ihyst hysteresis voltage s3, s5 0.2 v inleak logic input leakage current s3, s5, mode -1 1 m a v invddqset input leakage/ bias current vddqset -1 1 undervoltage and overvoltage protection ovp detect 110% 115% 120% vddq ovp trip threshold v ovp voltage hysteresis 5% vddq ovp propagation t ovpdel 1.5 m s delay (5) uvp detect 70% v uvp output uvp trip threshold hysteresis 10% output uvp propagation t uvpdel 32 delay (5) cycle t uvpen output uvp enable delay (5) 1007 thermal shutdown shutdown temperature 160 t sdn thermal sdn threshold (5) c hysteresis 10 (5) specified by design. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 7 product folder link(s): tps51116
device information tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com terminal functions terminal no. i/o description name pwp rge output of the transconductance amplifier for phase compensation. connect to v5in to disable comp 8 6 i/o gm amplifier and use d-cap? mode. current sense comparator input (-) for resistor current sense scheme. or overcurrent trip cs 15 16 i/o voltage setting input for r ds(on) current sense scheme if connected to v5in (pwp), v5filt (rge) through the voltage setting resistor. drvh 19 21 o switching (top) mosfet gate drive output. drvl 17 19 o rectifying (bottom) mosfet gate drive output. gnd 5 3 - signal ground. connect to minus terminal of the vtt ldo output capacitor. cs_gnd - 17 current sense comparator input (+) and ground for powergood circuit. switching (top) mosfet gate driver return. current sense comparator input (-) for r ds(on) ll 18 20 i/o current sense. mode 6 4 i discharge mode setting pin. see vddq and vtt discharge control section. nc - 7,12 no connect. ground for rectifying (bottom) mosfet gate driver (pwp, rge). also current sense pgnd 16 18 - comparator input(+) and ground for powergood circuit (pwp). powergood signal open drain output, in high state when vddq output voltage is within the pgood 13 13 o target range. s3 11 10 i s3 signal input. s5 12 11 i s5 signal input. v5in 14 15 i 5-v power supply input for internal circuits (pwp) and mosfet gate drivers (pwp, rge). filtered 5-v power supply input for internal circuits. connect r-c network from v5in to v5filt - 14 i v5filt. vbst 20 22 i/o switching (top) mosfet driver bootstrap voltage input. vddqset 10 9 i vddq output voltage setting pin. see vddq output voltage selection section. vddq reference input for vtt and vttref. power supply for the vttref. discharge vddqsns 9 8 i/o current sinking terminal for vddq non-tracking discharge. output voltage feedback input for vddq output if vddqset pin is connected to v5in or gnd. vldoin 1 23 i power supply for the vtt ldo. vtt 2 24 o power output for the vtt ldo. vttgnd 3 1 - power ground output for the vtt ldo. vttref 7 5 o vttref buffered reference output. voltage sense input for the vtt ldo. connect to plus terminal of the vtt ldo output vttsns 4 2 i capacitor. 8 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 9 product folder link(s): tps51116 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 vldoin vtt vttgnd vttsns gnd mode vttref comp vddqsns vddqset vbst drvh ll drvl pgnd cs v5in pgood s5 s3 pwp p ackage (t op view) ncvddqsns vddqset s3 s5 nc 78 9 10 11 12 rge p ackage (bott om view) 2423 22 21 20 19 vtt vldoin vbst drvh ll drvl 1 2 3 4 5 6 18 17 16 15 14 13 vttgndvttsns gnd mode vttref comp pgnd cs_gnd cs v5in v5filt pgood
tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com functional block diagram (pwp) 10 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 functional block diagram (rge) copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 11 product folder link(s): tps51116
detailed description vddq smps, dual pwm operation modes tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com the tps51116 is an integrated power management solution which combines a synchronous buck controller, a 10-ma buffered reference and a high-current sink/source low-dropout linear regulator (ldo) in a small 20-pin htssop package or a 24-pin qfn package. each of these rails generates vddq, vttref and vtt that required with ddr/ddr2/ddr3 memory systems. the switch mode power supply (smps) portion employs external n-channel mosfets to support high current for ddr/ddr2/ddr3 memory ? s vdd/vddq. the preset output voltage is selectable from 2.5 v or 1.8 v. user defined output voltage is also possible and can be adjustable from 0.75 v to 3 v. input voltage range of the smps is 3 v to 28 v. the smps runs an adaptive on-time pwm operation at high-load condition and automatically reduces frequency to keep excellent efficiency down to several ma. current sensing scheme uses either r ds(on) of the external rectifying mosfet for a low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying mosfet for more accurate current limit. the output of the switcher is sensed by vddqsns pin to generate one-half vddq for the 10-ma buffered reference (vttref) and the vtt active termination supply. the vtt ldo can source and sink up to 3-a peak current with only 20- m f (two 10- m f in parallel) ceramic output capacitors. vttref tracks vddq/2 within 1% of vddq. vtt output tracks vttref within 20 mv at no load condition while 40 mv at full load. the ldo input can be separated from vddq and optionally connected to a lower voltage by using vldoin pin. this helps reducing power dissipation in sourcing phase. thetps51116 is fully compatible to jedec ddr/ddr2 specifications at s3/s5 sleep state (see table 2 ). the part has two options of output discharge function when both vtt and vddq are disabled. the tracking discharge mode discharges vddq and vtt outputs through the internal ldo transistors and then vtt output tracks half of vddq voltage during discharge. the non-tracking discharge mode discharges outputs using internal discharge mosfets which are connected to vddqsns and vtt. the current capability of these discharge fets are limited and discharge occurs more slowly than the tracking discharge. these discharge functions can be disabled by selecting non-discharge mode. the main control loop of the smps is designed as an adaptive on-time pulse width modulation (pwm) controller. it supports two control schemes which are a current mode and a proprietary d-cap? mode. d-cap? mode uses internal compensation circuit and is suitable for low external component count configuration with an appropriate amount of esr at the output capacitor(s). current mode control has more flexibility, using external compensation network, and can be used to achieve stable operation with very low esr capacitor(s) such as ceramic or specialty polymer capacitors. these control modes are selected by the comp terminal connection. if the comp pin is connected to v5in, tps51116 works in the d-cap? mode, otherwise it works in the current mode. vddq output voltage is monitored at a feedback point voltage. if vddqset is connected to v5in or gnd, this feedback point is the output of the internal resistor divider inside vddqsns pin. if an external resistor divider is connected to vddqset pin, vddqset pin itself becomes the feedback point (see vddq output voltage selection section). at the beginning of each cycle, the synchronous top mosfet is turned on, or becomes on state. this mosfet is turned off, or becomes off state, after internal one shot timer expires. this one shot is determined by v in and v out to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (see pwm frequency and adaptive on-time control section). the mosfet is turned on again when feedback information indicates insufficient output voltage and inductor current information indicates below the overcurrent limit. repeating operation in this manner, the controller regulates the output voltage. the synchronous bottom or the rectifying mosfet is turned on each off state to keep the conduction loss minimum. the rectifying mosfet is turned off when inductor current information detects zero level. this enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current. in the current mode control scheme, the transconductance amplifier generates a target current level corresponding to the voltage difference between the feedback point and the internal 750 mv reference. during the off state, the pwm comparator monitors the inductor current signal as well as this target current level, and when the inductor current signal comes lower than the target current level, the comparator provides set signal to initiate the next on state. the voltage feedback gain is adjustable outside the controller device to support various types of output mosfets and capacitors. in the d-cap? mode, the transconductance amplifier is disabled and the pwm comparator compares the feedback point voltage and the internal 750 mv reference during the off state. when the feedback point comes lower than the reference voltage, the comparator provides set signal to initiate the next on state. 12 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
vddq smps, light load condition (1) low-side driver high-side driver current sensing scheme tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 tps51116 automatically reduces switching frequency at light load condition to maintain high efficiency. this reduction of frequency is achieved smoothly and without increase of v out ripple or load regulation. detail operation is described as follows. as the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. the rectifying mosfet is turned off when this zero inductor current is detected. as the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next on cycle. the on-time is kept the same as that in the heavy load condition. in reverse, when the output current increase from light load to heavy load, switching frequency increases to the constant 400 khz as the inductor current reaches to the continuous conduction. the transition load point to the light load operation i out(ll) (i.e. the threshold between continuous and discontinuous conduction mode) can be calculated in equation 1 : where f is the pwm switching frequency (400 khz) switching frequency versus output current in the light load condition is a function of l, f, v in and v out , but it decreases almost proportional to the output current from the i out(ll) given above. for example, it is 40 khz at i out(ll) /10 and 4 khz at i out(ll) /100. the low-side driver is designed to drive high-current, low-r ds(on) , n-channel mosfet(s). the drive capability is represented by its internal resistance, which are 3 ? ? for v5in to drvl and 0.9 ? for drvl to pgnd. a dead-time to prevent shoot through is internally generated between top mosfet off to bottom mosfet on, and bottom mosfet off to top mosfet on. 5-v bias voltage is delivered from v5in supply. the instantaneous drive current is supplied by an input capacitor connected between v5in and gnd. the average drive current is equal to the gate charge at v gs = 5 v times switching frequency. this gate drive current as well as the high-side gate drive current times 5 v makes the driving power which needs to be dissipated from tps51116 package. the high-side driver is designed to drive high-current, low-r ds(on) n-channel mosfet(s). when configured as a floating driver, 5-v bias voltage is delivered from v5in supply. the average drive current is also calculated by the gate charge at v gs = 5v times switching frequency. the instantaneous drive current is supplied by the flying capacitor between vbst and ll pins. the drive capability is represented by its internal resistance, which are 3 ? ? for vbst to drvh and 0.9 ? for drvh to ll. in order to provide both good accuracy and cost effective solution, tps51116 supports both of external resistor sensing and mosfet r ds(on) sensing. for resistor sensing scheme, an appropriate current sensing resistor should be connected between the source terminal of the bottom mosfet and pgnd. cs pin is connected to the mosfet source terminal node. the inductor current is monitored by the voltage between pgnd pin and cs pin. for r ds(on) sensing scheme, cs pin should be connected to v5in (pwp), or v5filt (rge) through the trip voltage setting resistor, r trip . in this scheme, cs terminal sinks 10- m a i trip current and the trip level is set to the voltage across the r trip . the inductor current is monitored by the voltage between pgnd pin and ll pin so that ll pin should be connected to the drain terminal of the bottom mosfet. i trip has 4500ppm/ c temperature slope to compensate the temperature dependency of the r ds(on) . in either scheme, pgnd is used as the positive current sensing node so that pgnd should be connected to the proper current sensing device, i.e. the sense resistor or the source terminal of the bottom mosfet. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 13 product folder link(s): tps51116 i out(ll) 1 2 l f (v in v out ) v out v in
pwm frequency and adaptive on-time control vddq output voltage selection vtt linear regulator and vttref outputs management by s3, s5 control tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com tps51116 employs adaptive on-time control scheme and does not have a dedicated oscillator on board. however, the device runs with fixed 400-khz pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. the on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio is kept as v out /v in technically with the same cycle time. although the tps51116 does not have a pin connected to vin, the input voltage is monitored at ll pin during the on state. this helps pin count reduction to make the part compact without sacrificing its performance. in order to secure minimum on-time during startup, feed-forward from the output voltage is enabled after the output becomes 750 mv or larger. tps51116 can be used for both of ddr (v vddq = 2.5 v) and ddr2 (v vddq = 1.8 v) power supply and adjustable output voltage (0.75 v < v vddq < 3 v) by connecting vddqset pin as shown in table 1 . use adjustable output voltage scheme for ddr3 application. table 1. vddqset and output voltages vddqset vddq (v) vttref and vtt note gnd 2.5 v vddqsns /2 ddr v5in 1.8 v vddqsns /2 ddr2 fb resistors 1.5 v vddqsns /2 ddr3 r up = r down =75 k ? fb resistors adjustable v vddqsns /2 0.75 v < v vddq < 3 v (1) tps51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking current up to 3 a. this vtt linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to keep tracking the vttref within 40 mv at all conditions including fast load transient. to achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, vttsns, should be connected to the positive node of vtt output capacitor(s) as a separate trace from vtt pin. for stable operation, total capacitance of the vtt output terminal can be equal to or greater than 20 m f. it is recommended to attach two 10- m f ceramic capacitors in parallel to minimize the effect of esr and esl. if esr of the output capacitor is greater than 2 m , insert an rc filter between the output and the vttsns input to achieve loop stability. the rc filter time constant should be almost the same or slightly lower than the time constant made by the output capacitor and its esr. vttref block consists of on-chip 1/2 divider, lpf and buffer. this regulator also has sink and source capability up to 10 ma. bypass vttref to gnd by a 0.033- m f ceramic capacitor for stable operation. in the ddr/ddr2/ddr3 memory applications, it is important to keep vddq always higher than vtt/vttref including both start-up and shutdown. tps51116 provides this management by simply connecting both s3 and s5 terminals to the sleep-mode signals such as slp_s3 and slp_s5 in the notebook pc system. all of vddq, vttref and vtt are turned on at s0 state (s3 = s5 = high). in s3 state (s3 = low, s5 = high), vddq and vttref voltages are kept on while vtt is turned off and left at high impedance (high-z) state. the vtt output is floated and does not sink or source current in this state. in s4/s5 states (s3 = s5 = low), all of the three outputs are disabled. outputs are discharged to ground according to the discharge mode selected by mode pin (see vddq and vtt discharge control section). each state code represents as follow; s0 = full on, s3 = suspend to ram (str), s4 = suspend to disk (std), s5 = soft off. (see table 2 ) table 2. s3 and s5 control state s3 s5 vddq vttref vtt s0 hi hi on on on s3 lo hi on on off (hi-z) s4/s5 lo lo off (discharge) off (discharge) off (discharge) (1) v vddq 1.2 v when used as vldoin. 14 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
soft-start and powergood (2) (3) tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 the soft start function of the smps is achieved by ramping up reference voltage and two-stage current clamp. at the starting point, the reference voltage is set to 650 mv (87% of its target value) and the overcurrent threshold is set half of the nominal value. when uvp comparator detects vddq become greater than 80% of the target, the reference voltage is raised toward 750 mv using internal 4-bit dac. this takes approximately 85 m s. the overcurrent threshold is released to nominal value at the end of this period. the powergood signal waits another 45 m s after the reference voltage reaches 750 mv and the vddq voltage becomes good (above 95% of the target voltage), then turns off powergood open-drain mosfet. the soft-start function of the vtt ldo is achieved by current clamp. the current limit threshold is also changed in two stages using an internal powergood signal dedicated for ldo. during vtt is below the powergood threshold, the current limit level is cut into 60% (2.2 a).this allows the output capacitors to be charged with low and constant current that gives linear ramp up of the output. when the output comes up to the good state, the overcurrent limit level is released to normal value (3.8 a). tps51116 has an independent counter for each output, but the pgood signal indicates only the status of vddq and does not indicate vtt powergood externally. see figure 1 . figure 1. vddq soft-start and powergood timing soft-start duration, t vddqss , t vttss are functions of output capacitances. where i vddqocp is the current limit value for vddq switcher calculated by equation 5 . where, i vttocl = 2.2 a (typ). in each of the two previous calculations, no load current during start-up are assumed. note that both switchers and the ldo do not start up with full load condition. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 15 product folder link(s): tps51116 t vttss c vtt v vtt i vttocl t vddqss 2 c vddq v vddq 0.8 i vddqocp 85 s v ocl v vddq v pgood v s5 80% 87% 100% 85 m s 45 m s udg?04066
vddq and vtt discharge control current protection for vddq (4) (5) current protection for vtt tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com tps51116 discharges vddq, vttref and vtt outputs during s3 and s5 are both low. there are two different discharge modes. the discharge mode can be set by connecting mode pin as shown in table 3 . table 3. discharge selection mode discharge mode v5in no discharge vddq tracking discharge gnd non-tracking discharge when in tracking-discharge mode, tps51116 discharges outputs through the internal vtt regulator transistors and vtt output tracks half of vddq voltage during this discharge. note that vddq discharge current flows via vldoin to ldognd thus vldoin must be connected to vddq output in this mode. the internal ldo can handle up to 3 a and discharge quickly. after vddq is discharged down to 0.2 v, the internal ldo is turned off and the operation mode is changed to the non-tracking-discharge mode. when in non-tracking-discharge mode, tps51116 discharges outputs using internal mosfets which are connected to vddqsns and vtt. the current capability of these mosfets are limited to discharge slowly. note that vddq discharge current flows from vddqsns to pgnd in this mode. in case of no discharge mode, tps51116 does not discharge output charge at all. the smps has cycle-by-cycle overcurrent limiting control. the inductor current is monitored during the off state and the controller keeps the off state during the inductor current is larger than the overcurrent trip level. the trip level and current sense scheme are determined by cs pin connection (see current sensing scheme section). for resistor sensing scheme, the trip level, v trip , is fixed value of 60 mv. for r ds(on) sensing scheme, cs terminal sinks 10 m a and the trip level is set to the voltage across this r trip resistor. as the comparison is done during the off state, v trip sets valley level of the inductor current. thus, the load current at overcurrent threshold, i ocp , can be calculated as shown in equation 5 . in an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. if the output voltage becomes less than powergood level, the v trip is cut into half and the output voltage tends to be even lower. eventually, it crosses the undervoltage protection threshold and shutdown. the ldo has an internally fixed constant overcurrent limiting of 3.8 a while operating at normal condition. this trip point is reduced to 2.2 a before the output voltage comes within 5% of the target voltage or goes outside of 10% of the target voltage. 16 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116 i ocp v trip r ds(on) i ripple 2 v trip r ds(on) 1 2 l f v in v out v out v in v trip (mv) r trip (k ) 10 ( a)
overvoltage and undervoltage protection for vddq v5in (pwp), v5filt (rge) undervoltage lockout (uvlo) protection v5in (pwp), v5filt (rge) input capacitor thermal shutdown tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 tps51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. if vddqset is connected to v5in or gnd, the feedback voltage is made by an internal resistor divider inside vddqsns pin. if an external resistor divider is connected to vddqset pin, the feedback voltage is vddqset voltage itself. when the feedback voltage becomes higher than 115% of the target voltage, the ovp comparator output goes high and the circuit latches as the top mosfet driver off and the bottom mosfet driver on. also, tps51116 monitors vddqsns voltage directly and if it becomes greater than 4 v tps51116 turns off the top mosfet driver. when the feedback voltage becomes lower than 70% of the target voltage, the uvp comparator output goes high and an internal uvp delay counter begins counting. after 32 cycles, tps51116 latches off both top and bottom mosfets. this function is enabled after 1007 cycles of smps operation to ensure startup. tps51116 has 5-v supply undervoltage lockout protection (uvlo). when the v5in (pwp) voltage or v5filt (rge) voltage is lower than uvlo threshold voltage, smps, vttldo and vttref are shut off. this is a non-latch protection. add a ceramic capacitor with a value between 1.0 m f and 4.7 m f placed close to the v5in (pwp) pin or v5filt (rge) pin to stabilize 5 v from any parasitic impedance from the supply. tps51116 monitors the temperature of itself. if the temperature exceeds the threshold value, 160 c (typ), smps, vttldo and vttref are shut off. this is a non-latch protection and the operation is resumed when the device is cooled down by about 10 c. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 17 product folder link(s): tps51116
application information loop compensation and external parts selection current mode operation (6) (7) (8) (9) tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com a buck converter using tps51116 current mode operation can be partitioned into three portions, a voltage divider, an error amplifier and a switching modulator. by linearizing the switching modulator, we can derive the transfer function of the whole system. since current mode scheme directly controls the inductor current, the modulator can be linearized as shown in figure 2 . figure 2. linearizing the modulator here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal model. as a result, a modulated current source including the power inductor can be modeled as a current source with its transconductance of 1/r s and the output capacitor represent the modulator portion. this simplified model is applicable in the frequency space up to approximately a half of the switching frequency. one note is, although the inductance has no influence to small signal model, it has influence to the large signal model as it limits slew rate of the current source. this means the buck converter ? s load transient response, one of the large signal behaviors, can be improved by using smaller inductance without affecting the loop stability. total open loop transfer function of the whole system is given by equation 6 . assuming rl>>esr, r o >>r c and c c >>c c2 , each transfer function of the three blocks is shown starting with equation 7 . there are three poles and two zeros in h(s). each pole and zero is given by the following five equations. 18 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116 h 3 (s) (1 s c o esr) 1 s c o rl rl r s h(s) h 1 (s) h 2 (s) h 3 (s) h 2 (s) gm r o 1 s c c r c 1 s c c r o 1 s c c2 r c h 1 (s) r2 ( r2 r1 )
(10) (11) (12) (13) (14) (15) (16) (17) (18) (19) tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 usually, each frequency of those poles and zeros is lower than the 0 db frequency, f 0 . however, the f 0 should be kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. the f 0 is given by equation 15 . based on small signal analysis above, the external components can be selected by following manner. 1. choose the inductor. the inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. the inductor also needs to have low dcr to achieve good efficiency, as well as enough room above peak inductor current before saturation. the peak inductor current can be estimated as shown in equation 17 . 2. choose rectifying (bottom) mosfet. when r ds(on) sensing scheme is selected, the rectifying mosfet ? s on-resistance is used as this r s so that lower r ds(on) does not always promise better performance. in order to clearly detect inductor current, minimum r s recommended is to give 15 mv or larger ripple voltage with the inductor ripple current. this promises smooth transition from ccm to dcm or vice versa. upper side of the r ds(on) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency more at high-load conditions. when using external resistor current sensing, there is no restriction for low r ds(on) . however, the current sensing resistance r s itself affects the efficiency 3. choose output capacitor(s). in cases of organic semiconductor capacitors (os-con) or specialty polymer capacitors (sp-cap), esr to achieve required ripple value at stable state or transient load conditions determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. the peak-to-peak ripple value can be estimated by esr times the inductor ripple current for stable state, or esr times the load current step for a fast transient load response. in case of ceramic capacitor(s), usually esr is small enough to meet ripple requirement. on the other hand, transient undershoot and overshoot driven by output capacitance becomes the key factor to determine the capacitor(s). 4. determine f 0 and calculate r c using equation 18 . note that higher r c shows faster transient response in cost of unstableness. if the transient response is not enough even with high r c value, try increasing the out put capacitance. recommended f 0 is f osc /4. then r c can be derived by equation 19 . 5. calculate c c2 . purpose of this capacitance is to cancel zero caused by esr of the output capacitor. in case copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 19 product folder link(s): tps51116 i ind(peak) v trip r ds(on) 1 l f v in(max) v out v out v in(max) f 0 1 2 r1 r1 r2 gm c o r c r s 1 2 0.75 v out gm c o r c r s p1 1 c c r o z1 1 c c r c l 1 i ind(ripple) f v in(max) v out v out v in(max) 2 i out(max) f v in(max) v out v out v in(max) r c 2.8 v out c o [ f] r s [m ] r c 2 f 0 v out 0.75 c o gm r s p2 1 c o rl p3 1 c c2 r c z2 1 c o esr
(20) (21) (22) (23) d-cap? mode operation (24) tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com of ceramic capacitor(s) is used, no need for c c2 . 6. calculate c c . the purpose of c c is to cut dc component to obtain high dc feedback gain. however, as it causes phase delay, another zero to cancel this effect at f 0 frequency is need. this zero, w z1, is determined by cc and rc. recommended w z1 is 10 times lower to the f 0 frequency. 7. when using adjustable mode, determine the value of r1 and r2. . a buck converter system using d-cap? mode can be simplified as below. figure 3. linearizing the modulator the vddqsns voltage is compare with internal reference voltage after divider resistors. the pwm comparator determines the timing to turn on top mosfet. the gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. the dc output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. for the loop stability, the 0-db frequency, f 0 , defined below need to be lower than 1/3 of the switching frequency. as f 0 is determined solely by the output capacitor ? s characteristics, loop stability of d-cap? mode is determined by the capacitor ? s chemistry. for example, specialty polymer capacitors (sp-cap) have c o in the order of several 100 m f and esr in range of 10 m ? . these makes f 0 in the order of 100 khz or less and the loop is then stable. however, ceramic capacitors have f 0 at more than 700 khz, which is not suitable for this operational mode. although d-cap? mode provides many advantages such as ease-of-use, minimum external components configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient amount of feedback signal needs to be provided by external circuit to reduce jitter level. the required signal level is approximately 15 mv at comparing point. this gives v ripple = (v out /0.75) x 15 (mv) at the output node. the output capacitor ? s esr should meet this requirement. 20 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116 z2 1 c o esr p3 1 c c2 r c r1 v out 0.75 0.75 r2 c c2 c o esr r c f 0 1 2 esr c o f sw 3 f z1 1 2 c c r c f 0 10
(25) thermal design (26) (27) (28) tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 the external components selection is much simple in d-cap? mode. 1. choose inductor. this section is the same as the current mode. please refer to the instructions in the current mode operation section. 2. choose output capacitor(s).organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. determine esr to meet required ripple voltage above. a quick approximation is shown in equation 25 . primary power dissipation of tps51116 is generated from vtt regulator. vtt current flow in both source and sink directions generate power dissipation from the part. in the source phase, potential difference between vldoin and vtt times vtt current becomes the power dissipation, w dsrc . in this case, if vldoin is connected to an alternative power supply lower than vddq voltage, power loss can be decreased. for the sink phase, vtt voltage is applied across the internal ldo regulator, and the power dissipation, w dsnk , is calculated by equation 27 : since this device does not sink and source the current at the same time and i vtt varies rapidly with time, actual power dissipation need to be considered for thermal design is an average of above value. another power consumption is the current used for internal control circuitry from v5in supply and vldoin supply. v5in supports both the internal circuit and external mosfets drive current. the former current is in the vldoin supply can be estimated as 1.5 ma or less at normal operational conditions. these powers need to be effectively dissipated from the package. maximum power dissipation allowed to the package is calculated by equation 28 , where t j(max) is 125 c t a(max) is the maximum ambient temperature in the system q ja is the thermal resistance from the silicon junction to the ambient copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 21 product folder link(s): tps51116 esr v out 0.015 i ripple 0.75 v out i out(max) 60 [m ] w dsnk v vtt i vtt w dsrc v vldoin v vtt i vtt w pkg t j(max) t a(max) ja
layout considerations tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com this thermal resistance strongly depends on the board layout. tps51116 is assembled in a thermally enhanced powerpad? package that has exposed die pad underneath the body. for improved thermal performance, this die pad needs to be attached to ground trace via thermal land on the pcb. this ground trace acts as a heat sink/spread. the typical thermal resistance, 39.6 c/w, is achieved based on a 6.5 mm 3.4 mm thermal land with eight vias without air flow. it can be improved by using larger thermal land and/or increasing vias number. further information about powerpad? and its recommended board layout is described in (slma002). this document is available at http:\\www.ti.com. certain points must be considered before designing a layout using the tps51116. pcb trace defined as ll node, which connects to source of switching mosfet, drain of rectifying mosfet and high-voltage side of the inductor, should be as short and wide as possible. consider adding a small snubber circuit, consists of 3 ? and 1 nf, between ll and pgnd in case a high-frequency surge is observed on the ll voltage waveform. all sensitive analog traces such as vddqsns, vttsns and cs should placed away from high-voltage switching nodes such as ll, drvl or drvh nodes to avoid coupling. vldoin should be connected to vddq output with short and wide trace. if different power source is used for vldoin, an input bypass capacitor should be placed to the pin as close as possible with short and wide connection. the output capacitor for vtt should be placed close to the pin with short and wide connection in order to avoid additional esr and/or esl of the trace. vttsns should be connected to the positive node of vtt output capacitor(s) as a separate trace from the high current power line and is strongly recommended to avoid additional esr and/or esl. if it is needed to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point. also, it is recommended to minimize any additional esr and/or esl of ground trace between gnd pin and the output capacitor(s). consider adding lpf at vttsns in case esr of the vtt output capacitor(s) is larger than 2 m ? . vddqsns can be connected separately from vldoin. remember that this sensing potential is the reference voltage of vttref. avoid any noise generative lines. negative node of vtt output capacitor(s) and vttref capacitor should be tied together by avoiding common impedance to the high current path of the vtt source/sink current. gnd (signal gnd) pin node represents the reference potential for vttref and vtt outputs. connect gnd to negative nodes of vtt capacitor(s), vttref capacitor and vddq capacitor(s) with care to avoid additional esr and/or esl. gnd and pgnd (power ground) should be connected together at a single point. connect cs_gnd (rge) to source of rectifying mosfet using kevin connection. avoid common trace for high-current paths such as the mosfet to the output capacitors or the pgnd to the mosfet trace. in case of using external current sense resistor, apply the same care and connect it to the positive side (ground side) of the resistor. pgnd is the return path for rectifying mosfet gate drive. use 0.65 mm (25mil) or wider trace. connect to source of rectifying mosfet with shortest possible path. place a v5filt filter capacitor (rge) close to the tps51116, within 12 mm (0.5 inches) if possible. the trace from the cs pin should avoid high-voltage switching nodes such as those for ll, vbst, drvh, drvl or pgood. in order to effectively remove heat from the package, prepare thermal land and solder to the package ? s thermal pad. wide trace of the component-side copper, connected to this thermal land, helps heat spreading. numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground plane(s) should be used to help dissipation. do not connect pgnd to this thermal land underneath the package. 22 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 figure 4. d-cap? mode, pwp package figure 5. d-cap? mode, rge package table 4. d-cap? mode schematic components symbol specification manufacturer part number r1 5.1 k ? - r2 100 k ? - r3 75 k ? - r4 (100 v vddq ? 75) k ? - r5 5.1 ? m1 30 v, 13 m ? international rectifier irf7821 m2 30 v, 5 m ? international rectifier irf7832 copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 23 product folder link(s): tps51116
tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com figure 6. current mode, pwp package figure 7. current mode, rge package table 5. current mode schematic components symbol specification manufacturer part number r1 6 m ? , 1% vishay wsl-2521 0.006 r2 100 k ? - - r5 5.1 ? m0 30 v, 13 m ? international rectifier irf7821 m1 30 v, 5 m ? international rectifier irf7832 24 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116
typical characteristics tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 all data in the following graphs are measured from the pwp packaged device. v5in supply current v5in shutdown current vs vs junction temperature junction temperature figure 8. figure 9. v5in supply current vldoin supply current vs vs load current temperature figure 10. figure 11. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 25 product folder link(s): tps51116 t j ? junction t emperature ? c i vldoin ? vldoin supply current ? m a 0 ?50 0 50 100 150 1.00.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 t j ? junction t emperature ? c i v5in1 ? v5in shutdown current ? m a 0 ?50 0 50 100 150 1.00.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ?50 2.0 0 0 1.81.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 50 100 150 t j ? junction t emperature ? c i v5in1 ? v5in supply current ? ma i vtt ? vtt current ? a i v5in ? v5in supply current ? ma ?2 30 ?1 0 1 2 1 2 74 5 6 10 8 9 ddr2 v vtt = 0.9 v
tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com typical characteristics (continued) cs current vddq discharge current vs vs junction temperature junction temperature figure 12. figure 13. vtt discharge current overvoltage and undervoltage threshold vs vs junction temperature junction temperature figure 14. figure 15. 26 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116 t j ? junction t emperature ? c i disch ? vtt discharge current ? ma 1510 2520 30 ?50 0 50 100 150 t j ? junction t emperature ? c i trip ? cs current ? m a 20 ?50 0 50 100 150 6 84 10 14 1612 pgood = hi pgood = lo t j ? junction t emperature ? c i disch ? vddq discharge current ? ma 30 40 50 70 8060 20 10 ?50 0 50 100 150 t j ? junction t emperature ? c v trip ? ovp/uvp t rip threshold ? % 60 ?50 0 50 100 150 80 120100 140 v uvp v ovp
tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 typical characteristics (continued) switching frequency switching frequency vs vs input voltage output current figure 16. figure 17. vddq output voltage vddq output voltage vs vs output current (ddr) input voltage (ddr2) figure 18. figure 19. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 27 product folder link(s): tps51116 4 8 12 16 20 24 30 1.785 1.795 1.8001.790 1.815 1.8201.810 1.805 1.780 v in ? input v oltage ? v v vddq ? vddq output v oltage ? v d?cap ? mode i vddq = 0 a i vddq = 10 a v in ? input v oltage ? v f sw ? switching frequency ? khz ddr2 4 390370 8 12 16 20 24 28 380 420400 410 430 d-cap ? mode i vddq = 7 a ddr 0 2 1.785 1.795 1.8001.790 1.815 1.8201.810 1.805 1.780 4 6 8 10 i vddq ? vddq output current ? a v vddq ? vddq output v oltage ? v d?cap ? mode v in = 12 v 0 0 2 4 6 8 10 100 150 50 300 400 450350 250 200 i vddq ? vddq output current ? a f sw ? switching frequency ? khz ddr2 d?cap ? mode v in = 12 v ddr
tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com typical characteristics (continued) vtt output voltage vtt output voltage vs vs output current (ddr) output current (ddr2) figure 20. figure 21. vttref output voltage vttref output voltage vs vs output current (ddr) output current (ddr2) figure 22. figure 23. 28 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116 i vttref ? vttref current ? ma v vttref ? vttref v oltage ? v ?10 ?5 0 5 10 0.8970.896 0.898 0.899 0.900 0.901 0.902 0.903 0.904 ddr2 ?10 1.2451.244 ?5 0 5 10 1.246 1.247 1.248 1.249 1.250 1.251 1.252 i vttref ? vttref current ? ma v vttref ? vttref v oltage ? v ddr i vtt ? vtt output current ? a v vtt ? vtt output v oltage ? v ?5 1.221.20 ?4 ?3 ?2 ?1 0 1 2 3 4 5 1.21 1.251.23 1.24 1.281.26 1.27 1.29 1.30 v vldoin = 2.5 v v vldoin = 1.8 v i vtt ? vtt output current ? a v vtt ? vtt output v oltage ? v ?3 0.880.86 ?2 ?1 0 1 2 3 0.87 0.910.89 0.90 0.940.92 0.93 v vldoin = 1.5 v v vldoin = 1.2 v v vldoin = 1.8 v
tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 typical characteristics (continued) vttref output voltage vtt output voltage vs vs output current (ddr3) output current (ddr3) figure 24. figure 25. vddq efficiency (ddr) vddq efficiency (ddr2) vs vs vddq current vddq current figure 26. figure 27. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 29 product folder link(s): tps51116 -3 0.73 0.71 -2 0.74 0.72 0.77 0.75 0.78 0.76 0.79 v vldoin = 1.5 v -1 0 i vtt - vtt output current - a 1 2 3 i vtt - vtt output voltage - v 0.001 6050 0.01 0.1 1 10 8070 100 90 i vddq ? vddq current ? a efficiency ? % v vddq = 2.5 v v in = 8 v v in = 20 v v in = 12 v 0.001 6050 0.01 0.1 1 10 8070 100 90 v vddq = 1.8 v v in = 8 v v in = 20 v v in = 12 v i vddq ? vddq current ? a efficiency ? % -10 0.735 -5 0 5 10 i vttref - vttref current - ma 0.74 0.745 0.75 0.755 0.76 0.765 i vtt - vtt output voltage - v ddr3
tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com typical characteristics (continued) figure 28. ripple waveforms - heavy load condition figure 29. vddq load transient response figure 30. vtt load transient response figure 31. vddq, vtt, and vttref start-up waveforms 30 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116 t ? t ime ? 100 m s/div vddq vttref pgood s5 i vddq = i vttref = 0 a t ? t ime ? 20 m s/div v vddq (50 mv/div) v vtt (20 mv/div) v vttref (20 mv/div) i vtt (2 a/div) t ? t ime ? 20 m s/div v vddq (50 mv/div) i vddq (5 a/div) i ind (5 a/div) t ? t ime ? 2 m s/div v vddq (50 mv/div) i vddq (2 a/div) v vttref (10 mv/div) v vtt (10 mv/div)
tps51116 www.ti.com ................................................................................................................................................................ slus609h ? may 2004 ? revised july 2009 typical characteristics (continued) figure 32. soft-start waveforms tracking discharge figure 33. soft-stop waveforms non-tracking discharge vddq bode plot (current mode) vtt bode plot, source (ddr2) gain and phase gain and phase vs vs frequency frequency figure 34. figure 35. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 31 product folder link(s): tps51116 100 ?40?80 1 k 100 k 1 m ?60 20 ?20 0 8040 60 ?90 45?45 0 18090 135?180 ?135 f ? frequency ? hz gain ? db phase ? phase gain i vddq = 7 a 10 k t ? t ime ? 1 ms/div vddq vttref vtt s5 i vddq = i vtt = i vttref = 0 a gain ? db phase ? 10 k ?40?80 100 k 1 m 10 m ?60 20 ?20 0 8040 60 ?90 45?45 0 18090 135?180 ?135 phase gain f ? frequency ? hz i vtt = ?1 a t ? t ime ? 200 m s/div vddq vttref vtt s5 i vddq = i vtt = i vttref = 0 a
tps51116 slus609h ? may 2004 ? revised july 2009 ................................................................................................................................................................ www.ti.com typical characteristics (continued) vtt bode plot, sink (ddr2) gain and phase vs frequency figure 36. 32 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder link(s): tps51116 10 k ?40?80 100 k 1 m 10 m ?60 20 ?20 0 8040 60 ?90 45?45 0 18090 135?180 ?135 f ? frequency ? hz gain ? db phase gain i vtt = 1 a phase ?
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tps51116pwp active htssop pwp 20 70 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tps51116pwpg4 active htssop pwp 20 70 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tps51116pwpr active htssop pwp 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tps51116pwprg4 active htssop pwp 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TPS51116RGER active vqfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TPS51116RGERg4 active vqfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tps51116rget active vqfn rge 24 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tps51116rgetg4 active vqfn rge 24 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 16-jul-2009 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps51116pwpr htssop pwp 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 TPS51116RGER vqfn rge 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 TPS51116RGER vqfn rge 24 3000 330.0 12.4 4.3 4.3 1.1 8.0 12.0 q2 tps51116rget vqfn rge 24 250 180.0 12.4 4.3 4.3 1.1 8.0 12.0 q2 package materials information www.ti.com 18-may-2011 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps51116pwpr htssop pwp 20 2000 346.0 346.0 33.0 TPS51116RGER vqfn rge 24 3000 346.0 346.0 29.0 TPS51116RGER vqfn rge 24 3000 370.0 355.0 55.0 tps51116rget vqfn rge 24 250 195.0 200.0 45.0 package materials information www.ti.com 18-may-2011 pack materials-page 2

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