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specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 62911hkpc 20110419-s00002 no.a1957-1/45 LC749870W overview the LC749870W is a digital video decoder that converts ntsc, pal and secam video signals into digital component video signals. digital video data can be outp ut easily by inputting ntsc, pal and secam video signals. the output data format is compatible with itu-r bt.656. features ? supports ntsc (m, 4.43), pal (b, d, g, h, i, m, n, 60), and secam video signal inputs. ? on-chip video switch that supports 4 video inputs ? 10-bit adc (sampling at 27mhz) ? automatic gain control (agc) function ? digital clamp circuit ? digital automatic color control (acc) circuit ? sync separation circuit ? signal-to-noise (s/n) detection capabilities ? non-standard signal detection function ? no signal detection function ? adaptive two-dimensional y/c separation circuit ? ntsc/pal/secam demodulator circuit ? clock rate conversion circuit ? picture quality improvement (sharpness, co ntrast, brightness, cti, uv gain, hue) ? 8-bit itu-r bt.656 output format itu-r bt.656 (8bit ycbcr 4:2:2 with sav/eav) 8bit ycbcr 4:2:2 with syncs ? i 2 c control (100k/400kbps, 2 types of slave address selectable) cmos ic silicon gate ntsc/pal/secam digital video decoder orderin g numbe r : ena1957
LC749870W no.a1957-2/45 ic specifications ? power supply voltage i/o: analog 3.3v, digital 1.8v or 3.3v core: analog 1.8v, digital 1.1v ? maximum operating frequency: 30mhz ? package: sqfp64 applications ? small-size monitors specifications absolute maximum ratings at ta = 25 c, dv ss = 0v, av ss = 0v parameter symbol conditions ratings unit maximum supply voltage (i/o) dv dd 33 xv dd 33 av dd 33 -0.3 to +3.95 v maximum supply voltage (core) dv dd 11 xv dd 11 -0.3 to +1.8 v digital input voltage v i -0.3 to dv dd 33+0.3 v digital output voltage v o -0.3 to dv dd 33+0.3 v operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c allowable operation ranges at ta = 25 c, dv ss = 0v, av ss = 0v parameter symbol conditions min typ max unit av dd 33 xv dd 33 3.0 3.3 3.6 v supply voltage (i/o) dv dd 33 1.7 1.8 or 3.3 3.6 v supply voltage (core) dv dd 11 xv dd 11 1.0 1.1 1.2 v input voltage range v in 0 dv dd 33 v dc characteristics at ta = -30 to +70 c, dv dd 33 = 1.7 to 3.63v, av dd 33 = 3.0 to 3.63v, dv dd 11 = 1.0 to 1.2v parameter symbol conditions min typ max unit cmos level inputs 0.7dv dd 33 v input high-level voltage v ih cmos level schmitt inputs 0.7dv dd 33 v cmos level inputs 0 0.3dv dd 33 v input low-level voltage v il cmos level schmitt inputs 0 0.3dv dd 33 v v i = v dd 10 a input high-level current i ih v i = v dd , with pull-down resistance 100 a input low-level current i il v i = v ss -10 a output high-level voltage v oh cmos (pin e/g: i oh = -4ma, f: i oh = -6ma) v dd -0.4 v output low-level voltage v ol cmos 0.4 v output leakage current i oz when in high-impedance output mode -10 10 a dv dd 11 = 1.1v, dv dd 33 = 3.3v 159 k pull-down register r dn dv dd 11 = 1.1v, dv dd 33 = 1.8v 95 k output open, tck=27mh z, natural image. ta = 25 c, dv dd 33 = 3.3v, av dd 33 = 3.3v, dv dd 11 = 1.1v 42 ma operating current drain i ddop output open, tck=27mh z, natural image. ta = 25 c, dv dd 33 = 1.8v, av dd 33 = 3.3v, dv dd 11 = 1.1v 38 ma static current drain *1 i ddst output open, v i = v ss , ta = 25 c 10 a *1: there is an input pin which builds in pull down resistance. note that there is no guarantee about static consumption current depending on circuit configuration.
LC749870W no.a1957-3/45 package dimensions unit : mm (typ) 3190a pin assignment top view 1 16 17 32 33 48 49 64 LC749870W cko dv ss gpio0 dv ss dv ss data6 data4 data7 data5 data3 data2 data1 i 2 csel data0 dv dd 11 dv dd 33 intreq dv ss dv ss dv ss dv ss md0 md2 scl md1 sda reset pdwn dv dd 11 test refpkv refnkv xin xv dd 33 xv ss ain0 av ss 33 afevrtc svo av ss 33 av dd 33 ain1 av ss 33 ain2 av dd 33 ain3 vrt vrb dv dd 33 dv dd 11 dv ss xv ss dv ss gpio3 gpio1 vs ck13 hs de gpio2 dv dd 11 field xv dd 11 xout 10.0 10.0 12.0 12.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (1.25) 116 17 32 33 48 49 64 sanyo : sqfp64(10x10)
LC749870W no.a1957-4/45 pin descriptions i/o type pin no. symbol i/o type connected to notes 1 cko o f cmos digital data synchronous clock output 2 dv ss p gnd digital 3 gpio0 i/o g cmos digital for test 4 data6 i/o g cmos digital video signal output 5 data4 i/o g cmos digital video signal output 6 data7 i/o g cmos digital video signal output (msb) 7 dv ss p gnd digital 8 data5 i/o g cmos digital video signal output 9 data3 i/o g cmos digital video signal output 10 data2 i/o g cmos digital video signal output 11 data1 i/o g cmos digital video signal output 12 i 2 csel i c cmos digital i 2 c slave select l = 0x88, h = 0x8a 13 data0 i/o g cmos digital video signal output (lsb) 14 dv ss p gnd digital 15 dv dd 11 p core voltage digital 16 dv dd 33 p i/o voltage digital 17 intreq o e cmos digital interrupt (?h? active) 18 dv ss p gnd digital 19 md0 i d cmos digital for test (connect to gnd) 20 dv ss p gnd digital 21 md2 i d cmos digital for test (connect to gnd) 22 scl i d cmos digital i 2 c clock 23 md1 i d cmos digital for test (connect to gnd) 24 sda i/o g cmos digital i 2 c data input/output 25 reset i b cmos digital system reset (?l? active) 26 pdwn i b cmos digital power down control 27 dv dd 11 p core voltage digital 28 test i c cmos digital for test (connect to gnd) 29 dv ss p gnd digital 30 dv ss p gnd digital 31 refpkv i a analog adc top reference buffer-amp input 32 refnkv i a analog adc bottom reference buffer-amp input 33 vrt i a analog adc top reference voltage input 34 vrb i a analog adc bottom reference voltage input 35 av ss 33 p gnd analog 36 ain3 i a analog video signal input (cvbs) 37 av dd 33 p analog voltage analog 38 ain2 i a analog video signal input (cvbs) 39 av ss 33 p gnd analog 40 ain1 i a analog video signal input (cvbs) 41 av dd 33 p analog voltage analog 42 ain0 i a analog video signal input (cvbs) 43 av ss 33 p gnd analog 44 svo o a analog afe svo output 45 afevrtc i a analog adc d-range control voltage external input 46 xv ss p gnd digital 47 xv dd 33 p i/o voltage digital 48 xin i h cmos digital x?tal input 49 xout o h cmos digital x?tal output 50 xv dd 11 p core voltage digital continued on next page.
LC749870W no.a1957-5/45 continued from preceding page. i/o type pin no. pin symbol i/o type connected to notes 51 xv ss p gnd digital 52 dv ss p gnd digital 53 field i/o g cmos digital field signal 54 dv dd 11 p core voltage digital 55 gpio2 i/o g cmos digital for test 56 de i/o g cmos digital data enable signal 57 hs i/o g cmos digital horizontal sync signal 58 ck13 o f cmos digital clock output (13.5mhz) 59 vs i/o g cmos digital vertical sync signal 60 gpio1 i/o g cmos digital for test 61 dv ss p gnd digital 62 gpio3 i/o g cmos digital for test 63 dv dd 11 p core voltage digital 64 dv dd 33 p i/o voltage digital
LC749870W no.a1957-6/45 pin circuits i/o type function equivalent circuit applicable pins a analog input/output ain0, ain1, ain2, ain3, vrt, vrb, refpkv, refnkv, svo, afevrtc b schmitt trigger cmos input pdwn, reset c cmos input with built-in pull-down resistor i 2 csel, test d cmos input scl, md0, md1, md2 e 2ma/4ma switching 3-state drive cmos output intreq f 4ma/8ma switching 3-state drive cmos output cko, ck13 g 2ma/4ma switching 3-state drive cmos input/output sda, gpio0, gpio1, gpio2, gpio3, data0, data1, data2, data3, data4, data5, data6, data7, field, de, vs, hs h oscillator xin, xout
LC749870W no.a1957-7/45 pin connection 1) adc and its peripherals 2) unused pin handling (please be sure to perform except input open processing) ain0 to ain3: open pdwn: pull up test, md0, md1, md2: pull down reset: must always be configured for input. gpio0 to gpio3: open data0 to data7: open field, de, vs, hs: open cko, ck13: open intreq: open svo: open 0.1
LC749870W no.a1957-8/45 block diagram cko ck13 data[7:0] hs v s de field intreq xin reset ain0 ain1 ain2 ain3 test pdwn sda afe + adc 1ch scl i 2 csel data interpola- tion lpf apc digital clamp sync separa- tion agc timing gen sram sram sram nt/pal demo- dulation secam demo- dulation 2d y/c separat- ion mux clock rate conversion sharpness contrast brightness output formatter cti hue uv gain lc749870 i 2 c
LC749870W no.a1957-9/45 input/output timing 1) input clock timing pin name parameter symbol min typ max unit clock cycle t ck 37 ns xin duty 50 % 2) output data timing pin name parameter symbol min typ max unit clock cycle t ck 37 ns cko duty 50 % output data delay time (dv dd 33 = 2.6 to 3.6v) pins e,g: 4ma setting pin f: 8ma setting t ac -3 3 ns output data delay time (dv dd 33 = 2.6 to 3.6v) pins e,g: 2ma setting pin f: 4ma setting t ac -3 6 ns output data delay time (dv dd 33 = 1.7 to 1.9v) pins e,g: 4ma setting pin f: 8ma setting t ac -5 4 ns data*, hs,vs,de,field, intreq output data delay time (dv dd 33 = 1.7 to 1.9v) pins e,g: 2ma setting pin f: 4ma setting t ac -6 9 ns t lo t ck t ac cko output data dv dd 33/2 dv dd 33/2 t ho dv dd 33/2 xin t ck t hi t li
LC749870W no.a1957-10/45 register specifications bank0 (afe + adc) re gister specification sub- address bit name bit- size function name functions initial value 7 i2c_bgrpwdb 1 band gap reference power down control 0: power down 1: normal operation 0 h 6 i2c_svopwdb 1 afe svo amp power down control 0: svo amp circuit off 1: svo amp circuit on 0 h 5 i2c_ selfclppwdb 1 afe self clamp circuit power down control 0: self clamp off 1: self clamp on 0 h 4 i2c_afepwdb 1 afe power down control 0: afe power down 1: afe normal operation 0 h 3 1 2 amp circuit and 2 amp bias circuit power down control 0: power down 1: normal operation 0 h 2 1 reference voltage generation circuit 1 power down control 0: power down 1: normal operation 0 h 1 1 reference voltage generation circuit 2 power down control 0: power down 1: normal operation 0 h 00 h 0 i2c_adcpwdb 1 clock generation circuit power down control 0: power down 1: normal operation 0 h 7 i2c_lpfpwdb 1 power down control lpf buffer circuit power down control 0: power down 1: normal operation 0 h 6:5 i2c_ainsel 2 input switch control afe 4-input selector control signal (when in normal operation) 00: ain0 01: ain1 10: ain2 11: ain3 0 h 4 i2c_clplpfon 1 lpf enable control lpf enable control of afe self clamp circuit 0: lpf off 1: lpf on 0 h 3:2 - 2 for test for test normally set to 0 h 0 h 01 h 1:0 - 2 for test for test normally set to 0 h 0 h 7 i2c_scarton 1 agc mode control afe d-range control voltage external input select control 0: agc mode 1: non-agc mode 0 h 6 - 1 for test for test normally set to 0 h 0 h 02 h 5:0 - 6 for test for test normally set to 00 h 00 h 7 - 1 for test for test normally set to 0 h 0 h 3:1 - 3 for test for test normally set to 0 h 0 h 03 h 0 - 1 for test for test normally set to 0 h 0 h 5:4 - 2 for test for test normally set to 0 h 0 h 3 - 1 for test for test normally set to 1 h 0 h 04 h 2:0 - 3 for test for test normally set to 4 h 0 h 7 1 for test normally set to 0 h 0 h 6 1 for test normally set to 0 h 0 h 5 1 for test normally set to 0 h 0 h 4 1 reserved 0 h 3 1 reserved 0 h 2 1 reserved 0 h 1 1 reserved 0 h 05 h 0 - 1 for test for test normally set to 0 h 0 h continued on next page.
LC749870W no.a1957-11/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 7 1 for test normally set to 0 h 0 h 6 1 for test normally set to 0 h 0 h 5 1 for test normally set to 0 h 0 h 4 1 for test normally set to 0 h 0 h 3 1 for test normally set to 0 h 0 h 2 1 for test normally set to 0 h 0 h 1 1 for test normally set to 0 h 0 h 06 h 0 1 for test normally set to 0 h 0 h 7 1 for test normally set to 0 h 0 h 6 1 for test normally set to 0 h 0 h 5 1 for test normally set to 0 h 0 h 4 1 for test normally set to 0 h 0 h 3 1 for test normally set to 0 h 0 h 2 1 for test normally set to 0 h 0 h 1 1 for test normally set to 0 h 0 h 07 h 0 - 1 for test for test normally set to 0 h 0 h 1 i2c_iosel2 1 clock output current drive capability clock output current drive capability switching 0: 4ma 1: 8ma 0 h 08 h 0 i2c_iosel1 1 signal output current drive capability signal output current drive capability switching 0: 2ma 1: 4ma 0 h 09 h to 0f h - - - - - - 7 i2c_srst 1 soft reset software reset of digital video signal processing block 0: reset on 1: reset off 0 h 10 h 0 - 1 for test for test normally set to 0 h 0 h 7:6 - 2 for test for test normally set to 0 h 0 h 11 h 1:0 - 2 for test for test normally set to 0 h 0 h 12 h 0 i2c_ckinv 1 clock output invert clock output (cko) invert control 0: normal 1: invert 0 h 6:4 - 3 for test normally set to 0 h 0 h 13 h 2:0 - 3 for test normally set to 0 h 0 h 14 h 7:0 - 8 for test normally set to 0 h 00 h 15 h 7:0 - 8 for test normally set to 0 h 00 h 16 h 7:0 - 8 for test for test normally set to 0 h 00 h
LC749870W no.a1957-12/45 bank1 (digital video signal processing block 1) register specifications sub- address bit name bit- size function name functions initial value 5:4 - 2 for test for test normally set to 0 h 0 h 00 h 0 - 1 for test for test normally set to 0 h 0 h 7:6 i2a_accon 2 acc control acc on/off switching 00: off 01: on 1x: amplifier fixed 1 h 5:4 i2a_accframe 2 number of update frames number of update frame select 00: 1 frame 01: 2 frames 10: 4 frames 11: 8 frames 0 h 01 h 3:0 - 4 for test for test normally set to 0 h 0 h 7:3 i2a_accselamp 5 acc amplifier fixed mode acc amplifier fixed mode gain adjustment -5 to +26db 00 h 02 h 2:0 i2a_tmctrl 3 auto mode switching auto/manual mode switching 000: auto 001: ntsc-m 010: ntsc-4.43 011: pal 100: pal-m 101: pal-n 110: pal-60 111: secam 0 h 03 h 7:0 - 8 for test for test normally set to 20 h 20 h 04 h 7:0 - 8 for test for test normally set to 80 h 80 h 05 h 7:0 - 8 for test normally set to 40 h 40 h 06 h 7:0 - 8 for test for test normally set to 10 h 10 h 07 h 7:0 - 8 for test for test normally set to 80 h 80 h 08 h 7:0 - 8 for test for test normally set to 00 h 00 h 09 h 7:0 - 8 for test for test normally set to 80 h 80 h 7:5 - 3 for test for test normally set to 5 h 5 h 4 - 1 for test for test normally set to 0 h 0 h 0a h 3:0 - 4 for test for test normally set to 2 h 2 h 7:4 - 4 for test normally set to 3 h 3 h 0b h 3:0 - 4 for test for test normally set to 3 h 3 h 7 - 1 for test for test normally set to 0 h 0 h 0c h 6:0 - 7 for test for test normally set to 18 h 18 h 0d h 7:0 - 8 for test for test normally set to a0 h a0 h 0e h - - - - - - 0f h 7:0 - 8 for test for test normally set to 60 h 60 h 10 h 7:0 - 8 for test for test normally set to 80 h 80 h 7:4 4 for test normally set to c h c h 11 h 3:0 - 4 for test for test normally set to 8 h 8 h 7:6 - 2 for test for test normally set to 3 h 3 h 5:4 - 2 for test normally set to 3 h 3 h 3 - 1 for test for test normally set to 1 h 1 h 12 h 2:0 - 3 for test for test normally set to 0 h 0 h continued on next page.
LC749870W no.a1957-13/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 6:4 - 3 for test for test normally set to 0 h 0 h 13 h 1:0 - 2 for test for test normally set to 2 h 2 h 14 h 7:0 - 8 for test normally set to 96 h 96 h 15 h 7:0 - 8 for test normally set to 64 h 64 h 16 h 7:0 - 8 for test for test normally set to 64 h 64 h 7:4 i2a_atmode 4 video system auto-detect switch auto mode switching (it takes effect at i2a_tmctrl=3?h0.) 0000: manual mode 0001: auto0 (ntsc/pal) 0010: auot1 (pal/secam) 0011: auto2 (ntsc/pal-n/pal-m) 0100: auto3 (ntsc/pal/secam) 0101: auto4 (ntsc/pal/ secam/pal-n/pal-m) 0110: auto5 (auto0+ntsc-443/pal-60) 0111: auto6 (auto1+ntsc-443/pal-60) 1000: auto7 (auto2+ntsc-443/pal-60) 1001: auto8 (auto3+ntsc-443/pal-60) 1010: auto9 (auto4+ntsc-443/pal-60) 1011 to 1111: full f h 3:2 i2a_fscsel 2 fsc select fsc select at manual mode 00: 3.579545mhz 01: 4.43361875mhz 10: 3.57561149mhz 11: 3.58205625mhz 1 h 1 i2a_scansel 1 scanning line number select scanning line number select at manual mode 0: 525i 1: 625i 0 h 17 h 0 i2a_ntpalsel 1 ntsc/pal select ntsc/pal select at manual mode 0: ntsc 1: pal 0 h 7:6 - 2 for test normally set to 3 h 3 h 5:4 - 2 for test for test normally set to 0 h 0 h 1 - 1 for test for test normally set to 1 h 1 h 18 h 0 i2a_secamsel 1 secam select secam select at manual mode 0: not secam 1: secam 0 h 19 h 6:0 - 7 for test normally set to 7f h 7f h 1a h 6:0 - 7 for test for test normally set to 00 h 00 h 2 i2a_dcon 1 digital clamp on/off setting digital clamp on/off setting 0: off 1: on 1 h 1 i2a_dcline 1 detection level update unit switching pedestal level update unit switching 0: each frame 1: each line 0 h 1b h 0 - 1 for test for test normally set to 0 h 0 h 1c h 6:0 i2a_stdlevy 7 pedestal level setting target pedestal level setting level setting range: 236 to 363lsb 40 h 7:5 i2a_tcdc 3 time constant setting digital clamp time constant setting 000: time constant none 001: 1/2 010: 1/4 011: 1/8 100: 1/16 101: 1/32 110: 1/64 111: 1/128 0 h 1d h 4:0 i2a_framedc 5 update field number setting pedestal level update field number setting setting range: 0 to 31 fields 10 h 1e h 6:0 - 7 for test for test normally set to 00 h 00 h 1f h 4:0 - 5 for test for test normally set to 17 h 17 h continued on next page.
LC749870W no.a1957-14/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 7 i2a_filsel 1 lpf characteristic switch lpf characteristic switching for sync separation (it takes effect at i2a_autofil = 1?b0.) 0: cutoff frequency 0.35mhz 1: cutoff frequency 1.4mhz 1 h 6 i2a_autofil 1 lpf characteristic auto-switching setting lpf characteristics automatic switching setting for sync separation 0: off 1: on 1 h 5 - 1 for test for test normally set to 1 h 1 h 4 - 1 for test for test normally set to 0 h 0 h 20 h 3:0 - 4 for test normally set to f h f h 21 h 7:0 - 8 for test for test normally set to 55 h 55 h 7 - 1 for test normally set to 1 h 1 h 6 - 1 for test for test normally set to 0 h 0 h 5 1 input signal system auto/manual setting 0: auto setting 1: manual setting 0 h 4 i2a_manmode 1 input signal line number auto/manual setting 0: auto setting 1: manual setting 0 h 22 h 2:0 i2a_tvmode 3 input signal system setting (it takes effect at i2a_manmode[1] = 1?b1) 000: ntsc-m 001: pal-m 010: pal-n 011: pal-gbi 100: secam 0 h 6 i2a_insig 1 input signal system setting input signal line number setting (it takes effect at i2a_manmode[0] = 1?b0) 0: 625 lines 1: 525 lines 1 h 5:4 - 2 for test for test normally set to 1 h 1 h 23 h 3:0 - 4 for test for test normally set to 1 h 1 h 7 i2a_sldet 1 slice level setting sync separation slice level auto-setting 0: manual setting 1: auto setting 1 h 5:4 i2a_tclev 2 slice level time constant setting slice level time constant setting 00: 1/2 01: 1/4 10: 1/8 11: 1/16 1 h 24 h 3:2 i2a_levad 2 initial slice level setting slice level initial value setting 00: 60lsb 01: 80lsb 10: 100lsb 11: 120lsb as for an initial value of the slice level, the above value is added to the detected sync tip level. 3 h 25 h 7:0 i2a_slst 8 slice level level setting range: 236 to 363lsb setting slice level setting (it takes effect at i2a_sldet = 1?b0) settable in 4 lsb units setting range: 0 to 1020lsb 08 h 7:4 - 4 for test normally set to 7 h 7 h 26 h 3:0 - 4 for test normally set to 9 h 9 h 7:4 - 4 for test for test normally set to 7 h 7 h 3:2 - 2 for test normally set to 3 h 3 h 27 h 1:0 - 2 for test for test normally set to 0 h 0 h 7:4 - 4 for test normally set to 3 h 3 h 28 h 3:0 - 4 for test for test normally set to 1 h 1 h continued on next page.
LC749870W no.a1957-15/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 7 - 1 for test for test normally set to 1 h 1 h 6:4 - 3 for test normally set to 1 h 1 h 29 h 2:0 - 3 for test for test normally set to 7 h 7 h 2a h 7:0 - 8 for test normally set to 04 h 04 h 2b h 7:0 - 8 for test normally set to 14 h 14 h 2c h 7:0 - 8 for test normally set to 00 h 00 h 2d h 7:0 - 8 for test for test normally set to 03 h 03 h 2e h 6:4 - 3 for test normally set to 4 h 4 h 2f h 5:0 - 6 for test normally set to 02 h 02 h 30 h 5:0 - 6 for test for test normally set to 01 h 01 h 31 h 7:0 i2a_hspad 8 h-sync positioning h-sync position adjustment 05 h 7 - 1 for test for test normally set to 0 h 0 h 6 - 1 for test normally set to 1 h 1 h 5 - 1 for test for test normally set to 1 h 1 h 4 - 1 for test normally set to 1 h 1 h 32 h 3:0 - 4 for test for test normally set to 0 h 0 h 33 h 7:0 - 8 for test for test normally set to cb h cb h 34 h 7:0 - 8 for test for test normally set to ca h ca h 35 h 7:0 - 8 for test for test normally set to cd h cd h 6 - 1 for test for test normally set to 1 h 1 h 5 - 1 for test for test normally set to 0 h 0 h 4 i2a_fixln 1 line number fixed mode on/off setting line number fixed mode on/off setting 0: off 1: on 1 h 36 h 2:0 i2a_vstart 3 v-sync positioning v-sync position adjustment 3 h 7:5 i2a_vbstart 3 v-blank positioning v-blank position adjustment 3 h 37 h 4:0 i2a_hbstart 5 h-blank rising positioning h-blank rising position adjustment 0f h 7:5 i2a_vbwidth 3 v-blank width adjustment v-blank width adjustment 3 h 38 h 4:0 i2a_hbend 5 h-blank falling positioning h-blank falling position adjustment 0f h continued on next page.
LC749870W no.a1957-16/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 39 h 7:0 - 8 for test for test normally set to 50 h 50 h 3a h 7:0 - 8 for test for test normally set to 10 h 10 h 3b h 7:0 - 8 for test for test normally set to 24 h 24 h 3c h 7:0 - 8 for test for test normally set to f1 h f1 h 3d h 7:0 - 8 for test for test normally set to 93 h 93 h 3e h 7:0 - 8 for test for test normally set to 50 h 50 h 3f h 7:0 - 8 for test for test normally set to 30 h 30 h 40 h 7:0 - 8 for test for test normally set to 18 h 18 h 41 h 7:0 - 8 for test for test normally set to 25 h 25 h 42 h 7:0 - 8 for test for test normally set to 23 h 23 h 43 h 7:0 - 8 for test for test normally set to c8 h c8 h 7 1 no signal detection on/off setting 0: off 1: on 1 h 6 i2a_nsdon 1 no signal detection on/off setting forced no signal mode on/off setting (it takes effect at i2a_nsdon[1] = 1?b0) 0: off 1: on 1 h 4 - 1 for test for test normally set to 0 h 0 h 3:2 i2a_nsdthh 2 threshold settin g where signals can be measured 0 h 44 h 1:0 i2a_nsdthl 2 no signal detection threshold setting threshold setting where no signal can be measured 1 h 5 - 1 for test for test normally set to 0 h 0 h 3:2 - 2 for test for test normally set to 1 h 1 h 45 h 1:0 - 2 for test for test normally set to 1 h 1 h 46 h 4:0 - 5 for test normally set to 10 h 10 h 47 h 5:0 - 6 for test for test normally set to 3f h 3f h 5 - 1 for test for test normally set to 0 h 0 h 3 - 1 for test for test normally set to 0 h 0 h 2 - 1 for test for test normally set to 0 h 0 h 48 h 1 i2a_exagcon 1 external agc on/off setting external agc on/off setting 0: off 1: on 0 h 49 h 7:0 - 8 for test normally set to 00 h 00 h 4a h 7:0 - 8 for test for test normally set to 00 h 00 h 4b h 7:0 i2a_synlev 8 sync level setting agc target sync level setting setting range: 158 to 413lsb 80 h 6:4 i2a_frmcnt 3 update field number setting agc update field number setting 0 h 4c h 3:0 i2a_fixgain 4 fixed gain setting fixed gain setting setting range: -6 to +9db 6 h continued on next page.
LC749870W no.a1957-17/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 7:6 i2a_tcagc 2 time constant setting agc time constant setting 00: no time constant 01: 1/2 10: 1/4 11: 1/8 0 h 4d h 4:0 i2a_exagcinit 5 external agc gain value setting external agc initial gain value setting 0f h 7:6 i2a_amplimit 2 amplifier limit switching agc amplifier limit switching 00: 3db 01: 6db 10: 9db 11: 12db 0 h 4e h 4:0 - 5 for test for test normally set to 00 h 00 h 7:5 i2a_nlfield 3 update field number setting noise detection results upd ate field number setting 000: 1 field 001: 2 fields 010: 4 fields 011: 8 fields 100: 16 fields 101: 32 fields 110: 64 fields 111: 128 fields 0 h 4f h 4:0 - 5 for test for test normally set to 0f h 0f h 5:4 - 2 for test for test normally set to 2 h 2 h 50 h 3:0 - 4 for test for test normally set to 0 h 0 h 51 h 6:0 52 h 7:0 i2a_nlth 15 noise detection threshold setting threshold value setting of noise detection 0c80 h 5:4 i2a_selntpal 2 system detection select system detection select 00: both ntsc/pal (line number is distinguished.) 01: only ntsc 10: only pal 11: both ntsc/pal 0 h 2 i2a_autodet 1 system auto-detection on/off setting system auto-detection on/off setting 0: off 1: on 0 h 53 h 0 i2a_nostddet 1 non-standard detection on/off setting non-standard detection on/off setting 0: off 1: on 0 h 54 h 1:0 i2a_hselformat 2 system designation input signal system designation (it takes effect at i2a_autodet = 1?b0) 00: 576i 01: 480i 10: 576i (non-standard) 11: 480i (non-standard) 1 h 5 - 1 for test for test normally set to 0 h 0 h 4 - 1 for test for test normally set to 0 h 0 h 3:2 - 2 for test for test normally set to 0 h 0 h 55 h 1:0 - 2 for test for test normally set to 3 h 3 h 6:4 - 3 for test for test normally set to 0 h 0 h 56 h 2:0 - 3 for test for test normally set to 0 h 0 h 6:4 - 3 for test for test normally set to 5 h 5 h 3 - 1 for test for test normally set to 1 h 1 h 2 - 1 for test normally set to 0 h 0 h 57 h 1:0 - 2 for test for test normally set to 2 h 2 h continued on next page.
LC749870W no.a1957-18/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 58 h 7:0 - 8 for test normally set to 0c h 0c h 59 h 5:0 - 6 for test normally set to 32 h 32 h 5a h 7:0 - 8 for test normally set to f0 h f0 h 5b h 5:0 - 6 for test normally set to 05 h 05 h 5c 7:0 - 8 for test normally set to 28 h 28 h 6:4 - 3 for test normally set to 4 h 4 h 5d h 2:0 - 3 for test normally set to 3 h 3 h 5e h 7:0 - 8 for test for test normally set to 0a h 0a h 7:6 - 2 for test normally set to 3 h 3 h 5:4 - 2 for test normally set to 3 h 3 h 3:2 - 2 for test normally set to 3 h 3 h 5f h 1:0 - 2 for test normally set to 3 h 3 h 7:6 - 2 for test normally set to 3 h 3 h 5:4 - 2 for test normally set to 3 h 3 h 3:2 - 2 for test normally set to 3 h 3 h 60 h 1:0 - 2 for test for test normally set to 3 h 3 h 7:4 - 4 for test normally set to 0 h 0 h 61 h 3:0 - 4 for test for test normally set to 0 h 0 h 62 h to 6f h - - - - - - 70 h 1:0 71 h 7:0 - 10 for test read only - 72 h 0 nosig 1 no signal detection no signal detection result read only - 73 h to 74 h - - - - - - 7 nldout 1 s/n detection result read only - 75 h 6:0 76 h 7:0 nldet 15 s/n detection noise level read only - 77 h 0 - 1 for test read only - 5:4 hsysformat 2 system detection system detection result read only - 1 - 1 for test read only - 78 h 0 - 1 for test read only - continued on next page.
LC749870W no.a1957-19/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 3 douth 1 non-standard detection result (h) when non-standard is detected in field-blanking period 0: normal 1: special reproduction read only - 2 douth2 1 non-standard detection result (h) 0: standard 1: non-standard read only - 1 doutv 1 non-standard detection result (v) 0: standard 1: non-standard read only - 79 h 0 doutsta 1 non-standard detection stability judgment result 0: stable 1: unstable read only - 7a h 4:0 - 5 for test read only - 7b h to 8a h - - - - - - 8b h 0 - 1 for test for test normally set to 0 h 0 h 8c h 0 - 1 for test for test normally set to 0 h 0 h 8d h - - - - - - 8e h 0 - 1 for test for test normally set to 0 h 0 h
LC749870W no.a1957-20/45 bank2 (digital video signal processing block 2) register specification sub- address bit name bit- size function name functions initial value 7 - 1 for test for test normally set to 0 h 0 h 6 i2byc_ softreset 1 soft reset soft reset y/c separation is initialized on the rising edge of the register clock 0 h 5:3 i2byc_ sel_format 3 input switching setting input switching (it takes effect at i2byc_insel[0] = 0) 000: ntsc 010: pal-m 100: pal 110: pal-n xx1: secam 0 h 2 1 for test for test normally set to 1 h 1 h 1 1 for test for test normally set to 1 h 1 h 00 h 0 i2byc_insel 1 input switching setting input switching setting 0: i2byc_sel_pal[7:6] 1: insel(input port) 1 h 01 h 7:0 - 8 for test for test normally set to 16 h 16 h 02 h 7:0 - 2 for test for test normally set to 16 h 16 h 7:6 2 for test normally set to 3 h 3 h 5 1 for test normally set to 0 h 0 h 4 1 for test normally set to 1 h 1 h 03 h 3:0 - 4 for test for test normally set to 4 h 4 h 7:4 4 for test normally set to 4 h 4 h 3 1 for test normally set to 0 h 0 h 2 1 for test normally set to 0 h 0 h 1 1 for test normally set to 0 h 0 h 04 h 0 - for test for test normally set to 0 h 0 h 7 1 for test for test normally set to 0 h 0 h 6:5 2 vertical high region line comb setting line comb vertical high region element bsf coefficient select 00: bsf1 01: bsf2 10: bsf3 11: bsf4 3 h 4 1 for test for test normally set to 0 h 0 h 3 1 dot interference reduction setting dot interference reduction bsf 0: off 1: on 1 h 2 1 for test normally set to 1 h 1 h 05 h 1:0 i2byc_2dcomb2 2 for test for test normally set to 2 h 2 h 7:5 3 for test normally set to 2 h 2 h 3 1 for test normally set to 0 h 0 h 1 1 for test normally set to 0 h 0 h 06 h 0 - 1 for test for test normally set to 0 h 0 h continued on next page.
LC749870W no.a1957-21/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 7 1 for test normally set to 1 h 1 h 6 1 for test normally set to 1 h 1 h 5 1 for test for test normally set to 1 h 1 h 4 1 cross color reduction on/off cross color reduction 0: off 1: on 0 h 3 1 for test normally set to 1 h 1 h 2 1 for test for test normally set to 1 h 1 h 1 1 for test for test normally set to 1 h 1 h 07 h 0 i2byc_2dcomb4 1 for test for test normally set to 0 h 0 h 7 1 for test for test normally set to 0 h 0 h 6 1 for test for test normally set to 1 h 1 h 5 1 for test normally set to 1 h 1 h 4 1 for test normally set to 1 h 1 h 3:2 2 for test normally set to 1 h 1 h 1 1 for test normally set to 1 h 1 h 08 h 0 - 1 for test for test normally set to 1 h 1 h 7 1 for test for test normally set to 1 h 1 h 6 1 for test normally set to 1 h 1 h 09 h 5 - 1 for test for test normally set to 1 h 1 h 7 1 one dimensional filter setting adaptive two dimensional filter enable/disable setting 0: two dimensional 1: adaptive two dimensional 1 h 6 1 for test normally set to 1 h 1 h 5 1 for test normally set to 1 h 1 h 4 1 for test normally set to 1 h 1 h 3:2 2 for test normally set to 3 h 3 h 1 1 for test normally set to 1 h 1 h 0a h 0 i2byc_2dcomb8 1 for test for test normally set to 1 h 1 h 7:4 4 for test normally set to 4 h 4 h 0b h 3:0 - 4 for test for test normally set to 4 h 4 h 7:4 4 for test normally set to 7 h 7 h 0c h 3:0 - 4 for test for test normally set to 8 h 8 h 0d h 7:0 - 8 for test for test normally set to 0c h 0c h 0e h 7:0 - 8 for test for test normally set to 14 h 14 h continued on next page.
LC749870W no.a1957-22/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 7:4 4 vertical enhancer gain setting 000: off 001: 2/8 times to 0111: 8/8 times to 1111: 16/8 times 0 h 0f h 3:0 i2byc_2dvenh 4 vertical enhancer setting vertical enhancer coring setting 0 h 10 h 7:0 - 8 for test for test normally set to 4b h 4b h 7 1 for test normally set to 0 h 0 h 6 1 for test normally set to 0 h 0 h 5 1 for test normally set to 0 h 0 h 4 1 for test normally set to 0 h 0 h 2 1 for test normally set to 0 h 0 h 1 1 for test normally set to 0 h 0 h 11 h 0 - 1 for test for test normally set to 0 h 0 h 7 1 for test normally set to 0 h 0 h 6 1 for test normally set to 0 h 0 h 5 1 for test normally set to 0 h 0 h 4 1 for test normally set to 0 h 0 h 2 1 for test normally set to 0 h 0 h 1 1 for test normally set to 0 h 0 h 12 h 0 - 1 for test for test normally set to 0 h 0 h 7 1 for test normally set to 0 h 0 h 5 1 for test normally set to 0 h 0 h 4 1 for test normally set to 0 h 0 h 3 1 for test normally set to 0 h 0 h 2 1 for test normally set to 0 h 0 h 1 1 for test normally set to 1 h 1 h 13 h 0 - 1 for test for test normally set to 1 h 1 h 14 h 0 - 1 for test for test normally set to 0 h 0 h continued on next page.
LC749870W no.a1957-23/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 7 1 for test for test normally set to 0 h 0 h 6 1 for test for test normally set to 0 h 0 h 5:4 2 for test normally set to 0 h 0 h 3 1 for test normally set to 0 h 0 h 2 1 for test normally set to 0 h 0 h 15 h 1 - 1 for test for test normally set to 0 h 0 h 7:4 4 one dimensional bpf select one dimensional bpf select 000: bpf0 to 1011: bpf11 4 h 3:1 3 bpf for secam select one dimensional bpf select for secam 000: bpf0 to 111: bpf7 2 h 16 h 0 i2byc_1dfil 1 one dimensional filter on one dimensional filter on/off setting 0: line comb filter 1: one dimension filter 0 h 17 h to 1f h - - - - - - 20 h 7:0 - 8 for test for test normally set to 2c h 2c h 5 - 1 for test for test normally set to 0 h 0 h 4 - 1 for test for test normally set to 1 h 1 h 3 - 1 for test for test normally set to 1 h 1 h 21 h 2:0 - 3 for test for test normally set to 0 h 0 h 22 h to 25 h - - - - - - 26 h 7:0 i2bcd_ugain 8 cb gain setting gain control of cb signal 80 h 27 h 7:0 i2bcd_vgain 8 cr gain setting gain control of cr signal 80 h 28 h - - - - - - 4:3 - 2 for test for test normally set to 0 h 0 h 29 h 2:0 - 3 for test normally set to 0 h 0 h 2a h 7:0 - 8 for test for test normally set to 80 h 80 h 2b h - - - - - - 2c h 7:0 - 8 for test for test normally set to 80 h 80 h 2d h to 2f h - - - - - - 3 - 1 for test for test normally set to 0 h 0 h 2 i2bac_ sw_acc_ntpal 1 acc ntsc/pal setting 0: ntsc = 286lsb 1: pal = 300lsb (when acc_bstlv is center value) 0 h 30 h 1:0 i2bac_acc_on 2 acc on acc on/off setting 00: off 01: on 1x: gain fix 1 h 31 h 7:0 i2bac_ acc_bstlv 8 acc target value setting 158 to 413lsb 80 h 32 h 3:0 i2bac_ acc_timcon 4 acc setting maximum value of time constant, characteristics select setting range: 1 time to 16 times 3 h 33 h 1:0 - 2 for test for test normally set to 0 h 0 h continued on next page.
LC749870W no.a1957-24/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 34 h 3:0 i2bac_ckill_on 4 color killer on/off setting 0000: off 0001: on by apc 0010: on by acc 0011: on by apc + acc 0100: on at the time of noncompliant signal input 0101: on by apc and at the time of noncompliant signal input 0110: on by acc and at the time of noncompliant signal input 0111: on by apc + acc and at the time of noncompliant signal input 1xxx: forced on 7 h 35 h 4:0 i2bac_ckill_lv 5 threshold value killer is turned on by burst-amplitude 3 h 36 h 4:0 i2bac_ ckill_hyst 5 color killer setting threshold value killer is turned off by burst-amplitude 0 h 37 h 1:0 - 2 for test for test normally set to 1 h 1 h 38 h to 3a h - - - - - - 3b h 4:0 - 5 for test normally set to 0 h 0 h 3c h 2:0 - 3 for test for test normally set to 0 h 0 h 3d h 1:0 - 2 for test for test normally set to 0 h 0 h 3e h 4:0 i2bac_ acc_selamp 5 acc setting gain setting at acc_on = 2?b1x setting range: -6 to 32db 0 h 3f h - - - - - - 5 - 1 for test for test normally set to 1 h 1 h 4 - 1 for test for test normally set to 0 h 0 h 40 h 3:0 i2bse_bellf0 4 bell filter f0 select 8 h 7:4 i2bse_bellq 4 bell filter q select 8 h 41 h 3:2 i2bse_bellamp 2 bell filter setting bell filter amplifier select 0: 1 time 1: 2 times 1 h 2 - 1 for test for test normally set to 1 h 1 h 42 h 1:0 i2bse_clpfsel 2 lpf setting after fm demodulation lpf select after fm demodulation 2 h 43 h 5:0 - 6 for test normally set to 28 h 28 h 44 h 7:0 - 8 for test normally set to 40 h 40 h 3:2 - 2 for test normally set to 3 h 3 h 45 h 1:0 - 2 for test for test normally set to 3 h 3 h continued on next page.
LC749870W no.a1957-25/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 6:4 - 3 for test for test normally set to 1 h 1 h 3 - 1 for test normally set to 1 h 1 h 2:1 - 2 for test normally set to 3 h 3 h 46 h 0 - 1 for test normally set to 0 h 0 h 47 h 5:0 - 6 for test normally set to 1 h 1 h 48 h 3:0 - 4 for test normally set to 1 h 1 h 49 h 6:0 - 7 for test normally set to 40 h 40 h 4a h 6:0 - 7 for test for test normally set to 40 h 40 h 4b h 5:0 - 6 for test for test normally set to 3 h 3 h 4c h 5:0 - 6 for test for test normally set to a h a h 4d h to 4f h - - - - - - 2 - 1 for test normally set to 1 h 1 h 1 - 1 for test normally set to 0 h 0 h 50 h 0 - 1 for test for test normally set to 0 h 0 h 51 h 7:0 i2bse_ugain 8 80 h 52 h 7:0 i2bse_vgain 8 cb/cr gain control 0 to 3.984375 0 = 0 64 = 1 128 = 2 255 = 3.984375 80 h 53 h 7:0 i2bse_uoffset 8 80 h 54 h 7:0 i2bse_voffset 8 secam chroma adjustment cb/cr offset adjustment -128 to 127 0 = -128 128 = 0 255 = 127 80 h 5 - 1 for test for test normally set to 0 h 0 h 4:3 i2bse_deiir 2 de-emphasis filter setting de-emphasis filter select 0 h 55 h 2:0 - 3 for test for test normally set to 0 h 0 h 56 h to 5f h - - - - - - 60 h 7:0 - 8 for test for test normally set to f h f h 61 h 7:0 - 8 for test for test normally set to 64 h 64 h continued on next page.
LC749870W no.a1957-26/45 continued from preceding page. sub- address bit name bit- size function name functions initial value 7 1 for test for test normally set to 0 h 0 h 6 1 for test for test normally set to 1 h 1 h 5 1 for test for test normally set to 0 h 0 h 4 1 for test for test normally set to 0 h 0 h 62 h 3 - 1 for test for test normally set to 0 h 0 h 63 h - - - - - - 7 1 for test for test normally set to 0 h 0 h 6 1 for test for test normally set to 0 h 0 h 3 1 tv mode select 0: auto setting 1: manual setting with tvmode[2: 0] 0 h 2 1 frequency select 0: 50hz (625 lines) 1: 60hz (525 lines) 0 h 64 h 1:0 i2bcv_tvmode 2 system setting 0: ntsc 1: pal-m 2: pal 3: pal-n 0 h 7:6 2 for test for test normally set to 0 h 0 h 65 h 2:0 - 3 for test for test normally set to 1 h 1 h 66 h - - - - - - 7:6 2 for test for test normally set to 0 h 0 h 5 1 for test for test normally set to 0 h 0 h 4 1 for test for test normally set to 0 h 0 h 3:1 3 for test for test normally set to 0 h 0 h 67 h 0 - 1 for test for test normally set to 0 h 0 h 68 h to 69 h - - - - - - 6a h 7:0 - 8 for test for test normally set to 10 h 10 h 6b h to 70 h - - - - - - 71 h 5:0 i2bsr_gain 6 contrast adjustment 20 h 72 h 5:0 i2bsr_ofst 6 sub contrast/ brightness setting brightness adjustment 20 h 73 h to 7b h - - - - - - 1 - 1 for test for test normally set to 0 h 0 h 7c h 0 i2bsr_setup 1 setup setup processing 1 h 7d h to 7f h - - - - - - 80 h 0 - 1 for test normally set to 1 h 1 h 81 h 0 - 1 for test for test normally set to 0 h 0 h 82 h to 9f h - - - - - - continued on next page.
LC749870W no.a1957-27/45 continued from preceding page. sub- address bit name bit- size function name functions initial value a0 h 2:0 - 3 for test normally set to 0 h 0 h a1 h 2:0 - 3 for test for test normally set to 0 h 0 h
LC749870W no.a1957-28/45 bank3 (digital video signal processing block 3) register specification sub- address bit name bit- size function name functions initial value 2 i2dsh_lpfoff 1 sharpness setting sharpness lpf on/off setting 0: on 1: off 0 h 1 - 1 for test for test normally set to 0 h 0 h 00 h 0 i2dsh_on 1 sharpness on/off setting 0: off 1: on 0 h 01 h 5:0 i2dsh_att 6 sharpness att value setting setting range: -47.5 to 12db 10 h 02 h 2:0 i2dsh_corr 3 sharpness coring threshold 0 h 03 h 3:0 i2dsh_filter 4 sharpness setting sharpness characteristic select 1 h 2 - 1 for test normally set to 0 h 0 h 1 - 1 for test normally set to 0 h 0 h 04 h 0 - 1 for test for test normally set to 1 h 1 h 05 h 0 - 1 for test for test normally set to 0 h 0 h 06 h 7:0 i2dcb_cont 8 contrast adjustment 80 h 07 h 7:0 i2dcb_bright 8 contrast/ brightness setting brightness adjustment 80 h 08 h 6:0 i2dhu_hue 7 hue setting hue adjustment 40 h 09 h 7:0 i2duv_ugain 8 cb gain control b4 h 0a h 7:0 i2duv_vgain 8 u/v gain setting cr gain control b4 h 0b h to 0e h - - - - - - 0f h 1:0 - 2 for test for test normally set to 1 h 1 h 3:1 i2dct_smp 3 cti correction tap coefficient 0 h 10 h 0 i2dct_ctien 1 cti on/off setting 0: off 1: on 0 h 7:4 i2dct_corr 4 cti coring threshold 0 h 11 h 3:0 i2dct_gain 4 cti setting cti gain gain=c_gain/8 (0 c_gain 15) 6 h 7:4 - 4 for test normally set to 0 h 0 h 12 h 3:0 - 1 for test for test normally set to 0 h 0 h 5:4 i2d65_ autobback 2 no signal output mode 00: black background 01: blue background 10: off 11: bl 0 h 3 i2d65_sepia 1 0: normal output 1: sepia output 0 h 2 i2d65_601lim 1 0: signal level 1 to 254 1: y level 16 to 235, c level 16 to 240 0 h 1 i2d65_avoff 1 656 conversion setting 0: 656 with sav,eav 1: no sav, eav 1 h 13 h 0 - 1 for test for test normally set to 0 h 0 h 14 h to 1f h - - - - - - 20 h 1:0 - 2 for test normally set to 0 h 0 h 21 h 1:0 - 2 for test for test normally set to 0 h 0 h
LC749870W no.a1957-29/45 function descriptions 1. cpu i/f the LC749870W registers are controlled by i 2 c. 1) i 2 c the LC749870W supports high-speed mode slave operation (400 khz) and the slave address is as follows. bit[7] (msb) bit[6] bit[5] bit[4] bit[ 3] bit[2] bit[1] bit[0] (lsb) 1 0 0 0 1 0 i 2 csel r/w *note: the bit 1 is decided according to the i 2 csel pin condition. bit 0 r/w: 0 = write, 1 = read write mode ? auto address increment. ? as shown below, after the start condition, the settings must be made in the following order: slave address (w), ack waiting, write start sub address, ack waiting, write data. the stop condition must be set last. data can be transmitted continuously from the write start sub addre ss using the auto addres s increment function. [st] [slave address(w)] [a ] [sub address] [a ] [data] [a ] [data] ? ? ? [sp] read mode ? auto address increment. ? the read start sub address must be assigned in write mode. ? as shown below, after the start condition, first set the slav e address (w), ack waiting and read start sub address. next, set the start condition again or set the st art condition after setting the stop conditio n. next set the slave address (r) and ack waiting in read mode. the data for each sub address is output continuously from the read start sub address data using the auto address incremen t function. after receiving the data for each sub address, return the ack. finally, set the stop condition. [st] [slave address (w)] [a ] [sub address] [st] [slave address(r)] [a ] [data ] [a] [data ] [a] [data ] ? ? ? [sp] or [st] [slave address (w)] [a ] [sub address] [sp] [st] [slave address(r)] [a ] [data ] [a] [data ] [a] [data ] ? ? ? [sp] [st]: start condition [sp]: stop condition [a]: ack [a ]: ack waiting [data]: data transmission [data ]: data reception
LC749870W no.a1957-30/45 2) bank each register is allocated to the bank depending on its f unction (refer to table 1). after the bank is specified, the register can be controlled. the bank is spec ified by setting the bank code to sub address ff h . note that the register cannot be transmitted or received if codes other than the bank codes in table1 are specified. table 1 allocation of bank bank bank code controlled function 0 01 h afe + adc 1 02 h digital video signal processing block 1 (data interpolator, apc, agc, digital clamp, sync separator, timing generator, video system detection, s/n detection, non-standard signal detection, no-signal detection) 2 04 h digital video signal processing block 2 (y/c separator, color demodulator, clock rate converter) 3 08 h digital video signal processing block 3 (sharpness, contrast/brightness, cti, hue, uv gain) ? auto address increment. [st] [slave address (w)] [a ] [ff h ] [a ] [bank code] [sp] [st]: start condition [sp]: stop condition [a]: ack [data]: data transmission
LC749870W no.a1957-31/45 2. afe and adc this ic (LC749870W) incorporates 1-channel of video afe and 10-bit 30mhz adc. ? analog clamp (self-clamp circuit) the self clamp circuit clamps the sync-tip without supplying clamp pulses to afe module. when the self-clamp function is not used, it can be placed in power down mode using i 2 c_selfclppwdb. ? sync-tip clamp specifications ? low pass filter before self-clamp a primary lpf with a 1mhz cutoff frequency has been inserted in the stage before the self-clamp circuit as a measure to deal with the high-frequency noise that is present in weak electric fields. the lpf functio n is for minimizing shifts in the clamp levels of the self-clamp when high-frequency noise components are present in the video signals. the lpf can be set to on or off using i 2 c_clplpfon. fig.1 self clamp in weak electric fields input video signal (sd) high frequency noise o f 1mhz or more 0v 0.35v sync tip clamp when lpf is off clamping is performed at the lower limit level of the noise components. due to the effect of the noise, the clamp level shifts. clamping is performed at the level at which the noise components are removed. it is clamped at its original position. sync tip clamp when lpf is on (adc-input reference) a dc output code 1023 1 512 147 878 356 * the figures represent the va lues under ideal conditions. clamp setting self clamp setting selfclppwdb 1: self clamp enable main clamp level setting mainclplvcnt [1:0] 00: main clamp level 0.35v 0.35v 1.35v 0.85v 0.65v 1.55v 0.15v 1.4vp-p range 1.0vp analog input digital output
LC749870W no.a1957-32/45 ? agc mode and non-agc mode switch between non-agc mode and agc mode using i 2 c_scarton. non-agc mode is used when the amplitude of the video signal is steady in the environment of a strong electric field. the maximum of the sync tip clamped analog video input amplitude assumes 1.0vp-p in non-agc mode. the adc full-scale input range is fixed at 1.4vp-p. agc mode is used when the amplitude of the video signal is unsteady in the environment of a weak electric field. the maximum of the sync tip clamped analog video input amplitude assumes a value no greater than from 0.7vp-p (-3db) to 1.4vp-p (+3db) in agc mode. because the afevrtc is controlled according to the amplitude of sync detected by the decoder, agc mode is enabled by varying the adc full-scale input range. 3. data interpolator data interpolator converts the input video signal sampled at 27mhz into 4fsc data. supported video systems are shown in the following table. table 2: supported video system input output video system sampling clock data transfer rate clock lock method ntsc 27mhz 14.318180mhz burst lock pal-b, g, d, k, i 27mhz 17.734476mhz burst lock pal-m 27mhz 14.302444mhz burst lock pal-n 27mhz 14.328224mhz burst lock ntsc4.43 27mhz 17.7344 76mhz burst lock pal-60 27mhz 17.734476mhz burst lock secam 27mhz 13.5mhz h lock 4. apc (auto phase control) in order to burst lock input video signals, the apc circuit detects the color burst phase er ror. the data interpolation coefficient is calculated using the detected phase error, and is then output to the data interpolator circuit. it is equipped with a function to turn on the color killer when not burst-locked, and also has an acc circuit to maintain the amplitude of the carrier chrominance signal at a constant level. 5. agc (auto gain control) the agc keeps the sync level constant by automatically calculating an appropriate gain value from the input video signal sync level and amplifying the input video signal. because the agc circuit includes a time constant circuit, following rapid changes in the input video signal can be suppressed. fig.2 waveform change before and after agc sync level pedestal level sync tip level a fter agc before agc
LC749870W no.a1957-33/45 6. digital clamp the digital clamp circuit detects the pedestal level of the input video signal, and keeps th e level constant. because the digital clamp includes a time constant circuit, following rapid changes in the input video signal can be suppressed. fig.3 waveform change before and after digital clamp 7. sync separator the sync separator circuit separates hori zontal and vertical sync signals out of the input vi deo signals. because an lpf is built in, the sync signal can be separated even in a weak electric field. the weak electric field is detected using the s/n detection result. moreover, the stability of the sync sign al in the weak electric field is improved by the internal afc circuit. fig. 4 shows the lpf charact eristics for the sync separator. ?filsel = 1?b0? is the characteristic of an lpf for a weak electric field, and ?filsel = 1?b1? is the characteristic of an lpf for a stro ng electric field. fig.4 lpf characteristic for sync separator 8. timing generator using the sync signal separated by the sync separator circ uit, the timing generator generates various timing signals to be used for each module as well as for horizontal and vertical blanking signals. the adjustments of timing signals are possible by setting the corresponding register (s) as follows: positioning of horizontal sync signal: i2a_hspad positioning of vertical sync signal: i2a_vstart positioning of horizontal blanking signal: i2a_hbstart, i2a_hbend positioning and width adjustment of vertical blanking signal: i2a_ vbstart, i2a_vbwidth 0lsb target pedestal level input signal before clamp a fter clamp
LC749870W no.a1957-34/45 9. two-dimensional y/c separation the y/c separator switches adaptive two-dimensional y/c separation and one-dimensional y/c separation according to the input video system. the table below shows the relationship between input video system and y/c separation method. table 3 relationship between input video system and y/c separation method video system y/c separation filter ntsc adaptive two-dimensional y/c separation ntsc-4.43 one-dimensional y/c separation pal-b, g, d, k, i, m, n adaptive two-dimensional y/c separation pal-60 one-dimensional y/c separation secam one-dimensional y/c separation 1) adaptive two-dimensional y/c separation the correlation between lines is detected in the vertical lpf and bpf, and the system switches between upper two line processing and lower two or three line processing, based on the results. the adaptive two-dimensional y/c separation and two-dimensional y/c separation can be switched using i2 byc_2dcomb8 [7]. note that the y/c separation filter is switched to one-dimensional y/c separation when i2byc_ 1dfil [0] is set to 1?b1 ( i2byc_1dfil [0] = 1?b1). ? y signal = (vertical low frequency co mponent) + (horizontal low frequency component of vertical high frequency component) ? c signal = horizontal high frequency component of vertical high frequency component fig.5 basic block diagram of two-dimens ional y/c separation (line comb filter) ? 1 line chroma detector when 1 line chroma is separated with the two-dimensional y/c separation, the dot interference is generated because there is no correlation between lines. ther efore, 1 line chroma is detected and dot interference reduction is attempted by subtracting chroma components. when the following conditions exist, it is judged to be 1 line chroma. (1) no chroma changes in the line (horizontal direction). (2) chroma changes between lines (vertical direction). (3) luminance changes between lines (vertical direction). horizontalbpf separation y output separation c output composite signal input horizontal frequency vertical frequency 3.58mhz 525/4cph pass range vertical frequency horizontal frequency 3.58mhz 525/4cph pass range vertical bpf vertical lpf horizontallpf vertical frequency horizontal frequency 3.58mhz 525/4cph pass range vertical frequency horizontal frequency 3.58mhz 525/4cph pass range vertical frequency pass range horizontal frequency 3.58mhz 525/4cph
LC749870W no.a1957-35/45 ? 3 line median processing when the vertical color in the dvd color bar changes and blurs, dot interference may be generated. dot interference reduction is attempted by detecting this location and removing the chroma components. fig.6 dot interference when the following conditions exist as a result of comparing the bpf values for each line, the chroma components must be removed. (1) when there is a match between the median value of each line and the pixel of the line at the center. (2) when there is a change between lines. ? y signal bypass processing if the chroma band component of the separated y signal is compared with the chroma band component of the signal before separation, and if the chroma band of the signal befo re separation is smaller, the signal is output as a y signal. ? c signal bypass processing if a c signal processed by the comb filter is compared with the result processed by the bpf, and if the result of the bpf is smaller, the bpf processing result is output as a c signal. ? dot interference reduction the line comb filter need not add hlvh *1 to the y signal if there is a complete line correlation, such as with the color bar. such an addition will only increase the dot interference shown in fig. 6 above. ther efore, when a location with strong line correlation is detected, the horizontal bsf pass band of hlvh to be added to the y signal is narrowed, and the dot interference is reduced. the dot interference reduction bsf can be set to on or off using i2byc_2dcomb2[3]. *1: horizontal low frequency component of vertical high frequency component ? cross color reduction when a location with weak line correlation is detected, the bpf pass band in the subsequent stage of the c signal is narrowed, and the cross color is reduced. cross color reduction can be set to on or off using i2byc_2dcomb4 [4]. w y cy gr ma r b dvd sg
LC749870W no.a1957-36/45 2) one-dimensional y/c separation (bpf) y/c separation is performed by using bpf. the bpf charact eristics for ntsc/pal and for secam are selected by i2byc_1dfil [7:1]. it is forced to one-dimensional y/c separation when i2byc_1dfil [0] is set to 1?b1 (i2byc_1dfil [0] = 1?b1). when performing adaptive two-dimensional y/c separation, i2byc_1dfil [0] must be set to 1?b0 (i2byc_1dfil [0] = 1?b0) . fig.7 and 8 show the characteristics of bpf. fig.7 bpf characteristic for ntsc/pal fig.8 bpf characteristic for secam -60 -50 -40 -30 -20 -10 0 10 01234567 frequency[mhz] [db] bpf0 bpf1 bpf2 bpf3 bpf4 bpf5 bpf6 bpf7 bpf8 bpf9 bpf10 bpf11 -60 -50 -40 -30 -20 -10 0 10 0123456 frequency[mhz] [db] bpf0 bpf1 bpf2 bpf3 bpf4 bpf5 bpf6 bpf7
LC749870W no.a1957-37/45 10. chrominance signal processing in chrominance signal processing, u/v axial demodulation is performed on the carrier chrominance signal after y/c separation, and the uv signal is output. 1) acc (auto color control) acc maintains a constant carrier chrominance signal amplitude for ntsc and pal. the amplitude is kept constant by observing the color burst amplitude of the input carrier chrominance signal, an d controlling the amplifier according to the amplitude level. it can also turn on the color killer when the color burst amplitude is small. i2bac_acc_on switches between acc on and off. 2) color killer the color killer masks the carrier chro minance signal so that a monochrome image is output. when entering the detection results from apc or acc circuits or an incompatible signal, the color killer is turned on and off. the color killer can be set using i2bac_ckill_on. 3) ntsc/pal color decoder the ntsc/pal color decoder demodulates the carrier chrominance signal into color component signals (u/v). ? color demodulator and low pass filter the cb/cr signal is demodulated by multiplying the chro minance signal and phase-controlled color sub-carrier (4fsc). fig. 9 shows the block diagram. fig.9 color demodulator the lpf characteristic after demodulation is shown in fig.10. fig.10 lpf characteristic after demodulation lpf chrominance signal color sub-carrier 10 10 cb/cr signal -60 -50 -40 -30 -20 -10 0 10 01234567 frequency[mhz] magnitude[db]
LC749870W no.a1957-38/45 ? uvgain (cb/cr gain control) the uvgain adjustment changes the cb/cr signal gain based on a center value. fig.11 shows the block diagram. the gain can be controlled using i2bcd_ugain and i2bcd_vgain. fig.11 uvgain block diagram 4) secam color decoder the secam color decoder demodulates the carrier chrominance signal into color difference signals (u/v). ? bell filter the bell filter is used to maintain the color sub-carrier amplitude of the y/c-separated chrominance signal constant. the f0 parameter can be selected using i2bse_bellf0, and the q parameter using i2bse_bellq. fig.12 bell filter characteristics cbin (crin) ? u(v)gain 8bits /128 + cbout (crout) 10 center(512lsb) bell filter characteristic -14 -12 -10 -8 -6 -4 -2 0 3.75 3.95 4.15 4.35 4.55 4.75 frequency[mhz] gain[db] i2_bellq=0 standard condition i2_bellq=15
LC749870W no.a1957-39/45 ? low pass filter the lpf is used to reduce noise in fm demodulated db/dr signals. the characteristics of the lpf can be selected using i2bse_clpfsel. fig.13 lpf characteristics ? uv gain and offset adjustment the uv gain adjustment is performed to convert db/dr to cb/cr, and the uv offset fine adjustment is also performed. the uv gain can be adjusted by changing i2 bse_ugain and i2bse_vgain, and the uv offset can be adjusted by i2bse_uoffs et and i2bse_voffset. fig.14 uv gain and offset adjustment gain offset db dr cb cr lpf characteristic -60 -50 -40 -30 -20 -10 0 10 0123456 frequency[mhz] gain[db] lpf0 lpf1 lpf2 lpf3
LC749870W no.a1957-40/45 ? de-emphasis filter the de-emphasis filter characteristics can be selected using i2bse_deiir. fig.15 de-emphasis filter characteristics 11. automatic video standard recognition the video input standard is recognized automatically. auto matic video standard recognition can be set to on or off using i2a_autodet. 12. s/n detection s/n detection determines the video input noise level. during a vertical blanking period, the detection of noise is processed while the detection enable signal is high. the level of s/n detection can be controlled using i2a_nlth. fig.16 s/n detection 13. non-standard detectionn this function determines whether the video input is non-standard. the video input is judged standard/non-standard by observing any variation from the standard vsync cycle. odd line even line detection enable signal 128clk de-emphasis filter characteristic -25 -20 -15 -10 -5 0 0.01 0.1 1 10 frequency[mhz] gain[db] def0 def1 def2 def3
LC749870W no.a1957-41/45 14. no signal detection this function detects no signal state. the result of no signal detection is output to the intreq pin. no signal detection function can be turned on or off using i2a_nsdon [1]. note that i2a_nsdon [0] is available when no signal detection is off. 15. clock rate conversion the sampling rate converter converts an input video signal sampled at 4fsc into 13.5mhz, and outputs synchronized signals with video data. 16. sharpness sharpness of the image can be adjusted by detecting and forcibly correcting the edge of the luminance signal when the image is scanned horizontally. adjustments to the enhancing frequency range and level of enhancement are possible. sharpness can be turned on or off using i2dsh_on.the enhancing frequency range can be selected using i2dsh_filter, and the level of enhancem ent can be adjusted using i2dsh_att. 17. contrast/brightness brightness adjusts the brightness of the entire screen and contrast adjusts the brightness gain. 1) contrast contrast can be controlled using i2dcb_cont. 00 h : 0 to 80 h : 1 to ff h : 2 2) brightness brightness can be controlled using i2dcb_bright. 00 h : -128 to 80 h : 0 to ff h : +127 18. cti (color transient improvement) the color transient can be improved by steepening the slope of the input signal. processed video without overshoot or undershoot can provide more natural video images. the cti can be switched between on and off using i2dct_ctien. the gain can be controlled using i2dct_gain. the higher the i2dct_gain is set, the more effective the cti will be. cti coring can be controlled using i2dct_corr. the higher the i2dct_corr is set, the less effective coring will be for extremely small amounts of noise. the cti?s tap parameter can be selected using i2dct_smp. the higher the i2dct_smp is set, the more the cti characteristics shift toward lower frequencies. 19. hue the hue of the screen as a whole can be adjusted. (ref er to fig.17.) the phase angle can be selected using i2dhu_hue. 0 h : -45 to 80 h : 0 to ff h : 44 (with approx. 0.7 increments) fig.17 hue r b standard plus plus standard minus minus
LC749870W no.a1957-42/45 20. u/ v gain the saturation (color density) is adjusted by varying the cb and cr gain. the cb gain can be adjusted using i2duv_ugain, and the cr gain using i2duv_vgain. 21. 8-bit output format conversion the 8-bit output format is converted to a format that is compatible with the itu-r bt.656 format output. blue back color can be output in non-signal mode using i2d65_autobback. sepia color can be output using i2d65_sepia. fig.18 timing chart (itu-r bt.656) * the processing is being performed by a 27mhz free-run clock, and so the number of pixels in one line cannot be guaranteed. the data in the period from sav to eav can be guaranteed, so read the data using the sav standard. (data cannot be read using the eav standard.) * if equipment without an itu-r bt.656 interface is connected, connect the hs and vs, or de and read the data. figure 19 timing chart (ycbcr 4:2:2) * thwbp shown in figure 19 has the same value fo r each format. it can be adjusted by registers. y0 y1 y2 y3 cb0 sav y0 cr0 y1 cr0 cr1 cb0 cb1 eav cb358 y716 cr358 y717 cb359 y718 cr359 y719 ? y719 ? y718 cr359 cb359 ? ? y715 clock 27mhz input data enable y cr cb output data enable itu-r bt.656 y0 y1 y2 y3 cb0 sav y0 cr0 y1 cr0 cr1 cb0 cb1 eav cb358 y716 cr358 y717 cb359 y718 cr359 y719 ? y719 ? y718 cr359 cb359 ? ? y715 clock 27mhz ? input data enable y cr cb ? output data enable itu-r bt.656 y0 y1 y2 y3 cb0 y0 cr0 y1 cr0 cr1 cb0 cb1 cb358 y716 cr358 y717 cb359 y718 cr359 y719 ? y719 ? y718 cr359 cb359 ? ? y715 clock 27mhz input data enable y cr cb output data enable ycbcr 4:2:2 thwbp y0 y1 y2 y3 cb0 y0 cr0 y1 cr0 cr1 cb0 cb1 cb358 y716 cr358 y717 cb359 y718 cr359 y719 ? y719 ? y718 cr359 cb359 ? ? y715 clock 27mhz ? input data enable y cr cb ? output data enable hs
LC749870W no.a1957-43/45 application example sda a in0 a in1 a in2 a in3 refpkv vrt vrb a fevrtc xin xout refnkv scl reset pdwn a v dd 33 a v ss 33 dv dd 33 dv ss data[7:0] ck0 ck13 hs vs de field intreq md0 md1 md2 test dv ss dv dd 11 10k 0.1 75 i 2 c controller 0.1 0 12pf 12pf 10
LC749870W no.a1957-44/45 other (usage precautions) 1. precaution when turning-on the power as shown in the figure belo w, start transf er of the i 2 c bus command after factoring in the power-on time (a), rst operation time (b) and command transfer start time (c). a: power-on time this is the time taken from power-on to when the *v dd 11 operating voltage has reached the lowest level (0.99v) and operation has stabilized. the power-on-time depend s on the characteristics of the power ics and other components, so it must be checked separately. with regard to *v dd 33 and *v dd 11, *v dd 11 must be turned on after *v dd 33 has turned on. b: reset operation time this is the time during which the ?l?level must be applied continuously for a period of 10ms or more to the reset pin after the pdwn is released (?h? level). c: command transfer start time at least an interval of 10ms is requi red from the time reset pin is released (?h? level) to the start of command transfer. 1.0v 0.75v dd 3.0v dv dd 33 xv dd 33 av dd 33 dv dd 11 xv dd 11 reset 0.2v dd 2v command a b c
LC749870W ps no.a1957-45/45 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. 2. precaution when turning-off the power as a basic rule, power-off must be performed in the reverse sequence of power-on. however, no problems are posed if there is no wait time. a: power-off time this is the time it takes to reach the i o supply voltage and for operation to stabilize from the lowest level (0.99v) of the *v dd 11 operating supply voltage. with regard to *v dd 33 and *v dd 11, *v dd 33 must be turned off after *v dd 11 has been turned off or they must be turned off at the same time. this catalog provides information as of june, 2011. specifications and information herein are subject to change without notice. a 3.0v dv dd 33 xv dd 33 av dd 33 0.99v dv dd 11 xv dd 11

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