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| stellaris? lm3s1p51 microcontroller data sheet copyright ? 2007-2011 texas instruments incorporated ds-lm3s1p51-9538 texas instruments-advance information
copyright copyright ? 2007-2011 texas instruments incorporated all rights reserved. stellaris and stellarisware are registered trademarks of texas instruments incorporated. arm and thumb are registered trademarks and cortex is a trademark of arm limited. other names and brands may be claimed as the property of others. advance information concerns new products in the sampling or preproduction phase of development. characteristic data and other specifcations are subject to change without notice. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. texas instruments incorporated 108 wild basin, suite 350 austin, tx 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm march 20, 2011 2 texas instruments-advance information table of contents revision history ............................................................................................................................. 28 about this document .................................................................................................................... 35 audience .............................................................................................................................................. 35 about this manual ................................................................................................................................ 35 related documents ............................................................................................................................... 35 documentation conventions .................................................................................................................. 36 1 architectural overview .......................................................................................... 38 1.1 functional overview ...................................................................................................... 40 1.1.1 arm cortex-m3 ............................................................................................................ 40 1.1.2 on-chip memory ........................................................................................................... 42 1.1.3 serial communications peripherals ................................................................................ 43 1.1.4 system integration ........................................................................................................ 47 1.1.5 advanced motion control ............................................................................................... 52 1.1.6 analog .......................................................................................................................... 54 1.1.7 jtag and arm serial wire debug ................................................................................ 56 1.1.8 packaging and temperature .......................................................................................... 56 1.2 target applications ........................................................................................................ 56 1.3 high-level block diagram ............................................................................................. 57 1.4 hardware details .......................................................................................................... 59 2 the cortex-m3 processor ...................................................................................... 60 2.1 block diagram .............................................................................................................. 61 2.2 overview ...................................................................................................................... 62 2.2.1 system-level interface .................................................................................................. 62 2.2.2 integrated configurable debug ...................................................................................... 62 2.2.3 trace port interface unit (tpiu) ..................................................................................... 63 2.2.4 cortex-m3 system component details ........................................................................... 63 2.3 programming model ...................................................................................................... 64 2.3.1 processor mode and privilege levels for software execution ........................................... 64 2.3.2 stacks .......................................................................................................................... 64 2.3.3 register map ................................................................................................................ 65 2.3.4 register descriptions .................................................................................................... 66 2.3.5 exceptions and interrupts .............................................................................................. 79 2.3.6 data types ................................................................................................................... 79 2.4 memory model .............................................................................................................. 79 2.4.1 memory regions, types and attributes ........................................................................... 81 2.4.2 memory system ordering of memory accesses .............................................................. 81 2.4.3 behavior of memory accesses ....................................................................................... 82 2.4.4 software ordering of memory accesses ......................................................................... 82 2.4.5 bit-banding ................................................................................................................... 84 2.4.6 data storage ................................................................................................................ 86 2.4.7 synchronization primitives ............................................................................................. 86 2.5 exception model ........................................................................................................... 87 2.5.1 exception states ........................................................................................................... 88 2.5.2 exception types ............................................................................................................ 88 2.5.3 exception handlers ....................................................................................................... 91 3 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 2.5.4 vector table .................................................................................................................. 92 2.5.5 exception priorities ....................................................................................................... 93 2.5.6 interrupt priority grouping .............................................................................................. 93 2.5.7 exception entry and return ........................................................................................... 93 2.6 fault handling .............................................................................................................. 95 2.6.1 fault types ................................................................................................................... 96 2.6.2 fault escalation and hard faults .................................................................................... 96 2.6.3 fault status registers and fault address registers ........................................................ 97 2.6.4 lockup ......................................................................................................................... 97 2.7 power management ...................................................................................................... 97 2.7.1 entering sleep modes ................................................................................................... 98 2.7.2 wake up from sleep mode ............................................................................................ 98 2.8 instruction set summary ............................................................................................... 99 3 cortex-m3 peripherals ......................................................................................... 103 3.1 functional description ................................................................................................. 103 3.1.1 system timer (systick) ............................................................................................... 103 3.1.2 nested vectored interrupt controller (nvic) .................................................................. 104 3.1.3 system control block (scb) ........................................................................................ 106 3.1.4 memory protection unit (mpu) ..................................................................................... 106 3.2 register map .............................................................................................................. 111 3.3 system timer (systick) register descriptions .............................................................. 113 3.4 nvic register descriptions .......................................................................................... 117 3.5 system control block (scb) register descriptions ........................................................ 130 3.6 memory protection unit (mpu) register descriptions .................................................... 159 4 jtag interface ...................................................................................................... 169 4.1 block diagram ............................................................................................................ 170 4.2 signal description ....................................................................................................... 170 4.3 functional description ................................................................................................. 171 4.3.1 jtag interface pins ..................................................................................................... 171 4.3.2 jtag tap controller ................................................................................................... 173 4.3.3 shift registers ............................................................................................................ 173 4.3.4 operational considerations .......................................................................................... 174 4.4 initialization and configuration ..................................................................................... 176 4.5 register descriptions .................................................................................................. 177 4.5.1 instruction register (ir) ............................................................................................... 177 4.5.2 data registers ............................................................................................................ 179 5 system control ..................................................................................................... 181 5.1 signal description ....................................................................................................... 181 5.2 functional description ................................................................................................. 181 5.2.1 device identification .................................................................................................... 182 5.2.2 reset control .............................................................................................................. 182 5.2.3 non-maskable interrupt ............................................................................................... 187 5.2.4 power control ............................................................................................................. 187 5.2.5 clock control .............................................................................................................. 188 5.2.6 system control ........................................................................................................... 195 5.3 initialization and configuration ..................................................................................... 197 5.4 register map .............................................................................................................. 197 5.5 register descriptions .................................................................................................. 199 march 20, 2011 4 texas instruments-advance information table of contents 6 hibernation module .............................................................................................. 282 6.1 block diagram ............................................................................................................ 283 6.2 signal description ....................................................................................................... 283 6.3 functional description ................................................................................................. 284 6.3.1 register access timing ............................................................................................... 285 6.3.2 hibernation clock source ............................................................................................ 285 6.3.3 battery management ................................................................................................... 287 6.3.4 real-time clock .......................................................................................................... 287 6.3.5 non-volatile memory ................................................................................................... 288 6.3.6 power control using hib ............................................................................................. 288 6.3.7 power control using vdd3on mode ........................................................................... 288 6.3.8 initiating hibernate ...................................................................................................... 288 6.3.9 interrupts and status ................................................................................................... 289 6.4 initialization and configuration ..................................................................................... 289 6.4.1 initialization ................................................................................................................. 289 6.4.2 rtc match functionality (no hibernation) .................................................................... 290 6.4.3 rtc match/wake-up from hibernation ......................................................................... 290 6.4.4 external wake-up from hibernation .............................................................................. 291 6.4.5 rtc or external wake-up from hibernation .................................................................. 291 6.4.6 register reset ............................................................................................................ 291 6.5 register map .............................................................................................................. 292 6.6 register descriptions .................................................................................................. 293 7 internal memory ................................................................................................... 310 7.1 block diagram ............................................................................................................ 310 7.2 functional description ................................................................................................. 310 7.2.1 sram ........................................................................................................................ 311 7.2.2 rom .......................................................................................................................... 311 7.2.3 flash memory ............................................................................................................. 313 7.3 register map .............................................................................................................. 317 7.4 flash memory register descriptions (flash control offset) ............................................ 318 7.5 memory register descriptions (system control offset) .................................................. 330 8 micro direct memory access (dma) ................................................................ 346 8.1 block diagram ............................................................................................................ 347 8.2 functional description ................................................................................................. 347 8.2.1 channel assignments .................................................................................................. 348 8.2.2 priority ........................................................................................................................ 349 8.2.3 arbitration size ............................................................................................................ 349 8.2.4 request types ............................................................................................................ 349 8.2.5 channel configuration ................................................................................................. 350 8.2.6 transfer modes ........................................................................................................... 352 8.2.7 transfer size and increment ........................................................................................ 360 8.2.8 peripheral interface ..................................................................................................... 360 8.2.9 software request ........................................................................................................ 360 8.2.10 interrupts and errors .................................................................................................... 361 8.3 initialization and configuration ..................................................................................... 361 8.3.1 module initialization ..................................................................................................... 361 8.3.2 configuring a memory-to-memory transfer ................................................................... 361 8.3.3 configuring a peripheral for simple transmit ................................................................ 363 5 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 8.3.4 configuring a peripheral for ping-pong receive ............................................................ 364 8.3.5 configuring channel assignments ................................................................................ 367 8.4 register map .............................................................................................................. 367 8.5 dma channel control structure ................................................................................. 368 8.6 dma register descriptions ........................................................................................ 375 9 general-purpose input/outputs (gpios) ........................................................... 404 9.1 signal description ....................................................................................................... 404 9.2 functional description ................................................................................................. 409 9.2.1 data control ............................................................................................................... 410 9.2.2 interrupt control .......................................................................................................... 411 9.2.3 mode control .............................................................................................................. 412 9.2.4 commit control ........................................................................................................... 412 9.2.5 pad control ................................................................................................................. 413 9.2.6 identification ............................................................................................................... 413 9.3 initialization and configuration ..................................................................................... 413 9.4 register map .............................................................................................................. 414 9.5 register descriptions .................................................................................................. 417 10 general-purpose timers ...................................................................................... 460 10.1 block diagram ............................................................................................................ 461 10.2 signal description ....................................................................................................... 461 10.3 functional description ................................................................................................. 464 10.3.1 gptm reset conditions .............................................................................................. 465 10.3.2 timer modes ............................................................................................................... 465 10.3.3 dma operation ........................................................................................................... 470 10.3.4 accessing concatenated register values ..................................................................... 471 10.4 initialization and configuration ..................................................................................... 471 10.4.1 one-shot/periodic timer mode .................................................................................... 471 10.4.2 real-time clock (rtc) mode ...................................................................................... 472 10.4.3 input edge-count mode ............................................................................................... 472 10.4.4 input edge timing mode .............................................................................................. 473 10.4.5 pwm mode ................................................................................................................. 473 10.5 register map .............................................................................................................. 474 10.6 register descriptions .................................................................................................. 475 11 watchdog timers ................................................................................................. 506 11.1 block diagram ............................................................................................................ 507 11.2 functional description ................................................................................................. 507 11.2.1 register access timing ............................................................................................... 508 11.3 initialization and configuration ..................................................................................... 508 11.4 register map .............................................................................................................. 508 11.5 register descriptions .................................................................................................. 509 12 analog-to-digital converter (adc) ..................................................................... 531 12.1 block diagram ............................................................................................................ 532 12.2 signal description ....................................................................................................... 533 12.3 functional description ................................................................................................. 535 12.3.1 sample sequencers .................................................................................................... 535 12.3.2 module control ............................................................................................................ 536 12.3.3 hardware sample averaging circuit ............................................................................. 538 march 20, 2011 6 texas instruments-advance information table of contents 12.3.4 analog-to-digital converter .......................................................................................... 539 12.3.5 differential sampling ................................................................................................... 541 12.3.6 internal temperature sensor ........................................................................................ 544 12.3.7 digital comparator unit ............................................................................................... 544 12.4 initialization and configuration ..................................................................................... 549 12.4.1 module initialization ..................................................................................................... 549 12.4.2 sample sequencer configuration ................................................................................. 550 12.5 register map .............................................................................................................. 550 12.6 register descriptions .................................................................................................. 552 13 universal asynchronous receivers/transmitters (uarts) ............................. 610 13.1 block diagram ............................................................................................................ 611 13.2 signal description ....................................................................................................... 611 13.3 functional description ................................................................................................. 613 13.3.1 transmit/receive logic ............................................................................................... 613 13.3.2 baud-rate generation ................................................................................................. 614 13.3.3 data transmission ...................................................................................................... 615 13.3.4 serial ir (sir) ............................................................................................................. 615 13.3.5 iso 7816 support ....................................................................................................... 616 13.3.6 modem handshake support ......................................................................................... 616 13.3.7 lin support ................................................................................................................ 618 13.3.8 fifo operation ........................................................................................................... 619 13.3.9 interrupts .................................................................................................................... 619 13.3.10 loopback operation .................................................................................................... 620 13.3.11 dma operation ........................................................................................................... 620 13.4 initialization and configuration ..................................................................................... 621 13.5 register map .............................................................................................................. 622 13.6 register descriptions .................................................................................................. 623 14 synchronous serial interface (ssi) .................................................................... 671 14.1 block diagram ............................................................................................................ 672 14.2 signal description ....................................................................................................... 672 14.3 functional description ................................................................................................. 673 14.3.1 bit rate generation ..................................................................................................... 674 14.3.2 fifo operation ........................................................................................................... 674 14.3.3 interrupts .................................................................................................................... 674 14.3.4 frame formats ........................................................................................................... 675 14.3.5 dma operation ........................................................................................................... 683 14.4 initialization and configuration ..................................................................................... 683 14.5 register map .............................................................................................................. 685 14.6 register descriptions .................................................................................................. 686 15 inter-integrated circuit (i 2 c) interface ................................................................ 714 15.1 block diagram ............................................................................................................ 715 15.2 signal description ....................................................................................................... 715 15.3 functional description ................................................................................................. 716 15.3.1 i 2 c bus functional overview ........................................................................................ 716 15.3.2 available speed modes ............................................................................................... 718 15.3.3 interrupts .................................................................................................................... 719 15.3.4 loopback operation .................................................................................................... 720 15.3.5 command sequence flow charts ................................................................................ 721 7 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 15.4 initialization and configuration ..................................................................................... 728 15.5 register map .............................................................................................................. 729 15.6 register descriptions (i 2 c master) ............................................................................... 730 15.7 register descriptions (i 2 c slave) ................................................................................. 742 16 inter-integrated circuit sound (i 2 s) interface .................................................... 751 16.1 block diagram ............................................................................................................ 752 16.2 signal description ....................................................................................................... 752 16.3 functional description ................................................................................................. 754 16.3.1 transmit ..................................................................................................................... 755 16.3.2 receive ...................................................................................................................... 759 16.4 initialization and configuration ..................................................................................... 761 16.5 register map .............................................................................................................. 762 16.6 register descriptions .................................................................................................. 763 17 analog comparators ............................................................................................ 787 17.1 block diagram ............................................................................................................ 787 17.2 signal description ....................................................................................................... 788 17.3 functional description ................................................................................................. 789 17.3.1 internal reference programming .................................................................................. 789 17.4 initialization and configuration ..................................................................................... 791 17.5 register map .............................................................................................................. 791 17.6 register descriptions .................................................................................................. 792 18 pulse width modulator (pwm) ............................................................................ 800 18.1 block diagram ............................................................................................................ 801 18.2 signal description ....................................................................................................... 802 18.3 functional description ................................................................................................. 805 18.3.1 pwm timer ................................................................................................................. 805 18.3.2 pwm comparators ...................................................................................................... 805 18.3.3 pwm signal generator ................................................................................................ 807 18.3.4 dead-band generator ................................................................................................. 808 18.3.5 interrupt/adc-trigger selector ..................................................................................... 808 18.3.6 synchronization methods ............................................................................................ 808 18.3.7 fault conditions .......................................................................................................... 809 18.3.8 output control block ................................................................................................... 810 18.4 initialization and configuration ..................................................................................... 811 18.5 register map .............................................................................................................. 811 18.6 register descriptions .................................................................................................. 814 19 quadrature encoder interface (qei) ................................................................... 873 19.1 block diagram ............................................................................................................ 873 19.2 signal description ....................................................................................................... 874 19.3 functional description ................................................................................................. 875 19.4 initialization and configuration ..................................................................................... 878 19.5 register map .............................................................................................................. 878 19.6 register descriptions .................................................................................................. 879 20 pin diagram .......................................................................................................... 896 21 signal tables ........................................................................................................ 898 21.1 100-pin lqfp package pin tables ............................................................................... 899 21.2 108-pin bga package pin tables ................................................................................ 930 march 20, 2011 8 texas instruments-advance information table of contents 21.3 connections for unused signals ................................................................................... 961 22 operating characteristics ................................................................................... 963 23 electrical characteristics .................................................................................... 964 23.1 dc characteristics ...................................................................................................... 964 23.1.1 maximum ratings ....................................................................................................... 964 23.1.2 recommended dc operating conditions ...................................................................... 964 23.1.3 on-chip low drop-out (ldo) regulator characteristics ................................................ 965 23.1.4 hibernation module characteristics .............................................................................. 965 23.1.5 flash memory characteristics ...................................................................................... 965 23.1.6 gpio module characteristics ....................................................................................... 966 23.1.7 current specifications .................................................................................................. 966 23.2 ac characteristics ....................................................................................................... 970 23.2.1 load conditions .......................................................................................................... 970 23.2.2 clocks ........................................................................................................................ 970 23.2.3 power and brown-out characteristics ........................................................................... 973 23.2.4 jtag and boundary scan ............................................................................................ 975 23.2.5 reset ......................................................................................................................... 976 23.2.6 sleep modes ............................................................................................................... 977 23.2.7 hibernation module ..................................................................................................... 978 23.2.8 general-purpose i/o (gpio) ........................................................................................ 979 23.2.9 analog-to-digital converter (adc) ................................................................................ 980 23.2.10 synchronous serial interface (ssi) ............................................................................... 981 23.2.11 inter-integrated circuit (i 2 c) interface ........................................................................... 983 23.2.12 inter-integrated circuit sound (i 2 s) interface ................................................................. 984 23.2.13 analog comparator ..................................................................................................... 985 a register quick reference ................................................................................... 987 b ordering and contact information ................................................................... 1017 b.1 ordering information .................................................................................................. 1017 b.2 part markings ............................................................................................................ 1017 b.3 kits ........................................................................................................................... 1018 b.4 support information ................................................................................................... 1018 c package information .......................................................................................... 1019 c.1 100-pin lqfp package ............................................................................................. 1019 c.1.1 package dimensions ................................................................................................. 1019 c.1.2 tray dimensions ....................................................................................................... 1021 c.1.3 tape and reel dimensions ........................................................................................ 1021 c.2 108-ball bga package .............................................................................................. 1023 c.2.1 package dimensions ................................................................................................. 1023 c.2.2 tray dimensions ....................................................................................................... 1025 c.2.3 tape and reel dimensions ........................................................................................ 1026 9 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller list of figures figure 1-1. stellaris lm3s1p51 microcontroller high-level block diagram .............................. 58 figure 2-1. cpu block diagram ............................................................................................. 62 figure 2-2. tpiu block diagram ............................................................................................ 63 figure 2-3. cortex-m3 register set ........................................................................................ 65 figure 2-4. bit-band mapping ................................................................................................ 85 figure 2-5. data storage ....................................................................................................... 86 figure 2-6. vector table ......................................................................................................... 92 figure 2-7. exception stack frame ........................................................................................ 94 figure 3-1. srd use example ............................................................................................. 109 figure 4-1. jtag module block diagram .............................................................................. 170 figure 4-2. test access port state machine ......................................................................... 173 figure 4-3. idcode register format ................................................................................... 179 figure 4-4. bypass register format ................................................................................... 179 figure 4-5. boundary scan register format ......................................................................... 180 figure 5-1. basic rst configuration .................................................................................... 184 figure 5-2. external circuitry to extend power-on reset ....................................................... 184 figure 5-3. reset circuit controlled by switch ...................................................................... 185 figure 5-4. power architecture ............................................................................................ 188 figure 5-5. main clock tree ................................................................................................ 191 figure 6-1. hibernation module block diagram ..................................................................... 283 figure 6-2. using a crystal as the hibernation clock source ................................................. 286 figure 6-3. using a dedicated oscillator as the hibernation clock source with vdd3on mode ................................................................................................................ 286 figure 7-1. internal memory block diagram .......................................................................... 310 figure 8-1. dma block diagram ......................................................................................... 347 figure 8-2. example of ping-pong dma transaction ........................................................... 353 figure 8-3. memory scatter-gather, setup and configuration ................................................ 355 figure 8-4. memory scatter-gather, dma copy sequence .................................................. 356 figure 8-5. peripheral scatter-gather, setup and configuration ............................................. 358 figure 8-6. peripheral scatter-gather, dma copy sequence ............................................... 359 figure 9-1. digital i/o pads ................................................................................................. 409 figure 9-2. analog/digital i/o pads ...................................................................................... 410 figure 9-3. gpiodata write example ................................................................................. 411 figure 9-4. gpiodata read example ................................................................................. 411 figure 10-1. gptm module block diagram ............................................................................ 461 figure 10-2. timer daisy chain ............................................................................................. 467 figure 10-3. input edge-count mode example ....................................................................... 468 figure 10-4. 16-bit input edge-time mode example ............................................................... 469 figure 10-5. 16-bit pwm mode example ................................................................................ 470 figure 11-1. wdt module block diagram .............................................................................. 507 figure 12-1. implementation of two adc blocks .................................................................... 532 figure 12-2. adc module block diagram ............................................................................... 533 figure 12-3. adc sample phases ......................................................................................... 537 figure 12-4. doubling the adc sample rate .......................................................................... 538 figure 12-5. skewed sampling .............................................................................................. 538 figure 12-6. sample averaging example ............................................................................... 539 march 20, 2011 10 texas instruments-advance information table of contents figure 12-7. internal voltage conversion result ..................................................................... 540 figure 12-8. external voltage conversion result .................................................................... 541 figure 12-9. differential sampling range, v in_odd = 1.5 v ...................................................... 542 figure 12-10. differential sampling range, v in_odd = 0.75 v .................................................... 543 figure 12-11. differential sampling range, v in_odd = 2.25 v .................................................... 543 figure 12-12. internal temperature sensor characteristic ......................................................... 544 figure 12-13. low-band operation (cic=0x0 and/or ctc=0x0) ................................................ 547 figure 12-14. mid-band operation (cic=0x1 and/or ctc=0x1) ................................................. 548 figure 12-15. high-band operation (cic=0x3 and/or ctc=0x3) ................................................ 549 figure 13-1. uart module block diagram ............................................................................. 611 figure 13-2. uart character frame ..................................................................................... 614 figure 13-3. irda data modulation ......................................................................................... 616 figure 13-4. lin message ..................................................................................................... 618 figure 13-5. lin synchronization field ................................................................................... 619 figure 14-1. ssi module block diagram ................................................................................. 672 figure 14-2. ti synchronous serial frame format (single transfer) ........................................ 676 figure 14-3. ti synchronous serial frame format (continuous transfer) ................................ 677 figure 14-4. freescale spi format (single transfer) with spo=0 and sph=0 .......................... 677 figure 14-5. freescale spi format (continuous transfer) with spo=0 and sph=0 .................. 678 figure 14-6. freescale spi frame format with spo=0 and sph=1 ......................................... 679 figure 14-7. freescale spi frame format (single transfer) with spo=1 and sph=0 ............... 679 figure 14-8. freescale spi frame format (continuous transfer) with spo=1 and sph=0 ........ 680 figure 14-9. freescale spi frame format with spo=1 and sph=1 ......................................... 681 figure 14-10. microwire frame format (single frame) ........................................................ 681 figure 14-11. microwire frame format (continuous transfer) ............................................. 682 figure 14-12. microwire frame format, ssifss input setup and hold requirements ............ 683 figure 15-1. i 2 c block diagram ............................................................................................. 715 figure 15-2. i 2 c bus configuration ........................................................................................ 716 figure 15-3. start and stop conditions ............................................................................. 717 figure 15-4. complete data transfer with a 7-bit address ....................................................... 717 figure 15-5. r/s bit in first byte ............................................................................................ 718 figure 15-6. data validity during bit transfer on the i 2 c bus ................................................... 718 figure 15-7. master single transmit .................................................................................. 722 figure 15-8. master single receive ..................................................................................... 723 figure 15-9. master transmit with repeated start ........................................................... 724 figure 15-10. master receive with repeated start ............................................................. 725 figure 15-11. master receive with repeated start after transmit with repeated start .............................................................................................................. 726 figure 15-12. master transmit with repeated start after receive with repeated start .............................................................................................................. 727 figure 15-13. slave command sequence ................................................................................ 728 figure 16-1. i 2 s block diagram ............................................................................................. 752 figure 16-2. i 2 s data transfer ............................................................................................... 755 figure 16-3. left-justified data transfer ................................................................................ 755 figure 16-4. right-justified data transfer .............................................................................. 755 figure 17-1. analog comparator module block diagram ......................................................... 787 figure 17-2. structure of comparator unit .............................................................................. 789 figure 17-3. comparator internal reference structure ............................................................ 790 11 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 18-1. pwm module diagram ....................................................................................... 802 figure 18-2. pwm generator block diagram .......................................................................... 802 figure 18-3. pwm count-down mode .................................................................................... 806 figure 18-4. pwm count-up/down mode .............................................................................. 807 figure 18-5. pwm generation example in count-up/down mode ........................................... 807 figure 18-6. pwm dead-band generator ............................................................................... 808 figure 19-1. qei block diagram ............................................................................................ 874 figure 19-2. quadrature encoder and velocity predivider operation ........................................ 877 figure 20-1. 100-pin lqfp package pin diagram .................................................................. 896 figure 20-2. 108-ball bga package pin diagram (top view) ................................................... 897 figure 23-1. typical current across frequency, pll bypassed ............................................... 969 figure 23-2. typical current across frequency, using pll ..................................................... 970 figure 23-3. load conditions ................................................................................................ 970 figure 23-4. power-on reset timing ..................................................................................... 973 figure 23-5. brown-out reset timing .................................................................................... 974 figure 23-6. power-on reset and voltage parameters ........................................................... 974 figure 23-7. voltage requirements when using an external v ddc source ............................... 975 figure 23-8. jtag test clock input timing ............................................................................. 976 figure 23-9. jtag test access port (tap) timing .................................................................. 976 figure 23-10. external reset timing (rst ) .............................................................................. 977 figure 23-11. software reset timing ....................................................................................... 977 figure 23-12. watchdog reset timing ..................................................................................... 977 figure 23-13. mosc failure reset timing ............................................................................... 977 figure 23-14. hibernation module timing with internal oscillator running in hibernation ............ 978 figure 23-15. hibernation module timing with internal oscillator stopped in hibernation ............ 979 figure 23-16. vdd ramp when waking from hibernation ......................................................... 979 figure 23-17. adc input equivalency diagram ......................................................................... 981 figure 23-18. ssi timing for ti frame format (frf=01), single transfer timing measurement .................................................................................................... 982 figure 23-19. ssi timing for microwire frame format (frf=10), single transfer ................. 982 figure 23-20. ssi timing for spi frame format (frf=00), with sph=1 ..................................... 983 figure 23-21. i 2 c timing ......................................................................................................... 984 figure 23-22. i 2 s master mode transmit timing ....................................................................... 984 figure 23-23. i 2 s master mode receive timing ........................................................................ 985 figure 23-24. i 2 s slave mode transmit timing ......................................................................... 985 figure 23-25. i 2 s slave mode receive timing .......................................................................... 985 figure c-1. 100-pin lqfp package dimensions ................................................................. 1019 figure c-2. 100-pin lqfp tray dimensions ........................................................................ 1021 figure c-3. 100-pin lqfp tape and reel dimensions ......................................................... 1022 figure c-4. 108-ball bga package dimensions .................................................................. 1023 figure c-5. 108-ball bga tray dimensions ......................................................................... 1025 figure c-6. 108-ball bga tape and reel dimensions .......................................................... 1026 march 20, 2011 12 texas instruments-advance information table of contents list of tables table 1. revision history .................................................................................................. 28 table 2. documentation conventions ................................................................................ 36 table 2-1. summary of processor mode, privilege level, and stack use ................................ 65 table 2-2. processor register map ....................................................................................... 66 table 2-3. psr register combinations ................................................................................. 71 table 2-4. memory map ....................................................................................................... 79 table 2-5. memory access behavior ..................................................................................... 82 table 2-6. sram memory bit-banding regions .................................................................... 84 table 2-7. peripheral memory bit-banding regions ............................................................... 84 table 2-8. exception types .................................................................................................. 90 table 2-9. interrupts ............................................................................................................ 90 table 2-10. exception return behavior ................................................................................... 95 table 2-11. faults ................................................................................................................. 96 table 2-12. fault status and fault address registers .............................................................. 97 table 2-13. cortex-m3 instruction summary ........................................................................... 99 table 3-1. core peripheral register regions ....................................................................... 103 table 3-2. memory attributes summary .............................................................................. 106 table 3-3. tex, s, c, and b bit field encoding ................................................................... 109 table 3-4. cache policy for memory attribute encoding ....................................................... 110 table 3-5. ap bit field encoding ........................................................................................ 110 table 3-6. memory region attributes for stellaris microcontrollers ........................................ 110 table 3-7. peripherals register map ................................................................................... 111 table 3-8. interrupt priority levels ...................................................................................... 138 table 3-9. example size field values ................................................................................ 166 table 4-1. signals for jtag_swd_swo (100lqfp) ........................................................... 170 table 4-2. signals for jtag_swd_swo (108bga) ............................................................ 171 table 4-3. jtag port pins state after power-on reset or rst assertion .............................. 172 table 4-4. jtag instruction register commands ................................................................. 177 table 5-1. signals for system control & clocks (100lqfp) .................................................. 181 table 5-2. signals for system control & clocks (108bga) ................................................... 181 table 5-3. reset sources ................................................................................................... 182 table 5-4. clock source options ........................................................................................ 189 table 5-5. possible system clock frequencies using the sysdiv field ............................... 192 table 5-6. examples of possible system clock frequencies using the sysdiv2 field .......... 192 table 5-7. examples of possible system clock frequencies with div400=1 ......................... 193 table 5-8. system control register map ............................................................................. 198 table 5-9. rcc2 fields that override rcc fields ............................................................... 218 table 6-1. signals for hibernate (100lqfp) ........................................................................ 283 table 6-2. signals for hibernate (108bga) .......................................................................... 284 table 6-3. hibernation module clock operation ................................................................... 290 table 6-4. hibernation module register map ....................................................................... 292 table 7-1. flash memory protection policy combinations .................................................... 314 table 7-2. user-programmable flash memory resident registers ....................................... 317 table 7-3. flash register map ............................................................................................ 318 table 8-1. dma channel assignments .............................................................................. 348 table 8-2. request type support ....................................................................................... 350 13 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 8-3. control structure memory map ........................................................................... 351 table 8-4. channel control structure .................................................................................. 351 table 8-5. dma read example: 8-bit peripheral ................................................................ 360 table 8-6. dma interrupt assignments .............................................................................. 361 table 8-7. channel control structure offsets for channel 30 ................................................ 362 table 8-8. channel control word configuration for memory transfer example ...................... 362 table 8-9. channel control structure offsets for channel 7 .................................................. 363 table 8-10. channel control word configuration for peripheral transmit example .................. 364 table 8-11. primary and alternate channel control structure offsets for channel 8 ................. 365 table 8-12. channel control word configuration for peripheral ping-pong receive example ............................................................................................................ 366 table 8-13. dma register map .......................................................................................... 367 table 9-1. gpio pins with non-zero reset values .............................................................. 405 table 9-2. gpio pins and alternate functions (100lqfp) ................................................... 405 table 9-3. gpio pins and alternate functions (108bga) ..................................................... 407 table 9-4. gpio pad configuration examples ..................................................................... 413 table 9-5. gpio interrupt configuration example ................................................................ 414 table 9-6. gpio pins with non-zero reset values .............................................................. 415 table 9-7. gpio register map ........................................................................................... 415 table 9-8. gpio pins with non-zero reset values .............................................................. 428 table 9-9. gpio pins with non-zero reset values .............................................................. 434 table 9-10. gpio pins with non-zero reset values .............................................................. 436 table 9-11. gpio pins with non-zero reset values .............................................................. 439 table 9-12. gpio pins with non-zero reset values .............................................................. 446 table 10-1. available ccp pins ............................................................................................ 461 table 10-2. signals for general-purpose timers (100lqfp) .................................................. 462 table 10-3. signals for general-purpose timers (108bga) .................................................... 463 table 10-4. general-purpose timer capabilities .................................................................... 464 table 10-5. 16-bit timer with prescaler configurations ......................................................... 466 table 10-6. timers register map .......................................................................................... 474 table 11-1. watchdog timers register map .......................................................................... 509 table 12-1. signals for adc (100lqfp) ............................................................................... 533 table 12-2. signals for adc (108bga) ................................................................................. 534 table 12-3. samples and fifo depth of sequencers ............................................................ 535 table 12-4. differential sampling pairs ................................................................................. 541 table 12-5. adc register map ............................................................................................. 550 table 13-1. signals for uart (100lqfp) ............................................................................. 612 table 13-2. signals for uart (108bga) ............................................................................... 612 table 13-3. flow control mode ............................................................................................. 617 table 13-4. uart register map ........................................................................................... 622 table 14-1. signals for ssi (100lqfp) ................................................................................. 673 table 14-2. signals for ssi (108bga) ................................................................................... 673 table 14-3. ssi register map .............................................................................................. 685 table 15-1. signals for i2c (100lqfp) ................................................................................. 715 table 15-2. signals for i2c (108bga) ................................................................................... 715 table 15-3. examples of i 2 c master timer period versus speed mode ................................... 719 table 15-4. inter-integrated circuit (i 2 c) interface register map ............................................. 729 table 15-5. write field decoding for i2cmcs[3:0] field ......................................................... 734 march 20, 2011 14 texas instruments-advance information table of contents table 16-1. signals for i2s (100lqfp) ................................................................................. 753 table 16-2. signals for i2s (108bga) ................................................................................... 753 table 16-3. i 2 s transmit fifo interface ................................................................................ 756 table 16-4. crystal frequency (values from 3.5795 mhz to 5 mhz) ........................................ 757 table 16-5. crystal frequency (values from 5.12 mhz to 8.192 mhz) ..................................... 757 table 16-6. crystal frequency (values from 10 mhz to 14.3181 mhz) .................................... 758 table 16-7. crystal frequency (values from 16 mhz to 16.384 mhz) ...................................... 758 table 16-8. i 2 s receive fifo interface ................................................................................. 760 table 16-9. audio formats configuration .............................................................................. 762 table 16-10. inter-integrated circuit sound (i 2 s) interface register map ................................... 763 table 17-1. signals for analog comparators (100lqfp) ........................................................ 788 table 17-2. signals for analog comparators (108bga) .......................................................... 788 table 17-3. internal reference voltage and acrefctl field values ..................................... 790 table 17-4. analog comparators register map ..................................................................... 791 table 18-1. signals for pwm (100lqfp) .............................................................................. 803 table 18-2. signals for pwm (108bga) ................................................................................ 804 table 18-3. pwm register map ............................................................................................ 812 table 19-1. signals for qei (100lqfp) ................................................................................. 874 table 19-2. signals for qei (108bga) .................................................................................. 875 table 19-3. qei register map .............................................................................................. 879 table 21-1. gpio pins with default alternate functions ........................................................ 898 table 21-2. signals by pin number ....................................................................................... 899 table 21-3. signals by signal name ..................................................................................... 909 table 21-4. signals by function, except for gpio ................................................................. 917 table 21-5. gpio pins and alternate functions ..................................................................... 925 table 21-6. possible pin assignments for alternate functions ................................................ 928 table 21-7. signals by pin number ....................................................................................... 930 table 21-8. signals by signal name ..................................................................................... 940 table 21-9. signals by function, except for gpio ................................................................. 949 table 21-10. gpio pins and alternate functions ..................................................................... 956 table 21-11. possible pin assignments for alternate functions ................................................ 959 table 21-12. connections for unused signals (100-pin lqfp) ................................................. 961 table 21-13. connections for unused signals, 108-pin bga .................................................... 961 table 22-1. temperature characteristics ............................................................................... 963 table 22-2. thermal characteristics ..................................................................................... 963 table 22-3. esd absolute maximum ratings ........................................................................ 963 table 23-1. maximum ratings .............................................................................................. 964 table 23-2. recommended dc operating conditions ............................................................ 964 table 23-3. ldo regulator characteristics ........................................................................... 965 table 23-4. hibernation module dc characteristics ............................................................... 965 table 23-5. flash memory characteristics ............................................................................ 965 table 23-6. gpio module dc characteristics ........................................................................ 966 table 23-7. nominal power consumption ............................................................................. 966 table 23-8. detailed current specifications ........................................................................... 967 table 23-9. hibernation detailed current specifications ......................................................... 968 table 23-10. external v ddc source current specifications ....................................................... 968 table 23-11. current consumption vs. frequency, pll bypassed ............................................ 969 table 23-12. current consumption vs. frequency, using pll .................................................. 969 15 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 23-13. phase locked loop (pll) characteristics ........................................................... 971 table 23-14. actual pll frequency ........................................................................................ 971 table 23-15. piosc clock characteristics .............................................................................. 971 table 23-16. 30-khz clock characteristics .............................................................................. 972 table 23-17. hibernation clock characteristics ....................................................................... 972 table 23-18. hib oscillator input characteristics ..................................................................... 972 table 23-19. main oscillator clock characteristics .................................................................. 972 table 23-20. mosc oscillator input characteristics ................................................................ 973 table 23-21. system clock characteristics with adc operation ............................................... 973 table 23-22. power characteristics ........................................................................................ 973 table 23-23. jtag characteristics ......................................................................................... 975 table 23-24. reset characteristics ......................................................................................... 976 table 23-25. sleep modes ac characteristics ......................................................................... 977 table 23-26. hibernation module ac characteristics ............................................................... 978 table 23-27. gpio characteristics ......................................................................................... 979 table 23-28. adc characteristics ........................................................................................... 980 table 23-29. adc module external reference characteristics ................................................. 981 table 23-30. adc module internal reference characteristics .................................................. 981 table 23-31. ssi characteristics ............................................................................................ 981 table 23-32. i 2 c characteristics ............................................................................................. 983 table 23-33. i 2 s master clock (receive and transmit) ............................................................ 984 table 23-34. i 2 s slave clock (receive and transmit) .............................................................. 984 table 23-35. i 2 s master mode ................................................................................................ 984 table 23-36. i 2 s slave mode ................................................................................................. 985 table 23-37. analog comparator characteristics ..................................................................... 985 table 23-38. analog comparator voltage reference characteristics ........................................ 986 table b-1. part ordering information ................................................................................. 1017 march 20, 2011 16 texas instruments-advance information table of contents list of registers the cortex-m3 processor ............................................................................................................. 60 register 1: cortex general-purpose register 0 (r0) ........................................................................... 67 register 2: cortex general-purpose register 1 (r1) ........................................................................... 67 register 3: cortex general-purpose register 2 (r2) ........................................................................... 67 register 4: cortex general-purpose register 3 (r3) ........................................................................... 67 register 5: cortex general-purpose register 4 (r4) ........................................................................... 67 register 6: cortex general-purpose register 5 (r5) ........................................................................... 67 register 7: cortex general-purpose register 6 (r6) ........................................................................... 67 register 8: cortex general-purpose register 7 (r7) ........................................................................... 67 register 9: cortex general-purpose register 8 (r8) ........................................................................... 67 register 10: cortex general-purpose register 9 (r9) ........................................................................... 67 register 11: cortex general-purpose register 10 (r10) ....................................................................... 67 register 12: cortex general-purpose register 11 (r11) ........................................................................ 67 register 13: cortex general-purpose register 12 (r12) ....................................................................... 67 register 14: stack pointer (sp) ........................................................................................................... 68 register 15: link register (lr) ............................................................................................................ 69 register 16: program counter (pc) ..................................................................................................... 70 register 17: program status register (psr) ........................................................................................ 71 register 18: priority mask register (primask) .................................................................................... 75 register 19: fault mask register (faultmask) .................................................................................. 76 register 20: base priority mask register (basepri) ............................................................................ 77 register 21: control register (control) ........................................................................................... 78 cortex-m3 peripherals ................................................................................................................. 103 register 1: systick control and status register (stctrl), offset 0x010 ........................................... 114 register 2: systick reload value register (streload), offset 0x014 .............................................. 116 register 3: systick current value register (stcurrent), offset 0x018 ........................................... 117 register 4: interrupt 0-31 set enable (en0), offset 0x100 .................................................................. 118 register 5: interrupt 32-54 set enable (en1), offset 0x104 ................................................................ 119 register 6: interrupt 0-31 clear enable (dis0), offset 0x180 .............................................................. 120 register 7: interrupt 32-54 clear enable (dis1), offset 0x184 ............................................................ 121 register 8: interrupt 0-31 set pending (pend0), offset 0x200 ........................................................... 122 register 9: interrupt 32-54 set pending (pend1), offset 0x204 ......................................................... 123 register 10: interrupt 0-31 clear pending (unpend0), offset 0x280 ................................................... 124 register 11: interrupt 32-54 clear pending (unpend1), offset 0x284 .................................................. 125 register 12: interrupt 0-31 active bit (active0), offset 0x300 ............................................................. 126 register 13: interrupt 32-54 active bit (active1), offset 0x304 ........................................................... 127 register 14: interrupt 0-3 priority (pri0), offset 0x400 ......................................................................... 128 register 15: interrupt 4-7 priority (pri1), offset 0x404 ......................................................................... 128 register 16: interrupt 8-11 priority (pri2), offset 0x408 ....................................................................... 128 register 17: interrupt 12-15 priority (pri3), offset 0x40c .................................................................... 128 register 18: interrupt 16-19 priority (pri4), offset 0x410 ..................................................................... 128 register 19: interrupt 20-23 priority (pri5), offset 0x414 ..................................................................... 128 register 20: interrupt 24-27 priority (pri6), offset 0x418 ..................................................................... 128 register 21: interrupt 28-31 priority (pri7), offset 0x41c .................................................................... 128 register 22: interrupt 32-35 priority (pri8), offset 0x420 ..................................................................... 128 17 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 23: interrupt 36-39 priority (pri9), offset 0x424 ..................................................................... 128 register 24: interrupt 40-43 priority (pri10), offset 0x428 ................................................................... 128 register 25: interrupt 44-47 priority (pri11), offset 0x42c ................................................................... 128 register 26: interrupt 48-51 priority (pri12), offset 0x430 ................................................................... 128 register 27: interrupt 52-54 priority (pri13), offset 0x434 ................................................................... 128 register 28: software trigger interrupt (swtrig), offset 0xf00 .......................................................... 130 register 29: auxiliary control (actlr), offset 0x008 .......................................................................... 131 register 30: cpu id base (cpuid), offset 0xd00 ............................................................................... 133 register 31: interrupt control and state (intctrl), offset 0xd04 ........................................................ 134 register 32: vector table offset (vtable), offset 0xd08 .................................................................... 137 register 33: application interrupt and reset control (apint), offset 0xd0c ......................................... 138 register 34: system control (sysctrl), offset 0xd10 ....................................................................... 140 register 35: configuration and control (cfgctrl), offset 0xd14 ....................................................... 142 register 36: system handler priority 1 (syspri1), offset 0xd18 ......................................................... 144 register 37: system handler priority 2 (syspri2), offset 0xd1c ........................................................ 145 register 38: system handler priority 3 (syspri3), offset 0xd20 ......................................................... 146 register 39: system handler control and state (syshndctrl), offset 0xd24 .................................... 147 register 40: configurable fault status (faultstat), offset 0xd28 ..................................................... 151 register 41: hard fault status (hfaultstat), offset 0xd2c .............................................................. 157 register 42: memory management fault address (mmaddr), offset 0xd34 ........................................ 158 register 43: bus fault address (faultaddr), offset 0xd38 .............................................................. 159 register 44: mpu type (mputype), offset 0xd90 ............................................................................. 160 register 45: mpu control (mpuctrl), offset 0xd94 .......................................................................... 161 register 46: mpu region number (mpunumber), offset 0xd98 ....................................................... 163 register 47: mpu region base address (mpubase), offset 0xd9c ................................................... 164 register 48: mpu region base address alias 1 (mpubase1), offset 0xda4 ....................................... 164 register 49: mpu region base address alias 2 (mpubase2), offset 0xdac ...................................... 164 register 50: mpu region base address alias 3 (mpubase3), offset 0xdb4 ....................................... 164 register 51: mpu region attribute and size (mpuattr), offset 0xda0 ............................................... 166 register 52: mpu region attribute and size alias 1 (mpuattr1), offset 0xda8 .................................. 166 register 53: mpu region attribute and size alias 2 (mpuattr2), offset 0xdb0 .................................. 166 register 54: mpu region attribute and size alias 3 (mpuattr3), offset 0xdb8 .................................. 166 system control ............................................................................................................................ 181 register 1: device identification 0 (did0), offset 0x000 ..................................................................... 200 register 2: brown-out reset control (pborctl), offset 0x030 ........................................................ 202 register 3: raw interrupt status (ris), offset 0x050 .......................................................................... 203 register 4: interrupt mask control (imc), offset 0x054 ...................................................................... 205 register 5: masked interrupt status and clear (misc), offset 0x058 .................................................. 207 register 6: reset cause (resc), offset 0x05c ................................................................................ 209 register 7: run-mode clock configuration (rcc), offset 0x060 ......................................................... 211 register 8: xtal to pll translation (pllcfg), offset 0x064 ............................................................. 215 register 9: gpio high-performance bus control (gpiohbctl), offset 0x06c ................................... 216 register 10: run-mode clock configuration 2 (rcc2), offset 0x070 .................................................... 218 register 11: main oscillator control (moscctl), offset 0x07c ........................................................... 221 register 12: deep sleep clock configuration (dslpclkcfg), offset 0x144 ........................................ 222 register 13: precision internal oscillator calibration (piosccal), offset 0x150 ................................... 224 register 14: precision internal oscillator statistics (pioscstat), offset 0x154 .................................... 226 register 15: i 2 s mclk configuration (i2smclkcfg), offset 0x170 ..................................................... 227 march 20, 2011 18 texas instruments-advance information table of contents register 16: device identification 1 (did1), offset 0x004 ..................................................................... 229 register 17: device capabilities 0 (dc0), offset 0x008 ........................................................................ 231 register 18: device capabilities 1 (dc1), offset 0x010 ........................................................................ 232 register 19: device capabilities 2 (dc2), offset 0x014 ........................................................................ 234 register 20: device capabilities 3 (dc3), offset 0x018 ........................................................................ 236 register 21: device capabilities 4 (dc4), offset 0x01c ....................................................................... 238 register 22: device capabilities 5 (dc5), offset 0x020 ........................................................................ 240 register 23: device capabilities 6 (dc6), offset 0x024 ........................................................................ 242 register 24: device capabilities 7 (dc7), offset 0x028 ........................................................................ 243 register 25: device capabilities 8 adc channels (dc8), offset 0x02c ................................................ 247 register 26: device capabilities 9 adc digital comparators (dc9), offset 0x190 ................................. 249 register 27: non-volatile memory information (nvmstat), offset 0x1a0 ............................................. 251 register 28: run mode clock gating control register 0 (rcgc0), offset 0x100 ................................... 252 register 29: sleep mode clock gating control register 0 (scgc0), offset 0x110 ................................. 255 register 30: deep sleep mode clock gating control register 0 (dcgc0), offset 0x120 ....................... 258 register 31: run mode clock gating control register 1 (rcgc1), offset 0x104 ................................... 260 register 32: sleep mode clock gating control register 1 (scgc1), offset 0x114 ................................. 263 register 33: deep-sleep mode clock gating control register 1 (dcgc1), offset 0x124 ....................... 266 register 34: run mode clock gating control register 2 (rcgc2), offset 0x108 ................................... 269 register 35: sleep mode clock gating control register 2 (scgc2), offset 0x118 ................................. 271 register 36: deep sleep mode clock gating control register 2 (dcgc2), offset 0x128 ....................... 273 register 37: software reset control 0 (srcr0), offset 0x040 ............................................................. 275 register 38: software reset control 1 (srcr1), offset 0x044 ............................................................. 277 register 39: software reset control 2 (srcr2), offset 0x048 ............................................................. 280 hibernation module ..................................................................................................................... 282 register 1: hibernation rtc counter (hibrtcc), offset 0x000 ......................................................... 294 register 2: hibernation rtc match 0 (hibrtcm0), offset 0x004 ....................................................... 295 register 3: hibernation rtc match 1 (hibrtcm1), offset 0x008 ....................................................... 296 register 4: hibernation rtc load (hibrtcld), offset 0x00c ........................................................... 297 register 5: hibernation control (hibctl), offset 0x010 ..................................................................... 298 register 6: hibernation interrupt mask (hibim), offset 0x014 ............................................................. 301 register 7: hibernation raw interrupt status (hibris), offset 0x018 .................................................. 303 register 8: hibernation masked interrupt status (hibmis), offset 0x01c ............................................ 305 register 9: hibernation interrupt clear (hibic), offset 0x020 ............................................................. 307 register 10: hibernation rtc trim (hibrtct), offset 0x024 ............................................................... 308 register 11: hibernation data (hibdata), offset 0x030-0x12c ............................................................ 309 internal memory ........................................................................................................................... 310 register 1: flash memory address (fma), offset 0x000 .................................................................... 319 register 2: flash memory data (fmd), offset 0x004 ......................................................................... 320 register 3: flash memory control (fmc), offset 0x008 ..................................................................... 321 register 4: flash controller raw interrupt status (fcris), offset 0x00c ............................................ 324 register 5: flash controller interrupt mask (fcim), offset 0x010 ........................................................ 325 register 6: flash controller masked interrupt status and clear (fcmisc), offset 0x014 ..................... 326 register 7: flash memory control 2 (fmc2), offset 0x020 ................................................................. 327 register 8: flash write buffer valid (fwbval), offset 0x030 ............................................................. 328 register 9: flash control (fctl), offset 0x0f8 ................................................................................. 329 register 10: flash write buffer n (fwbn), offset 0x100 - 0x17c .......................................................... 330 register 11: rom control (rmctl), offset 0x0f0 .............................................................................. 331 19 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: flash memory protection read enable 0 (fmpre0), offset 0x130 and 0x200 ................... 332 register 13: flash memory protection program enable 0 (fmppe0), offset 0x134 and 0x400 ............... 333 register 14: boot configuration (bootcfg), offset 0x1d0 ................................................................. 334 register 15: user register 0 (user_reg0), offset 0x1e0 .................................................................. 336 register 16: user register 1 (user_reg1), offset 0x1e4 .................................................................. 337 register 17: user register 2 (user_reg2), offset 0x1e8 .................................................................. 338 register 18: user register 3 (user_reg3), offset 0x1ec ................................................................. 339 register 19: flash memory protection read enable 1 (fmpre1), offset 0x204 .................................... 340 register 20: flash memory protection read enable 2 (fmpre2), offset 0x208 .................................... 341 register 21: flash memory protection read enable 3 (fmpre3), offset 0x20c ................................... 342 register 22: flash memory protection program enable 1 (fmppe1), offset 0x404 ............................... 343 register 23: flash memory protection program enable 2 (fmppe2), offset 0x408 ............................... 344 register 24: flash memory protection program enable 3 (fmppe3), offset 0x40c ............................... 345 micro direct memory access (dma) ........................................................................................ 346 register 1: dma channel source address end pointer (dmasrcendp), offset 0x000 ...................... 369 register 2: dma channel destination address end pointer (dmadstendp), offset 0x004 ................ 370 register 3: dma channel control word (dmachctl), offset 0x008 .................................................. 371 register 4: dma status (dmastat), offset 0x000 ............................................................................ 376 register 5: dma configuration (dmacfg), offset 0x004 ................................................................... 378 register 6: dma channel control base pointer (dmactlbase), offset 0x008 .................................. 379 register 7: dma alternate channel control base pointer (dmaaltbase), offset 0x00c .................... 380 register 8: dma channel wait-on-request status (dmawaitstat), offset 0x010 ............................. 381 register 9: dma channel software request (dmaswreq), offset 0x014 ......................................... 382 register 10: dma channel useburst set (dmauseburstset), offset 0x018 .................................... 383 register 11: dma channel useburst clear (dmauseburstclr), offset 0x01c ................................. 384 register 12: dma channel request mask set (dmareqmaskset), offset 0x020 .............................. 385 register 13: dma channel request mask clear (dmareqmaskclr), offset 0x024 ........................... 386 register 14: dma channel enable set (dmaenaset), offset 0x028 ................................................... 387 register 15: dma channel enable clear (dmaenaclr), offset 0x02c ............................................... 388 register 16: dma channel primary alternate set (dmaaltset), offset 0x030 .................................... 389 register 17: dma channel primary alternate clear (dmaaltclr), offset 0x034 ................................. 390 register 18: dma channel priority set (dmaprioset), offset 0x038 ................................................. 391 register 19: dma channel priority clear (dmaprioclr), offset 0x03c .............................................. 392 register 20: dma bus error clear (dmaerrclr), offset 0x04c ........................................................ 393 register 21: dma channel assignment (dmachasgn), offset 0x500 ................................................. 394 register 22: dma peripheral identification 0 (dmaperiphid0), offset 0xfe0 ......................................... 395 register 23: dma peripheral identification 1 (dmaperiphid1), offset 0xfe4 ......................................... 396 register 24: dma peripheral identification 2 (dmaperiphid2), offset 0xfe8 ......................................... 397 register 25: dma peripheral identification 3 (dmaperiphid3), offset 0xfec ........................................ 398 register 26: dma peripheral identification 4 (dmaperiphid4), offset 0xfd0 ......................................... 399 register 27: dma primecell identification 0 (dmapcellid0), offset 0xff0 ........................................... 400 register 28: dma primecell identification 1 (dmapcellid1), offset 0xff4 ........................................... 401 register 29: dma primecell identification 2 (dmapcellid2), offset 0xff8 ........................................... 402 register 30: dma primecell identification 3 (dmapcellid3), offset 0xffc ........................................... 403 general-purpose input/outputs (gpios) ................................................................................... 404 register 1: gpio data (gpiodata), offset 0x000 ............................................................................ 418 register 2: gpio direction (gpiodir), offset 0x400 ......................................................................... 419 register 3: gpio interrupt sense (gpiois), offset 0x404 .................................................................. 420 march 20, 2011 20 texas instruments-advance information table of contents register 4: gpio interrupt both edges (gpioibe), offset 0x408 ........................................................ 421 register 5: gpio interrupt event (gpioiev), offset 0x40c ................................................................ 422 register 6: gpio interrupt mask (gpioim), offset 0x410 ................................................................... 423 register 7: gpio raw interrupt status (gpioris), offset 0x414 ........................................................ 424 register 8: gpio masked interrupt status (gpiomis), offset 0x418 ................................................... 425 register 9: gpio interrupt clear (gpioicr), offset 0x41c ................................................................ 427 register 10: gpio alternate function select (gpioafsel), offset 0x420 ............................................ 428 register 11: gpio 2-ma drive select (gpiodr2r), offset 0x500 ........................................................ 430 register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 ........................................................ 431 register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 ........................................................ 432 register 14: gpio open drain select (gpioodr), offset 0x50c ......................................................... 433 register 15: gpio pull-up select (gpiopur), offset 0x510 ................................................................ 434 register 16: gpio pull-down select (gpiopdr), offset 0x514 ........................................................... 436 register 17: gpio slew rate control select (gpioslr), offset 0x518 ................................................ 438 register 18: gpio digital enable (gpioden), offset 0x51c ................................................................ 439 register 19: gpio lock (gpiolock), offset 0x520 ............................................................................ 441 register 20: gpio commit (gpiocr), offset 0x524 ............................................................................ 442 register 21: gpio analog mode select (gpioamsel), offset 0x528 ................................................... 444 register 22: gpio port control (gpiopctl), offset 0x52c ................................................................. 446 register 23: gpio peripheral identification 4 (gpioperiphid4), offset 0xfd0 ....................................... 448 register 24: gpio peripheral identification 5 (gpioperiphid5), offset 0xfd4 ....................................... 449 register 25: gpio peripheral identification 6 (gpioperiphid6), offset 0xfd8 ....................................... 450 register 26: gpio peripheral identification 7 (gpioperiphid7), offset 0xfdc ...................................... 451 register 27: gpio peripheral identification 0 (gpioperiphid0), offset 0xfe0 ....................................... 452 register 28: gpio peripheral identification 1 (gpioperiphid1), offset 0xfe4 ....................................... 453 register 29: gpio peripheral identification 2 (gpioperiphid2), offset 0xfe8 ....................................... 454 register 30: gpio peripheral identification 3 (gpioperiphid3), offset 0xfec ...................................... 455 register 31: gpio primecell identification 0 (gpiopcellid0), offset 0xff0 .......................................... 456 register 32: gpio primecell identification 1 (gpiopcellid1), offset 0xff4 .......................................... 457 register 33: gpio primecell identification 2 (gpiopcellid2), offset 0xff8 .......................................... 458 register 34: gpio primecell identification 3 (gpiopcellid3), offset 0xffc ......................................... 459 general-purpose timers ............................................................................................................. 460 register 1: gptm configuration (gptmcfg), offset 0x000 .............................................................. 476 register 2: gptm timer a mode (gptmtamr), offset 0x004 ........................................................... 477 register 3: gptm timer b mode (gptmtbmr), offset 0x008 ........................................................... 479 register 4: gptm control (gptmctl), offset 0x00c ........................................................................ 481 register 5: gptm interrupt mask (gptmimr), offset 0x018 .............................................................. 484 register 6: gptm raw interrupt status (gptmris), offset 0x01c ..................................................... 486 register 7: gptm masked interrupt status (gptmmis), offset 0x020 ................................................ 489 register 8: gptm interrupt clear (gptmicr), offset 0x024 .............................................................. 492 register 9: gptm timer a interval load (gptmtailr), offset 0x028 ................................................ 494 register 10: gptm timer b interval load (gptmtbilr), offset 0x02c ................................................ 495 register 11: gptm timer a match (gptmtamatchr), offset 0x030 .................................................. 496 register 12: gptm timer b match (gptmtbmatchr), offset 0x034 ................................................. 497 register 13: gptm timer a prescale (gptmtapr), offset 0x038 ....................................................... 498 register 14: gptm timer b prescale (gptmtbpr), offset 0x03c ...................................................... 499 register 15: gptm timera prescale match (gptmtapmr), offset 0x040 ........................................... 500 register 16: gptm timerb prescale match (gptmtbpmr), offset 0x044 ........................................... 501 21 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 17: gptm timer a (gptmtar), offset 0x048 ....................................................................... 502 register 18: gptm timer b (gptmtbr), offset 0x04c ....................................................................... 503 register 19: gptm timer a value (gptmtav), offset 0x050 ............................................................... 504 register 20: gptm timer b value (gptmtbv), offset 0x054 .............................................................. 505 watchdog timers ......................................................................................................................... 506 register 1: watchdog load (wdtload), offset 0x000 ...................................................................... 510 register 2: watchdog value (wdtvalue), offset 0x004 ................................................................... 511 register 3: watchdog control (wdtctl), offset 0x008 ..................................................................... 512 register 4: watchdog interrupt clear (wdticr), offset 0x00c .......................................................... 514 register 5: watchdog raw interrupt status (wdtris), offset 0x010 .................................................. 515 register 6: watchdog masked interrupt status (wdtmis), offset 0x014 ............................................. 516 register 7: watchdog test (wdttest), offset 0x418 ....................................................................... 517 register 8: watchdog lock (wdtlock), offset 0xc00 ..................................................................... 518 register 9: watchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 ................................. 519 register 10: watchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 ................................. 520 register 11: watchdog peripheral identification 6 (wdtperiphid6), offset 0xfd8 ................................. 521 register 12: watchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc ................................ 522 register 13: watchdog peripheral identification 0 (wdtperiphid0), offset 0xfe0 ................................. 523 register 14: watchdog peripheral identification 1 (wdtperiphid1), offset 0xfe4 ................................. 524 register 15: watchdog peripheral identification 2 (wdtperiphid2), offset 0xfe8 ................................. 525 register 16: watchdog peripheral identification 3 (wdtperiphid3), offset 0xfec ................................. 526 register 17: watchdog primecell identification 0 (wdtpcellid0), offset 0xff0 .................................... 527 register 18: watchdog primecell identification 1 (wdtpcellid1), offset 0xff4 .................................... 528 register 19: watchdog primecell identification 2 (wdtpcellid2), offset 0xff8 .................................... 529 register 20: watchdog primecell identification 3 (wdtpcellid3 ), offset 0xffc .................................. 530 analog-to-digital converter (adc) ............................................................................................. 531 register 1: adc active sample sequencer (adcactss), offset 0x000 ............................................. 553 register 2: adc raw interrupt status (adcris), offset 0x004 ........................................................... 554 register 3: adc interrupt mask (adcim), offset 0x008 ..................................................................... 556 register 4: adc interrupt status and clear (adcisc), offset 0x00c .................................................. 558 register 5: adc overflow status (adcostat), offset 0x010 ............................................................ 561 register 6: adc event multiplexer select (adcemux), offset 0x014 ................................................. 563 register 7: adc underflow status (adcustat), offset 0x018 ........................................................... 568 register 8: adc sample sequencer priority (adcsspri), offset 0x020 ............................................. 569 register 9: adc sample phase control (adcspc), offset 0x024 ...................................................... 571 register 10: adc processor sample sequence initiate (adcpssi), offset 0x028 ................................. 573 register 11: adc sample averaging control (adcsac), offset 0x030 ................................................. 575 register 12: adc digital comparator interrupt status and clear (adcdcisc), offset 0x034 ................. 576 register 13: adc control (adcctl), offset 0x038 ............................................................................. 578 register 14: adc sample sequence input multiplexer select 0 (adcssmux0), offset 0x040 ............... 579 register 15: adc sample sequence control 0 (adcssctl0), offset 0x044 ........................................ 581 register 16: adc sample sequence result fifo 0 (adcssfifo0), offset 0x048 ................................ 584 register 17: adc sample sequence result fifo 1 (adcssfifo1), offset 0x068 ................................ 584 register 18: adc sample sequence result fifo 2 (adcssfifo2), offset 0x088 ................................ 584 register 19: adc sample sequence result fifo 3 (adcssfifo3), offset 0x0a8 ............................... 584 register 20: adc sample sequence fifo 0 status (adcssfstat0), offset 0x04c ............................. 585 register 21: adc sample sequence fifo 1 status (adcssfstat1), offset 0x06c ............................. 585 register 22: adc sample sequence fifo 2 status (adcssfstat2), offset 0x08c ............................ 585 march 20, 2011 22 texas instruments-advance information table of contents register 23: adc sample sequence fifo 3 status (adcssfstat3), offset 0x0ac ............................ 585 register 24: adc sample sequence 0 operation (adcssop0), offset 0x050 ...................................... 587 register 25: adc sample sequence 0 digital comparator select (adcssdc0), offset 0x054 .............. 589 register 26: adc sample sequence input multiplexer select 1 (adcssmux1), offset 0x060 ............... 591 register 27: adc sample sequence input multiplexer select 2 (adcssmux2), offset 0x080 ............... 591 register 28: adc sample sequence control 1 (adcssctl1), offset 0x064 ........................................ 592 register 29: adc sample sequence control 2 (adcssctl2), offset 0x084 ........................................ 592 register 30: adc sample sequence 1 operation (adcssop1), offset 0x070 ...................................... 594 register 31: adc sample sequence 2 operation (adcssop2), offset 0x090 ..................................... 594 register 32: adc sample sequence 1 digital comparator select (adcssdc1), offset 0x074 .............. 595 register 33: adc sample sequence 2 digital comparator select (adcssdc2), offset 0x094 .............. 595 register 34: adc sample sequence input multiplexer select 3 (adcssmux3), offset 0x0a0 ............... 597 register 35: adc sample sequence control 3 (adcssctl3), offset 0x0a4 ........................................ 598 register 36: adc sample sequence 3 operation (adcssop3), offset 0x0b0 ..................................... 599 register 37: adc sample sequence 3 digital comparator select (adcssdc3), offset 0x0b4 .............. 600 register 38: adc digital comparator reset initial conditions (adcdcric), offset 0xd00 ..................... 601 register 39: adc digital comparator control 0 (adcdcctl0), offset 0xe00 ....................................... 606 register 40: adc digital comparator control 1 (adcdcctl1), offset 0xe04 ....................................... 606 register 41: adc digital comparator control 2 (adcdcctl2), offset 0xe08 ....................................... 606 register 42: adc digital comparator control 3 (adcdcctl3), offset 0xe0c ...................................... 606 register 43: adc digital comparator control 4 (adcdcctl4), offset 0xe10 ....................................... 606 register 44: adc digital comparator control 5 (adcdcctl5), offset 0xe14 ....................................... 606 register 45: adc digital comparator control 6 (adcdcctl6), offset 0xe18 ....................................... 606 register 46: adc digital comparator control 7 (adcdcctl7), offset 0xe1c ...................................... 606 register 47: adc digital comparator range 0 (adcdccmp0), offset 0xe40 ....................................... 609 register 48: adc digital comparator range 1 (adcdccmp1), offset 0xe44 ....................................... 609 register 49: adc digital comparator range 2 (adcdccmp2), offset 0xe48 ....................................... 609 register 50: adc digital comparator range 3 (adcdccmp3), offset 0xe4c ...................................... 609 register 51: adc digital comparator range 4 (adcdccmp4), offset 0xe50 ....................................... 609 register 52: adc digital comparator range 5 (adcdccmp5), offset 0xe54 ....................................... 609 register 53: adc digital comparator range 6 (adcdccmp6), offset 0xe58 ....................................... 609 register 54: adc digital comparator range 7 (adcdccmp7), offset 0xe5c ...................................... 609 universal asynchronous receivers/transmitters (uarts) ..................................................... 610 register 1: uart data (uartdr), offset 0x000 ............................................................................... 624 register 2: uart receive status/error clear (uartrsr/uartecr), offset 0x004 ........................... 626 register 3: uart flag (uartfr), offset 0x018 ................................................................................ 629 register 4: uart irda low-power register (uartilpr), offset 0x020 ............................................. 632 register 5: uart integer baud-rate divisor (uartibrd), offset 0x024 ............................................ 633 register 6: uart fractional baud-rate divisor (uartfbrd), offset 0x028 ....................................... 634 register 7: uart line control (uartlcrh), offset 0x02c ............................................................... 635 register 8: uart control (uartctl), offset 0x030 ......................................................................... 637 register 9: uart interrupt fifo level select (uartifls), offset 0x034 ........................................... 641 register 10: uart interrupt mask (uartim), offset 0x038 ................................................................. 643 register 11: uart raw interrupt status (uartris), offset 0x03c ...................................................... 647 register 12: uart masked interrupt status (uartmis), offset 0x040 ................................................. 650 register 13: uart interrupt clear (uarticr), offset 0x044 ............................................................... 653 register 14: uart dma control (uartdmactl), offset 0x048 .......................................................... 655 register 15: uart lin control (uartlctl), offset 0x090 ................................................................. 656 23 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 16: uart lin snap shot (uartlss), offset 0x094 ............................................................... 657 register 17: uart lin timer (uartltim), offset 0x098 ..................................................................... 658 register 18: uart peripheral identification 4 (uartperiphid4), offset 0xfd0 ..................................... 659 register 19: uart peripheral identification 5 (uartperiphid5), offset 0xfd4 ..................................... 660 register 20: uart peripheral identification 6 (uartperiphid6), offset 0xfd8 ..................................... 661 register 21: uart peripheral identification 7 (uartperiphid7), offset 0xfdc ..................................... 662 register 22: uart peripheral identification 0 (uartperiphid0), offset 0xfe0 ...................................... 663 register 23: uart peripheral identification 1 (uartperiphid1), offset 0xfe4 ...................................... 664 register 24: uart peripheral identification 2 (uartperiphid2), offset 0xfe8 ...................................... 665 register 25: uart peripheral identification 3 (uartperiphid3), offset 0xfec ..................................... 666 register 26: uart primecell identification 0 (uartpcellid0), offset 0xff0 ........................................ 667 register 27: uart primecell identification 1 (uartpcellid1), offset 0xff4 ........................................ 668 register 28: uart primecell identification 2 (uartpcellid2), offset 0xff8 ........................................ 669 register 29: uart primecell identification 3 (uartpcellid3), offset 0xffc ........................................ 670 synchronous serial interface (ssi) ............................................................................................ 671 register 1: ssi control 0 (ssicr0), offset 0x000 .............................................................................. 687 register 2: ssi control 1 (ssicr1), offset 0x004 .............................................................................. 689 register 3: ssi data (ssidr), offset 0x008 ...................................................................................... 691 register 4: ssi status (ssisr), offset 0x00c ................................................................................... 692 register 5: ssi clock prescale (ssicpsr), offset 0x010 .................................................................. 694 register 6: ssi interrupt mask (ssiim), offset 0x014 ......................................................................... 695 register 7: ssi raw interrupt status (ssiris), offset 0x018 .............................................................. 696 register 8: ssi masked interrupt status (ssimis), offset 0x01c ........................................................ 698 register 9: ssi interrupt clear (ssiicr), offset 0x020 ....................................................................... 700 register 10: ssi dma control (ssidmactl), offset 0x024 ................................................................. 701 register 11: ssi peripheral identification 4 (ssiperiphid4), offset 0xfd0 ............................................. 702 register 12: ssi peripheral identification 5 (ssiperiphid5), offset 0xfd4 ............................................. 703 register 13: ssi peripheral identification 6 (ssiperiphid6), offset 0xfd8 ............................................. 704 register 14: ssi peripheral identification 7 (ssiperiphid7), offset 0xfdc ............................................ 705 register 15: ssi peripheral identification 0 (ssiperiphid0), offset 0xfe0 ............................................. 706 register 16: ssi peripheral identification 1 (ssiperiphid1), offset 0xfe4 ............................................. 707 register 17: ssi peripheral identification 2 (ssiperiphid2), offset 0xfe8 ............................................. 708 register 18: ssi peripheral identification 3 (ssiperiphid3), offset 0xfec ............................................ 709 register 19: ssi primecell identification 0 (ssipcellid0), offset 0xff0 ............................................... 710 register 20: ssi primecell identification 1 (ssipcellid1), offset 0xff4 ............................................... 711 register 21: ssi primecell identification 2 (ssipcellid2), offset 0xff8 ............................................... 712 register 22: ssi primecell identification 3 (ssipcellid3), offset 0xffc ............................................... 713 inter-integrated circuit (i 2 c) interface ........................................................................................ 714 register 1: i 2 c master slave address (i2cmsa), offset 0x000 ........................................................... 731 register 2: i 2 c master control/status (i2cmcs), offset 0x004 ........................................................... 732 register 3: i 2 c master data (i2cmdr), offset 0x008 ......................................................................... 736 register 4: i 2 c master timer period (i2cmtpr), offset 0x00c ........................................................... 737 register 5: i 2 c master interrupt mask (i2cmimr), offset 0x010 ......................................................... 738 register 6: i 2 c master raw interrupt status (i2cmris), offset 0x014 ................................................. 739 register 7: i 2 c master masked interrupt status (i2cmmis), offset 0x018 ........................................... 740 register 8: i 2 c master interrupt clear (i2cmicr), offset 0x01c ......................................................... 741 register 9: i 2 c master configuration (i2cmcr), offset 0x020 ............................................................ 742 march 20, 2011 24 texas instruments-advance information table of contents register 10: i 2 c slave own address (i2csoar), offset 0x800 ............................................................ 743 register 11: i 2 c slave control/status (i2cscsr), offset 0x804 ........................................................... 744 register 12: i 2 c slave data (i2csdr), offset 0x808 ........................................................................... 746 register 13: i 2 c slave interrupt mask (i2csimr), offset 0x80c ........................................................... 747 register 14: i 2 c slave raw interrupt status (i2csris), offset 0x810 ................................................... 748 register 15: i 2 c slave masked interrupt status (i2csmis), offset 0x814 .............................................. 749 register 16: i 2 c slave interrupt clear (i2csicr), offset 0x818 ............................................................ 750 inter-integrated circuit sound (i 2 s) interface ............................................................................ 751 register 1: i 2 s transmit fifo data (i2stxfifo), offset 0x000 .......................................................... 764 register 2: i 2 s transmit fifo configuration (i2stxfifocfg), offset 0x004 ...................................... 765 register 3: i 2 s transmit module configuration (i2stxcfg), offset 0x008 .......................................... 766 register 4: i 2 s transmit fifo limit (i2stxlimit), offset 0x00c ........................................................ 768 register 5: i 2 s transmit interrupt status and mask (i2stxism), offset 0x010 ..................................... 769 register 6: i 2 s transmit fifo level (i2stxlev), offset 0x018 .......................................................... 770 register 7: i 2 s receive fifo data (i2srxfifo), offset 0x800 .......................................................... 771 register 8: i 2 s receive fifo configuration (i2srxfifocfg), offset 0x804 ...................................... 772 register 9: i 2 s receive module configuration (i2srxcfg), offset 0x808 ........................................... 773 register 10: i 2 s receive fifo limit (i2srxlimit), offset 0x80c ......................................................... 775 register 11: i 2 s receive interrupt status and mask (i2srxism), offset 0x810 ..................................... 776 register 12: i 2 s receive fifo level (i2srxlev), offset 0x818 ........................................................... 777 register 13: i 2 s module configuration (i2scfg), offset 0xc00 ............................................................ 778 register 14: i 2 s interrupt mask (i2sim), offset 0xc10 ......................................................................... 780 register 15: i 2 s raw interrupt status (i2sris), offset 0xc14 ............................................................... 782 register 16: i 2 s masked interrupt status (i2smis), offset 0xc18 ......................................................... 784 register 17: i 2 s interrupt clear (i2sic), offset 0xc1c ......................................................................... 786 analog comparators ................................................................................................................... 787 register 1: analog comparator masked interrupt status (acmis), offset 0x000 .................................. 793 register 2: analog comparator raw interrupt status (acris), offset 0x004 ....................................... 794 register 3: analog comparator interrupt enable (acinten), offset 0x008 ......................................... 795 register 4: analog comparator reference voltage control (acrefctl), offset 0x010 ....................... 796 register 5: analog comparator status 0 (acstat0), offset 0x020 ..................................................... 797 register 6: analog comparator status 1 (acstat1), offset 0x040 ..................................................... 797 register 7: analog comparator control 0 (acctl0), offset 0x024 ..................................................... 798 register 8: analog comparator control 1 (acctl1), offset 0x044 ..................................................... 798 pulse width modulator (pwm) .................................................................................................... 800 register 1: pwm master control (pwmctl), offset 0x000 ................................................................ 815 register 2: pwm time base sync (pwmsync), offset 0x004 ........................................................... 816 register 3: pwm output enable (pwmenable), offset 0x008 .......................................................... 817 register 4: pwm output inversion (pwminvert), offset 0x00c ....................................................... 819 register 5: pwm output fault (pwmfault), offset 0x010 ................................................................ 821 register 6: pwm interrupt enable (pwminten), offset 0x014 ........................................................... 823 register 7: pwm raw interrupt status (pwmris), offset 0x018 ........................................................ 825 register 8: pwm interrupt status and clear (pwmisc), offset 0x01c ................................................ 827 register 9: pwm status (pwmstatus), offset 0x020 ...................................................................... 829 register 10: pwm fault condition value (pwmfaultval), offset 0x024 ............................................ 831 register 11: pwm enable update (pwmenupd), offset 0x028 ........................................................... 833 25 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: pwm0 control (pwm0ctl), offset 0x040 ....................................................................... 836 register 13: pwm1 control (pwm1ctl), offset 0x080 ....................................................................... 836 register 14: pwm2 control (pwm2ctl), offset 0x0c0 ....................................................................... 836 register 15: pwm0 interrupt and trigger enable (pwm0inten), offset 0x044 ..................................... 841 register 16: pwm1 interrupt and trigger enable (pwm1inten), offset 0x084 ..................................... 841 register 17: pwm2 interrupt and trigger enable (pwm2inten), offset 0x0c4 .................................... 841 register 18: pwm0 raw interrupt status (pwm0ris), offset 0x048 ..................................................... 844 register 19: pwm1 raw interrupt status (pwm1ris), offset 0x088 ..................................................... 844 register 20: pwm2 raw interrupt status (pwm2ris), offset 0x0c8 .................................................... 844 register 21: pwm0 interrupt status and clear (pwm0isc), offset 0x04c ............................................ 846 register 22: pwm1 interrupt status and clear (pwm1isc), offset 0x08c ............................................ 846 register 23: pwm2 interrupt status and clear (pwm2isc), offset 0x0cc ............................................ 846 register 24: pwm0 load (pwm0load), offset 0x050 ........................................................................ 848 register 25: pwm1 load (pwm1load), offset 0x090 ........................................................................ 848 register 26: pwm2 load (pwm2load), offset 0x0d0 ....................................................................... 848 register 27: pwm0 counter (pwm0count), offset 0x054 ................................................................. 849 register 28: pwm1 counter (pwm1count), offset 0x094 ................................................................. 849 register 29: pwm2 counter (pwm2count), offset 0x0d4 ................................................................ 849 register 30: pwm0 compare a (pwm0cmpa), offset 0x058 .............................................................. 850 register 31: pwm1 compare a (pwm1cmpa), offset 0x098 .............................................................. 850 register 32: pwm2 compare a (pwm2cmpa), offset 0x0d8 .............................................................. 850 register 33: pwm0 compare b (pwm0cmpb), offset 0x05c ............................................................. 851 register 34: pwm1 compare b (pwm1cmpb), offset 0x09c ............................................................. 851 register 35: pwm2 compare b (pwm2cmpb), offset 0x0dc ............................................................. 851 register 36: pwm0 generator a control (pwm0gena), offset 0x060 ................................................. 852 register 37: pwm1 generator a control (pwm1gena), offset 0x0a0 ................................................. 852 register 38: pwm2 generator a control (pwm2gena), offset 0x0e0 ................................................. 852 register 39: pwm0 generator b control (pwm0genb), offset 0x064 ................................................. 855 register 40: pwm1 generator b control (pwm1genb), offset 0x0a4 ................................................. 855 register 41: pwm2 generator b control (pwm2genb), offset 0x0e4 ................................................. 855 register 42: pwm0 dead-band control (pwm0dbctl), offset 0x068 ................................................. 858 register 43: pwm1 dead-band control (pwm1dbctl), offset 0x0a8 ................................................. 858 register 44: pwm2 dead-band control (pwm2dbctl), offset 0x0e8 ................................................. 858 register 45: pwm0 dead-band rising-edge delay (pwm0dbrise), offset 0x06c .............................. 859 register 46: pwm1 dead-band rising-edge delay (pwm1dbrise), offset 0x0ac .............................. 859 register 47: pwm2 dead-band rising-edge delay (pwm2dbrise), offset 0x0ec .............................. 859 register 48: pwm0 dead-band falling-edge-delay (pwm0dbfall), offset 0x070 .............................. 860 register 49: pwm1 dead-band falling-edge-delay (pwm1dbfall), offset 0x0b0 .............................. 860 register 50: pwm2 dead-band falling-edge-delay (pwm2dbfall), offset 0x0f0 .............................. 860 register 51: pwm0 fault source 0 (pwm0fltsrc0), offset 0x074 .................................................... 861 register 52: pwm1 fault source 0 (pwm1fltsrc0), offset 0x0b4 .................................................... 861 register 53: pwm2 fault source 0 (pwm2fltsrc0), offset 0x0f4 .................................................... 861 register 54: pwm0 fault source 1 (pwm0fltsrc1), offset 0x078 .................................................... 863 register 55: pwm1 fault source 1 (pwm1fltsrc1), offset 0x0b8 .................................................... 863 register 56: pwm2 fault source 1 (pwm2fltsrc1), offset 0x0f8 .................................................... 863 register 57: pwm0 minimum fault period (pwm0minfltper), offset 0x07c ..................................... 866 register 58: pwm1 minimum fault period (pwm1minfltper), offset 0x0bc ..................................... 866 register 59: pwm2 minimum fault period (pwm2minfltper), offset 0x0fc ..................................... 866 march 20, 2011 26 texas instruments-advance information table of contents register 60: pwm0 fault pin logic sense (pwm0fltsen), offset 0x800 ............................................ 867 register 61: pwm1 fault pin logic sense (pwm1fltsen), offset 0x880 ............................................ 867 register 62: pwm2 fault pin logic sense (pwm2fltsen), offset 0x900 ............................................ 867 register 63: pwm3 fault pin logic sense (pwm3fltsen), offset 0x980 ............................................ 867 register 64: pwm0 fault status 0 (pwm0fltstat0), offset 0x804 .................................................... 868 register 65: pwm1 fault status 0 (pwm1fltstat0), offset 0x884 .................................................... 868 register 66: pwm2 fault status 0 (pwm2fltstat0), offset 0x904 .................................................... 868 register 67: pwm0 fault status 1 (pwm0fltstat1), offset 0x808 .................................................... 870 register 68: pwm1 fault status 1 (pwm1fltstat1), offset 0x888 .................................................... 870 register 69: pwm2 fault status 1 (pwm2fltstat1), offset 0x908 .................................................... 870 quadrature encoder interface (qei) .......................................................................................... 873 register 1: qei control (qeictl), offset 0x000 ................................................................................ 880 register 2: qei status (qeistat), offset 0x004 ................................................................................ 883 register 3: qei position (qeipos), offset 0x008 .............................................................................. 884 register 4: qei maximum position (qeimaxpos), offset 0x00c ....................................................... 885 register 5: qei timer load (qeiload), offset 0x010 ....................................................................... 886 register 6: qei timer (qeitime), offset 0x014 ................................................................................. 887 register 7: qei velocity counter (qeicount), offset 0x018 ............................................................. 888 register 8: qei velocity (qeispeed), offset 0x01c .......................................................................... 889 register 9: qei interrupt enable (qeiinten), offset 0x020 ............................................................... 890 register 10: qei raw interrupt status (qeiris), offset 0x024 ............................................................. 892 register 11: qei interrupt status and clear (qeiisc), offset 0x028 ..................................................... 894 27 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller revision history the revision history table notes changes made between the indicated revisions of the lm3s1p51 data sheet. table 1. revision history description revision date clarified "reset control" section in the "system control" chapter. corrected usb pll speed in "main clock tree" diagram. clarified hibernation module initialization and configuration. corrected reset value for dma channel wait-on-request status (dmawaitstat) register. corrected "gpio pins with non-zero reset values" table. clarified that that the timer reload only happens in periodic mode. clarified that only bit 0 in the watchdog control (wdtctl) register is protected from writes once set. added "sample averaging example" diagram to adc chapter. corrected "ssi timing for spi frame format" figure. in "electrical characteristics" chapter: C deleted t pormin parameter from "power characteristics" table, and deleted corresponding diagram. C added t adcsamp sample time parameter to "adc characteristics" table. additional minor data sheet clarifications and corrections. 9538 march 2011 clarified main oscillator verification circuit sequence. added note that there must be a delay of 3 system clocks after the module clock is enabled before any of that module's registers are accessed. clarified initialization and configuration procedure in "analog comparators" chapter. in electrical characteristics chapter: C added specification for maximum input voltage on a non-power pin when the microcontroller is unpowered (v non parameter in maximum ratings table). C replaced preliminary current consumption specifications with nominal power consumption, maximum current specifications, and typical current consumption vs. frequency sections. C clarified reset, and power and brown-out characteristics and added a new specification for powering down before powering back up. C added characteristics required when using an external regulator to provide power for v ddc . additional minor data sheet clarifications and corrections. 9161 january 2011 march 20, 2011 28 texas instruments-advance information revision history table 1. revision history (continued) description revision date information on advanced encryption standard (aes) cryptography tables and cyclic redundancy check (crc) error detection functionality was inadvertently omitted from some datasheets. this has been added. in apint register, changed bit name from sysresetreq to sysresreq. added debug (debug priority) bit field to syspri3 register. clarified flash memory caution. restructured the general-purpose timer chapter to combine duplicated text. combined high and low bit fields in gptmtailr , gptmtamatchr , gptmtar , gptmtav , gptmtbilr , gptmtamatchr , gptmtbr and gptmtbv registers for compatibility with future releases. removed mention of false-start bit detection in the uart chapter. this feature is not supported. added ssi master clock restriction that ssiclk cannot be faster than 25 mhz. changed i 2 c master and slave register base addresses and offsets to be relative to i 2 c module base, so register base and offsets were changed for all i 2 c slave registers. in electrical characteristics chapter: C added single-ended clock source input voltage values to "recommended dc operating conditions" table. C deleted oscillation mode value from "mosc oscillator input characteristics" table. C added t vdd2_3 supply voltage parameter to "reset characteristics" table. C added "power-on reset and voltage parameters" timing diagram. C added t vddrise_hib su"pply voltage parameter to "hibernation module ac characteristics" table. C added "vdd ramp when waking from hibernation" timing diagram. 8832 december 2010 29 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 1. revision history (continued) description revision date reorganized arm cortex-m3 processor core, memory map and interrupts chapters, creating two new chapters, the cortex-m3 processor and cortex-m3 peripherals. much additional content was added, including all the cortex-m3 registers. changed register names to be consistent with stellarisware ? names: the cortex-m3 interrupt control and status (icsr) register to the interrupt control and state (intctrl) register, and the cortex-m3 interrupt set enable (setna) register to the interrupt 0-31 set enable (en0) register. in the system control chapter: C corrected reset sources table (see table 5-3 on page 182). C added section "special considerations for reset." in the hibernation module chapter, added section special considerations when using a 4.194304-mhz crystal on page 287. clarified how reset operation affects the hibernation module (register reset on page 291). in the internal memory chapter: C added clarification of instruction execution during flash operations. C deleted rom version (rmver) register as it is not used. modified figure 9-1 on page 409 and figure 9-2 on page 410 to clarify operation of the gpio inputs when used as an alternate function. corrected bit field in gpio analog mode select (gpioamsel) register to be eight-bits wide, bits[7:0]. in general-purpose timers chapter, clarified operation of the 32-bit rtc mode. in operating characteristics chapter, corrected thermal resistance (junction to ambient) value to 32. in electrical characteristics chapter: C added "input voltage for a gpio configured as an analog input" value to table 23-1 on page 964. C added parameter (gpio input leakage current) to table 23-6 on page 966. C corrected nom values for and in table 23-7 on page 966. C corrected reset timing in table 23-24 on page 976. C corrected values for in table 23-26 on page 978. C specified max value for in table 23-29 on page 981. C corrected values for ( rise/fall time) in table 23-31 on page 981. C added i 2 c characteristics table (see table 23-32 on page 983). added dimensions for tray and tape and reel shipping mediums. 7794 september 2010 in "thermal characteristics" table, corrected thermal resistance value from 34 to 32. 7413 june 2010 march 20, 2011 30 texas instruments-advance information revision history table 1. revision history (continued) description revision date removed 4.194304-mhz crystal as a source for the system clock and pll. summarized rom contents descriptions in the "internal memory" chapter and removed various rom appendices. clarified dma channel terminology: changed name of dma channel alternate select (dmachalt) register to dma channel assignment (dmachasgn) register, changed chalt bit field to chasgn, and changed terminology from primary and alternate channels to primary and secondary channels. in signal tables chapter, added table "connections for unused signals." in "electrical characteristics" chapter: C in "reset characteristics" table, corrected supply voltage (vdd) rise time. C clarified figure "sdram initialization and load mode register timing". 7299 june 2010 added data sheets for five new stellaris? tempest-class parts: lm3s1r26, lm3s1621, lm3s1b21, lm3s9781, and lm3s9b81. additional minor data sheet clarifications and corrections. 7164 may 2010 added pin table "possible pin assignments for alternate functions", which lists the signals based on number of possible pin assignments. this table can be used to plan how to configure the pins for a particular functionality. additional minor data sheet clarifications and corrections. 7101 may 2010 extended tbrl bit field in gptmtbr register. additional minor data sheet clarifications and corrections. 6983 march 2010 renamed the user_dbg register to the bootcfg register in the internal memory chapter. added information on how to use a gpio pin to force the rom boot loader to execute on reset. added three figures to the adc chapter on sample phase control. 6912 march 2010 31 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 1. revision history (continued) description revision date added 108-ball bga package. in "system control" chapter: C clarified functional description for external reset and brown-out reset. C clarified debug access port operation after sleep modes. C corrected the reset value of the run-mode clock configuration 2 (rcc2) register. in "internal memory" chapter, clarified wording on flash memory access errors and added a section on interrupts to the flash memory description. added clarification about timer operating modes and added register descriptions for the gptm timer n prescale match (gptmtnpmr) registers. clarified register descriptions for gptm timer a value (gptmtav) and gptm timer b value (gptmtbv) registers. corrected the reset value of the adc sample sequence result fifo n (adcssfifon) registers. added adc sample phase control (adcspc) register at offset 0x24. added caution note to the i 2 c master timer period (i2cmtpr) register description and changed field width to 7 bits. made these changes to the operating characteristics chapter: C added storage temperature ratings to "temperature characteristics" table C added "esd absolute maximum ratings" table made these changes to the electrical characteristics chapter: C in "flash memory characteristics" table, corrected mass erase time C added sleep and deep-sleep wake-up times ("sleep modes ac characteristics" table) C in "reset characteristics" table, corrected units for supply voltage (vdd) rise time C added table entry for vdd3on power consumption to table 23-7 on page 966. added additional driverlib functions to appendix. 6790 february 2010 march 20, 2011 32 texas instruments-advance information revision history table 1. revision history (continued) description revision date released new 1000, 3000, 5000 and 9000 series stellaris ? devices. the idcode value was corrected to be 0x4ba0.0477. clarified that the bit in the icsr register in the nvic is also a source for nmi. clarified the use of the ldo. to clarify clock operation, reorganized clocking section, changed the bit to the bit and the bit to the bit in the rcc2 register, added tables, and rewrote descriptions. corrected bit description of the field in the dslpclkcfg register. removed the dsflashcfg register at system control offset 0x14c as it does not function correctly. removed the and fields from the dcgc0 as they have no function in deep-sleep mode. corrected address offsets for the flash write buffer (fwbn) registers. added flash control (fctl) register at internal memory offset 0x0f8 to help control frequent power cycling when hibernation is not used. changed the name of the epi channels for clarification: epi0_tx became epi0_wfifo and epi0_rx became epi0_nbrfifo. this change was also made in the dc7 bit descriptions. removed the dmachis register at dma module offset 0x504 as it does not function correctly. corrected alternate channel assignments for the dma controller. major improvements to the epi chapter. episdramcfg2 register was deleted as its function is not needed. clarified pwm source for adc triggering changed ssi set up and hold times to be expressed in system clocks, not ns. updated electrical characteristics chapter with latest data. changes were made to hibernation, adc and epi content. additional minor data sheet clarifications and corrections. 6458 october 2009 33 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 1. revision history (continued) description revision date corrected values for maxadc0spd and maxadc1spd bits in dc1, rcgc0 , scgc0 , and dcgc0 registers. corrected figure "ti synchronous serial frame format (single transfer)". changed hib pin from type ttl to type od. made a number of corrections to the electrical characteristics chapter: C deleted v bat and v refa parameters from and added footnotes to recommended dc operating conditions table. C modified hibernation module dc characteristics table. C deleted nominal and maximum current specifications section. C deleted sdram read command timing, sdram write command timing, sdram write burst timing, sdram precharge command timing and sdram cas latency timing figures and replaced with sdram read timing and sdram write timing figures. C modified host-bus 8/16 mode write timing figure. C modified general-purpose mode read and write timing figure. C major changes to adc characteristics tables, including adding additonal tables and diagram. added missing rom_i2sintstatus function to rom driverlib functions appendix. corrected ordering part numbers. additional minor data sheet clarifications and corrections. 5930 july 2009 in system control chapter, clarified power-on reset and external reset pin descriptions in "reset sources" section. added missing comparator output pin bits to dc3 register; reset value changed as well. clarified explanation of nonvolatile register programming in internal memory chapter. added explanation of reset value to fmpre0/1/2/3 , fmppe0/1/2/3 , user_dbg , and user_reg0 registers. in request type support table in dma chapter, corrected general-purpose timer row. in general-purpose timers chapter, clarified dma operation. added table "preliminary current consumption" to characteristics chapter. corrected nom and max values in "hibernation detailed current specifications" table. corrected nom and max values in epi characteristics table. added "csn to output invalid" parameter to epi table "epi host-bus 8 and host-bus 16 interface characteristics" and figure "host-bus 8/16 mode read timing". corrected inl, dnl, off and gain values in adc characteristics table. updated rom driverlib appendix with revc0 functions. updated part ordering numbers. additional minor data sheet clarifications and corrections. 5779 june 2009 started tracking revision history. 5285 may 2009 march 20, 2011 34 texas instruments-advance information revision history about this document this data sheet provides reference information for the lm3s1p51 microcontroller, describing the functional blocks of the system-on-chip (soc) device designed around the arm? cortex?-m3 core. audience this manual is intended for system software developers, hardware designers, and application developers. about this manual this document is organized into sections that correspond to each major feature. related documents the following related documents are available on the stellaris ? web site at www.ti.com/stellaris: stellaris? errata arm? cortex?-m3 errata cortex?-m3 instruction set technical user's manual stellaris? boot loader user's guide stellaris? graphics library user's guide stellaris? peripheral driver library user's guide stellaris? rom users guide the following related documents are also referenced: arm? debug interface v5 architecture specification ieee standard 1149.1-test access port and boundary-scan architecture this documentation list was current as of publication date. please check the web site for additional documentation, including application notes and white papers. 35 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller documentation conventions this document uses the conventions shown in table 2 on page 36. table 2. documentation conventions meaning notation general register notation apb registers are indicated in uppercase bold. for example, pborctl is the power-on and brown-out reset control register. if a register name contains a lowercase n, it represents more than one register. for example, srcrn represents any (or all) of the three software reset control registers: srcr0, srcr1 , and srcr2 . register a single bit in a register. bit two or more consecutive and related bits. bit field a hexadecimal increment to a register's address, relative to that module's base address as specified in table 2-4 on page 79. offset 0x nnn registers are numbered consecutively throughout the document to aid in referencing them. the register number has no meaning to software. register n register bits marked reserved are reserved for future use. in most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. to provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved the range of register bits inclusive from xx to yy. for example, 31:15 means bits 15 through 31 in that register. yy:xx this value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. register bit/field types software can read this field. the bit or field is cleared by hardware after reading the bit/field. rc software can read this field. always write the chip reset value. ro software can read or write this field. r/w software can read or write this field. writing to it with any value clears the register. r/wc software can read or write this field. a write of a 0 to a w1c bit does not affect the bit value in the register. a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. this register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. r/w1c software can read or write a 1 to this field. a write of a 0 to a r/w1s bit does not affect the bit value in the register. r/w1s software can write this field. a write of a 0 to a w1c bit does not affect the bit value in the register. a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. a read of the register returns no meaningful data. this register is typically used to clear the corresponding bit in an interrupt register. w1c only a write by software is valid; a read of the register returns no meaningful data. wo this value in the register bit diagram shows the bit/field value after any reset, unless noted. register bit/field reset value bit cleared to 0 on chip reset. 0 bit set to 1 on chip reset. 1 nondeterministic. - pin/signal notation pin alternate function; a pin defaults to the signal without the brackets. [ ] refers to the physical connection on the package. pin refers to the electrical signal encoding of a pin. signal march 20, 2011 36 texas instruments-advance information about this document table 2. documentation conventions (continued) meaning notation change the value of the signal from the logically false state to the logically true state. for active high signals, the asserted signal value is 1 (high); for active low signals, the asserted signal value is 0 (low). the active polarity (high or low) is defined by the signal name (see signal and signal below). assert a signal change the value of the signal from the logically true state to the logically false state. deassert a signal signal names are in uppercase and in the courier font. an overbar on a signal name indicates that it is active low. to assert signal is to drive it low; to deassert signal is to drive it high. signal signal names are in uppercase and in the courier font. an active high signal has no overbar. to assert signal is to drive it high; to deassert signal is to drive it low. signal numbers an uppercase x indicates any of several values is allowed, where x can be any legal pattern. for example, a binary value of 0x00 can be either 0100 or 0000, a hex value of 0xx is 0x0 or 0x1, and so on. x hexadecimal numbers have a prefix of 0x. for example, 0x00ff is the hexadecimal number ff. all other numbers within register tables are assumed to be binary. within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 0x 37 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 1 architectural overview texas instruments is the industry leader in bringing 32-bit capabilities and the full benefits of arm ? cortex ? -m3-based microcontrollers to the broadest reach of the microcontroller market. for current users of 8- and 16-bit mcus, stellaris ? with cortex-m3 offers a direct path to the strongest ecosystem of development tools, software and knowledge in the industry. designers who migrate to stellaris benefit from great tools, small code footprint and outstanding performance. even more important, designers can enter the arm ecosystem with full confidence in a compatible roadmap from $1 to 1 ghz. for users of current 32-bit mcus, the stellaris family offers the industrys first implementation of cortex-m3 and the thumb-2 instruction set. with blazingly-fast responsiveness, thumb-2 technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density and performance. thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system cost while delivering 25 percent better performance. the texas instruments stellaris family of microcontrollersthe first arm cortex-m3 based controllersbrings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. these pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. the lm3s1p51 microcontroller has the following features: arm cortex-m3 processor core C 80-mhz operation; 100 dmips performance C arm cortex systick timer C nested vectored interrupt controller (nvic) on-chip memory C 64 kb single-cycle flash memory up to 50 mhz; a prefetch buffer improves performance above 50 mhz C 24 kb single-cycle sram C internal rom loaded with stellarisware ? software: ? stellaris peripheral driver library ? stellaris boot loader ? advanced encryption standard (aes) cryptography tables ? cyclic redundancy check (crc) error detection functionality advanced serial integration C three uarts with irda and iso 7816 support (one uart with full modem controls) C two i 2 c modules C two synchronous serial interface modules (ssi) C integrated interchip sound (i 2 s) module system integration C direct memory access controller (dma) march 20, 2011 38 texas instruments-advance information architectural overview C system control and clocks including on-chip precision 16-mhz oscillator C four 32-bit timers (up to eight 16-bit) C eight capture compare pwm pins (ccp) C lower-power battery-backed hibernation module C real-time clock in hibernation module C two watchdog timers ? one timer runs off the main oscillator ? one timer runs off the precision internal oscillator C up to 67 gpios, depending on configuration ? highly flexible pin muxing allows use as gpio or one of several peripheral functions ? independently configurable to 2, 4 or 8 ma drive capability ? up to 4 gpios can have 18 ma drive capability advanced motion control C six advanced pwm outputs for motion and energy applications C four fault inputs to promote low-latency shutdown C two quadrature encoder inputs (qei) analog C two 10-bit analog-to-digital converters (adc) with 16 analog input channels and a sample rate of one million samples/second C two analog comparators C 16 digital comparators C on-chip voltage regulator jtag and arm serial wire debug (swd) 100-pin lqfp and 108-ball bga package industrial (-40c to 85c) temperature range the lm3s1p51 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, hvac and building control, gaming equipment, motion control, medical instrumentation, and fire and security. for applications requiring extreme conservation of power, the lm3s1p51 microcontroller features a battery-backed hibernation module to efficiently power down the lm3s1p51 to a low-power state during extended periods of inactivity. with a power-up/power-down sequencer, a continuous time counter (rtc), a pair of match registers, an apb interface to the system bus, and dedicated non-volatile memory, the hibernation module positions the lm3s1p51 microcontroller perfectly for battery applications. 39 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller in addition, the lm3s1p51 microcontroller offers the advantages of arm's widely available development tools, system-on-chip (soc) infrastructure ip applications, and a large user community. additionally, the microcontroller uses arm's thumb?-compatible thumb-2 instruction set to reduce memory requirements and, thereby, cost. finally, the lm3s1p51 microcontroller is code-compatible to all members of the extensive stellaris family; providing flexibility to fit our customers' precise needs. texas instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. see ordering and contact information on page 1017 for ordering information for stellaris family devices. 1.1 functional overview the following sections provide an overview of the features of the lm3s1p51 microcontroller. the page number in parentheses indicates where that feature is discussed in detail. ordering and support information can be found in ordering and contact information on page 1017. 1.1.1 arm cortex-m3 the following sections provide an overview of the arm cortex-m3 processor core and instruction set, the integrated system timer (systick) and the nested vectored interrupt controller. 1.1.1.1 processor core (see page 60) all members of the stellaris product family, including the lm3s1p51 microcontroller, are designed around an arm cortex-m3 processor core. the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. 32-bit arm cortex-m3 architecture optimized for small-footprint embedded applications outstanding processing performance combined with fast interrupt handling thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit arm core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications C single-cycle multiply instruction and hardware divide C atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control C unaligned data access, enabling data to be efficiently packed into memory fast code execution permits slower processor clock or increases sleep mode time harvard architecture characterized by separate buses for instruction and data efficient processor core, system and memories hardware division and fast multiplier deterministic, high-performance interrupt handling for time-critical applications march 20, 2011 40 texas instruments-advance information architectural overview memory protection unit (mpu) to provide a privileged mode for protected operating system functionality enhanced system debug with extensive breakpoint and trace capabilities serial wire debug and serial wire trace reduce the number of pins required for debugging and tracing migration from the arm7 processor family for better performance and power efficiency optimized for single-cycle flash memory usage ultra-low power consumption with integrated sleep modes 80-mhz operation 1.25 dmips/mhz 1.1.1.2 memory map (see page 79) a memory map lists the location of instructions and data in memory. the memory map for the lm3s1p51 controller can be found in memory model on page 79. register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. 1.1.1.3 system timer (systick) (see page 103) arm cortex-m3 includes an integrated system timer, systick. systick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. the counter can be used in several different ways, for example: an rtos tick timer that fires at a programmable rate (for example, 100 hz) and invokes a systick routine a high-speed alarm timer using the system clock a variable rate alarm or signal timerthe duration is range-dependent on the reference clock used and the dynamic range of the counter a simple counter used to measure time to completion and time used an internal clock-source control based on missing/meeting durations. 1.1.1.4 nested vectored interrupt controller (nvic) (see page 104) the lm3s1p51 controller includes the arm nested vectored interrupt controller (nvic). the nvic and cortex-m3 prioritize and handle all exceptions in handler mode. the processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (isr). the interrupt vector is fetched in parallel to the state saving, enabling efficient interrupt entry. the processor supports tail-chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. software can set eight priority levels on 7 exceptions (system handlers) and 47 interrupts. deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining external non-maskable interrupt signal (nmi) available for immediate execution of nmi handler for safety critical applications 41 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller dynamically reprioritizable interrupts exceptional interrupt handling via hardware implementation of required register manipulations 1.1.1.5 system control block (scb) (see page 106) the scb provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.1.1.6 memory protection unit (mpu) (see page 106) the mpu supports the standard arm7 protected memory system architecture (pmsa) model. the mpu provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.1.2 on-chip memory the following sections describe the on-chip memory modules. 1.1.2.1 sram (see page 311) the lm3s1p51 microcontroller provides 24 kb of single-cycle on-chip sram. the internal sram of the stellaris devices is located at offset 0x2000.0000 of the device memory map. because read-modify-write (rmw) operations are very time consuming, arm has introduced bit-banding technology in the cortex-m3 processor. with a bit-band-enabled processor, certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. data can be transferred to and from the sram using the micro direct memory access controller (dma). 1.1.2.2 flash memory (see page 313) the lm3s1p51 microcontroller provides 64 kb of single-cycle on-chip flash memory (above 50 mhz, the flash memory can be accessed in a single cycle as long as the code is linear; branches incur a one-cycle stall). the flash memory is organized as a set of 1-kb blocks that can be individually erased. erasing a block causes the entire contents of the block to be reset to all 1s. these blocks are paired into a set of 2-kb blocks that can be individually protected. the blocks can be marked as read-only or execute-only, providing different levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.1.2.3 rom (see page 311) the lm3s1p51 rom is preprogrammed with the following software and programs: stellaris peripheral driver library stellaris boot loader advanced encryption standard (aes) cryptography tables cyclic redundancy check (crc) error-detection functionality march 20, 2011 42 texas instruments-advance information architectural overview the stellaris peripheral driver library is a royalty-free software library for controlling on-chip peripherals with a boot-loader capability. the library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. in addition, the library is designed to take full advantage of the stellar interrupt performance of the arm cortex-m3 core. no special pragmas or custom assembly code prologue/epilogue functions are required. for applications that require in-field programmability, the royalty-free stellaris boot loader can act as an application loader and support in-field firmware updates. the advanced encryption standard (aes) is a publicly defined encryption standard used by the u.s. government. aes is a strong encryption method with reasonable performance and size. in addition, it is fast in both hardware and software, is fairly easy to implement, and requires little memory. the texas instruments encryption package is available with full source code, and is based on lesser general public license (lgpl) source. an lgpl means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source). modifications to the package source, however, must be open source. crc (cyclic redundancy check) is a technique to validate a span of data has the same contents as when previously checked. this technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that flash memory contents have not been changed, and for other cases where the data needs to be validated. a crc is preferred over a simple checksum (e.g. xor all bits) because it catches changes more readily. 1.1.3 serial communications peripherals the lm3s1p51 controller supports both asynchronous and synchronous serial communications with: three uarts with irda and iso 7816 support (one uart with full modem controls) two i 2 c modules two synchronous serial interface modules (ssi) integrated interchip sound (i 2 s) module the following sections provide more detail on each of these communications functions. 1.1.3.1 uart (see page 610) a universal asynchronous receiver/transmitter (uart) is an integrated circuit used for rs-232c serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. the lm3s1p51 microcontroller includes three fully programmable 16c550-type uarts. although the functionality is similar to a 16c550 uart, this uart design is not register compatible. the uart can generate individually masked interrupts from the rx, tx, modem status, and error conditions. the module generates a single combined interrupt when any of the interrupts are asserted and are unmasked. the three uarts have the following features: programmable baud-rate generator allowing speeds up to 5 mbps for regular speed (divide by 16) and 10 mbps for high speed (divide by 8) separate 16x8 transmit (tx) and receive (rx) fifos to reduce cpu interrupt service loading 43 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller programmable fifo length, including 1-byte deep operation providing conventional double-buffered interface fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 standard asynchronous communication bits for start, stop, and parity line-break generation and detection fully programmable serial interface characteristics C 5, 6, 7, or 8 data bits C even, odd, stick, or no-parity bit generation/detection C 1 or 2 stop bit generation irda serial-ir (sir) encoder/decoder providing C programmable use of irda serial infrared (sir) or uart input/output C support of irda sir encoder/decoder functions for data rates up to 115.2 kbps half-duplex C support of normal 3/16 and low-power (1.41-2.23 s) bit durations C programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration support for communication with iso 7816 smart cards full modem handshake support (on uart1) lin protocol support standard fifo-level and end-of-transmission interrupts efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive single request asserted when data is in the fifo; burst request asserted at programmed fifo level C transmit single request asserted when there is space in the fifo; burst request asserted at programmed fifo level 1.1.3.2 i 2 c (see page 714) the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sda and a serial clock line scl). the i 2 c bus interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture. march 20, 2011 44 texas instruments-advance information architectural overview each device on the i 2 c bus can be designated as either a master or a slave. each i 2 c module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. both the i 2 c master and slave can generate interrupts. the lm3s1p51 microcontroller includes two i 2 c modules with the following features: devices on the i 2 c bus can be designated as either a master or a slave C supports both transmitting and receiving data as either a master or a slave C supports simultaneous master and slave operation four i 2 c modes C master transmit C master receive C slave transmit C slave receive two transmission speeds: standard (100 kbps) and fast (400 kbps) master and slave interrupt generation C master generates interrupts when a transmit or receive operation completes (or aborts due to an error) C slave generates interrupts when data has been transferred or requested by a master or when a start or stop condition is detected master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 1.1.3.3 ssi (see page 671) synchronous serial interface (ssi) is a four-wire bi-directional communications interface that converts data between parallel and serial. the ssi module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. the ssi module can be configured as either a master or slave device. as a slave device, the ssi module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. the tx and rx paths are buffered with separate internal fifos. the ssi module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the ssi module's input clock. bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. the lm3s1p51 microcontroller includes two ssi modules with the following features: programmable interface operation for freescale spi, microwire, or texas instruments synchronous serial interfaces master or slave operation programmable clock bit rate and prescaler 45 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller separate transmit and receive fifos, each 16 bits wide and 8 locations deep programmable data frame size from 4 to 16 bits internal loopback test mode for diagnostic/debug testing standard fifo-based interrupts and end-of-transmission interrupt efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive single request asserted when data is in the fifo; burst request asserted when fifo contains 4 entries C transmit single request asserted when there is space in the fifo; burst request asserted when fifo contains 4 entries 1.1.3.4 inter-integrated circuit sound (i 2 s) interface (see page 751) the i 2 s interface is a configurable serial audio core that contains a transmit module and a receive module. the module is configurable for the i 2 s as well as left-justified and right-justified serial audio formats. data can be in one of four modes: stereo, mono, compact 16-bit stereo and compact 8-bit stereo. the transmit and receive modules each have an 8-entry audio-sample fifo. an audio sample can consist of a left and right stereo sample, a mono sample, or a left and right compact stereo sample. in compact 16-bit stereo, each fifo entry contains both the 16-bit left and 16-bit right samples, allowing efficient data transfers and requiring less memory space. in compact 8-bit stereo, each fifo entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements further. both the transmitter and receiver are capable of being a master or a slave. the stellaris i 2 s interface has the following features: configurable audio format supporting i 2 s, left-justification, and right-justification configurable sample size from 8 to 32 bits mono and stereo support 8-, 16-, and 32-bit fifo interface for packing memory independent transmit and receive 8-entry fifos configurable fifo-level interrupt and dma requests independent transmit and receive mclk direction control transmit and receive internal mclk sources independent transmit and receive control for serial clock and word select mclk and sclk can be independently set to master or slave configurable transmit zero or last sample when fifo empty march 20, 2011 46 texas instruments-advance information architectural overview efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C burst requests C channel requests asserted when fifo contains required amount of data 1.1.4 system integration the lm3s1p51 microcontroller provides a variety of standard system functions integrated into the device, including: direct memory access controller (dma) system control and clocks including on-chip precision 16-mhz oscillator four 32-bit timers (up to eight 16-bit) eight capture compare pwm pins (ccp) lower-power battery-backed hibernation module real-time clock in hibernation module two watchdog timers C one timer runs off the main oscillator C one timer runs off the precision internal oscillator up to 67 gpios, depending on configuration C highly flexible pin muxing allows use as gpio or one of several peripheral functions C independently configurable to 2, 4 or 8 ma drive capability C up to 4 gpios can have 18 ma drive capability the following sections provide more detail on each of these functions. 1.1.4.1 direct memory access (see page 346) the lm3s1p51 microcontroller includes a direct memory access (dma) controller, known as micro-dma (dma). the dma controller provides a way to offload data transfer tasks from the cortex-m3 processor, allowing for more efficient use of the processor and the available bus bandwidth. the dma controller can perform transfers between memory and peripherals. it has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. the dma controller provides the following features: arm primecell ? 32-channel configurable dma controller support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes C basic for simple transfer scenarios C ping-pong for continuous data flow C scatter-gather for a programmable list of arbitrary transfers initiated from a single request 47 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller highly flexible and configurable channel operation C independently configured and operated channels C dedicated channels for supported on-chip modules C primary and secondary channel assignments C one channel each for receive and transmit path for bidirectional modules C dedicated channel for software-initiated transfers C per-channel configurable priority scheme C optional software-initiated requests for any channel two levels of priority design optimizations for improved bus access performance between dma controller and the processor core C dma controller access is subordinate to core access C ram striping C peripheral bus segmentation data sizes of 8, 16, and 32 bits transfer size is programmable in binary steps from 1 to 1024 source and destination address increment size of byte, half-word, word, or no increment maskable peripheral requests 1.1.4.2 system control and clocks (see page 181) system control determines the overall operation of the device. it provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. device identification information: version, part number, sram size, flash memory size, and so on power control C on-chip fixed low drop-out (ldo) voltage regulator C hibernation module handles the power-up/down 3.3 v sequencing and control for the core digital logic and analog circuits C low-power options for microcontroller: sleep and deep-sleep modes with clock gating C low-power options for on-chip modules: software controls shutdown of individual peripherals and memory C 3.3-v supply brown-out detection and reporting via interrupt or reset march 20, 2011 48 texas instruments-advance information architectural overview multiple clock sources for microcontroller system clock C precision oscillator (piosc): on-chip resource providing a 16 mhz 1% frequency at room temperature ? 16 mhz 3% across temperature ? can be recalibrated with 7-bit trim resolution ? software power down control for low power modes C main oscillator (mosc): a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the osc0 input pin, or an external crystal is connected across the osc0 input and osc1 output pins. ? external oscillator used with or without on-chip pll: select supported frequencies from 1 mhz to 16.384 mhz. ? external crystal: from dc to maximum device speed C internal 30-khz oscillator: on chip resource providing a 30 khz 50% frequency, used during power-saving modes C 32.768-khz external oscillator for the hibernation module: eliminates need for additional crystal for main clock source flexible reset sources C power-on reset (por) C reset pin assertion C brown-out reset (bor) detector alerts to system power drops C software reset C watchdog timer reset C mosc failure 1.1.4.3 programmable timers (see page 460) programmable timers can be used to count or time external events that drive the timer input pins. each gptm block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit real-time clock (rtc). timers can also be used to trigger analog-to-digital (adc) conversions. the general-purpose timer module (gptm) contains four gptm blocks with the following functional options: operating modes: C 16- or 32-bit programmable one-shot timer C 16- or 32-bit programmable periodic timer C 16-bit general-purpose timer with an 8-bit prescaler C 32-bit real-time clock (rtc) when using an external 32.768-khz clock as the input C 16-bit input-edge count- or time-capture modes 49 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller C 16-bit pwm mode with software-programmable output inversion of the pwm signal count up or down eight capture compare pwm pins (ccp) daisy chaining of timer modules to allow a single timer to initiate multiple timing events adc event trigger user-enabled stalling when the microcontroller asserts cpu halt flag during debug (excluding rtc mode) ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. efficient transfers using micro direct memory access controller (dma) C dedicated channel for each timer C burst request generated on timer interrupt 1.1.4.4 ccp pins (see page 467) capture compare pwm pins (ccp) can be used by the general-purpose timer module to time/count external events using the ccp pin as an input. alternatively, the gptm can generate a simple pwm output on the ccp pin. the lm3s1p51 microcontroller includes eight capture compare pwm pins (ccp) that can be programmed to operate in the following modes: capture: the gp timer is incremented/decremented by programmed events on the ccp input. the gp timer captures and stores the current timer value when a programmed event occurs. compare: the gp timer is incremented/decremented by programmed events on the ccp input. the gp timer compares the current value with a stored value and generates an interrupt when a match occurs. pwm: the gp timer is incremented/decremented by the system clock. a pwm signal is generated based on a match between the counter value and a value stored in a match register and is output on the ccp pin. 1.1.4.5 hibernation module (see page 282) the hibernation module provides logic to switch power off to the main processor and peripherals and to wake on external or time-based events. the hibernation module includes power-sequencing logic and has the following features: 32-bit real-time counter (rtc) C two 32-bit rtc match registers for timed wake-up and interrupt generation C rtc predivider trim for making fine adjustments to the clock rate two mechanisms for power control C system power control using discrete external regulator march 20, 2011 50 texas instruments-advance information architectural overview C on-chip power control using internal switches under register control dedicated pin for waking using an external signal rtc operational and hibernation memory valid as long as v bat is valid low-battery detection, signaling, and interrupt generation clock source from a 32.768-khz external oscillator or a 4.194304-mhz crystal; 32.768-khz external oscillator can be used for main controller clock 64 32-bit words of non-volatile memory to save state during hibernation programmable interrupts for rtc match, external wake, and low battery events 1.1.4.6 watchdog timers (see page 506) a watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. the stellaris watchdog timer can generate an interrupt or a reset when a time-out value is reached. in addition, the watchdog timer is arm firm-compliant and can be configured to generate an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second time-out. once the watchdog timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. the lm3s1p51 microcontroller has two watchdog timer modules: watchdog timer 0 uses the system clock for its timer clock; watchdog timer 1 uses the piosc as its timer clock. the stellaris watchdog timer module has the following features: 32-bit down counter with a programmable load register separate watchdog clock with an enable programmable interrupt generation logic with interrupt masking lock register protection from runaway software reset generation logic with an enable/disable user-enabled stalling when the microcontroller asserts the cpu halt flag during debug 1.1.4.7 programmable gpios (see page 404) general-purpose input/output (gpio) pins offer flexibility for a variety of connections. the stellaris gpio module is comprised of nine physical gpio blocks, each corresponding to an individual gpio port. the gpio module is firm-compliant (compliant to the arm foundation ip for real-time microcontrollers specification) and supports 0-67 programmable input/output pins. the number of gpios available depends on the peripherals being used (see signal tables on page 898 for the signals available to each gpio pin). up to 67 gpios, depending on configuration highly flexible pin muxing allows use as gpio or one of several peripheral functions 5-v-tolerant in input configuration fast toggle capable of a change every two clock cycles 51 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller two means of port access: either advanced high-performance bus (ahb) with better back-to-back access performance, or the legacy advanced peripheral bus (apb) for backwards-compatibility with existing code programmable control for gpio interrupts C interrupt generation masking C edge-triggered on rising, falling, or both C level-sensitive on high or low values bit masking in both read and write operations through address lines can be used to initiate an adc sample sequence pins configured as digital inputs are schmitt-triggered programmable control for gpio pad configuration C weak pull-up or pull-down resistors C 2-ma, 4-ma, and 8-ma pad drive for digital communication; up to four pads can be configured with an 18-ma pad drive for high-current applications C slew rate control for the 8-ma drive C open drain enables C digital input enables 1.1.5 advanced motion control the lm3s1p51 microcontroller provides motion control functions integrated into the device, including: six advanced pwm outputs for motion and energy applications four fault inputs to promote low-latency shutdown two quadrature encoder inputs (qei) the following provides more detail on these motion control functions. 1.1.5.1 pwm (see page 800) pulse width modulation (pwm) is a powerful technique for digitally encoding analog signal levels. high-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. typical applications include switching power supplies and motor control. the lm3s1p51 pwm module consists of three pwm generator blocks and a control block. each pwm generator block contains one timer (16-bit down or up/down counter), two comparators, a pwm signal generator, a dead-band generator, and an interrupt/adc-trigger selector. each pwm generator block produces two pwm signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. each pwm generator has the following features: march 20, 2011 52 texas instruments-advance information architectural overview four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled one 16-bit counter C runs in down or up/down mode C output frequency controlled by a 16-bit load value C load value updates can be synchronized C produces output signals at zero and load value two pwm comparators C comparator value updates can be synchronized C produces output signals on match pwm signal generator C output pwm signal is constructed based on actions taken as a result of the counter and pwm comparator output signals C produces two independent pwm signals dead-band generator C produces two pwm signals with programmable dead-band delays suitable for driving a half-h bridge C can be bypassed, leaving input pwm signals unmodified can initiate an adc sample sequence the control block determines the polarity of the pwm signals and which signals are passed through to the pins. the output of the pwm generation blocks are managed by the output control block before being passed to the device pins. the pwm control block has the following options: pwm output enable of each pwm signal optional output inversion of each pwm signal (polarity control) optional fault handling for each pwm signal synchronization of timers in the pwm generator blocks synchronization of timer/comparator updates across the pwm generator blocks synchronization of pwm output enables across the pwm generator blocks interrupt status summary of the pwm generator blocks extended fault capabilities with multiple fault signals, programmable polarities, and filtering pwm generators can be operated independently or synchronized with other generators 53 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 1.1.5.2 qei (see page 873) a quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. by monitoring both the number of pulses and the relative phase of the two signals, the position, direction of rotation, and speed can be tracked. in addition, a third channel, or index signal, can be used to reset the position counter. the stellaris quadrature encoder with index (qei) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. the input frequency of the qei inputs may be as high as 1/4 of the processor frequency (for example, 20 mhz for a 80-mhz system). the lm3s1p51 microcontroller includes two qei modules providing control of two motors at the same time with the following features: position integrator that tracks the encoder position programmable noise filter on the inputs velocity capture using built-in timer the input frequency of the qei inputs may be as high as 1/4 of the processor frequency (for example, 12.5 mhz for a 50-mhz system) interrupt generation on: C index pulse C velocity-timer expiration C direction change C quadrature error detection 1.1.6 analog the lm3s1p51 microcontroller provides analog functions integrated into the device, including: two 10-bit analog-to-digital converters (adc) with 16 analog input channels and a sample rate of one million samples/second two analog comparators 16 digital comparators on-chip voltage regulator the following provides more detail on these analog functions. 1.1.6.1 adc (see page 531) an analog-to-digital converter (adc) is a peripheral that converts a continuous analog voltage to a discrete digital number. the stellaris adc module features 10-bit conversion resolution and supports 16 input channels plus an internal temperature sensor. four buffered sample sequencers allow rapid sampling of up to 16 analog input sources without controller intervention. each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. each adc module has a digital comparator function that allows the conversion value to be diverted to a comparison unit that provides eight digital comparators. march 20, 2011 54 texas instruments-advance information architectural overview the lm3s1p51 microcontroller provides two adc modules with the following features: 16 shared analog input channels single-ended and differential-input configurations on-chip internal temperature sensor maximum sample rate of one million samples/second optional phase shift in sample time programmable from 22.5o to 337.5o four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result fifos flexible trigger control C controller (software) C timers C analog comparators C pwm C gpio hardware averaging of up to 64 samples for improved accuracy digital comparison unit providing eight digital comparators converter uses an internal 3-v reference or an external reference power and ground for the analog circuitry is separate from the digital power and ground efficient transfers using micro direct memory access controller (dma) C dedicated channel for each sample sequencer C adc module uses burst requests for dma 1.1.6.2 analog comparators (see page 787) an analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. the lm3s1p51 microcontroller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt or adc event. the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the adc to cause it to start capturing a sample sequence. the interrupt generation and adc triggering logic is separate. this means, for example, that an interrupt can be generated on a rising edge and the adc triggered on a falling edge. the lm3s1p51 microcontroller provides two independent integrated analog comparators with the following functions: 55 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller compare external pin input to external pin input or to internal programmable voltage reference compare a test voltage against any one of the following voltages: C an individual external reference voltage C a shared single external reference voltage C a shared internal reference voltage 1.1.7 jtag and arm serial wire debug (see page 169) the joint test action group (jtag) port is an ieee standard that defines a test access port and boundary scan architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. the tap, instruction register (ir), and data registers (dr) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. the jtag port also provides a means of accessing and controlling design-for-test features such as i/o pin observation and control, scan testing, and debugging. texas instruments replaces the arm sw-dp and jtag-dp with the arm serial wire jtag debug port (swj-dp) interface. the swj-dp interface combines the swd and jtag debug ports into one module providing all the normal jtag debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. the swj-dp interface has the following features: ieee 1149.1-1990 compatible test access port (tap) controller four-bit instruction register (ir) chain for storing jtag instructions ieee standard instructions: bypass, idcode, sample/preload, extest and intest arm additional instructions: apacc, dpacc and abort integrated arm serial wire debug (swd) C serial wire jtag debug port (swj-dp) C flash patch and breakpoint (fpb) unit for implementing breakpoints C data watchpoint and trace (dwt) unit for implementing watchpoints, trigger resources, and system profiling C instrumentation trace macrocell (itm) for support of printf style debugging C trace port interface unit (tpiu) for bridging to a trace port analyzer 1.1.8 packaging and temperature industrial-range 100-pin rohs-compliant lqfp package industrial-range 108-ball rohs-compliant bga package 1.2 target applications the stellaris family is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities such as: march 20, 2011 56 texas instruments-advance information architectural overview test and measurement equipment factory automation hvac and building control gaming equipment motion control medical instrumentation fire and security power and energy transportation 1.3 high-level block diagram figure 1-1 on page 58 depicts the features on the stellaris lm3s1p51 microcontroller. note that there are two on-chip buses that connect the core to the peripherals. the advanced peripheral bus (apb) bus is the legacy bus. the advanced high-performance bus (ahb) bus provides better back-to-back access performance than the apb bus. 57 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 1-1. stellaris lm3s1p51 microcontroller high-level block diagram march 20, 2011 58 texas instruments-advance information architectural overview lm3s1p51 arm? cor te x?-m3 (80 mhz) nvic mpu flash (64 kb) boot loader dr iv erlib aes & crc r om dcode b us icode b us jt a g/swd system control and cloc ks (w/ precis . osc.) bus matr ix system bus sram (24 kb) system peripherals w atchdog timers (2) dma hiber nation module gener al- pur pose timers (4) gpios (67) serial peripherals u ar ts (3) i2c (2) ssi (2) i2s analog peripherals adc channels (16) analog compar ators (2) mo tion contr ol peripherals qei (2) pwm (6) adv anced p er ipher al bus (apb) adv anced high-p erf or mance bus (ahb) 1.4 hardware details details on the pins and package can be found in the following sections: pin diagram on page 896 signal tables on page 898 operating characteristics on page 963 electrical characteristics on page 964 package information on page 1019 59 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 2 the cortex-m3 processor the arm? cortex?-m3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. features include: 32-bit arm ? cortex ? -m3 architecture optimized for small-footprint embedded applications outstanding processing performance combined with fast interrupt handling thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit arm core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications C single-cycle multiply instruction and hardware divide C atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control C unaligned data access, enabling data to be efficiently packed into memory fast code execution permits slower processor clock or increases sleep mode time harvard architecture characterized by separate buses for instruction and data efficient processor core, system and memories hardware division and fast multiplier deterministic, high-performance interrupt handling for time-critical applications memory protection unit (mpu) to provide a privileged mode for protected operating system functionality enhanced system debug with extensive breakpoint and trace capabilities serial wire debug and serial wire trace reduce the number of pins required for debugging and tracing migration from the arm7 processor family for better performance and power efficiency optimized for single-cycle flash memory usage ultra-low power consumption with integrated sleep modes 80-mhz operation 1.25 dmips/mhz the stellaris ? family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. march 20, 2011 60 texas instruments-advance information the cortex-m3 processor this chapter provides information on the stellaris implementation of the cortex-m3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. for technical details on the instruction set, see the cortex?-m3 instruction set technical user's manual. 2.1 block diagram the cortex-m3 processor is built on a high-performance processor core, with a 3-stage pipeline harvard architecture, making it ideal for demanding embedded applications. the processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division. to facilitate the design of cost-sensitive devices, the cortex-m3 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. the cortex-m3 processor implements a version of the thumb? instruction set, ensuring high code density and reduced program memory requirements. the cortex-m3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. the cortex-m3 processor closely integrates a nested interrupt controller (nvic), to deliver industry-leading interrupt performance. the stellaris nvic includes a non-maskable interrupt (nmi) and provides eight interrupt priority levels. the tight integration of the processor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing interrupt latency. the hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. interrupt handlers do not require any assembler stubs which removes code overhead from the isrs. tail-chaining optimization also significantly reduces the overhead when switching from one isr to another. to optimize low-power designs, the nvic integrates with the sleep modes, including deep-sleep mode, which enables the entire device to be rapidly powered down. 61 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 2-1. cpu block diagram 2.2 overview 2.2.1 system-level interface the cortex-m3 processor provides multiple interfaces using amba? technology to provide high-speed, low-latency memory accesses. the core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe boolean data handling. the cortex-m3 processor has a memory protection unit (mpu) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis. 2.2.2 integrated configurable debug the cortex-m3 processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional jtag port or a 2-pin serial wire debug (swd) port that is ideal for microcontrollers and other small package devices. the stellaris implementation replaces the arm sw-dp and jtag-dp with the arm coresight?-compliant serial wire jtag debug port (swj-dp) interface. the swj-dp interface combines the swd and jtag debug ports into one module. see the arm? debug interface v5 architecture specification for details on swj-dp. for system trace, the processor integrates an instrumentation trace macrocell (itm) alongside data watchpoints and a profiling unit. to enable simple and cost-effective profiling of the system trace events, a serial wire viewer (swv) can export a stream of software-generated messages, data trace, and profiling information through a single pin. march 20, 2011 62 texas instruments-advance information the cortex-m3 processor 3 u l y d w h 3 h u l s k h u d o % x v l q w h u q d o ' d w d : d w f k s r l q w d q g 7 u d f h , q w h u u x s w v ' h e x j 6 o h h s , q v w u x p h q w d w l r q 7 u d f h 0 d f u r f h o o 7 u d f h 3 r u w , q w h u i d f h 8 q l w & 0 & r u h , q v w u x f w l r q v ' d w d ) o d v k 3 d w f k d q g % u h d n s r l q w 0 h p r u \ 3 u r w h f w l r q 8 q l w ' h e x j $ f f h v v 3 r u w 1 h v w h g 9 h f w r u h g , q w h u u x s w & r q w u r o o h u 6 h u l d o : l u h - 7 $ * ' h e x j 3 r u w % x v 0 d w u l [ $ g y 3 h u l s k h u d o % x v , f r g h e x v ' f r g h e x v 6 \ v w h p e x v 5 2 0 7 d e o h 6 h u l d o : l u h 2 x w s x w 7 u d f h 3 r u w 6 : 2 $ 5 0 & r u w h [ 0 the flash patch and breakpoint unit (fpb) provides up to eight hardware breakpoint comparators that debuggers can use. the comparators in the fpb also provide remap functions of up to eight words in the program code in the code memory region. this enables applications stored in a read-only area of flash memory to be patched in another area of on-chip sram or flash memory. if a patch is required, the application programs the fpb to remap a number of addresses. when those addresses are accessed, the accesses are redirected to a remap table specified in the fpb configuration. for more information on the cortex-m3 debug capabilities, see the arm? debug interface v5 architecture specification . 2.2.3 trace port interface unit (tpiu) the tpiu acts as a bridge between the cortex-m3 trace data from the itm, and an off-chip trace port analyzer, as shown in figure 2-2 on page 63. figure 2-2. tpiu block diagram 2.2.4 cortex-m3 system component details the cortex-m3 includes the following system components: systick a 24-bit count-down timer that can be used as a real-time operating system (rtos) tick timer or as a simple counter (see system timer (systick) on page 103). nested vectored interrupt controller (nvic) an embedded interrupt controller that supports low latency interrupt processing (see nested vectored interrupt controller (nvic) on page 104). system control block (scb) 63 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller $ 7 % , q w h u i d f h $ v \ q f k u r q r x v ) , ) 2 $ 3 % , q w h u i d f h 7 u d f h 2 x w v h u l d o l ] h u ' h e x j $ 7 % 6 o d y h 3 r u w $ 3 % 6 o d y h 3 r u w 6 h u l d o : l u h 7 u d f h 3 r u w 6 : 2 the programming model interface to the processor. the scb provides system implementation information and system control, including configuration, control, and reporting of system exceptions( see system control block (scb) on page 106). memory protection unit (mpu) improves system reliability by defining the memory attributes for different memory regions. the mpu provides up to eight different regions and an optional predefined background region (see memory protection unit (mpu) on page 106). 2.3 programming model this section describes the cortex-m3 programming model. in addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. 2.3.1 processor mode and privilege levels for software execution the cortex-m3 has two modes of operation: thread mode used to execute application software. the processor enters thread mode when it comes out of reset. handler mode used to handle exceptions. when the processor has finished exception processing, it returns to thread mode. in addition, the cortex-m3 has two privilege levels: unprivileged in this mode, software has the following restrictions: C limited access to the msr and mrs instructions and no use of the cps instruction C no access to the system timer, nvic, or system control block C possibly restricted access to memory or peripherals privileged in this mode, software can use all the instructions and has access to all resources. in thread mode, the control register (see page 78) controls whether software execution is privileged or unprivileged. in handler mode, software execution is always privileged. only privileged software can write to the control register to change the privilege level for software execution in thread mode. unprivileged software can use the svc instruction to make a supervisor call to transfer control to privileged software. 2.3.2 stacks the processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. when the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. the processor implements march 20, 2011 64 texas instruments-advance information the cortex-m3 processor two stacks: the main stack and the process stack, with independent copies of the stack pointer (see the sp register on page 68). in thread mode, the control register (see page 78) controls whether the processor uses the main stack or the process stack. in handler mode, the processor always uses the main stack. the options for processor operations are shown in table 2-1 on page 65. table 2-1. summary of processor mode, privilege level, and stack use stack used privilege level use processor mode main stack or process stack a privileged or unprivileged a applications thread main stack always privileged exception handlers handler a. see control (page 78). 2.3.3 register map figure 2-3 on page 65 shows the cortex-m3 register set. table 2-2 on page 66 lists the core registers. the core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. figure 2-3. cortex-m3 register set 65 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 3 5 / 5 5 3 & 5 5 5 5 5 5 5 5 5 5 5 5 5 5 / r z u h j l v w h u v + l j k u h j l v w h u v 0 6 3 3 6 3 3 6 5 3 5 , 0 $ 6 . ) $ 8 / 7 0 $ 6 . % $ 6 ( 3 5 , & 2 1 7 5 2 / * h q h u d o s x u s r v h u h j l v w h u v 6 w d f n 3 r l q w h u / l q n 5 h j l v w h u 3 u r j u d p & r x q w h u 3 u r j u d p v w d w x v u h j l v w h u ( [ f h s w l r q p d v n u h j l v w h u v & 2 1 7 5 2 / u h j l v w h u 6 s h f l d o u h j l v w h u v % d q n h g y h u v l r q r i 6 3 table 2-2. processor register map see page description reset type name offset 67 cortex general-purpose register 0 - r/w r0- 67 cortex general-purpose register 1 - r/w r1- 67 cortex general-purpose register 2 - r/w r2- 67 cortex general-purpose register 3 - r/w r3- 67 cortex general-purpose register 4 - r/w r4- 67 cortex general-purpose register 5 - r/w r5- 67 cortex general-purpose register 6 - r/w r6- 67 cortex general-purpose register 7 - r/w r7- 67 cortex general-purpose register 8 - r/w r8- 67 cortex general-purpose register 9 - r/w r9- 67 cortex general-purpose register 10 - r/w r10 - 67 cortex general-purpose register 11 - r/w r11 - 67 cortex general-purpose register 12 - r/w r12 - 68 stack pointer - r/w sp- 69 link register 0xffff.ffff r/w lr- 70 program counter - r/w pc- 71 program status register 0x0100.0000 r/w psr - 75 priority mask register 0x0000.0000 r/w primask - 76 fault mask register 0x0000.0000 r/w faultmask - 77 base priority mask register 0x0000.0000 r/w basepri - 78 control register 0x0000.0000 r/w control - 2.3.4 register descriptions this section lists and describes the cortex-m3 registers, in the order shown in figure 2-3 on page 65. the core registers are not memory mapped and are accessed by register name rather than offset. note: the register type shown in the register descriptions refers to type during program execution in thread mode and handler mode. debug access can differ. march 20, 2011 66 texas instruments-advance information the cortex-m3 processor register 1: cortex general-purpose register 0 (r0) register 2: cortex general-purpose register 1 (r1) register 3: cortex general-purpose register 2 (r2) register 4: cortex general-purpose register 3 (r3) register 5: cortex general-purpose register 4 (r4) register 6: cortex general-purpose register 5 (r5) register 7: cortex general-purpose register 6 (r6) register 8: cortex general-purpose register 7 (r7) register 9: cortex general-purpose register 8 (r8) register 10: cortex general-purpose register 9 (r9) register 11: cortex general-purpose register 10 (r10) register 12: cortex general-purpose register 11 (r11) register 13: cortex general-purpose register 12 (r12) the rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. cortex general-purpose register 0 (r0) type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field register data. - r/w data 31:0 67 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 14: stack pointer (sp) the stack pointer (sp) is register r13. in thread mode, the function of this register changes depending on the asp bit in the control register (control) register. when the asp bit is clear, this register is the main stack pointer (msp) . when the asp bit is set, this register is the process stack pointer (psp) . on reset, the asp bit is clear, and the processor loads the msp with the value from address 0x0000.0000. the msp can only be accessed in privileged mode; the psp can be accessed in either privileged or unprivileged mode. stack pointer (sp) type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sp r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sp r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field this field is the address of the stack pointer. - r/w sp 31:0 march 20, 2011 68 texas instruments-advance information the cortex-m3 processor register 15: link register (lr) the link register (lr ) is register r14, and it stores the return information for subroutines, function calls, and exceptions. lr can be accessed from either privileged or unprivileged mode. exc_return is loaded into lr on exception entry. see table 2-10 on page 95 for the values and description. link register (lr) type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 link r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 link r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field this field is the return address. 0xffff.ffff r/w link 31:0 69 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 16: program counter (pc) the program counter (pc) is register r15, and it contains the current program address. on reset, the processor loads the pc with the value of the reset vector, which is at address 0x0000.0004. bit 0 of the reset vector is loaded into the thumb bit of the epsr at reset and must be 1. the pc register can be accessed in either privileged or unprivileged mode. program counter (pc) type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 pc r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pc r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field this field is the current program address. - r/w pc 31:0 march 20, 2011 70 texas instruments-advance information the cortex-m3 processor register 17: program status register (psr) note: this register is also referred to as xpsr . the program status register (psr) has three functions, and the register bits are assigned to the different functions: application program status register (apsr) , bits 31:27, execution program status register (epsr) , bits 26:24, 15:10 interrupt program status register (ipsr) , bits 6:0 the psr , ipsr , and epsr registers can only be accessed in privileged mode; the apsr register can be accessed in either privileged or unprivileged mode. apsr contains the current state of the condition flags from previous instruction executions. epsr contains the thumb state bit and the execution state bits for the if-then ( it ) instruction or the interruptible-continuable instruction ( ici ) field for an interrupted load multiple or store multiple instruction. attempts to read the epsr directly through application software using the msr instruction always return zero. attempts to write the epsr using the msr instruction in application software are always ignored. fault handlers can examine the epsr value in the stacked psr to determine the operation that faulted (see exception entry and return on page 93). ipsr contains the exception type number of the current interrupt service routine (isr). these registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the msr or mrs instructions. for example, all of the registers can be read using psr with the mrs instruction, or apsr only can be written to using apsr with the msr instruction. page 71 shows the possible register combinations for the psr . see the mrs and msr instruction descriptions in the cortex?-m3 instruction set technical user's manual for more information about how to access the program status registers. table 2-3. psr register combinations combination type register apsr , epsr , and ipsr r/w a , b psr epsr and ipsr ro iepsr apsr and ipsr r/w a iapsr apsr and epsr r/w b eapsr a. the processor ignores writes to the ipsr bits. b. reads of the epsr bits return zero, and the processor ignores writes to these bits. program status register (psr) type r/w, reset 0x0100.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved thumb ici / it q v c z n ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 isrnum reserved ici / it ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 71 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field apsr negative or less flag description value the previous operation result was negative or less than. 1 the previous operation result was positive, zero, greater than, or equal. 0 the value of this bit is only meaningful when accessing psr or apsr . 0 r/w n 31 apsr zero flag description value the previous operation result was zero. 1 the previous operation result was non-zero. 0 the value of this bit is only meaningful when accessing psr or apsr . 0 r/w z 30 apsr carry or borrow flag description value the previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. 1 the previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. 0 the value of this bit is only meaningful when accessing psr or apsr . 0 r/w c 29 apsr overflow flag description value the previous operation resulted in an overflow. 1 the previous operation did not result in an overflow. 0 the value of this bit is only meaningful when accessing psr or apsr . 0 r/w v 28 apsr dsp overflow and saturation flag description value dsp overflow or saturation has occurred. 1 dsp overflow or saturation has not occurred since reset or since the bit was last cleared. 0 the value of this bit is only meaningful when accessing psr or apsr . this bit is cleared by software using an mrs instruction. 0 r/w q 27 march 20, 2011 72 texas instruments-advance information the cortex-m3 processor description reset type name bit/field epsr ici / it status these bits, along with bits 15:10, contain the interruptible-continuable instruction ( ici ) field for an interrupted load multiple or store multiple instruction or the execution state bits of the it instruction. when epsr holds the ici execution state, bits 26:25 are zero. the if-then block contains up to four instructions following a 16-bit it instruction. each instruction in the block is conditional. the conditions for the instructions are either all the same, or some can be the inverse of others. see the cortex?-m3 instruction set technical user's manual for more information. the value of this field is only meaningful when accessing psr or epsr . 0x0 ro ici / it 26:25 epsr thumb state this bit indicates the thumb state and should always be set. the following can clear the thumb bit: the blx, bx and pop{pc} instructions restoration from the stacked xpsr value on an exception return bit 0 of the vector value on an exception entry attempting to execute instructions when this bit is clear results in a fault or lockup. see lockup on page 97 for more information. the value of this bit is only meaningful when accessing psr or epsr . 1 ro thumb 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 23:16 epsr ici / it status these bits, along with bits 26:25, contain the interruptible-continuable instruction ( ici ) field for an interrupted load multiple or store multiple instruction or the execution state bits of the it instruction. when an interrupt occurs during the execution of an ldm, stm, push or pop instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. after servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. when epsr holds the ici execution state, bits 11:10 are zero. the if-then block contains up to four instructions following a 16-bit it instruction. each instruction in the block is conditional. the conditions for the instructions are either all the same, or some can be the inverse of others. see the cortex?-m3 instruction set technical user's manual for more information. the value of this field is only meaningful when accessing psr or epsr . 0x0 ro ici / it 15:10 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 9:7 73 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ipsr isr number this field contains the exception type number of the current interrupt service routine (isr). description value thread mode 0x00 reserved 0x01 nmi 0x02 hard fault 0x03 memory management fault 0x04 bus fault 0x05 usage fault 0x06 reserved 0x07-0x0a svcall 0x0b reserved for debug 0x0c reserved 0x0d pendsv 0x0e systick 0x0f interrupt vector 0 0x10 interrupt vector 1 0x11 ... ... interrupt vector 54 0x46 reserved 0x47-0x7f see exception types on page 88 for more information. the value of this field is only meaningful when accessing psr or ipsr . 0x00 ro isrnum 6:0 march 20, 2011 74 texas instruments-advance information the cortex-m3 processor register 18: priority mask register (primask) the primask register prevents activation of all exceptions with programmable priority. reset, non-maskable interrupt (nmi), and hard fault are the only exceptions with fixed priority. exceptions should be disabled when they might impact the timing of critical tasks. this register is only accessible in privileged mode. the msr and mrs instructions are used to access the primask register, and the cps instruction may be used to change the value of the primask register. see the cortex?-m3 instruction set technical user's manual for more information on these instructions. for more information on exception priority levels, see exception types on page 88. priority mask register (primask) type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 primask reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 priority mask description value prevents the activation of all exceptions with configurable priority. 1 no effect. 0 0 r/w primask 0 75 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 19: fault mask register (faultmask) the faultmask register prevents activation of all exceptions except for the non-maskable interrupt (nmi). exceptions should be disabled when they might impact the timing of critical tasks. this register is only accessible in privileged mode. the msr and mrs instructions are used to access the faultmask register, and the cps instruction may be used to change the value of the faultmask register. see the cortex?-m3 instruction set technical user's manual for more information on these instructions. for more information on exception priority levels, see exception types on page 88. fault mask register (faultmask) type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 faultmask reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 fault mask description value prevents the activation of all exceptions except for nmi. 1 no effect. 0 the processor clears the faultmask bit on exit from any exception handler except the nmi handler. 0 r/w faultmask 0 march 20, 2011 76 texas instruments-advance information the cortex-m3 processor register 20: base priority mask register (basepri) the basepri register defines the minimum priority for exception processing. when basepri is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the basepri value. exceptions should be disabled when they might impact the timing of critical tasks. this register is only accessible in privileged mode. for more information on exception priority levels, see exception types on page 88. base priority mask register (basepri) type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved basepri reserved ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 base priority any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. the primask register can be used to mask all exceptions with programmable priority levels. higher priority exceptions have lower priority levels. description value all exceptions are unmasked. 0x0 all exceptions with priority level 1-7 are masked. 0x1 all exceptions with priority level 2-7 are masked. 0x2 all exceptions with priority level 3-7 are masked. 0x3 all exceptions with priority level 4-7 are masked. 0x4 all exceptions with priority level 5-7 are masked. 0x5 all exceptions with priority level 6-7 are masked. 0x6 all exceptions with priority level 7 are masked. 0x7 0x0 r/w basepri 7:5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 4:0 77 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 21: control register (control) the control register controls the stack used and the privilege level for software execution when the processor is in thread mode. this register is only accessible in privileged mode. handler mode always uses msp , so the processor ignores explicit writes to the asp bit of the control register when in handler mode. the exception entry and return mechanisms automatically update the control register based on the exc_return value (see table 2-10 on page 95). in an os environment, threads running in thread mode should use the process stack and the kernel and exception handlers should use the main stack. by default, thread mode uses msp . to switch the stack pointer used in thread mode to psp , either use the msr instruction to set the asp bit, as detailed in the cortex?-m3 instruction set technical user's manual , or perform an exception return to thread mode with the appropriate exc_return value, as shown in table 2-10 on page 95. note: when changing the stack pointer, software must use an isb instruction immediately after the msr instruction, ensuring that instructions after the isb execute use the new stack pointer. see the cortex?-m3 instruction set technical user's manual . control register (control) type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tmpl asp reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 active stack pointer description value psp is the current stack pointer. 1 msp is the current stack pointer 0 in handler mode, this bit reads as zero and ignores writes. the cortex-m3 updates this bit automatically on exception return. 0 r/w asp 1 thread mode privilege level description value unprivileged software can be executed in thread mode. 1 only privileged software can be executed in thread mode. 0 0 r/w tmpl 0 march 20, 2011 78 texas instruments-advance information the cortex-m3 processor 2.3.5 exceptions and interrupts the cortex-m3 processor supports interrupts and system exceptions. the processor and the nested vectored interrupt controller (nvic) prioritize and handle all exceptions. an exception changes the normal flow of software control. the processor uses handler mode to handle all exceptions except for reset. see exception entry and return on page 93 for more information. the nvic registers control interrupt handling. see nested vectored interrupt controller (nvic) on page 104 for more information. 2.3.6 data types the cortex-m3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. the processor also supports 64-bit data transfer instructions. all instruction and data memory accesses are little endian. see memory regions, types and attributes on page 81 for more information. 2.4 memory model this section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. the processor has a fixed memory map that provides up to 4 gb of addressable memory. the memory map for the lm3s1p51 controller is provided in table 2-4 on page 79. in this manual, register addresses are given as a hexadecimal increment, relative to the modules base address as shown in the memory map. the regions for sram and peripherals include bit-band regions. bit-banding provides atomic operations to bit data (see bit-banding on page 84). the processor reserves regions of the private peripheral bus (ppb) address range for core peripheral registers (see cortex-m3 peripherals on page 103). note: within the memory map, all reserved space returns a bus fault when read or written. table 2-4. memory map for details, see page ... description end start memory 313 on-chip flash 0x0000.ffff 0x0000.0000 - reserved 0x00ff.ffff 0x0001.0000 311 reserved for rom 0x1fff.ffff 0x0100.0000 311 bit-banded on-chip sram 0x2000.5fff 0x2000.0000 - reserved 0x21ff.ffff 0x2000.6000 311 bit-band alias of 0x2000.0000 through 0x200f.ffff 0x220b.ffff 0x2200.0000 - reserved 0x3fff.ffff 0x220c.0000 firm peripherals 509 watchdog timer 0 0x4000.0fff 0x4000.0000 509 watchdog timer 1 0x4000.1fff 0x4000.1000 - reserved 0x4000.3fff 0x4000.2000 417 gpio port a 0x4000.4fff 0x4000.4000 417 gpio port b 0x4000.5fff 0x4000.5000 417 gpio port c 0x4000.6fff 0x4000.6000 79 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 2-4. memory map (continued) for details, see page ... description end start 417 gpio port d 0x4000.7fff 0x4000.7000 686 ssi0 0x4000.8fff 0x4000.8000 686 ssi1 0x4000.9fff 0x4000.9000 - reserved 0x4000.bfff 0x4000.a000 623 uart0 0x4000.cfff 0x4000.c000 623 uart1 0x4000.dfff 0x4000.d000 623 uart2 0x4000.efff 0x4000.e000 - reserved 0x4001.ffff 0x4000.f000 peripherals 730 i 2 c 0 0x4002.0fff 0x4002.0000 730 i 2 c 1 0x4002.1fff 0x4002.1000 - reserved 0x4002.3fff 0x4002.2000 417 gpio port e 0x4002.4fff 0x4002.4000 417 gpio port f 0x4002.5fff 0x4002.5000 417 gpio port g 0x4002.6fff 0x4002.6000 417 gpio port h 0x4002.7fff 0x4002.7000 814 pwm 0x4002.8fff 0x4002.8000 - reserved 0x4002.bfff 0x4002.9000 879 qei0 0x4002.cfff 0x4002.c000 879 qei1 0x4002.dfff 0x4002.d000 - reserved 0x4002.ffff 0x4002.e000 475 timer 0 0x4003.0fff 0x4003.0000 475 timer 1 0x4003.1fff 0x4003.1000 475 timer 2 0x4003.2fff 0x4003.2000 475 timer 3 0x4003.3fff 0x4003.3000 - reserved 0x4003.7fff 0x4003.4000 552 adc0 0x4003.8fff 0x4003.8000 552 adc1 0x4003.9fff 0x4003.9000 - reserved 0x4003.bfff 0x4003.a000 787 analog comparators 0x4003.cfff 0x4003.c000 417 gpio port j 0x4003.dfff 0x4003.d000 - reserved 0x4005.3fff 0x4003.e000 763 i 2 s0 0x4005.4fff 0x4005.4000 - reserved 0x4005.7fff 0x4005.5000 417 gpio port a (ahb aperture) 0x4005.8fff 0x4005.8000 417 gpio port b (ahb aperture) 0x4005.9fff 0x4005.9000 417 gpio port c (ahb aperture) 0x4005.afff 0x4005.a000 417 gpio port d (ahb aperture) 0x4005.bfff 0x4005.b000 417 gpio port e (ahb aperture) 0x4005.cfff 0x4005.c000 417 gpio port f (ahb aperture) 0x4005.dfff 0x4005.d000 417 gpio port g (ahb aperture) 0x4005.efff 0x4005.e000 march 20, 2011 80 texas instruments-advance information the cortex-m3 processor table 2-4. memory map (continued) for details, see page ... description end start 417 gpio port h (ahb aperture) 0x4005.ffff 0x4005.f000 417 gpio port j (ahb aperture) 0x4006.0fff 0x4006.0000 - reserved 0x400f.bfff 0x4006.1000 293 hibernation module 0x400f.cfff 0x400f.c000 318 flash memory control 0x400f.dfff 0x400f.d000 199 system control 0x400f.efff 0x400f.e000 367 dma 0x400f.ffff 0x400f.f000 - reserved 0x41ff.ffff 0x4010.0000 - bit-banded alias of 0x4000.0000 through 0x400f.ffff 0x43ff.ffff 0x4200.0000 - reserved 0xdfff.ffff 0x4400.0000 private peripheral bus 62 instrumentation trace macrocell (itm) 0xe000.0fff 0xe000.0000 62 data watchpoint and trace (dwt) 0xe000.1fff 0xe000.1000 62 flash patch and breakpoint (fpb) 0xe000.2fff 0xe000.2000 - reserved 0xe000.dfff 0xe000.3000 87 cortex-m3 peripherals (systick, nvic, scb, and mpu) 0xe000.efff 0xe000.e000 - reserved 0xe003.ffff 0xe000.f000 63 trace port interface unit (tpiu) 0xe004.0fff 0xe004.0000 - reserved 0xffff.ffff 0xe004.1000 2.4.1 memory regions, types and attributes the memory map and the programming of the mpu split the memory map into regions. each region has a defined memory type, and some regions have additional memory attributes. the memory type and attributes determine the behavior of accesses to the region. the memory types are: normal: the processor can re-order transactions for efficiency and perform speculative reads. device: the processor preserves transaction order relative to other transactions to device or strongly ordered memory. strongly ordered: the processor preserves transaction order relative to all other transactions. the different ordering requirements for device and strongly ordered memory mean that the memory system can buffer a write to device memory but must not buffer a write to strongly ordered memory. an additional memory attribute is execute never (xn), which means the processor prevents instruction accesses. a fault exception is generated only on execution of an instruction executed from an xn region. 2.4.2 memory system ordering of memory accesses for most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. normally, if correct program execution depends on two memory accesses completing in program order, 81 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller software must insert a memory barrier instruction between the memory access instructions (see software ordering of memory accesses on page 82). however, the memory system does guarantee ordering of accesses to device and strongly ordered memory. for two memory access instructions a1 and a2, if both a1 and a2 are accesses to either device or strongly ordered memory, and if a1 occurs before a2 in program order, a1 is always observed before a2. 2.4.3 behavior of memory accesses table 2-5 on page 82 shows the behavior of accesses to each region in the memory map. see memory regions, types and attributes on page 81 for more information on memory types and the xn attribute. stellaris devices may have reserved memory areas within the address ranges shown below (refer to table 2-4 on page 79 for more information). table 2-5. memory access behavior description execute never (xn) memory type memory region address range this executable region is for program code. data can also be stored here. - normal code 0x0000.0000 - 0x1fff.ffff this executable region is for data. code can also be stored here. this region includes bit band and bit band alias areas (see table 2-6 on page 84). - normal sram 0x2000.0000 - 0x3fff.ffff this region includes bit band and bit band alias areas (see table 2-7 on page 84). xn device peripheral 0x4000.0000 - 0x5fff.ffff this executable region is for data. - normal external ram 0x6000.0000 - 0x9fff.ffff this region is for external device memory. xn device external device 0xa000.0000 - 0xdfff.ffff this region includes the nvic, system timer, and system control block. xn strongly ordered private peripheral bus 0xe000.0000- 0xe00f.ffff - - - reserved 0xe010.0000- 0xffff.ffff the code, sram, and external ram regions can hold programs. however, it is recommended that programs always use the code region because the cortex-m3 has separate buses that can perform instruction fetches and data accesses simultaneously. the mpu can override the default memory access behavior described in this section. for more information, see memory protection unit (mpu) on page 106. the cortex-m3 prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. 2.4.4 software ordering of memory accesses the order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: the processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. the processor has multiple bus interfaces. memory or devices in the memory map have different wait states. march 20, 2011 82 texas instruments-advance information the cortex-m3 processor some memory accesses are buffered or speculative. memory system ordering of memory accesses on page 81 describes the cases where the memory system guarantees the order of memory accesses. otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. the cortex-m3 has the following memory barrier instructions: the data memory barrier ( dmb ) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. the data synchronization barrier ( dsb ) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. the instruction synchronization barrier ( isb ) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. memory barrier instructions can be used in the following situations: mpu programming C if the mpu settings are changed and the change must be effective on the very next instruction, use a dsb instruction to ensure the effect of the mpu takes place immediately at the end of context switching. C use an isb instruction to ensure the new mpu setting takes effect immediately after programming the mpu region or regions, if the mpu configuration code was accessed using a branch or call. if the mpu configuration code is entered using exception mechanisms, then an isb instruction is not required. vector table if the program changes an entry in the vector table and then enables the corresponding exception, use a dmb instruction between the operations. the dmb instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. self-modifying code if a program contains self-modifying code, use an isb instruction immediately after the code modification in the program. the isb instruction ensures subsequent instruction execution uses the updated program. memory map switching if the system contains a memory map switching mechanism, use a dsb instruction after switching the memory map in the program. the dsb instruction ensures subsequent instruction execution uses the updated memory map. dynamic exception priority change when an exception priority has to change when the exception is pending or active, use dsb instructions after the change. the change then takes effect on completion of the dsb instruction. memory accesses to strongly ordered memory, such as the system control block, do not require the use of dmb instructions. for more information on the memory barrier instructions, see the cortex?-m3 instruction set technical user's manual . 83 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 2.4.5 bit-banding a bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. the bit-band regions occupy the lowest 1 mb of the sram and peripheral memory regions. accesses to the 32-mb sram alias region map to the 1-mb sram bit-band region, as shown in table 2-6 on page 84. accesses to the 32-mb peripheral alias region map to the 1-mb peripheral bit-band region, as shown in table 2-7 on page 84. for the specific address range of the bit-band regions, see table 2-4 on page 79. note: a word access to the sram or the peripheral bit-band alias region maps to a single bit in the sram or peripheral bit-band region. a word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. this allows bit band accesses to match the access requirements of the underlying peripheral. table 2-6. sram memory bit-banding regions instruction and data accesses memory region address range direct accesses to this memory range behave as sram memory accesses, but this region is also bit addressable through bit-band alias. sram bit-band region 0x2000.0000 - 0x200f.ffff data accesses to this region are remapped to bit band region. a write operation is performed as read-modify-write. instruction accesses are not remapped. sram bit-band alias 0x2200.0000 - 0x23ff.ffff table 2-7. peripheral memory bit-banding regions instruction and data accesses memory region address range direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. peripheral bit-band region 0x4000.0000 - 0x400f.ffff data accesses to this region are remapped to bit band region. a write operation is performed as read-modify-write. instruction accesses are not permitted. peripheral bit-band alias 0x4200.0000 - 0x43ff.ffff the following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset the position of the target bit in the bit-band memory region. bit_word_addr the address of the word in the alias memory region that maps to the targeted bit. bit_band_base the starting address of the alias region. byte_offset the number of the byte in the bit-band region that contains the targeted bit. march 20, 2011 84 texas instruments-advance information the cortex-m3 processor bit_number the bit position, 0-7, of the targeted bit. figure 2-4 on page 85 shows examples of bit-band mapping between the sram bit-band alias region and the sram bit-band region: the alias word at 0x23ff.ffe0 maps to bit 0 of the bit-band byte at 0x200f.ffff: 0x23ff.ffe0 = 0x2200.0000 + (0x000f.ffff*32) + (0*4) the alias word at 0x23ff.fffc maps to bit 7 of the bit-band byte at 0x200f.ffff: 0x23ff.fffc = 0x2200.0000 + (0x000f.ffff*32) + (7*4) the alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) the alias word at 0x2200.001c maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001c = 0x2200.0000+ (0*32) + (7*4) figure 2-4. bit-band mapping 2.4.5.1 directly accessing an alias region writing to a word in the alias region updates a single bit in the bit-band region. bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. 85 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller [ ) ) ) ) ( [ [ ) ) ) ) ( [ ) ) ) ) ( [ ) ) ) ) ( & [ ) ) ) ) ) [ ) ) ) ) ) [ ) ) ) ) ) [ ) ) ) ) ) & [ [ [ [ & [ [ [ & 0 % $ o l d v 5 h j l r q [ [ [ [ [ ) ) ) ) & [ ) ) ) ) ' [ ) ) ) ) ( [ ) ) ) ) ) 0 % 6 5 $ 0 % l w % d q g 5 h j l r q bits 31:1 of the alias word have no effect on the bit-band bit. writing 0x01 has the same effect as writing 0xff. writing 0x00 has the same effect as writing 0x0e. when reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. 2.4.5.2 directly accessing a bit-band region behavior of memory accesses on page 82 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 2.4.6 data storage the processor views memory as a linear collection of bytes numbered in ascending order from zero. for example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. figure 2-5 on page 86 illustrates how data is stored. figure 2-5. data storage 2.4.7 synchronization primitives the cortex-m3 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. a pair of synchronization primitives consists of: a load-exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. a store-exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. if this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write is performed. the pairs of load-exclusive and store-exclusive instructions are: the word instructions ldrex and strex the halfword instructions ldrexh and strexh march 20, 2011 86 texas instruments-advance information the cortex-m3 processor 0 h p r u \ 5 h j l v w h u $ g g u h v v $ $ o v e \ w h p v e \ w h $ $ % % % % % % % % the byte instructions ldrexb and strexb software must use a load-exclusive instruction with the corresponding store-exclusive instruction. to perform a guaranteed read-modify-write of a memory location, software must: 1. use a load-exclusive instruction to read the value of the location. 2. update the value, as required. 3. use a store-exclusive instruction to attempt to write the new value back to the memory location, and test the returned status bit. if the status bit is clear, the read-modify-write completed successfully; if the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. the software must retry the read-modify-write sequence. software can use the synchronization primitives to implement a semaphore as follows: 1. use a load-exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. if the semaphore is free, use a store-exclusive to write the claim value to the semaphore address. 3. if the returned status bit from step 2 indicates that the store-exclusive succeeded, then the software has claimed the semaphore. however, if the store-exclusive failed, another process might have claimed the semaphore after the software performed step 1. the cortex-m3 includes an exclusive access monitor that tags the fact that the processor has executed a load-exclusive instruction. the processor removes its exclusive access tag if: it executes a clrex instruction. it executes a store-exclusive instruction, regardless of whether the write succeeds. an exception occurs, which means the processor can resolve semaphore conflicts between different threads. for more information about the synchronization primitive instructions, see the cortex?-m3 instruction set technical user's manual . 2.5 exception model the arm cortex-m3 processor and the nested vectored interrupt controller (nvic) prioritize and handle all exceptions in handler mode. the processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, enabling efficient interrupt entry. the processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. table 2-8 on page 90 lists all exception types. software can set eight priority levels on seven of these exceptions (system handlers) as well as on 47 interrupts (listed in table 2-9 on page 90). priorities on the system handlers are set with the nvic system handler priority n (sysprin) registers. interrupts are enabled through the nvic interrupt set enable n (enn) register and prioritized with the nvic interrupt priority n (prin) registers. priorities can be grouped by splitting 87 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller priority levels into preemption priorities and subpriorities. all the interrupt registers are described in nested vectored interrupt controller (nvic) on page 104. internally, the highest user-programmable priority (0) is treated as fourth priority, after a reset, non-maskable interrupt (nmi), and a hard fault, in that order. note that 0 is the default priority for all the programmable priorities. important: after a write to clear an interrupt source, it may take several processor cycles for the nvic to see the interrupt source de-assert. thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the nvic sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. this situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). see nested vectored interrupt controller (nvic) on page 104 for more information on exceptions and interrupts. 2.5.1 exception states each exception is in one of the following states: inactive. the exception is not active and not pending. pending. the exception is waiting to be serviced by the processor. an interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. active. an exception that is being serviced by the processor but has not completed. note: an exception handler can interrupt the execution of another exception handler. in this case, both exceptions are in the active state. active and pending. the exception is being serviced by the processor, and there is a pending exception from the same source. 2.5.2 exception types the exception types are: reset. reset is invoked on power up or a warm reset. the exception model treats reset as a special form of exception. when reset is asserted, the operation of the processor stops, potentially at any point in an instruction. when reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. execution restarts as privileged execution in thread mode. nmi. a non-maskable interrupt (nmi) can be signaled using the nmi signal or triggered by software using the interrupt control and state (intctrl) register. this exception has the highest priority other than reset. nmi is permanently enabled and has a fixed priority of -2. nmis cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. hard fault. a hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. march 20, 2011 88 texas instruments-advance information the cortex-m3 processor memory management fault. a memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. the mpu or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. this fault is used to abort instruction accesses to execute never (xn) memory regions, even if the mpu is disabled. bus fault. a bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. this fault can be enabled or disabled. usage fault. a usage fault is an exception that occurs because of a fault related to instruction execution, such as: C an undefined instruction C an illegal unaligned access C invalid state on instruction execution C an error on exception return an unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. svcall. a supervisor call (svc) is an exception that is triggered by the svc instruction. in an os environment, applications can use svc instructions to access os kernel functions and device drivers. debug monitor. this exception is caused by the debug monitor (when not halting). this exception is only active when enabled. this exception does not activate if it is a lower priority than the current activation. pendsv. pendsv is a pendable, interrupt-driven request for system-level service. in an os environment, use pendsv for context switching when no other exception is active. pendsv is triggered using the interrupt control and state (intctrl) register. systick. a systick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. software can also generate a systick exception using the interrupt control and state (intctrl) register. in an os environment, the processor can use this exception as system tick. interrupt (irq). an interrupt, or irq, is an exception signaled by a peripheral or generated by a software request and fed through the nvic (prioritized). all interrupts are asynchronous to instruction execution. in the system, peripherals use interrupts to communicate with the processor. table 2-9 on page 90 lists the interrupts on the lm3s1p51 controller. for an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. privileged software can disable the exceptions that table 2-8 on page 90 shows as having configurable priority (see the syshndctrl register on page 147 and the dis0 register on page 120). for more information about hard faults, memory management faults, bus faults, and usage faults, see fault handling on page 95. 89 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 2-8. exception types activation vector address or offset b priority a vector number exception type stack top is loaded from the first entry of the vector table on reset. 0x0000.0000 - 0 - asynchronous 0x0000.0004 -3 (highest) 1 reset asynchronous 0x0000.0008 -2 2 non-maskable interrupt (nmi) - 0x0000.000c -1 3 hard fault synchronous 0x0000.0010 programmable c 4 memory management synchronous when precise and asynchronous when imprecise 0x0000.0014 programmable c 5 bus fault synchronous 0x0000.0018 programmable c 6 usage fault reserved - - 7-10 - synchronous 0x0000.002c programmable c 11 svcall synchronous 0x0000.0030 programmable c 12 debug monitor reserved - - 13 - asynchronous 0x0000.0038 programmable c 14 pendsv asynchronous 0x0000.003c programmable c 15 systick asynchronous 0x0000.0040 and above programmable d 16 and above interrupts a. 0 is the default priority for all the programmable priorities. b. see vector table on page 92. c. see syspri1 on page 144. d. see prin registers on page 128. table 2-9. interrupts description vector address or offset interrupt number (bit in interrupt registers) vector number processor exceptions 0x0000.0000 - 0x0000.003c - 0-15 gpio port a 0x0000.0040 0 16 gpio port b 0x0000.0044 1 17 gpio port c 0x0000.0048 2 18 gpio port d 0x0000.004c 3 19 gpio port e 0x0000.0050 4 20 uart0 0x0000.0054 5 21 uart1 0x0000.0058 6 22 ssi0 0x0000.005c 7 23 i 2 c0 0x0000.0060 8 24 pwm fault 0x0000.0064 9 25 pwm generator 0 0x0000.0068 10 26 pwm generator 1 0x0000.006c 11 27 pwm generator 2 0x0000.0070 12 28 qei0 0x0000.0074 13 29 adc0 sequence 0 0x0000.0078 14 30 adc0 sequence 1 0x0000.007c 15 31 march 20, 2011 90 texas instruments-advance information the cortex-m3 processor table 2-9. interrupts (continued) description vector address or offset interrupt number (bit in interrupt registers) vector number adc0 sequence 2 0x0000.0080 16 32 adc0 sequence 3 0x0000.0084 17 33 watchdog timers 0 and 1 0x0000.0088 18 34 timer 0a 0x0000.008c 19 35 timer 0b 0x0000.0090 20 36 timer 1a 0x0000.0094 21 37 timer 1b 0x0000.0098 22 38 timer 2a 0x0000.009c 23 39 timer 2b 0x0000.00a0 24 40 analog comparator 0 0x0000.00a4 25 41 analog comparator 1 0x0000.00a8 26 42 reserved - 27 43 system control 0x0000.00b0 28 44 flash memory control 0x0000.00b4 29 45 gpio port f 0x0000.00b8 30 46 gpio port g 0x0000.00bc 31 47 gpio port h 0x0000.00c0 32 48 uart2 0x0000.00c4 33 49 ssi1 0x0000.00c8 34 50 timer 3a 0x0000.00cc 35 51 timer 3b 0x0000.00d0 36 52 i 2 c1 0x0000.00d4 37 53 qei1 0x0000.00d8 38 54 reserved - 39-42 55-58 hibernation module 0x0000.00ec 43 59 reserved - 44-45 60-61 dma software 0x0000.00f8 46 62 dma error 0x0000.00fc 47 63 adc1 sequence 0 0x0000.0100 48 64 adc1 sequence 1 0x0000.0104 49 65 adc1 sequence 2 0x0000.0108 50 66 adc1 sequence 3 0x0000.010c 51 67 i 2 s0 0x0000.0110 52 68 reserved - 53 69 gpio port j 0x0000.0118 54 70 2.5.3 exception handlers the processor handles exceptions using: interrupt service routines (isrs). interrupts (irqx) are the exceptions handled by isrs. 91 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller fault handlers. hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. system handlers. nmi, pendsv, svcall, systick, and the fault exceptions are all system exceptions that are handled by system handlers. 2.5.4 vector table the vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. the vector table is constructed using the vector address or offset shown in table 2-8 on page 90. figure 2-6 on page 92 shows the order of the exception vectors in the vector table. the least-significant bit of each vector must be 1, indicating that the exception handler is thumb code figure 2-6. vector table on system reset, the vector table is fixed at address 0x0000.0000. privileged software can write to the vector table offset (vtable) register to relocate the vector table start address to a different memory location, in the range 0x0000.0200 to 0x3fff.fe00 (see vector table on page 92). note that when configuring the vtable register, the offset must be aligned on a 512-byte boundary. march 20, 2011 92 texas instruments-advance information the cortex-m3 processor , q l w l d o 6 3 y d o x h 5 h v h w + d u g i d x o w 1 0 , 0 h p r u \ p d q d j h p h q w i d x o w 8 v d j h i d x o w % x v i d x o w [ [ [ [ & [ [ [ 5 h v h u y h g 6 9 & d o o 3 h q g 6 9 5 h v h u y h g i r u ' h e x j 6 \ v w l f n , 5 4 5 h v h u y h g [ & [ [ & [ 2 i i v h w ( [ f h s w l r q q x p e h u 9 h f w r u , 5 4 , 5 4 [ , 5 4 [ [ & [ , 5 4 q x p e h u 2.5.5 exception priorities as table 2-8 on page 90 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except reset, hard fault, and nmi. if software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. for information about configuring exception priorities, see page 144 and page 128. note: configurable priority values for the stellaris implementation are in the range 0-7. this means that the reset, hard fault, and nmi exceptions, with fixed negative priority values, always have higher priority than any other exception. for example, assigning a higher priority value to irq[0] and a lower priority value to irq[1] means that irq[1] has higher priority than irq[0]. if both irq[1] and irq[0] are asserted, irq[1] is processed before irq[0]. if multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. for example, if both irq[0] and irq[1] are pending and have the same priority, then irq[0] is processed before irq[1]. when the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. if an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. however, the status of the new interrupt changes to pending. 2.5.6 interrupt priority grouping to increase priority control in systems with interrupts, the nvic supports priority grouping. this grouping divides each interrupt priority register entry into two fields: an upper field that defines the group priority a lower field that defines a subpriority within the group only the group priority determines preemption of interrupt exceptions. when the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. if multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. if multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest irq number is processed first. for information about splitting the interrupt priority fields into group priority and subpriority, see page 138. 2.5.7 exception entry and return descriptions of exception handling use the following terms: preemption. when the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. see interrupt priority grouping on page 93 for more information about preemption by an interrupt. when one exception preempts another, the exceptions are called nested exceptions. see exception entry on page 94 more information. return. return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not 93 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller handling a late-arriving exception. the processor pops the stack and restores the processor state to the state it had before the interrupt occurred. see exception return on page 95 for more information. tail-chaining. this mechanism speeds up exception servicing. on completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. late-arriving. this mechanism speeds up preemption. if a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. state saving is not affected by late arrival because the state saved is the same for both exceptions. therefore, the state saving continues uninterrupted. the processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. on return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 exception entry exception entry occurs when there is a pending exception with sufficient priority and either the processor is in thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. when one exception preempts another, the exceptions are nested. sufficient priority means the exception has more priority than any limits set by the mask registers (see primask on page 75, faultmask on page 76, and basepri on page 77). an exception with less priority than this is pending but is not handled by the processor. when the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. this operation is referred to as stacking and the structure of eight data words is referred to as stack frame . figure 2-7. exception stack frame immediately after stacking, the stack pointer indicates the lowest address in the stack frame. the stack frame includes the return address, which is the address of the next instruction in the interrupted program. this value is restored to the pc at exception return so that the interrupted program resumes. in parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. when stacking is complete, the processor starts executing the exception handler. at the same time, the processor writes an exc_return value to the lr , march 20, 2011 94 texas instruments-advance information the cortex-m3 processor 3 u h , 5 4 w r s r i v w d f n [ 3 6 5 3 & / 5 5 5 5 5 5 ^ d o l j q h u ` , 5 4 w r s r i v w d f n indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. if no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. if another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. 2.5.7.2 exception return exception return occurs when the processor is in handler mode and executes one of the following instructions to load the exc_return value into the pc : an ldm or pop instruction that loads the pc a bx instruction using any register an ldr instruction with the pc as the destination exc_return is the value loaded into the lr on exception entry. the exception mechanism relies on this value to detect when the processor has completed an exception handler. the lowest four bits of this value provide information on the return stack and processor mode. table 2-10 on page 95 shows the exc_return values with a description of the exception return behavior. exc_return bits 31:4 are all set. when this value is loaded into the pc , it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. table 2-10. exception return behavior description exc_return[31:0] reserved 0xffff.fff0 return to handler mode. exception return uses state from msp . execution uses msp after return. 0xffff.fff1 reserved 0xffff.fff2 - 0xffff.fff8 return to thread mode. exception return uses state from msp . execution uses msp after return. 0xffff.fff9 reserved 0xffff.fffa - 0xffff.fffc return to thread mode. exception return uses state from psp . execution uses psp after return. 0xffff.fffd reserved 0xffff.fffe - 0xffff.ffff 2.6 fault handling faults are a subset of the exceptions (see exception model on page 87). the following conditions generate a fault: a bus error on an instruction fetch or vector table load or a data access. 95 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller an internally detected error such as an undefined instruction or an attempt to change state with a bx instruction. attempting to execute an instruction from a memory region marked as non-executable (xn). an mpu fault because of a privilege violation or an attempt to access an unmanaged region. 2.6.1 fault types table 2-11 on page 96 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. see page 151 for more information about the fault status registers. table 2-11. faults bit name fault status register handler fault vect hard fault status (hfaultstat) hard fault bus error on a vector read forced hard fault status (hfaultstat) hard fault fault escalated to a hard fault ierr a memory management fault status (mfaultstat) memory management fault mpu or default memory mismatch on instruction access derr memory management fault status (mfaultstat) memory management fault mpu or default memory mismatch on data access mstke memory management fault status (mfaultstat) memory management fault mpu or default memory mismatch on exception stacking mustke memory management fault status (mfaultstat) memory management fault mpu or default memory mismatch on exception unstacking bstke bus fault status (bfaultstat) bus fault bus error during exception stacking bustke bus fault status (bfaultstat) bus fault bus error during exception unstacking ibus bus fault status (bfaultstat) bus fault bus error during instruction prefetch precise bus fault status (bfaultstat) bus fault precise data bus error impre bus fault status (bfaultstat) bus fault imprecise data bus error nocp usage fault status (ufaultstat) usage fault attempt to access a coprocessor undef usage fault status (ufaultstat) usage fault undefined instruction invstat usage fault status (ufaultstat) usage fault attempt to enter an invalid instruction set state b invpc usage fault status (ufaultstat) usage fault invalid exc_return value unalign usage fault status (ufaultstat) usage fault illegal unaligned load or store div0 usage fault status (ufaultstat) usage fault divide by 0 a. occurs on an access to an xn region even if the mpu is disabled. b. attempting to use an instruction set other than the thumb instruction set, or returning to a non load-store-multiple instruction with ici continuation. 2.6.2 fault escalation and hard faults all fault exceptions except for hard fault have configurable exception priority (see syspri1 on page 144). software can disable execution of the handlers for these faults (see syshndctrl on page 147). usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in exception model on page 87. march 20, 2011 96 texas instruments-advance information the cortex-m3 processor in some situations, a fault with configurable priority is treated as a hard fault. this process is called priority escalation, and the fault is described as escalated to hard fault . escalation to hard fault occurs when: a fault handler causes the same kind of fault as the one it is servicing. this escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. a fault handler causes a fault with the same or lower priority as the fault it is servicing. this situation happens because the handler for the new fault cannot preempt the currently executing fault handler. an exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. a fault occurs and the handler for that fault is not enabled. if a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. the fault handler operates but the stack contents are corrupted. note: only reset and nmi can preempt the fixed priority hard fault. a hard fault can preempt any exception other than reset, nmi, or another hard fault. 2.6.3 fault status registers and fault address registers the fault status registers indicate the cause of a fault. for bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in table 2-12 on page 97. table 2-12. fault status and fault address registers register description address register name status register name handler page 157 - hard fault status (hfaultstat) hard fault page 151 page 158 memory management fault address (mmaddr) memory management fault status (mfaultstat) memory management fault page 151 page 159 bus fault address (faultaddr) bus fault status (bfaultstat) bus fault page 151 - usage fault status (ufaultstat) usage fault 2.6.4 lockup the processor enters a lockup state if a hard fault occurs when executing the nmi or hard fault handlers. when the processor is in the lockup state, it does not execute any instructions. the processor remains in lockup state until it is reset or an nmi occurs. note: if the lockup state occurs from the nmi handler, a subsequent nmi does not cause the processor to leave the lockup state. 2.7 power management the cortex-m3 processor sleep modes reduce power consumption: sleep mode stops the processor clock. 97 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller deep-sleep mode stops the system clock and switches off the pll and flash memory. the sleepdeep bit of the system control (sysctrl) register selects which sleep mode is used (see page 140). for more information about the behavior of the sleep modes, see system control on page 195. this section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to sleep mode and deep-sleep mode. 2.7.1 entering sleep modes this section describes the mechanisms software can use to put the processor into one of the sleep modes. the system can generate spurious wake-up events, for example a debug operation wakes up the processor. therefore, software must be able to put the processor back into sleep mode after such an event. a program might have an idle loop to put the processor back to sleep mode. 2.7.1.1 wait for interrupt the wait for interrupt instruction, wfi , causes immediate entry to sleep mode unless the wake-up condition is true (see wake up from wfi or sleep-on-exit on page 98). when the processor executes a wfi instruction, it stops executing instructions and enters sleep mode. see the cortex?-m3 instruction set technical user's manual for more information. 2.7.1.2 wait for event the wait for event instruction, wfe , causes entry to sleep mode conditional on the value of a one-bit event register. when the processor executes a wfe instruction, it checks the event register. if the register is 0, the processor stops executing instructions and enters sleep mode. if the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. if the event register is 1, the processor must not enter sleep mode on execution of a wfe instruction. typically, this situation occurs if an sev instruction has been executed. software cannot access this register directly. see the cortex?-m3 instruction set technical user's manual for more information. 2.7.1.3 sleep-on-exit if the sleepexit bit of the sysctrl register is set, when the processor completes the execution of an exception handler, it returns to thread mode and immediately enters sleep mode. this mechanism can be used in applications that only require the processor to run when an exception occurs. 2.7.2 wake up from sleep mode the conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 2.7.2.1 wake up from wfi or sleep-on-exit normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. entry to the interrupt handler can be delayed by setting the primask bit and clearing the faultmask bit. if an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does march 20, 2011 98 texas instruments-advance information the cortex-m3 processor not execute the interrupt handler until the processor clears primask . for more information about primask and faultmask , see page 75 and page 76. 2.7.2.2 wake up from wfe the processor wakes up if it detects an exception with sufficient priority to cause exception entry. in addition, if the sevonpend bit in the sysctrl register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. for more information about sysctrl , see page 140. 2.8 instruction set summary the processor implements a version of the thumb instruction set. table 2-13 on page 99 lists the supported instructions. note: in table 2-13 on page 99: angle brackets, <>, enclose alternative forms of the operand braces, {}, enclose optional operands the operands column is not exhaustive op2 is a flexible second operand that can be either a register or a constant most instructions can use an optional condition code suffix for more information on the instructions and operands, see the instruction descriptions in the cortex?-m3 instruction set technical user's manual . table 2-13. cortex-m3 instruction summary flags brief description operands mnemonic n,z,c,v add with carry {rd,} rn, op2 adc, adcs n,z,c,v add {rd,} rn, op2 add, adds n,z,c,v add {rd,} rn , #imm12 add, addw - load pc-relative address rd, label adr n,z,c logical and {rd,} rn, op2 and, ands n,z,c arithmetic shift right rd, rm, table 2-13. cortex-m3 instruction summary (continued) flags brief description operands mnemonic - change processor state, disable interrupts i cpsid - change processor state, enable interrupts i cpsie - data memory barrier - dmb - data synchronization barrier - dsb n,z,c exclusive or {rd,} rn, op2 eor, eors - instruction synchronization barrier - isb - if-then condition block - it - load multiple registers, increment after rn{!}, reglist ldm - load multiple registers, decrement before rn{!}, reglist ldmdb, ldmea - load multiple registers, increment after rn{!}, reglist ldmfd, ldmia - load register with word rt, [rn, #offset] ldr - load register with byte rt, [rn, #offset] ldrb, ldrbt - load register with two bytes rt, rt2, [rn, #offset] ldrd - load register exclusive rt, [rn, #offset] ldrex - load register exclusive with byte rt, [rn] ldrexb - load register exclusive with halfword rt, [rn] ldrexh - load register with halfword rt, [rn, #offset] ldrh, ldrht - load register with signed byte rt, [rn, #offset] ldrsb, ldrsbt - load register with signed halfword rt, [rn, #offset] ldrsh, ldrsht - load register with word rt, [rn, #offset] ldrt n,z,c logical shift left rd, rm, table 2-13. cortex-m3 instruction summary (continued) flags brief description operands mnemonic - reverse byte order in each halfword rd, rn rev16 - reverse byte order in bottom halfword and sign extend rd, rn revsh n,z,c rotate right rd, rm, table 2-13. cortex-m3 instruction summary (continued) flags brief description operands mnemonic q unsigned saturate rd, #n, rm {,shift #s} usat - zero extend a byte {rd,} rm, {,ror #n} uxtb - zero extend a halfword {rd,} rm, {,ror #n} uxth q unsigned saturate rd, #n, rm {,shift #s} usat - zero extend a byte {rd,} rm {,ror #n} uxtb - zero extend a halfword {rd,} rm {,ror #n} uxth - wait for event - wfe - wait for interrupt - wfi march 20, 2011 102 texas instruments-advance information the cortex-m3 processor 3 cortex-m3 peripherals this chapter provides information on the stellaris ? implementation of the cortex-m3 processor peripherals, including: systick (see page 103) provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. nested vectored interrupt controller (nvic) (see page 104) C facilitates low-latency exception and interrupt handling C controls power management C implements system control registers system control block (scb) (see page 106) provides system implementation information and system control, including configuration, control, and reporting of system exceptions. memory protection unit (mpu) (see page 106) supports the standard armv7 protected memory system architecture (pmsa) model. the mpu provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. table 3-1 on page 103 shows the address map of the private peripheral bus (ppb). some peripheral register regions are split into two address regions, as indicated by two addresses listed. table 3-1. core peripheral register regions description (see page ...) core peripheral address 103 system timer 0xe000.e010-0xe000.e01f 104 nested vectored interrupt controller 0xe000.e100-0xe000.e4ef 0xe000.ef00-0xe000.ef03 106 system control block 0xe000.e008-0xe000.e00f 0xe000.ed00-0xe000.ed3f 106 memory protection unit 0xe000.ed90-0xe000.edb8 3.1 functional description this chapter provides information on the stellaris implementation of the cortex-m3 processor peripherals: systick, nvic, scb and mpu. 3.1.1 system timer (systick) cortex-m3 includes an integrated system timer, systick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. the counter can be used in several different ways, for example as: an rtos tick timer that fires at a programmable rate (for example, 100 hz) and invokes a systick routine. a high-speed alarm timer using the system clock. 103 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller a variable rate alarm or signal timerthe duration is range-dependent on the reference clock used and the dynamic range of the counter. a simple counter used to measure time to completion and time used. an internal clock source control based on missing/meeting durations. the count bit in the stctrl control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. the timer consists of three registers: systick control and status (stctrl) : a control and status counter to configure its clock, enable the counter, enable the systick interrupt, and determine counter status. systick reload value (streload) : the reload value for the counter, used to provide the counter's wrap value. systick current value (stcurrent) : the current value of the counter. when enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the streload register on the next clock edge, then decrements on subsequent clocks. clearing the streload register disables the counter on the next wrap. when the counter reaches zero, the count status bit is set. the count bit clears on reads. writing to the stcurrent register clears the register and the count status bit. the write does not trigger the systick exception logic. on a read, the current value is the value of the register at the time the register is accessed. the systick counter runs on the system clock. if this clock signal is stopped for low power mode, the systick counter stops. ensure software uses aligned word accesses to access the systick registers. note: when the processor is halted for debugging, the counter does not decrement. 3.1.2 nested vectored interrupt controller (nvic) this section describes the nested vectored interrupt controller (nvic) and the registers it uses. the nvic supports: 47 interrupts. a programmable priority level of 0-7 for each interrupt. a higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. low-latency exception and interrupt handling. level and pulse detection of interrupt signals. dynamic reprioritization of interrupts. grouping of priority values into group priority and subpriority fields. interrupt tail-chaining. an external non-maskable interrupt (nmi). march 20, 2011 104 texas instruments-advance information cortex-m3 peripherals the processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.1.2.1 level-sensitive and pulse interrupts the processor supports both level-sensitive and pulse interrupts. pulse interrupts are also described as edge-triggered interrupts. a level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. typically this happens because the isr accesses the peripheral, causing it to clear the interrupt request. a pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. to ensure the nvic detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the nvic detects the pulse and latches the interrupt. when the processor enters the isr, it automatically removes the pending state from the interrupt (see hardware and software control of interrupts on page 105 for more information). for a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the isr, the interrupt becomes pending again, and the processor must execute its isr again. as a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 3.1.2.2 hardware and software control of interrupts the cortex-m3 latches all interrupts. a peripheral interrupt becomes pending for one of the following reasons: the nvic detects that the interrupt signal is high and the interrupt is not active. the nvic detects a rising edge on the interrupt signal. software writes to the corresponding interrupt set-pending register bit, or to the software trigger interrupt (swtrig) register to make a software-generated interrupt pending. see the int bit in the pend0 register on page 122 or swtrig on page 130. a pending interrupt remains pending until one of the following: the processor enters the isr for the interrupt, changing the state of the interrupt from pending to active. then: C for a level-sensitive interrupt, when the processor returns from the isr, the nvic samples the interrupt signal. if the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the isr. otherwise, the state of the interrupt changes to inactive. C for a pulse interrupt, the nvic continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. in this case, when the processor returns from the isr the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the isr. if the interrupt signal is not pulsed while the processor is in the isr, when the processor returns from the isr the state of the interrupt changes to inactive. software writes to the corresponding interrupt clear-pending register bit C for a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. otherwise, the state of the interrupt changes to inactive. 105 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller C for a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.1.3 system control block (scb) the system control block (scb) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.1.4 memory protection unit (mpu) this section describes the memory protection unit (mpu). the mpu divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. the mpu supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. the memory attributes affect the behavior of memory accesses to the region. the cortex-m3 mpu defines eight separate memory regions, 0-7, and a background region. when memory regions overlap, a memory access is affected by the attributes of the region with the highest number. for example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. the background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. the cortex-m3 mpu memory map is unified, meaning that instruction accesses and data accesses have the same region settings. if a program accesses a memory location that is prohibited by the mpu, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an os environment. in an os environment, the kernel can update the mpu region setting dynamically based on the process to be executed. typically, an embedded os uses the mpu for memory protection. configuration of mpu regions is based on memory types (see memory regions, types and attributes on page 81 for more information). table 3-2 on page 106 shows the possible mpu region attributes. see the section called mpu configuration for a stellaris microcontroller on page 110 for guidelines for programming a microcontroller implementation. table 3-2. memory attributes summary description memory type all accesses to strongly ordered memory occur in program order. strongly ordered memory-mapped peripherals device normal memory normal to avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. ensure software uses aligned accesses of the correct size to access mpu registers: except for the mpu region attribute and size (mpuattr) register, all mpu registers must be accessed with aligned word accesses. the mpuattr register can be accessed with byte or aligned halfword or word accesses. march 20, 2011 106 texas instruments-advance information cortex-m3 peripherals the processor does not support unaligned accesses to mpu registers. when setting up the mpu, and if the mpu has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new mpu setup. 3.1.4.1 updating an mpu region to update the attributes for an mpu region, the mpu region number (mpunumber) , mpu region base address (mpubase) and mpuattr registers must be updated. each register can be programmed separately or with a multiple-word write to program all of these registers. you can use the mpubasex and mpuattrx aliases to program up to four regions simultaneously using an stm instruction. updating an mpu region using separate words this example simple code configures one region: ; r1 = region number ; r2 = size/enable ; r3 = attributes ; r4 = address ldr r0,=mpunumber ; 0xe000ed98, mpu region number register str r1, [r0, #0x0] ; region number str r4, [r0, #0x4] ; region base address strh r2, [r0, #0x8] ; region size and enable strh r3, [r0, #0xa] ; region attribute disable a region before writing new region settings to the mpu if you have previously enabled the region being changed. for example: ; r1 = region number ; r2 = size/enable ; r3 = attributes ; r4 = address ldr r0,=mpunumber ; 0xe000ed98, mpu region number register str r1, [r0, #0x0] ; region number bic r2, r2, #1 ; disable strh r2, [r0, #0x8] ; region size and enable str r4, [r0, #0x4] ; region base address strh r3, [r0, #0xa] ; region attribute orr r2, #1 ; enable strh r2, [r0, #0x8] ; region size and enable software must use memory barrier instructions: before mpu setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in mpu settings. after mpu setup, if it includes memory transfers that must use the new mpu settings. however, memory barrier instructions are not required if the mpu setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. software does not need any memory barrier instructions during mpu setup, because it accesses the mpu through the private peripheral bus (ppb), which is a strongly ordered memory region. 107 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller for example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a dsb instruction and an isb instruction should be used. a dsb is required after changing mpu settings, such as at the end of context switch. an isb is required if the code that programs the mpu region or regions is entered using a branch or call. if the programming sequence is entered using a return from exception, or by taking an exception, then an isb is not required. updating an mpu region using multi-word writes the mpu can be programmed directly using multi-word writes, depending how the information is divided. consider the following reprogramming: ; r1 = region number ; r2 = address ; r3 = size, attributes in one ldr r0, =mpunumber ; 0xe000ed98, mpu region number register str r1, [r0, #0x0] ; region number str r2, [r0, #0x4] ; region base address str r3, [r0, #0x8] ; region attribute, size and enable an stm instruction can be used to optimize this: ; r1 = region number ; r2 = address ; r3 = size, attributes in one ldr r0, =mpunumber ; 0xe000ed98, mpu region number register stm r0, {r1-r3} ; region number, address, attribute, size and enable this operation can be done in two words for pre-packed information, meaning that the mpu region base address (mpubase) register (see page 164) contains the required region number and has the valid bit set. this method can be used when the data is statically packed, for example in a boot loader: ; r1 = address and region number in one ; r2 = size and attributes in one ldr r0, =mpubase ; 0xe000ed9c, mpu region base register str r1, [r0, #0x0] ; region base address and region number combined ; with valid (bit 4) set str r2, [r0, #0x4] ; region attribute, size and enable an stm instruction can be used to optimize this: ; r1 = address and region number in one ; r2 = size and attributes in one ldr r0,=mpubase ; 0xe000ed9c, mpu region base register stm r0, {r1-r2} ; region base address, region number and valid bit, ; and region attribute, size and enable subregions regions of 256 bytes or more are divided into eight equal-sized subregions. set the corresponding bit in the srd field of the mpu region attribute and size (mpuattr) register (see page 166) to disable a subregion. the least-significant bit of the srd field controls the first subregion, and the most-significant bit controls the last subregion. disabling a subregion means another region march 20, 2011 108 texas instruments-advance information cortex-m3 peripherals overlapping the disabled range matches instead. if no other enabled region overlaps the disabled subregion, the mpu issues a fault. regions of 32, 64, and 128 bytes do not support subregions. with regions of these sizes, the srd field must be configured to 0x00 , otherwise the mpu behavior is unpredictable. example of srd use two regions with the same base address overlap. region one is 128 kb, and region two is 512 kb. to ensure the attributes from region one apply to the first 128 kb region, configure the srd field for region two to 0x03 to disable the first two subregions, as figure 3-1 on page 109 shows. figure 3-1. srd use example 3.1.4.2 mpu access permission attributes the access permission bits, tex, s, c, b, ap , and xn of the mpuattr register, control access to the corresponding memory region. if an access is made to an area of memory without the required permissions, then the mpu generates a permission fault. table 3-3 on page 109 shows the encodings for the tex, c, b , and s access permission bits. all encodings are shown for completeness, however the current implementation of the cortex-m3 does not support the concept of cacheability or shareability. refer to the section called mpu configuration for a stellaris microcontroller on page 110 for information on programming the mpu for stellaris implementations. table 3-3. tex, s, c, and b bit field encoding other attributes shareability memory type bc s tex - shareable strongly ordered 00 x a 000b - shareable device 10 x a 000 outer and inner write-through. no write allocate. not shareable normal 01 0 000 shareable normal 01 1 000 not shareable normal 11 0 000 shareable normal 11 1 000 outer and inner noncacheable. not shareable normal 00 0 001 shareable normal 00 1 001 - - reserved encoding 10 x a 001 - - reserved encoding 01 x a 001 outer and inner write-back. write and read allocate. not shareable normal 11 0 001 shareable normal 11 1 001 109 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 5 h j l r q ' l v d e o h g v x e u h j l r q ' l v d e o h g v x e u h j l r q 5 h j l r q z l w k v x e u h j l r q v % d v h d g g u h v v r i e r w k u h j l r q v 2 i i v h w i u r p e d v h d g g u h v v . % . % . % . % . % . % . % . % table 3-3. tex, s, c, and b bit field encoding (continued) other attributes shareability memory type bc s tex nonshared device. not shareable device 00 x a 010 - - reserved encoding 10 x a 010 - - reserved encoding x a 1 x a 010 cached memory (bb = outer policy, aa = inner policy). see table 3-4 for the encoding of the aa and bb bits. not shareable normal aa 0 1bb shareable normal aa 1 1bb a. the mpu ignores the value of this bit. table 3-4 on page 110 shows the cache policy for memory attribute encodings with a tex value in the range of 0x4-0x7. table 3-4. cache policy for memory attribute encoding corresponding cache policy encoding, aa or bb non-cacheable 00 write back, write and read allocate 01 write through, no write allocate 10 write back, no write allocate 11 table 3-5 on page 110 shows the ap encodings in the mpuattr register that define the access permissions for privileged and unprivileged software. table 3-5. ap bit field encoding description unprivileged permissions privileged permissions ap bit field all accesses generate a permission fault. no access no access 000 access from privileged software only. no access r/w 001 writes by unprivileged software generate a permission fault. ro r/w 010 full access. r/w r/w 011 reserved. unpredictable unpredictable 100 reads by privileged software only. no access ro 101 read-only, by privileged or unprivileged software. ro ro 110 read-only, by privileged or unprivileged software. ro ro 111 mpu configuration for a stellaris microcontroller stellaris microcontrollers have only a single processor and no caches. as a result, the mpu should be programmed as shown in table 3-6 on page 110. table 3-6. memory region attributes for stellaris microcontrollers memory type and attributes bcs tex memory region normal memory, non-shareable, write-through 010 000b flash memory normal memory, shareable, write-through 011 000b internal sram march 20, 2011 110 texas instruments-advance information cortex-m3 peripherals table 3-6. memory region attributes for stellaris microcontrollers (continued) memory type and attributes bcs tex memory region normal memory, shareable, write-back, write-allocate 111 000b external sram device memory, shareable 101 000b peripherals in current stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. however, using these settings for the mpu regions can make the application code more portable. the values given are for typical situations. 3.1.4.3 mpu mismatch when an access violates the mpu permissions, the processor generates a memory management fault (see exceptions and interrupts on page 79 for more information). the mfaultstat register indicates the cause of the fault. see page 151 for more information. 3.2 register map table 3-7 on page 111 lists the cortex-m3 peripheral systick, nvic, scb, and mpu registers. the offset listed is a hexadecimal increment to the register's address, relative to the core peripherals base address of 0xe000.e000. note: register spaces that are not used are reserved for future or internal use. software should not modify any reserved memory address. table 3-7. peripherals register map see page description reset type name offset system timer (systick) registers 114 systick control and status register 0x0000.0004 r/w stctrl 0x010 116 systick reload value register 0x0000.0000 r/w streload 0x014 117 systick current value register 0x0000.0000 r/wc stcurrent 0x018 nested vectored interrupt controller (nvic) registers 118 interrupt 0-31 set enable 0x0000.0000 r/w en0 0x100 119 interrupt 32-54 set enable 0x0000.0000 r/w en1 0x104 120 interrupt 0-31 clear enable 0x0000.0000 r/w dis0 0x180 121 interrupt 32-54 clear enable 0x0000.0000 r/w dis1 0x184 122 interrupt 0-31 set pending 0x0000.0000 r/w pend0 0x200 123 interrupt 32-54 set pending 0x0000.0000 r/w pend1 0x204 124 interrupt 0-31 clear pending 0x0000.0000 r/w unpend0 0x280 125 interrupt 32-54 clear pending 0x0000.0000 r/w unpend1 0x284 126 interrupt 0-31 active bit 0x0000.0000 ro active0 0x300 127 interrupt 32-54 active bit 0x0000.0000 ro active1 0x304 128 interrupt 0-3 priority 0x0000.0000 r/w pri0 0x400 111 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 3-7. peripherals register map (continued) see page description reset type name offset 128 interrupt 4-7 priority 0x0000.0000 r/w pri1 0x404 128 interrupt 8-11 priority 0x0000.0000 r/w pri2 0x408 128 interrupt 12-15 priority 0x0000.0000 r/w pri3 0x40c 128 interrupt 16-19 priority 0x0000.0000 r/w pri4 0x410 128 interrupt 20-23 priority 0x0000.0000 r/w pri5 0x414 128 interrupt 24-27 priority 0x0000.0000 r/w pri6 0x418 128 interrupt 28-31 priority 0x0000.0000 r/w pri7 0x41c 128 interrupt 32-35 priority 0x0000.0000 r/w pri8 0x420 128 interrupt 36-39 priority 0x0000.0000 r/w pri9 0x424 128 interrupt 40-43 priority 0x0000.0000 r/w pri10 0x428 128 interrupt 44-47 priority 0x0000.0000 r/w pri11 0x42c 128 interrupt 48-51 priority 0x0000.0000 r/w pri12 0x430 128 interrupt 52-54 priority 0x0000.0000 r/w pri13 0x434 130 software trigger interrupt 0x0000.0000 wo swtrig 0xf00 system control block (scb) registers 131 auxiliary control 0x0000.0000 r/w actlr 0x008 133 cpu id base 0x412f.c230 ro cpuid 0xd00 134 interrupt control and state 0x0000.0000 r/w intctrl 0xd04 137 vector table offset 0x0000.0000 r/w vtable 0xd08 138 application interrupt and reset control 0xfa05.0000 r/w apint 0xd0c 140 system control 0x0000.0000 r/w sysctrl 0xd10 142 configuration and control 0x0000.0200 r/w cfgctrl 0xd14 144 system handler priority 1 0x0000.0000 r/w syspri1 0xd18 145 system handler priority 2 0x0000.0000 r/w syspri2 0xd1c 146 system handler priority 3 0x0000.0000 r/w syspri3 0xd20 147 system handler control and state 0x0000.0000 r/w syshndctrl 0xd24 151 configurable fault status 0x0000.0000 r/w1c faultstat 0xd28 157 hard fault status 0x0000.0000 r/w1c hfaultstat 0xd2c 158 memory management fault address - r/w mmaddr 0xd34 159 bus fault address - r/w faultaddr 0xd38 memory protection unit (mpu) registers 160 mpu type 0x0000.0800 ro mputype 0xd90 march 20, 2011 112 texas instruments-advance information cortex-m3 peripherals table 3-7. peripherals register map (continued) see page description reset type name offset 161 mpu control 0x0000.0000 r/w mpuctrl 0xd94 163 mpu region number 0x0000.0000 r/w mpunumber 0xd98 164 mpu region base address 0x0000.0000 r/w mpubase 0xd9c 166 mpu region attribute and size 0x0000.0000 r/w mpuattr 0xda0 164 mpu region base address alias 1 0x0000.0000 r/w mpubase1 0xda4 166 mpu region attribute and size alias 1 0x0000.0000 r/w mpuattr1 0xda8 164 mpu region base address alias 2 0x0000.0000 r/w mpubase2 0xdac 166 mpu region attribute and size alias 2 0x0000.0000 r/w mpuattr2 0xdb0 164 mpu region base address alias 3 0x0000.0000 r/w mpubase3 0xdb4 166 mpu region attribute and size alias 3 0x0000.0000 r/w mpuattr3 0xdb8 3.3 system timer (systick) register descriptions this section lists and describes the system timer registers, in numerical order by address offset. 113 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: systick control and status register (stctrl), offset 0x010 note: this register can only be accessed from privileged mode. the systick stctrl register enables the systick features. systick control and status register (stctrl) base 0xe000.e000 offset 0x010 type r/w, reset 0x0000.0004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 count reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable inten clk_src reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 count flag description value the systick timer has not counted to 0 since the last time this bit was read. 0 the systick timer has counted to 0 since the last time this bit was read. 1 this bit is cleared by a read of the register or if the stcurrent register is written with any value. if read by the debugger using the dap, this bit is cleared only if the mastertype bit in the ahb-ap control register is clear. otherwise, the count bit is not changed by the debugger read. see the arm? debug interface v5 architecture specification for more information on mastertype. 0 ro count 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:3 clock source description value external reference clock. (not implemented for stellaris microcontrollers.) 0 system clock 1 because an external reference clock is not implemented, this bit must be set in order for systick to operate. 1 r/w clk_src 2 march 20, 2011 114 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field interrupt enable description value interrupt generation is disabled. software can use the count bit to determine if the counter has ever reached 0. 0 an interrupt is generated to the nvic when systick counts to 0. 1 0 r/w inten 1 enable description value the counter is disabled. 0 enables systick to operate in a multi-shot way. that is, the counter loads the reload value and begins counting down. on reaching 0, the count bit is set and an interrupt is generated if enabled by inten . the counter then loads the reload value again and begins counting. 1 0 r/w enable 0 115 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: systick reload value register (streload), offset 0x014 note: this register can only be accessed from privileged mode. the streload register specifies the start value to load into the systick current value (stcurrent) register when the counter reaches 0. the start value can be between 0x1 and 0x00ff.ffff. a start value of 0 is possible but has no effect because the systick interrupt and the count bit are activated when counting from 1 to 0. systick can be configured as a multi-shot timer, repeated over and over, firing every n+1 clock pulses, where n is any value from 1 to 0x00ff.ffff. for example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the reload field. systick reload value register (streload) base 0xe000.e000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reload reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 reload value value to load into the systick current value (stcurrent) register when the counter reaches 0. 0x00.0000 r/w reload 23:0 march 20, 2011 116 texas instruments-advance information cortex-m3 peripherals register 3: systick current value register (stcurrent), offset 0x018 note: this register can only be accessed from privileged mode. the stcurrent register contains the current value of the systick counter. systick current value register (stcurrent) base 0xe000.e000 offset 0x018 type r/wc, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 current reserved r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 current r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 current value this field contains the current value at the time the register is accessed. no read-modify-write protection is provided, so change with care. this register is write-clear. writing to it with any value clears the register. clearing this register also clears the count bit of the stctrl register. 0x00.0000 r/wc current 23:0 3.4 nvic register descriptions this section lists and describes the nvic registers, in numerical order by address offset. the nvic registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the configuration and control (cfgctrl) register. any other unprivileged mode access causes a bus fault. ensure software uses correctly aligned register accesses. the processor does not support unaligned accesses to nvic registers. an interrupt can enter the pending state even if it is disabled. before programming the vtable register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, nmi, and all enabled exceptions such as interrupts. for more information, see page 137. 117 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: interrupt 0-31 set enable (en0), offset 0x100 note: this register can only be accessed from privileged mode. the en0 register enables interrupts and shows which interrupts are enabled. bit 0 corresponds to interrupt 0; bit 31 corresponds to interrupt 31. see table 2-9 on page 90 for interrupt assignments. if a pending interrupt is enabled, the nvic activates the interrupt based on its priority. if an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the nvic never activates the interrupt, regardless of its priority. interrupt 0-31 set enable (en0) base 0xe000.e000 offset 0x100 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt enable description value on a read, indicates the interrupt is disabled. on a write, no effect. 0 on a read, indicates the interrupt is enabled. on a write, enables the interrupt. 1 a bit can only be cleared by setting the corresponding int[n] bit in the disn register. 0x0000.0000 r/w int 31:0 march 20, 2011 118 texas instruments-advance information cortex-m3 peripherals register 5: interrupt 32-54 set enable (en1), offset 0x104 note: this register can only be accessed from privileged mode. the en1 register enables interrupts and shows which interrupts are enabled. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 90 for interrupt assignments. if a pending interrupt is enabled, the nvic activates the interrupt based on its priority. if an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the nvic never activates the interrupt, regardless of its priority. interrupt 32-54 set enable (en1) base 0xe000.e000 offset 0x104 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt enable description value on a read, indicates the interrupt is disabled. on a write, no effect. 0 on a read, indicates the interrupt is enabled. on a write, enables the interrupt. 1 a bit can only be cleared by setting the corresponding int[n] bit in the dis1 register. 0x00.0000 r/w int 22:0 119 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 6: interrupt 0-31 clear enable (dis0), offset 0x180 note: this register can only be accessed from privileged mode. the dis0 register disables interrupts. bit 0 corresponds to interrupt 0; bit 31 corresponds to interrupt 31. see table 2-9 on page 90 for interrupt assignments. interrupt 0-31 clear enable (dis0) base 0xe000.e000 offset 0x180 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt disable description value on a read, indicates the interrupt is disabled. on a write, no effect. 0 on a read, indicates the interrupt is enabled. on a write, clears the corresponding int[n] bit in the en0 register, disabling interrupt [n]. 1 0x0000.0000 r/w int 31:0 march 20, 2011 120 texas instruments-advance information cortex-m3 peripherals register 7: interrupt 32-54 clear enable (dis1), offset 0x184 note: this register can only be accessed from privileged mode. the dis1 register disables interrupts. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 90 for interrupt assignments. interrupt 32-54 clear enable (dis1) base 0xe000.e000 offset 0x184 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt disable description value on a read, indicates the interrupt is disabled. on a write, no effect. 0 on a read, indicates the interrupt is enabled. on a write, clears the corresponding int[n] bit in the en1 register, disabling interrupt [n]. 1 0x00.0000 r/w int 22:0 121 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 8: interrupt 0-31 set pending (pend0), offset 0x200 note: this register can only be accessed from privileged mode. the pend0 register forces interrupts into the pending state and shows which interrupts are pending. bit 0 corresponds to interrupt 0; bit 31 corresponds to interrupt 31. see table 2-9 on page 90 for interrupt assignments. interrupt 0-31 set pending (pend0) base 0xe000.e000 offset 0x200 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt set pending description value on a read, indicates that the interrupt is not pending. on a write, no effect. 0 on a read, indicates that the interrupt is pending. on a write, the corresponding interrupt is set to pending even if it is disabled. 1 if the corresponding interrupt is already pending, setting a bit has no effect. a bit can only be cleared by setting the corresponding int[n] bit in the unpend0 register. 0x0000.0000 r/w int 31:0 march 20, 2011 122 texas instruments-advance information cortex-m3 peripherals register 9: interrupt 32-54 set pending (pend1), offset 0x204 note: this register can only be accessed from privileged mode. the pend1 register forces interrupts into the pending state and shows which interrupts are pending. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 90 for interrupt assignments. interrupt 32-54 set pending (pend1) base 0xe000.e000 offset 0x204 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt set pending description value on a read, indicates that the interrupt is not pending. on a write, no effect. 0 on a read, indicates that the interrupt is pending. on a write, the corresponding interrupt is set to pending even if it is disabled. 1 if the corresponding interrupt is already pending, setting a bit has no effect. a bit can only be cleared by setting the corresponding int[n] bit in the unpend1 register. 0x00.0000 r/w int 22:0 123 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 10: interrupt 0-31 clear pending (unpend0), offset 0x280 note: this register can only be accessed from privileged mode. the unpend0 register shows which interrupts are pending and removes the pending state from interrupts. bit 0 corresponds to interrupt 0; bit 31 corresponds to interrupt 31. see table 2-9 on page 90 for interrupt assignments. interrupt 0-31 clear pending (unpend0) base 0xe000.e000 offset 0x280 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt clear pending description value on a read, indicates that the interrupt is not pending. on a write, no effect. 0 on a read, indicates that the interrupt is pending. on a write, clears the corresponding int[n] bit in the pend0 register, so that interrupt [n] is no longer pending. setting a bit does not affect the active state of the corresponding interrupt. 1 0x0000.0000 r/w int 31:0 march 20, 2011 124 texas instruments-advance information cortex-m3 peripherals register 11: interrupt 32-54 clear pending (unpend1), offset 0x284 note: this register can only be accessed from privileged mode. the unpend1 register shows which interrupts are pending and removes the pending state from interrupts. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 90 for interrupt assignments. interrupt 32-54 clear pending (unpend1) base 0xe000.e000 offset 0x284 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt clear pending description value on a read, indicates that the interrupt is not pending. on a write, no effect. 0 on a read, indicates that the interrupt is pending. on a write, clears the corresponding int[n] bit in the pend1 register, so that interrupt [n] is no longer pending. setting a bit does not affect the active state of the corresponding interrupt. 1 0x00.0000 r/w int 22:0 125 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: interrupt 0-31 active bit (active0), offset 0x300 note: this register can only be accessed from privileged mode. the active0 register indicates which interrupts are active. bit 0 corresponds to interrupt 0; bit 31 corresponds to interrupt 31. see table 2-9 on page 90 for interrupt assignments. caution C do not manually set or clear the bits in this register. interrupt 0-31 active bit (active0) base 0xe000.e000 offset 0x300 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt active description value the corresponding interrupt is not active. 0 the corresponding interrupt is active, or active and pending. 1 0x0000.0000 ro int 31:0 march 20, 2011 126 texas instruments-advance information cortex-m3 peripherals register 13: interrupt 32-54 active bit (active1), offset 0x304 note: this register can only be accessed from privileged mode. the active1 register indicates which interrupts are active. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 90 for interrupt assignments. caution C do not manually set or clear the bits in this register. interrupt 32-54 active bit (active1) base 0xe000.e000 offset 0x304 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt active description value the corresponding interrupt is not active. 0 the corresponding interrupt is active, or active and pending. 1 0x00.0000 ro int 22:0 127 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 14: interrupt 0-3 priority (pri0), offset 0x400 register 15: interrupt 4-7 priority (pri1), offset 0x404 register 16: interrupt 8-11 priority (pri2), offset 0x408 register 17: interrupt 12-15 priority (pri3), offset 0x40c register 18: interrupt 16-19 priority (pri4), offset 0x410 register 19: interrupt 20-23 priority (pri5), offset 0x414 register 20: interrupt 24-27 priority (pri6), offset 0x418 register 21: interrupt 28-31 priority (pri7), offset 0x41c register 22: interrupt 32-35 priority (pri8), offset 0x420 register 23: interrupt 36-39 priority (pri9), offset 0x424 register 24: interrupt 40-43 priority (pri10), offset 0x428 register 25: interrupt 44-47 priority (pri11), offset 0x42c register 26: interrupt 48-51 priority (pri12), offset 0x430 register 27: interrupt 52-54 priority (pri13), offset 0x434 note: this register can only be accessed from privileged mode. the prin registers provide 3-bit priority fields for each interrupt. these registers are byte accessible. each register holds four priority fields that are assigned to interrupts as follows: interrupt prin register bit field interrupt [4n+3] bits 31:29 interrupt [4n+2] bits 23:21 interrupt [4n+1] bits 15:13 interrupt [4n] bits 7:5 see table 2-9 on page 90 for interrupt assignments. each priority level can be split into separate group priority and subpriority fields. the prigroup field in the application interrupt and reset control (apint) register (see page 138) indicates the position of the binary point that splits the priority and subpriority fields. these registers can only be accessed from privileged mode. march 20, 2011 128 texas instruments-advance information cortex-m3 peripherals interrupt 0-3 priority (pri0) base 0xe000.e000 offset 0x400 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved intc reserved intd ro ro ro ro ro r/w r/w r/w ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved inta reserved intb ro ro ro ro ro r/w r/w r/w ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt priority for interrupt [4n+3] this field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the interrupt priority register (n=0 for pri0 , and so on). the lower the value, the greater the priority of the corresponding interrupt. 0x0 r/w intd 31:29 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 28:24 interrupt priority for interrupt [4n+2] this field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the interrupt priority register (n=0 for pri0 , and so on). the lower the value, the greater the priority of the corresponding interrupt. 0x0 r/w intc 23:21 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 20:16 interrupt priority for interrupt [4n+1] this field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the interrupt priority register (n=0 for pri0 , and so on). the lower the value, the greater the priority of the corresponding interrupt. 0x0 r/w intb 15:13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 12:8 interrupt priority for interrupt [4n] this field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the interrupt priority register (n=0 for pri0 , and so on). the lower the value, the greater the priority of the corresponding interrupt. 0x0 r/w inta 7:5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 4:0 129 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 28: software trigger interrupt (swtrig), offset 0xf00 note: only privileged software can enable unprivileged access to the swtrig register. writing an interrupt number to the swtrig register generates a software generated interrupt (sgi). see table 2-9 on page 90 for interrupt assignments. when the mainpend bit in the configuration and control (cfgctrl) register (see page 142) is set, unprivileged software can access the swtrig register. software trigger interrupt (swtrig) base 0xe000.e000 offset 0xf00 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intid reserved wo wo wo wo wo wo ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 interrupt id this field holds the interrupt id of the required sgi. for example, a value of 0x3 generates an interrupt on irq3. 0x00 wo intid 5:0 3.5 system control block (scb) register descriptions this section lists and describes the system control block (scb) registers, in numerical order by address offset. the scb registers can only be accessed from privileged mode. all registers must be accessed with aligned word accesses except for the faultstat and syspri1 -syspri3 registers, which can be accessed with byte or aligned halfword or word accesses. the processor does not support unaligned accesses to system control block registers. march 20, 2011 130 texas instruments-advance information cortex-m3 peripherals register 29: auxiliary control (actlr), offset 0x008 note: this register can only be accessed from privileged mode. the actlr register provides disable bits for it folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. by default, this register is set to provide optimum performance from the cortex-m3 processor and does not normally require modification. auxiliary control (actlr) base 0xe000.e000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dismcyc diswbuf disfold reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 disable it folding description value no effect. 0 disables it folding. 1 in some situations, the processor can start executing the first instruction in an it block while it is still executing the it instruction. this behavior is called it folding , and improves performance, however, it folding can cause jitter in looping. if a task must avoid jitter, set the disfold bit before executing the task, to disable it folding. 0 r/w disfold 2 disable write buffer description value no effect. 0 disables write buffer use during default memory map accesses. in this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. 1 note: this bit only affects write buffers implemented in the cortex-m3 processor. 0 r/w diswbuf 1 131 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field disable interrupts of multiple cycle instructions description value no effect. 0 disables interruption of load multiple and store multiple instructions. in this situation, the interrupt latency of the processor is increased because any ldm or stm must complete before the processor can stack the current state and enter the interrupt handler. 1 0 r/w dismcyc 0 march 20, 2011 132 texas instruments-advance information cortex-m3 peripherals register 30: cpu id base (cpuid), offset 0xd00 note: this register can only be accessed from privileged mode. the cpuid register contains the arm? cortex?-m3 processor part number, version, and implementation information. cpu id base (cpuid) base 0xe000.e000 offset 0xd00 type ro, reset 0x412f.c230 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 con var imp ro ro ro ro ro ro ro ro r0 r0 r0 r0 r0 r0 r0 r0 type 1 1 1 1 0 1 0 0 1 0 0 0 0 0 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rev partno ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 reset description reset type name bit/field implementer code description value arm 0x41 0x41 r0 imp 31:24 variant number description value the rn value in the rnpn product revision identifier, for example, the 2 in r2p0. 0x2 0x2 ro var 23:20 constant description value always reads as 0xf. 0xf 0xf ro con 19:16 part number description value cortex-m3 processor. 0xc23 0xc23 ro partno 15:4 revision number description value the pn value in the rnpn product revision identifier, for example, the 0 in r2p0. 0x0 0x0 ro rev 3:0 133 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 31: interrupt control and state (intctrl), offset 0xd04 note: this register can only be accessed from privileged mode. the inctrl register provides a set-pending bit for the nmi exception, and set-pending and clear-pending bits for the pendsv and systick exceptions. in addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. when writing to inctrl , the effect is unpredictable when writing a 1 to both the pendsv and unpendsv bits, or writing a 1 to both the pendstset and pendstclr bits. interrupt control and state (intctrl) base 0xe000.e000 offset 0xd04 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vecpend reserved isrpend isrpre reserved pendstclr pendstset unpendsv pendsv reserved nmiset ro ro ro ro ro ro ro ro ro wo r/w wo r/w ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vecact reserved retbase vecpend ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field nmi set pending description value on a read, indicates an nmi exception is not pending. on a write, no effect. 0 on a read, indicates an nmi exception is pending. on a write, changes the nmi exception state to pending. 1 because nmi is the highest-priority exception, normally the processor enters the nmi exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. a read of this bit by the nmi exception handler returns 1 only if the nmi signal is reasserted while the processor is executing that handler. 0 r/w nmiset 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 30:29 pendsv set pending description value on a read, indicates a pendsv exception is not pending. on a write, no effect. 0 on a read, indicates a pendsv exception is pending. on a write, changes the pendsv exception state to pending. 1 setting this bit is the only way to set the pendsv exception state to pending. this bit is cleared by writing a 1 to the unpendsv bit. 0 r/w pendsv 28 march 20, 2011 134 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field pendsv clear pending description value on a write, no effect. 0 on a write, removes the pending state from the pendsv exception. 1 this bit is write only; on a register read, its value is unknown. 0 wo unpendsv 27 systick set pending description value on a read, indicates a systick exception is not pending. on a write, no effect. 0 on a read, indicates a systick exception is pending. on a write, changes the systick exception state to pending. 1 this bit is cleared by writing a 1 to the pendstclr bit. 0 r/w pendstset 26 systick clear pending description value on a write, no effect. 0 on a write, removes the pending state from the systick exception. 1 this bit is write only; on a register read, its value is unknown. 0 wo pendstclr 25 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 24 debug interrupt handling description value the release from halt does not take an interrupt. 0 the release from halt takes an interrupt. 1 this bit is only meaningful in debug mode and reads as zero when the processor is not in debug mode. 0 ro isrpre 23 interrupt pending description value no interrupt is pending. 0 an interrupt is pending. 1 this bit provides status for all interrupts excluding nmi and faults. 0 ro isrpend 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 21:19 135 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field interrupt pending vector number this field contains the exception number of the highest priority pending enabled exception. the value indicated by this field includes the effect of the basepri and faultmask registers, but not any effect of the primask register. description value no exceptions are pending 0x00 reserved 0x01 nmi 0x02 hard fault 0x03 memory management fault 0x04 bus fault 0x05 usage fault 0x06 reserved 0x07-0x0a svcall 0x0b reserved for debug 0x0c reserved 0x0d pendsv 0x0e systick 0x0f interrupt vector 0 0x10 interrupt vector 1 0x11 ... ... interrupt vector 54 0x46 reserved 0x47-0x7f 0x00 ro vecpend 18:12 return to base description value there are preempted active exceptions to execute. 0 there are no active exceptions, or the currently executing exception is the only active exception. 1 this bit provides status for all interrupts excluding nmi and faults. this bit only has meaning if the processor is currently executing an isr (the interrupt program status (ipsr) register is non-zero). 0 ro retbase 11 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 10:7 interrupt pending vector number this field contains the active exception number. the exception numbers can be found in the description for the vecpend field. if this field is clear, the processor is in thread mode. this field contains the same value as the isrnum field in the ipsr register. subtract 16 from this value to obtain the irq number required to index into the interrupt set enable (enn) , interrupt clear enable (disn ), interrupt set pending (pendn) , interrupt clear pending (unpendn) , and interrupt priority (prin) registers (see page 71). 0x00 ro vecact 6:0 march 20, 2011 136 texas instruments-advance information cortex-m3 peripherals register 32: vector table offset (vtable), offset 0xd08 note: this register can only be accessed from privileged mode. the vtable register indicates the offset of the vector table base address from memory address 0x0000.0000. vector table offset (vtable) base 0xe000.e000 offset 0xd08 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 offset base reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved offset ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:30 vector table base description value the vector table is in the code memory region. 0 the vector table is in the sram memory region. 1 0 r/w base 29 vector table offset when configuring the offset field, the offset must be aligned to the number of exception entries in the vector table. because there are 54 interrupts, the minimum alignment is 128 words. 0x000.00 r/w offset 28:9 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 8:0 137 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 33: application interrupt and reset control (apint), offset 0xd0c note: this register can only be accessed from privileged mode. the apint register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. to write to this register, 0x05fa must be written to the vectkey field, otherwise the write is ignored. the prigroup field indicates the position of the binary point that splits the intx fields in the interrupt priority (prix) registers into separate group priority and subpriority fields. table 3-8 on page 138 shows how the prigroup value controls this split. the bit numbers in the group priority field and subpriority field columns in the table refer to the bits in the inta field. for the intb field, the corresponding bits are 15:13; for intc , 23:21; and for intd , 31:29. note: determining preemption of an exception uses only the group priority field. table 3-8. interrupt priority levels subpriorities group priorities subpriority field group priority field binary point a prigroup bit field 1 8 none [7:5] bxxx. 0x0 - 0x4 2 4 [5] [7:6] bxx.y 0x5 4 2 [6:5] [7] bx.yy 0x6 8 1 [7:5] none b.yyy 0x7 a. intx field showing the binary point. an x denotes a group priority field bit, and a y denotes a subpriority field bit. application interrupt and reset control (apint) base 0xe000.e000 offset 0xd0c type r/w, reset 0xfa05.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vectkey r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vectreset vectclract sysresreq reserved prigroup reserved endianess wo wo wo ro ro ro ro ro r/w r/w r/w ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field register key this field is used to guard against accidental writes to this register. 0x05fa must be written to this field in order to change the bits in this register. on a read, 0xfa05 is returned. 0xfa05 r/w vectkey 31:16 data endianess the stellaris implementation uses only little-endian mode so this is cleared to 0. 0 ro endianess 15 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 14:11 march 20, 2011 138 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field interrupt priority grouping this field determines the split of group priority from subpriority (see table 3-8 on page 138 for more information). 0x0 r/w prigroup 10:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:3 system reset request description value no effect. 0 resets the core and all on-chip peripherals except the debug interface. 1 this bit is automatically cleared during the reset of the core and reads as 0. 0 wo sysresreq 2 clear active nmi / fault this bit is reserved for debug use and reads as 0. this bit must be written as a 0, otherwise behavior is unpredictable. 0 wo vectclract 1 system reset this bit is reserved for debug use and reads as 0. this bit must be written as a 0, otherwise behavior is unpredictable. 0 wo vectreset 0 139 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 34: system control (sysctrl), offset 0xd10 note: this register can only be accessed from privileged mode. the sysctrl register controls features of entry to and exit from low-power state. system control (sysctrl) base 0xe000.e000 offset 0xd10 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved sleepexit sleepdeep reserved sevonpend reserved ro r/w r/w ro r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 wake up on pending description value only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 0 enabled events and all interrupts, including disabled interrupts, can wake up the processor. 1 when an event or interrupt enters the pending state, the event signal wakes up the processor from wfe . if the processor is not waiting for an event, the event is registered and affects the next wfe. the processor also wakes up on execution of a sev instruction or an external event. 0 r/w sevonpend 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 deep sleep enable description value use sleep mode as the low power mode. 0 use deep-sleep mode as the low power mode. 1 0 r/w sleepdeep 2 march 20, 2011 140 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field sleep on isr exit description value when returning from handler mode to thread mode, do not sleep when returning to thread mode. 0 when returning from handler mode to thread mode, enter sleep or deep sleep on return from an isr. 1 setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0 r/w sleepexit 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 141 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 35: configuration and control (cfgctrl), offset 0xd14 note: this register can only be accessed from privileged mode. the cfgctrl register controls entry to thread mode and enables: the handlers for nmi, hard fault and faults escalated by the faultmask register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the swtrig register by unprivileged software (see page 130). configuration and control (cfgctrl) base 0xe000.e000 offset 0xd14 type r/w, reset 0x0000.0200 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 basethr mainpend reserved unaligned div0 reserved bfhfnmign stkalign reserved r/w r/w ro r/w r/w ro ro ro r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:10 stack alignment on exception entry description value the stack is 4-byte aligned. 0 the stack is 8-byte aligned. 1 on exception entry, the processor uses bit 9 of the stacked psr to indicate the stack alignment. on return from the exception, it uses this stacked bit to restore the correct stack alignment. 1 r/w stkalign 9 ignore bus fault in nmi and fault this bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. the setting of this bit applies to the hard fault, nmi, and faultmask escalated handlers. description value data bus faults caused by load and store instructions cause a lock-up. 0 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. 1 set this bit only when the handler and its data are in absolutely safe memory. the normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 0 r/w bfhfnmign 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 march 20, 2011 142 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field trap on divide by 0 this bit enables faulting or halting when the processor executes an sdiv or udiv instruction with a divisor of 0. description value do not trap on divide by 0. a divide by zero returns a quotient of 0. 0 trap on divide by 0. 1 0 r/w div0 4 trap on unaligned access description value do not trap on unaligned halfword and word accesses. 0 trap on unaligned halfword and word accesses. an unaligned access generates a usage fault. 1 unaligned ldm, stm, ldrd , and strd instructions always fault regardless of whether unaligned is set. 0 r/w unaligned 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2 allow main interrupt trigger description value disables unprivileged software access to the swtrig register. 0 enables unprivileged software access to the swtrig register (see page 130). 1 0 r/w mainpend 1 thread state control description value the processor can enter thread mode only when no exception is active. 0 the processor can enter thread mode from any level under the control of an exc_return value (see exception return on page 95 for more information). 1 0 r/w basethr 0 143 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 36: system handler priority 1 (syspri1), offset 0xd18 note: this register can only be accessed from privileged mode. the syspri1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. this register is byte-accessible. system handler priority 1 (syspri1) base 0xe000.e000 offset 0xd18 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved usage reserved ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved mem reserved bus ro ro ro ro ro r/w r/w r/w ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 usage fault priority this field configures the priority level of the usage fault. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w usage 23:21 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 20:16 bus fault priority this field configures the priority level of the bus fault. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w bus 15:13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 12:8 memory management fault priority this field configures the priority level of the memory management fault. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w mem 7:5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 4:0 march 20, 2011 144 texas instruments-advance information cortex-m3 peripherals register 37: system handler priority 2 (syspri2), offset 0xd1c note: this register can only be accessed from privileged mode. the syspri2 register configures the priority level, 0 to 7 of the svcall handler. this register is byte-accessible. system handler priority 2 (syspri2) base 0xe000.e000 offset 0xd1c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved svc ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field svcall priority this field configures the priority level of svcall. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w svc 31:29 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000 ro reserved 28:0 145 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 38: system handler priority 3 (syspri3), offset 0xd20 note: this register can only be accessed from privileged mode. the syspri3 register configures the priority level, 0 to 7 of the systick exception and pendsv handlers. this register is byte-accessible. system handler priority 3 (syspri3) base 0xe000.e000 offset 0xd20 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pendsv reserved tick ro ro ro ro ro r/w r/w r/w ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved debug reserved ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field systick exception priority this field configures the priority level of the systick exception. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w tick 31:29 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 28:24 pendsv priority this field configures the priority level of pendsv. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w pendsv 23:21 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 20:8 debug priority this field configures the priority level of debug. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w debug 7:5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0.0000 ro reserved 4:0 march 20, 2011 146 texas instruments-advance information cortex-m3 peripherals register 39: system handler control and state (syshndctrl), offset 0xd24 note: this register can only be accessed from privileged mode. the syshndctrl register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and svc exceptions as well as the active status of the system handlers. if a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. this register can be modified to change the pending or active status of system exceptions. an os kernel can write to the active bits to perform a context switch that changes the current exception type. caution C software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. ensure software that writes to this register retains and subsequently restores the current active status. if the value of a bit in this register must be modifed after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modifed. system handler control and state (syshndctrl) base 0xe000.e000 offset 0xd24 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mem bus usage reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mema busa reserved usga reserved svca mon reserved pndsv tick usagep memp busp svc r/w r/w ro r/w ro ro ro r/w r/w ro r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:19 usage fault enable description value disables the usage fault exception. 0 enables the usage fault exception. 1 0 r/w usage 18 bus fault enable description value disables the bus fault exception. 0 enables the bus fault exception. 1 0 r/w bus 17 147 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field memory management fault enable description value disables the memory management fault exception. 0 enables the memory management fault exception. 1 0 r/w mem 16 svc call pending description value an svc call exception is not pending. 0 an svc call exception is pending. 1 this bit can be modified to change the pending status of the svc call exception. 0 r/w svc 15 bus fault pending description value a bus fault exception is not pending. 0 a bus fault exception is pending. 1 this bit can be modified to change the pending status of the bus fault exception. 0 r/w busp 14 memory management fault pending description value a memory management fault exception is not pending. 0 a memory management fault exception is pending. 1 this bit can be modified to change the pending status of the memory management fault exception. 0 r/w memp 13 usage fault pending description value a usage fault exception is not pending. 0 a usage fault exception is pending. 1 this bit can be modified to change the pending status of the usage fault exception. 0 r/w usagep 12 systick exception active description value a systick exception is not active. 0 a systick exception is active. 1 this bit can be modified to change the active status of the systick exception, however, see the caution above before setting this bit. 0 r/w tick 11 march 20, 2011 148 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field pendsv exception active description value a pendsv exception is not active. 0 a pendsv exception is active. 1 this bit can be modified to change the active status of the pendsv exception, however, see the caution above before setting this bit. 0 r/w pndsv 10 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 9 debug monitor active description value the debug monitor is not active. 0 the debug monitor is active. 1 0 r/w mon 8 svc call active description value svc call is not active. 0 svc call is active. 1 this bit can be modified to change the active status of the svc call exception, however, see the caution above before setting this bit. 0 r/w svca 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 6:4 usage fault active description value usage fault is not active. 0 usage fault is active. 1 this bit can be modified to change the active status of the usage fault exception, however, see the caution above before setting this bit. 0 r/w usga 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2 bus fault active description value bus fault is not active. 0 bus fault is active. 1 this bit can be modified to change the active status of the bus fault exception, however, see the caution above before setting this bit. 0 r/w busa 1 149 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field memory management fault active description value memory management fault is not active. 0 memory management fault is active. 1 this bit can be modified to change the active status of the memory management fault exception, however, see the caution above before setting this bit. 0 r/w mema 0 march 20, 2011 150 texas instruments-advance information cortex-m3 peripherals register 40: configurable fault status (faultstat), offset 0xd28 note: this register can only be accessed from privileged mode. the faultstat register indicates the cause of a memory management fault, bus fault, or usage fault. each of these functions is assigned to a subregister as follows: usage fault status (ufaultstat) , bits 31:16 bus fault status (bfaultstat) , bits 15:8 memory management fault status (mfaultstat) , bits 7:0 faultstat is byte accessible. faultstat or its subregisters can be accessed as follows: the complete faultstat register, with a word access to offset 0xd28 the mfaultstat , with a byte access to offset 0xd28 the mfaultstat and bfaultstat , with a halfword access to offset 0xd28 the bfaultstat , with a byte access to offset 0xd29 the ufaultstat , with a halfword access to offset 0xd2a bits are cleared by writing a 1 to them. in a fault handler, the true faulting address can be determined by: 1. read and save the memory management fault address (mmaddr) or bus fault address (faultaddr) value. 2. read the mmarv bit in mfaultstat , or the bfarv bit in bfaultstat to determine if the mmaddr or faultaddr contents are valid. software must follow this sequence because another higher priority exception might change the mmaddr or faultaddr value. for example, if a higher priority handler preempts the current fault handler, the other fault might change the mmaddr or faultaddr value. configurable fault status (faultstat) base 0xe000.e000 offset 0xd28 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 undef invstat invpc nocp reserved unalign div0 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro r/w1c r/w1c ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ierr derr reserved mustke mstke reserved mmarv ibus precise impre bustke bstke reserved bfarv r/w1c r/w1c ro r/w1c r/w1c ro ro r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro r/w1c type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:26 151 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field divide-by-zero usage fault description value no divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 0 the processor has executed an sdiv or udiv instruction with a divisor of 0. 1 when this bit is set, the pc value stacked for the exception return points to the instruction that performed the divide by zero. trapping on divide-by-zero is enabled by setting the div0 bit in the configuration and control (cfgctrl) register (see page 142). this bit is cleared by writing a 1 to it. 0 r/w1c div0 25 unaligned access usage fault description value no unaligned access fault has occurred, or unaligned access trapping is not enabled. 0 the processor has made an unaligned memory access. 1 unaligned ldm, stm, ldrd , and strd instructions always fault regardless of the configuration of this bit. trapping on unaligned access is enabled by setting the unaligned bit in the cfgctrl register (see page 142). this bit is cleared by writing a 1 to it. 0 r/w1c unalign 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 23:20 no coprocessor usage fault description value a usage fault has not been caused by attempting to access a coprocessor. 0 the processor has attempted to access a coprocessor. 1 this bit is cleared by writing a 1 to it. 0 r/w1c nocp 19 invalid pc load usage fault description value a usage fault has not been caused by attempting to load an invalid pc value. 0 the processor has attempted an illegal load of exc_return to the pc as a result of an invalid context or an invalid exc_return value. 1 when this bit is set, the pc value stacked for the exception return points to the instruction that tried to perform the illegal load of the pc . this bit is cleared by writing a 1 to it. 0 r/w1c invpc 18 march 20, 2011 152 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field invalid state usage fault description value a usage fault has not been caused by an invalid state. 0 the processor has attempted to execute an instruction that makes illegal use of the epsr register. 1 when this bit is set, the pc value stacked for the exception return points to the instruction that attempted the illegal use of the execution program status register (epsr) register. this bit is not set if an undefined instruction uses the epsr register. this bit is cleared by writing a 1 to it. 0 r/w1c invstat 17 undefined instruction usage fault description value a usage fault has not been caused by an undefined instruction. 0 the processor has attempted to execute an undefined instruction. 1 when this bit is set, the pc value stacked for the exception return points to the undefined instruction. an undefined instruction is an instruction that the processor cannot decode. this bit is cleared by writing a 1 to it. 0 r/w1c undef 16 bus fault address register valid description value the value in the bus fault address (faultaddr) register is not a valid fault address. 0 the faultaddr register is holding a valid fault address. 1 this bit is set after a bus fault, where the address is known. other faults can clear this bit, such as a memory management fault occurring later. if a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. this action prevents problems if returning to a stacked active bus fault handler whose faultaddr register value has been overwritten. this bit is cleared by writing a 1 to it. 0 r/w1c bfarv 15 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 14:13 stack bus fault description value no bus fault has occurred on stacking for exception entry. 0 stacking for an exception entry has caused one or more bus faults. 1 when this bit is set, the sp is still adjusted but the values in the context area on the stack might be incorrect. a fault address is not written to the faultaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c bstke 12 153 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field unstack bus fault description value no bus fault has occurred on unstacking for a return from exception. 0 unstacking for a return from exception has caused one or more bus faults. 1 this fault is chained to the handler. thus, when this bit is set, the original return stack is still present. the sp is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the faultaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c bustke 11 imprecise data bus error description value an imprecise data bus error has not occurred. 0 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. 1 when this bit is set, a fault address is not written to the faultaddr register. this fault is asynchronous. therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. if a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the impre bit is set and one of the precise fault status bits is set. this bit is cleared by writing a 1 to it. 0 r/w1c impre 10 precise data bus error description value a precise data bus error has not occurred. 0 a data bus error has occurred, and the pc value stacked for the exception return points to the instruction that caused the fault. 1 when this bit is set, the fault address is written to the faultaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c precise 9 instruction bus error description value an instruction bus error has not occurred. 0 an instruction bus error has occurred. 1 the processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. when this bit is set, a fault address is not written to the faultaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c ibus 8 march 20, 2011 154 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field memory management fault address register valid description value the value in the memory management fault address (mmaddr) register is not a valid fault address. 0 the mmaddr register is holding a valid fault address. 1 if a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. this action prevents problems if returning to a stacked active memory management fault handler whose mmaddr register value has been overwritten. this bit is cleared by writing a 1 to it. 0 r/w1c mmarv 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 6:5 stack access violation description value no memory management fault has occurred on stacking for exception entry. 0 stacking for an exception entry has caused one or more access violations. 1 when this bit is set, the sp is still adjusted but the values in the context area on the stack might be incorrect. a fault address is not written to the mmaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c mstke 4 unstack access violation description value no memory management fault has occurred on unstacking for a return from exception. 0 unstacking for a return from exception has caused one or more access violations. 1 this fault is chained to the handler. thus, when this bit is set, the original return stack is still present. the sp is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the mmaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c mustke 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2 155 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field data access violation description value a data access violation has not occurred. 0 the processor attempted a load or store at a location that does not permit the operation. 1 when this bit is set, the pc value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the mmaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c derr 1 instruction access violation description value an instruction access violation has not occurred. 0 the processor attempted an instruction fetch from a location that does not permit execution. 1 this fault occurs on any access to an xn region, even when the mpu is disabled or not present. when this bit is set, the pc value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the mmaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c ierr 0 march 20, 2011 156 texas instruments-advance information cortex-m3 peripherals register 41: hard fault status (hfaultstat), offset 0xd2c note: this register can only be accessed from privileged mode. the hfaultstat register gives information about events that activate the hard fault handler. bits are cleared by writing a 1 to them. hard fault status (hfaultstat) base 0xe000.e000 offset 0xd2c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved forced dbg ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w1c r/w1c type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved vect reserved ro r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field debug event this bit is reserved for debug use. this bit must be written as a 0, otherwise behavior is unpredictable. 0 r/w1c dbg 31 forced hard fault description value no forced hard fault has occurred. 0 a forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. 1 when this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. this bit is cleared by writing a 1 to it. 0 r/w1c forced 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 29:2 vector table read fault description value no bus fault has occurred on a vector table read. 0 a bus fault occurred on a vector table read. 1 this error is always handled by the hard fault handler. when this bit is set, the pc value stacked for the exception return points to the instruction that was preempted by the exception. this bit is cleared by writing a 1 to it. 0 r/w1c vect 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 157 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 42: memory management fault address (mmaddr), offset 0xd34 note: this register can only be accessed from privileged mode. the mmaddr register contains the address of the location that generated a memory management fault. when an unaligned access faults, the address in the mmaddr register is the actual address that faulted. because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. bits in the memory management fault status (mfaultstat) register indicate the cause of the fault and whether the value in the mmaddr register is valid (see page 151). memory management fault address (mmaddr) base 0xe000.e000 offset 0xd34 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field fault address when the mmarv bit of mfaultstat is set, this field holds the address of the location that generated the memory management fault. - r/w addr 31:0 march 20, 2011 158 texas instruments-advance information cortex-m3 peripherals register 43: bus fault address (faultaddr), offset 0xd38 note: this register can only be accessed from privileged mode. the faultaddr register contains the address of the location that generated a bus fault. when an unaligned access faults, the address in the faultaddr register is the one requested by the instruction, even if it is not the address of the fault. bits in the bus fault status (bfaultstat) register indicate the cause of the fault and whether the value in the faultaddr register is valid (see page 151). bus fault address (faultaddr) base 0xe000.e000 offset 0xd38 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field fault address when the faultaddrv bit of bfaultstat is set, this field holds the address of the location that generated the bus fault. - r/w addr 31:0 3.6 memory protection unit (mpu) register descriptions this section lists and describes the memory protection unit (mpu) registers, in numerical order by address offset. the mpu registers can only be accessed from privileged mode. 159 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 44: mpu type (mputype), offset 0xd90 note: this register can only be accessed from privileged mode. the mputype register indicates whether the mpu is present, and if so, how many regions it supports. mpu type (mputype) base 0xe000.e000 offset 0xd90 type ro, reset 0x0000.0800 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 iregion reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 separate reserved dregion ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 number of i regions this field indicates the number of supported mpu instruction regions. this field always contains 0x00. the mpu memory map is unified and is described by the dregion field. 0x00 ro iregion 23:16 number of d regions description value indicates there are eight supported mpu data regions. 0x08 0x08 ro dregion 15:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:1 separate or unified mpu description value indicates the mpu is unified. 0 0 ro separate 0 march 20, 2011 160 texas instruments-advance information cortex-m3 peripherals register 45: mpu control (mpuctrl), offset 0xd94 note: this register can only be accessed from privileged mode. the mpuctrl register enables the mpu, enables the default memory map background region, and enables use of the mpu when in the hard fault, non-maskable interrupt (nmi), and fault mask register (faultmask) escalated handlers. when the enable and privdefen bits are both set: for privileged accesses, the default memory map is as described in memory model on page 79. any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. any access by unprivileged software that does not address an enabled memory region causes a memory management fault. execute never (xn) and strongly ordered rules always apply to the system control space regardless of the value of the enable bit. when the enable bit is set, at least one region of the memory map must be enabled for the system to function unless the privdefen bit is set. if the privdefen bit is set and no regions are enabled, then only privileged software can operate. when the enable bit is clear, the system uses the default memory map, which has the same memory attributes as if the mpu is not implemented (see table 2-5 on page 82 for more information). the default memory map applies to accesses from both privileged and unprivileged software. when the mpu is enabled, accesses to the system control space and vector table are always permitted. other areas are accessible based on regions and whether privdefen is set. unless hfnmiena is set, the mpu is not enabled when the processor is executing the handler for an exception with priority C1 or C2. these priorities are only possible when handling a hard fault or nmi exception or when faultmask is enabled. setting the hfnmiena bit enables the mpu when operating with these two priorities. mpu control (mpuctrl) base 0xe000.e000 offset 0xd94 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable hfnmiena privdefen reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 161 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field mpu default region this bit enables privileged software access to the default memory map. description value if the mpu is enabled, this bit disables use of the default memory map. any memory access to a location not covered by any enabled region causes a fault. 0 if the mpu is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. 1 when this bit is set, the background region acts as if it is region number -1. any region that is defined and enabled has priority over this default map. if the mpu is disabled, the processor ignores this bit. 0 r/w privdefen 2 mpu enabled during faults this bit controls the operation of the mpu during hard fault, nmi, and faultmask handlers. description value the mpu is disabled during hard fault, nmi, and faultmask handlers, regardless of the value of the enable bit. 0 the mpu is enabled during hard fault, nmi, and faultmask handlers. 1 when the mpu is disabled and this bit is set, the resulting behavior is unpredictable. 0 r/w hfnmiena 1 mpu enable description value the mpu is disabled. 0 the mpu is enabled. 1 when the mpu is disabled and the hfnmiena bit is set, the resulting behavior is unpredictable. 0 r/w enable 0 march 20, 2011 162 texas instruments-advance information cortex-m3 peripherals register 46: mpu region number (mpunumber), offset 0xd98 note: this register can only be accessed from privileged mode. the mpunumber register selects which memory region is referenced by the mpu region base address (mpubase) and mpu region attribute and size (mpuattr) registers. normally, the required region number should be written to this register before accessing the mpubase or the mpuattr register. however, the region number can be changed by writing to the mpubase register with the valid bit set (see page 164). this write updates the value of the region field. mpu region number (mpunumber) base 0xe000.e000 offset 0xd98 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 number reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 mpu region to access this field indicates the mpu region referenced by the mpubase and mpuattr registers. the mpu supports eight memory regions. 0x0 r/w number 2:0 163 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 47: mpu region base address (mpubase), offset 0xd9c register 48: mpu region base address alias 1 (mpubase1), offset 0xda4 register 49: mpu region base address alias 2 (mpubase2), offset 0xdac register 50: mpu region base address alias 3 (mpubase3), offset 0xdb4 note: this register can only be accessed from privileged mode. the mpubase register defines the base address of the mpu region selected by the mpu region number (mpunumber) register and can update the value of the mpunumber register. to change the current region number and update the mpunumber register, write the mpubase register with the valid bit set. the addr field is bits 31: n of the mpubase register. bits ( n -1):5 are reserved. the region size, as specified by the size field in the mpu region attribute and size (mpuattr) register, defines the value of n where: n = log 2 (region size in bytes) if the region size is configured to 4 gb in the mpuattr register, there is no valid addr field. in this case, the region occupies the complete memory map, and the base address is 0x0000.0000. the base address is aligned to the size of the region. for example, a 64-kb region must be aligned on a multiple of 64 kb, for example, at 0x0001.0000 or 0x0002.0000. mpu region base address (mpubase) base 0xe000.e000 offset 0xd9c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 region reserved valid addr r/w r/w r/w ro wo r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field base address mask bits 31: n in this field contain the region base address. the value of n depends on the region size, as shown above. the remaining bits ( n-1):5 are reserved. software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 r/w addr 31:5 march 20, 2011 164 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field region number valid description value the mpunumber register is not changed and the processor updates the base address for the region specified in the mpunumber register and ignores the value of the region field. 0 the mpunumber register is updated with the value of the region field and the base address is updated for the region specified in the region field. 1 this bit is always read as 0. 0 wo valid 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 region number on a write, contains the value to be written to the mpunumber register. on a read, returns the current region number in the mpunumber register. 0x0 r/w region 2:0 165 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 51: mpu region attribute and size (mpuattr), offset 0xda0 register 52: mpu region attribute and size alias 1 (mpuattr1), offset 0xda8 register 53: mpu region attribute and size alias 2 (mpuattr2), offset 0xdb0 register 54: mpu region attribute and size alias 3 (mpuattr3), offset 0xdb8 note: this register can only be accessed from privileged mode. the mpuattr register defines the region size and memory attributes of the mpu region specified by the mpu region number (mpunumber) register and enables that region and any subregions. the mpuattr register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. the mpu access permission attribute bits, xn, ap, tex, s, c , and b , control access to the corresponding memory region. if an access is made to an area of memory without the required permissions, then the mpu generates a permission fault. the size field defines the size of the mpu memory region specified by the mpunumber register as follows: (region size in bytes) = 2 (size+1) the smallest permitted region size is 32 bytes, corresponding to a size value of 4. table 3-9 on page 166 gives example size values with the corresponding region size and value of n in the mpu region base address (mpubase) register. table 3-9. example size field values note value of n a region size size encoding minimum permitted size 5 32 b 00100b (0x4) - 10 1 kb 01001b (0x9) - 20 1 mb 10011b (0x13) - 30 1 gb 11101b (0x1d) maximum possible size no valid addr field in mpubase ; the region occupies the complete memory map. 4 gb 11111b (0x1f) a. refers to the n parameter in the mpubase register (see page 164). mpu region attribute and size (mpuattr) base 0xe000.e000 offset 0xda0 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 b c s tex reserved ap reserved xn reserved r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable size reserved srd r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset march 20, 2011 166 texas instruments-advance information cortex-m3 peripherals description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:29 instruction access disable description value instruction fetches are enabled. 0 instruction fetches are disabled. 1 0 r/w xn 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27 access privilege for information on using this bit field, see table 3-5 on page 110. 0 r/w ap 26:24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 23:22 type extension mask for information on using this bit field, see table 3-3 on page 109. 0x0 r/w tex 21:19 shareable for information on using this bit, see table 3-3 on page 109. 0 r/w s 18 cacheable for information on using this bit, see table 3-3 on page 109. 0 r/w c 17 bufferable for information on using this bit, see table 3-3 on page 109. 0 r/w b 16 subregion disable bits description value the corresponding subregion is enabled. 0 the corresponding subregion is disabled. 1 region sizes of 128 bytes and less do not support subregions. when writing the attributes for such a region, configure the srd field as 0x00. see the section called subregions on page 108 for more information. 0x00 r/w srd 15:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 region size mask the size field defines the size of the mpu memory region specified by the mpunumber register. refer to table 3-9 on page 166 for more information. 0x0 r/w size 5:1 167 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field region enable description value the region is disabled. 0 the region is enabled. 1 0 r/w enable 0 march 20, 2011 168 texas instruments-advance information cortex-m3 peripherals 4 jtag interface the joint test action group (jtag) port is an ieee standard that defines a test access port and boundary scan architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. the tap, instruction register (ir), and data registers (dr) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. the jtag port also provides a means of accessing and controlling design-for-test features such as i/o pin observation and control, scan testing, and debugging. the jtag port is comprised of four pins: tck, tms, tdi , and tdo . data is transmitted serially into the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of the tap controller. for detailed information on the operation of the jtag port and tap controller, please refer to the ieee standard 1149.1-test access port and boundary-scan architecture . the stellaris ? jtag controller works with the arm jtag controller built into the cortex-m3 core by multiplexing the tdo outputs from both jtag controllers. arm jtag instructions select the arm tdo output while stellaris jtag instructions select the stellaris tdo output. the multiplexer is controlled by the stellaris jtag controller, which has comprehensive programming for the arm, stellaris, and unimplemented jtag instructions. the stellaris jtag module has the following features: ieee 1149.1-1990 compatible test access port (tap) controller four-bit instruction register (ir) chain for storing jtag instructions ieee standard instructions: bypass, idcode, sample/preload, extest and intest arm additional instructions: apacc, dpacc and abort integrated arm serial wire debug (swd) C serial wire jtag debug port (swj-dp) C flash patch and breakpoint (fpb) unit for implementing breakpoints C data watchpoint and trace (dwt) unit for implementing watchpoints, trigger resources, and system profiling C instrumentation trace macrocell (itm) for support of printf style debugging C trace port interface unit (tpiu) for bridging to a trace port analyzer see the arm? debug interface v5 architecture specification for more information on the arm jtag controller. 169 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 4.1 block diagram figure 4-1. jtag module block diagram 4.2 signal description table 4-1 on page 170 and table 4-2 on page 171 list the external signals of the jtag/swd controller and describe the function of each. the jtag/swd controller signals are alternate functions for some gpio signals, however note that the reset state of the pins is for the jtag/swd function. the jtag/swd controller signals are under commit protection and require a special process to be configured as gpios, see commit control on page 412. the column in the table below titled "pin mux/pin assignment" lists the gpio pin placement for the jtag/swd controller signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) is set to choose the jtag/swd function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the jtag/swd controller signals to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. table 4-1. signals for jtag_swd_swo (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name jtag/swd clk. ttl i pc0 (3) 80 swclk jtag tms and swdio. ttl i/o pc1 (3) 79 swdio jtag tdo and swo. ttl o pc3 (3) 77 swo jtag/swd clk. ttl i pc0 (3) 80 tck jtag tdi. ttl i pc2 (3) 78 tdi jtag tdo and swo. ttl o pc3 (3) 77 tdo march 20, 2011 170 texas instruments-advance information jtag interface , q v w u x f w l r q 5 h j l v w h u , 5 7 $ 3 & r q w u r o o h u % < 3 $ 6 6 ' d w d 5 h j l v w h u % r x q g d u \ 6 f d q ' d w d 5 h j l v w h u , ' & 2 ' ( ' d w d 5 h j l v w h u $ % 2 5 7 ' d w d 5 h j l v w h u ' 3 $ & & ' d w d 5 h j l v w h u $ 3 $ & & ' d w d 5 h j l v w h u 7 & . 7 0 6 7 ' , 7 ' 2 & r u w h [ 0 ' h e x j 3 r u w table 4-1. signals for jtag_swd_swo (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name jtag tms and swdio. ttl i pc1 (3) 79 tms a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 4-2. signals for jtag_swd_swo (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name jtag/swd clk. ttl i pc0 (3) a9 swclk jtag tms and swdio. ttl i/o pc1 (3) b9 swdio jtag tdo and swo. ttl o pc3 (3) a10 swo jtag/swd clk. ttl i pc0 (3) a9 tck jtag tdi. ttl i pc2 (3) b8 tdi jtag tdo and swo. ttl o pc3 (3) a10 tdo jtag tms and swdio. ttl i pc1 (3) b9 tms a. the ttl designation indicates the pin has ttl-compatible voltage levels. 4.3 functional description a high-level conceptual drawing of the jtag module is shown in figure 4-1 on page 170. the jtag module is composed of the test access port (tap) controller and serial shift chains with parallel update registers. the tap controller is a simple state machine controlled by the tck and tms inputs. the current state of the tap controller depends on the sequence of values captured on tms at the rising edge of tck . the tap controller determines when the serial shift chains capture new data, shift data from tdi towards tdo , and update the parallel load registers. the current state of the tap controller also determines whether the instruction register (ir) chain or one of the data register (dr) chains is being accessed. the serial shift chains with parallel load registers are comprised of a single instruction register (ir) chain and multiple data register (dr) chains. the current instruction loaded in the parallel load register determines which dr chain is captured, shifted, or updated during the sequencing of the tap controller. some instructions, like extest and intest, operate on data currently in a dr chain and do not capture, shift, or update any of the chains. instructions that are not implemented decode to the bypass instruction to ensure that the serial path between tdi and tdo is always connected (see table 4-4 on page 177 for a list of implemented instructions). see jtag and boundary scan on page 975 for jtag timing diagrams. note: of all the possible reset sources, only power-on reset (por) and the assertion of the rst input have any effect on the jtag module. the pin configurations are reset by both the rst input and por, whereas the internal jtag logic is only reset with por. see reset sources on page 182 for more information on reset. 4.3.1 jtag interface pins the jtag interface consists of four standard pins: tck, tms, tdi , and tdo . these pins and their associated state after a power-on reset or reset caused by the rst input are given in table 4-3. detailed information on each pin follows. refer to general-purpose input/outputs (gpios) on page 404 for information on how to reprogram the configuration of these pins. 171 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 4-3. jtag port pins state after power-on reset or rst assertion drive value drive strength internal pull-down internal pull-up data direction pin name n/a n/a disabled enabled input tck n/a n/a disabled enabled input tms n/a n/a disabled enabled input tdi high-z 2-ma driver disabled enabled output tdo 4.3.1.1 test clock input (tck) the tck pin is the clock for the jtag module. this clock is provided so the test logic can operate independently of any other system clocks and to ensure that multiple jtag tap controllers that are daisy-chained together can synchronously communicate serial test data between components. during normal operation, tck is driven by a free-running clock with a nominal 50% duty cycle. when necessary, tck can be stopped at 0 or 1 for extended periods of time. while tck is stopped at 0 or 1, the state of the tap controller does not change and data in the jtag instruction and data registers is not lost. by default, the internal pull-up resistor on the tck pin is enabled after reset, assuring that no clocking occurs if the pin is not driven from an external source. the internal pull-up and pull-down resistors can be turned off to save internal power as long as the tck pin is constantly being driven by an external source (see page 434 and page 436). 4.3.1.2 test mode select (tms) the tms pin selects the next state of the jtag tap controller. tms is sampled on the rising edge of tck . depending on the current tap state and the sampled value of tms , the next state may be entered. because the tms pin is sampled on the rising edge of tck , the ieee standard 1149.1 expects the value on tms to change on the falling edge of tck. holding tms high for five consecutive tck cycles drives the tap controller state machine to the test-logic-reset state. when the tap controller enters the test-logic-reset state, the jtag module and associated registers are reset to their default values. this procedure should be performed to initialize the jtag controller. the jtag test access port state machine can be seen in its entirety in figure 4-2 on page 173. by default, the internal pull-up resistor on the tms pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc1/tms ; otherwise jtag communication could be lost (see page 434). 4.3.1.3 test data input (tdi) the tdi pin provides a stream of serial information to the ir chain and the dr chains. tdi is sampled on the rising edge of tck and, depending on the current tap state and the current instruction, may present this data to the proper shift register chain. because the tdi pin is sampled on the rising edge of tck , the ieee standard 1149.1 expects the value on tdi to change on the falling edge of tck. by default, the internal pull-up resistor on the tdi pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc2/tdi ; otherwise jtag communication could be lost (see page 434). 4.3.1.4 test data output (tdo) the tdo pin provides an output stream of serial information from the ir chain or the dr chains. the value of tdo depends on the current tap state, the current instruction, and the data in the march 20, 2011 172 texas instruments-advance information jtag interface chain being accessed. in order to save power when the jtag port is not being used, the tdo pin is placed in an inactive drive state when not actively shifting out data. because tdo can be connected to the tdi of another controller in a daisy-chain configuration, the ieee standard 1149.1 expects the value on tdo to change on the falling edge of tck. by default, the internal pull-up resistor on the tdo pin is enabled after reset, assuring that the pin remains at a constant logic level when the jtag port is not being used. the internal pull-up and pull-down resistors can be turned off to save internal power if a high-z output value is acceptable during certain tap controller states (see page 434 and page 436). 4.3.2 jtag tap controller the jtag tap controller state machine is shown in figure 4-2. the tap controller state machine is reset to the test-logic-reset state on the assertion of a power-on-reset (por). in order to reset the jtag module after the microcontroller has been powered on, the tms input must be held high for five tck clock cycles, resetting the tap controller and all associated jtag chains. asserting the correct sequence on the tms pin allows the jtag module to shift in new instructions, shift in data, or idle during extended testing sequences. for detailed information on the function of the tap controller and the operations that occur in each state, please refer to ieee standard 1149.1 . figure 4-2. test access port state machine 4.3.3 shift registers the shift registers consist of a serial shift register chain and a parallel load register. the serial shift register chain samples specific information during the tap controllers capture states and allows 173 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 7 h v w / r j l f 5 h v h w 5 x q 7 h v w , g o h 6 h o h f w ' 5 6 f d q 6 h o h f w , 5 6 f d q & d s w x u h ' 5 & d s w x u h , 5 6 k l i w ' 5 6 k l i w , 5 ( [ l w ' 5 ( [ l w , 5 ( [ l w ' 5 ( [ l w , 5 3 d x v h ' 5 3 d x v h , 5 8 s g d w h ' 5 8 s g d w h , 5 this information to be shifted out on tdo during the tap controllers shift states. while the sampled data is being shifted out of the chain on tdo , new data is being shifted into the serial shift register on tdi . this new data is stored in the parallel load register during the tap controllers update states. each of the shift registers is discussed in detail in register descriptions on page 177. 4.3.4 operational considerations certain operational parameters must be considered when using the jtag module. because the jtag pins can be programmed to be gpios, board configuration and reset conditions on these pins must be considered. in addition, because the jtag module has integrated arm serial wire debug, the method for switching between these two operational modes is described below. 4.3.4.1 gpio functionality when the microcontroller is reset with either a por or rst , the jtag/swd port pins default to their jtag/swd configurations. the default configuration includes enabling digital functionality ( den[3:0] set in the port c gpio digital enable (gpioden) register), enabling the pull-up resistors ( pue[3:0] set in the port c gpio pull-up select (gpiopur) register), disabling the pull-down resistors (pde[3:0] cleared in the port c gpio pull-down select (gpiopdr) register) and enabling the alternate hardware function ( afsel[3:0] set in the port c gpio alternate function select (gpioafsel) register) on the jtag/swd pins. see page 428, page 434, page 436, and page 439. it is possible for software to configure these pins as gpios after reset by clearing afsel[3:0] in the port c gpioafsel register. if the user does not require the jtag/swd port for debugging or board-level testing, this provides four more gpios for use in the design. caution C it is possible to create a software sequence that prevents the debugger from connecting to the stellaris microcontroller. if the program code loaded into fash immediately changes the jtag pins to their gpio functionality, the debugger may not have enough time to connect and halt the controller before the jtag pin functionality switches. as a result, the debugger may be locked out of the part. this issue can be avoided with a software routine that restores jtag functionality based on an external or software trigger. the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7 ) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 428), gpio pull up select (gpiopur) register (see page 434), gpio pull-down select (gpiopdr) register (see page 436), and gpio digital enable (gpioden) register (see page 439) are not committed to storage unless the gpio lock (gpiolock) register (see page 441) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 442) have been set. 4.3.4.2 communication with jtag/swd because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the jtag/swd interface. in the capture-dr state, the result of the previous transaction, if any, is returned, together with a 3-bit ack response. software should check the ack response to see if the previous operation has completed before initiating a new transaction. alternatively, if the system clock is at least 8 times faster than the debug clock (tck or swclk ), the previous operation has enough time to complete and the ack bits do not have to be checked. march 20, 2011 174 texas instruments-advance information jtag interface 4.3.4.3 recovering a "locked" microcontroller note: performing the sequence below restores the nonvolatile registers discussed in nonvolatile register programming on page 317 to their factory default values. the mass erase of the flash memory caused by the sequence below occurs prior to the nonvolatile registers being restored. if software configures any of the jtag/swd pins as gpio and loses the ability to communicate with the debugger, there is a debug port unlock sequence that can be used to recover the microcontroller. performing a total of ten jtag-to-swd and swd-to-jtag switch sequences while holding the microcontroller in reset mass erases the flash memory. the debug port unlock sequence is: 1. assert and hold the rst signal. 2. perform steps 1 and 2 of the jtag-to-swd switch sequence on the section called jtag-to-swd switching on page 176. 3. perform steps 1 and 2 of the swd-to-jtag switch sequence on the section called swd-to-jtag switching on page 176. 4. perform steps 1 and 2 of the jtag-to-swd switch sequence. 5. perform steps 1 and 2 of the swd-to-jtag switch sequence. 6. perform steps 1 and 2 of the jtag-to-swd switch sequence. 7. perform steps 1 and 2 of the swd-to-jtag switch sequence. 8. perform steps 1 and 2 of the jtag-to-swd switch sequence. 9. perform steps 1 and 2 of the swd-to-jtag switch sequence. 10. perform steps 1 and 2 of the jtag-to-swd switch sequence. 11. perform steps 1 and 2 of the swd-to-jtag switch sequence. 12. release the rst signal. 13. wait 400 ms. 14. power-cycle the microcontroller. 4.3.4.4 arm serial wire debug (swd) in order to seamlessly integrate the arm serial wire debug (swd) functionality, a serial-wire debugger must be able to connect to the cortex-m3 core without having to perform, or have any knowledge of, jtag cycles. this integration is accomplished with a swd preamble that is issued before the swd session begins. the switching preamble used to enable the swd interface of the swj-dp module starts with the tap controller in the test-logic-reset state. from here, the preamble sequences the tap controller through the following states: run test idle, select dr, select ir, test logic reset, test logic reset, run test idle, run test idle, select dr, select ir, test logic reset, test logic reset, run test idle, run test idle, select dr, select ir, and test logic reset states. 175 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller stepping through this sequence of the tap state machine enables the swd interface and disables the jtag interface. for more information on this operation and the swd interface, see the arm? debug interface v5 architecture specification . because this sequence is a valid series of jtag operations that could be issued, the arm jtag tap controller is not fully compliant to the ieee standard 1149.1 . this instance is the only one where the arm jtag tap controller does not meet full compliance with the specification. due to the low probability of this sequence occurring during normal operation of the tap controller, it should not affect normal performance of the jtag interface. jtag-to-swd switching to switch the operating mode of the debug access port (dap) from jtag to swd mode, the external debug hardware must send the switching preamble to the microcontroller. the 16-bit tms command for switching to swd mode is defined as b1110.0111.1001.1110, transmitted lsb first. this command can also be represented as 0xe79e when transmitted lsb first. the complete switch sequence should consist of the following transactions on the tck/ swclk and tms/ swdio signals: 1. send at least 50 tck/ swclk cycles with tms/ swdio high to ensure that both jtag and swd are in their reset/idle states. 2. send the 16-bit jtag-to-swd switch command, 0xe79e, on tms. 3. send at least 50 tck/ swclk cycles with tms/ swdio high to ensure that if swj-dp was already in swd mode, the swd goes into the line reset state before sending the switch sequence. swd-to-jtag switching to switch the operating mode of the debug access port (dap) from swd to jtag mode, the external debug hardware must send a switch command to the microcontroller. the 16-bit tms command for switching to jtag mode is defined as b1110.0111.0011.1100, transmitted lsb first. this command can also be represented as 0xe73c when transmitted lsb first. the complete switch sequence should consist of the following transactions on the tck/ swclk and tms/ swdio signals: 1. send at least 50 tck/ swclk cycles with tms/ swdio high to ensure that both jtag and swd are in their reset/idle states. 2. send the 16-bit swd-to-jtag switch command, 0xe73c, on tms. 3. send at least 50 tck/ swclk cycles with tms/ swdio high to ensure that if swj-dp was already in jtag mode, the jtag goes into the test logic reset state before sending the switch sequence. 4.4 initialization and configuration after a power-on-reset or an external reset ( rst ), the jtag pins are automatically configured for jtag communication. no user-defined initialization or configuration is needed. however, if the user application changes these pins to their gpio function, they must be configured back to their jtag functionality before jtag communication can be restored. to return the pins to their jtag functions, enable the four jtag pins ( pc[3:0] ) for their alternate function using the gpioafsel register. in addition to enabling the alternate functions, any other changes to the gpio pad configurations on the four jtag pins ( pc[3:0] ) should be returned to their default settings. march 20, 2011 176 texas instruments-advance information jtag interface 4.5 register descriptions the registers in the jtag tap controller or shift register chains are not memory mapped and are not accessible through the on-chip advanced peripheral bus (apb). instead, the registers within the jtag controller are all accessed serially through the tap controller. these registers include the instruction register and the six data registers. 4.5.1 instruction register (ir) the jtag tap instruction register (ir) is a four-bit serial scan chain connected between the jtag tdi and tdo pins with a parallel load register. when the tap controller is placed in the correct states, bits can be shifted into the ir. once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. the decode of the ir bits is shown in table 4-4. a detailed explanation of each instruction, along with its associated data register, follows. table 4-4. jtag instruction register commands description instruction ir[3:0] drives the values preloaded into the boundary scan chain by the sample/preload instruction onto the pads. extest 0x0 drives the values preloaded into the boundary scan chain by the sample/preload instruction into the controller. intest 0x1 captures the current i/o values and shifts the sampled values out of the boundary scan chain while new preload data is shifted in. sample / preload 0x2 shifts data into the arm debug port abort register. abort 0x8 shifts data into and out of the arm dp access register. dpacc 0xa shifts data into and out of the arm ac access register. apacc 0xb loads manufacturing information defined by the ieee standard 1149.1 into the idcode chain and shifts it out. idcode 0xe connects tdi to tdo through a single shift register chain. bypass 0xf defaults to the bypass instruction to ensure that tdi is always connected to tdo. reserved all others 4.5.1.1 extest instruction the extest instruction is not associated with its own data register chain. instead, the extest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instruction. when the extest instruction is present in the instruction register, the preloaded data in the boundary scan data register associated with the outputs and output enables are used to drive the gpio pads rather than the signals coming from the core. with tests that drive known values out of the controller, this instruction can be used to verify connectivity. while the extest instruction is present in the instruction register, the boundary scan data register can be accessed to sample and shift out the current data and load new data into the boundary scan data register. 4.5.1.2 intest instruction the intest instruction is not associated with its own data register chain. instead, the intest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instruction. when the intest instruction is present in the instruction register, the preloaded data in the boundary scan data register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the gpio pads. with tests that drive known values into the controller, this instruction can be used for testing. it is important to note that although the rst input pin is on the boundary scan data register chain, it is only observable. 177 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller while the intest instruction is present in the instruction register, the boundary scan data register can be accessed to sample and shift out the current data and load new data into the boundary scan data register. 4.5.1.3 sample/preload instruction the sample/preload instruction connects the boundary scan data register chain between tdi and tdo . this instruction samples the current state of the pad pins for observation and preloads new test data. each gpio pad has an associated input, output, and output enable signal. when the tap controller enters the capture dr state during this instruction, the input, output, and output-enable signals to each of the gpio pads are captured. these samples are serially shifted out on tdo while the tap controller is in the shift dr state and can be used for observation or comparison in various tests. while these samples of the inputs, outputs, and output enables are being shifted out of the boundary scan data register, new data is being shifted into the boundary scan data register from tdi. once the new data has been shifted into the boundary scan data register, the data is saved in the parallel load registers when the tap controller enters the update dr state. this update of the parallel load register preloads data into the boundary scan data register that is associated with each input, output, and output enable. this preloaded data can be used with the extest and intest instructions to drive data into or out of the controller. see boundary scan data register on page 179 for more information. 4.5.1.4 abort instruction the abort instruction connects the associated abort data register chain between tdi and tdo . this instruction provides read and write access to the abort register of the arm debug access port (dap). shifting the proper data into this data register clears various error bits or initiates a dap abort of a previous request. see the abort data register on page 180 for more information. 4.5.1.5 dpacc instruction the dpacc instruction connects the associated dpacc data register chain between tdi and tdo . this instruction provides read and write access to the dpacc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to the arm debug and status registers. see dpacc data register on page 180 for more information. 4.5.1.6 apacc instruction the apacc instruction connects the associated apacc data register chain between tdi and tdo . this instruction provides read and write access to the apacc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the debug port. see apacc data register on page 180 for more information. 4.5.1.7 idcode instruction the idcode instruction connects the associated idcode data register chain between tdi and tdo . this instruction provides information on the manufacturer, part number, and version of the arm core. this information can be used by testing equipment and debuggers to automatically configure input and output data streams. idcode is the default instruction loaded into the jtag instruction register when a power-on-reset (por) is asserted, or the test-logic-reset state is entered. see idcode data register on page 179 for more information. march 20, 2011 178 texas instruments-advance information jtag interface 4.5.1.8 bypass instruction the bypass instruction connects the associated bypass data register chain between tdi and tdo . this instruction is used to create a minimum length serial path between the tdi and tdo ports. the bypass data register is a single-bit shift register. this instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the jtag scan chain by loading them with the bypass instruction. see bypass data register on page 179 for more information. 4.5.2 data registers the jtag module contains six data registers. these serial data register chains include: idcode, bypass, boundary scan, apacc, dpacc, and abort and are discussed in the following sections. 4.5.2.1 idcode data register the format for the 32-bit idcode data register defined by the ieee standard 1149.1 is shown in figure 4-3. the standard requires that every jtag-compliant microcontroller implement either the idcode instruction or the bypass instruction as the default instruction. the lsb of the idcode data register is defined to be a 1 to distinguish it from the bypass instruction, which has an lsb of 0. this definition allows auto-configuration test tools to determine which instruction is the default instruction. the major uses of the jtag port are for manufacturer testing of component assembly and program development and debug. to facilitate the use of auto-configuration debug tools, the idcode instruction outputs a value of 0x4ba0.0477. this value allows the debuggers to automatically configure themselves to work correctly with the cortex-m3 during debug. figure 4-3. idcode register format 4.5.2.2 bypass data register the format for the 1-bit bypass data register defined by the ieee standard 1149.1 is shown in figure 4-4. the standard requires that every jtag-compliant microcontroller implement either the bypass instruction or the idcode instruction as the default instruction. the lsb of the bypass data register is defined to be a 0 to distinguish it from the idcode instruction, which has an lsb of 1. this definition allows auto-configuration test tools to determine which instruction is the default instruction. figure 4-4. bypass register format 4.5.2.3 boundary scan data register the format of the boundary scan data register is shown in figure 4-5. each gpio pin, starting with a gpio pin next to the jtag port pins, is included in the boundary scan data register. each 179 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 7 ' 2 7 ' , 9 h u v l r q 3 d u w 1 x p e h u 0 d q x i d f w x u h u , ' 7 ' 2 7 ' , gpio pin has three associated digital signals that are included in the chain. these signals are input, output, and output enable, and are arranged in that order as shown in the figure. when the boundary scan data register is accessed with the sample/preload instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. the sampling of these values occurs on the rising edge of tck in the capture dr state of the tap controller. while the sampled data is being shifted out of the boundary scan chain in the shift dr state of the tap controller, new data can be preloaded into the chain for use with the extest and intest instructions. the extest instruction forces data out of the controller, and the intest instruction forces data into the controller. figure 4-5. boundary scan register format 4.5.2.4 apacc data register the format for the 35-bit apacc data register defined by arm is described in the arm? debug interface v5 architecture specification . 4.5.2.5 dpacc data register the format for the 35-bit dpacc data register defined by arm is described in the arm? debug interface v5 architecture specification . 4.5.2.6 abort data register the format for the 35-bit abort data register defined by arm is described in the arm? debug interface v5 architecture specification . march 20, 2011 180 texas instruments-advance information jtag interface , 1 7 ' , v w * 3 , 2 7 ' 2 2 8 7 2 ( , 1 p w k * 3 , 2 2 8 7 2 ( , 1 p w k * 3 , 2 2 8 7 2 ( , 1 * 3 , 2 q w k 2 8 7 2 ( 5 system control system control configures the overall operation of the device and provides information about the device. configurable features include reset control, nmi operation, power control, clock control, and low-power modes. 5.1 signal description table 5-1 on page 181 and table 5-2 on page 181 list the external signals of the system control module and describe the function of each. the nmi signal is the alternate function for the gpio pb7 signal and functions as a gpio after reset. pb7 is under commit protection and requires a special process to be configured as any alternate function or to subsequently return to the gpio function, see commit control on page 412. the column in the table below titled "pin mux/pin assignment" lists the gpio pin placement for the nmi signal. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the nmi function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the nmi signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. the remaining signals (with the word "fixed" in the pin mux/pin assignment column) have a fixed pin assignment and function. table 5-1. signals for system control & clocks (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name non-maskable interrupt. ttl i pb7 (4) 89 nmi main oscillator crystal input or an external clock reference input. analog i fixed 48 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed 49 osc1 system reset input. ttl i fixed 64 rst a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 5-2. signals for system control & clocks (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name non-maskable interrupt. ttl i pb7 (4) a8 nmi main oscillator crystal input or an external clock reference input. analog i fixed l11 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed m11 osc1 system reset input. ttl i fixed h11 rst a. the ttl designation indicates the pin has ttl-compatible voltage levels. 5.2 functional description the system control module provides the following capabilities: device identification, see device identification on page 182 181 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller local control, such as reset (see reset control on page 182), power (see power control on page 187) and clock control (see clock control on page 188) system control (run, sleep, and deep-sleep modes), see system control on page 195 5.2.1 device identification several read-only registers provide software with information on the microcontroller, such as version, part number, sram size, flash memory size, and other features. see the did0 (page 200), did1 (page 229), dc0-dc9 (page 231) and nvmstat (page 251) registers. 5.2.2 reset control this section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 reset sources the lm3s1p51 microcontroller has six sources of reset: 1. power-on reset (por) (see page 183). 2. external reset input pin ( rst ) assertion (see page 184). 3. internal brown-out (bor) detector (see page 185). 4. software-initiated reset (with the software reset registers) (see page 186). 5. a watchdog timer reset condition violation (see page 186). 6. mosc failure (see page 187). table 5-3 provides a summary of results of the various reset operations. table 5-3. reset sources on-chip peripherals reset? a jtag reset? core reset? reset source yes yes yes power-on reset yes yes yes rst yes yes yes brown-out reset yes yes yes software system request reset using the sysresreq bit in the apint register. no yes yes software system request reset using the vectreset bit in the apint register. yes b yes no software peripheral reset yes yes yes watchdog reset yes yes yes mosc failure reset a. refer to register reset on page 291 for information on how reset affects the hibernation module. b. programmable on a module-by-module basis using the software reset control registers. after a reset, the reset cause (resc) register is set with the reset cause. the bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal por march 20, 2011 182 texas instruments-advance information system control is the cause, in which case, all the bits in the resc register are cleared except for the por indicator. a bit in the resc register can be cleared by writing a 0. at any reset that resets the core, the user has the opportunity to direct the core to execute the rom boot loader or the application in flash memory by using any gpio signal as configured in the boot configuration (bootcfg) register. at reset, the rom is mapped over the flash memory so that the rom boot sequence is always executed. the boot sequence executed from rom is as follows: 1. the ba bit (below) is cleared such that rom is mapped to 0x01xx.xxxx and flash memory is mapped to address 0x0. 2. the bootcfg register is read. if the en bit is clear, the status of the specified gpio pin is compared with the specified polarity. if the status matches the specified polarity, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 3. if the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xffff.ffff, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 4. if there is valid data at address 0x0000.0004, the stack pointer ( sp ) is loaded from flash memory at address 0x0000.0000 and the program counter ( pc ) is loaded from address 0x0000.0004. the user application begins executing. for example, if the bootcfg register is written and committed with the value of 0x0000.3c01, then pb7 is examined at reset to determine if the rom boot loader should be executed. if pb7 is low, the core unconditionally begins executing the rom boot loader. if pb7 is high, then the application in flash memory is executed if the reset vector at location 0x0000.0004 is not 0xffff.ffff. otherwise, the rom boot loader is executed. 5.2.2.2 power-on reset (por) note: the jtag controller can only be reset by the power-on reset and the brown-out reset. the internal power-on reset (por) circuit monitors the power supply voltage (v dd ) and generates a reset signal to all of the internal logic including jtag when the power supply ramp reaches a threshold value (v th ). the microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete (see power and brown-out characteristics on page 973). for applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal por, the rst input may be used as discussed in external rst pin on page 184. the power-on reset sequence is as follows: 1. the microcontroller waits for internal por to go inactive. 2. the internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the internal por is only active on the initial power-up of the microcontroller and when the microcontroller wakes from hibernation. the power-on reset timing is shown in figure 23-4 on page 973. 183 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 5.2.2.3 external rst pin note: it is recommended that the trace for the rst signal must be kept as short as possible. be sure to place any components connected to the rst signal as close to the microcontroller as possible. if the application only uses the internal por circuit, the rst input must be connected to the power supply (v dd ) through an optional pull-up resistor (0 to 100k ?) as shown in figure 5-1 on page 184. figure 5-1. basic rst configuration r pu = 0 to 100 k the external reset pin ( rst ) resets the microcontroller including the core and all the on-chip peripherals except the jtag tap controller (see jtag interface on page 169). the external reset sequence is as follows: 1. the external reset pin ( rst ) is asserted for the duration specified by t min and then de-asserted (see reset on page 976). 2. the internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. to improve noise immunity and/or to delay reset at power up, the rst input may be connected to an rc network as shown in figure 5-2 on page 184. figure 5-2. external circuitry to extend power-on reset r pu = 1 k to 100 k c 1 = 1 nf to 10 f if the application requires the use of an external reset switch, figure 5-3 on page 185 shows the proper circuitry to use. march 20, 2011 184 texas instruments-advance information system control 3 8 & 5 6 7 6 w h o o d u l v ? 5 9 ' ' 3 8 5 6 7 6 w h o o d u l v ? 5 9 ' ' figure 5-3. reset circuit controlled by switch typical r pu = 10 k typical r s = 470 c 1 = 10 nf the r pu and c 1 components define the power-on delay. the external reset timing is shown in figure 23-10 on page 977. 5.2.2.4 brown-out reset (bor) note: the jtag controller can only be reset by the power-on reset and the brown-out reset. the microcontroller provides a brown-out detection circuit that triggers if the power supply (v dd ) drops below a brown-out threshold voltage (v bth ). if a brown-out condition is detected, the system may generate an interrupt or a system reset. the default condition is to generate an interrupt, so bor must be enabled. brown-out resets are controlled with the power-on and brown-out reset control (pborctl) register. the borior bit in the pborctl register must be set for a brown-out condition to trigger a reset; if borior is clear, an interrupt is generated. when a brown-out condition occurs during a flash program or erase operation, a full system reset is always triggered without regard to the setting in the pborctl register. the brown-out reset sequence is as follows: 1. when v dd drops below v bth , an internal bor condition is set. 2. if the bor condition exists, an internal reset is asserted. 3. the internal reset is released and the microcontroller fetches and loads the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. 4. the internal bor condition is reset after 500 s to prevent another bor condition from being set before software has a chance to investigate the original cause. the result of a brown-out reset is equivalent to that of an assertion of the external rst input, and the reset is held active until the proper v dd level is restored. the resc register can be examined in the reset interrupt handler to determine if a brown-out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. the internal brown-out reset timing is shown in figure 23-5 on page 974. 185 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 3 8 & 5 6 5 6 7 6 w h o o d u l v ? 5 9 ' ' 5.2.2.5 software reset software can reset a specific peripheral or generate a reset to the entire microcontroller. peripherals can be individually reset by software via three registers that control reset signals to each on-chip peripheral (see the srcrn registers, page 275). if the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. the encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see system control on page 195). the entire microcontroller, including the core, can be reset by software by setting the sysresreq bit in the application interrupt and reset control (apint) register. the software-initiated system reset sequence is as follows: 1. a software microcontroller reset is initiated by setting the sysresreq bit. 2. an internal reset is asserted. 3. the internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the core only can be reset by software by setting the vectreset bit in the apint register. the software-initiated core reset sequence is as follows: 1. a core reset is initiated by setting the vectreset bit. 2. an internal reset is asserted. 3. the internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the software-initiated system reset timing is shown in figure 23-11 on page 977. 5.2.2.6 watchdog timer reset the watchdog timer module's function is to prevent system hangs. the lm3s1p51 microcontroller has two watchdog timer modules in case one watchdog clock source fails. one watchdog is run off the system clock and the other is run off the precision internal oscillator (piosc). each module operates in the same manner except that because the piosc watchdog timer module is in a different clock domain, register accesses must have a time delay between them. the watchdog timer can be configured to generate an interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out. after the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of the watchdog timer load (wdtload) register and resumes counting down from that value. if the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the microcontroller. the watchdog timer reset sequence is as follows: 1. the watchdog timer times out for the second time without being serviced. 2. an internal reset is asserted. march 20, 2011 186 texas instruments-advance information system control 3. the internal reset is released and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. for more information on the watchdog timer module, see watchdog timers on page 506. the watchdog reset timing is shown in figure 23-12 on page 977. 5.2.3 non-maskable interrupt the microcontroller has three sources of non-maskable interrupt (nmi): the assertion of the nmi signal a main oscillator verification error the nmiset bit in the interrupt control and state (intctrl) register in the cortex ? -m3 (see page 134). software must check the cause of the interrupt in order to distinguish among the sources. 5.2.3.1 nmi pin the nmi signal is the alternate function for gpio port pin pb7 . the alternate function must be enabled in the gpio for the signal to be used as an interrupt, as described in general-purpose input/outputs (gpios) on page 404. note that enabling the nmi alternate function requires the use of the gpio lock and commit function just like the gpio port pins associated with jtag/swd functionality, see page 442. the active sense of the nmi signal is high; asserting the enabled nmi signal above v ih initiates the nmi interrupt sequence. 5.2.3.2 main oscillator verification failure the lm3s1p51 microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. if the main oscillator verification circuit is enabled and a failure occurs, a power-on reset is generated and control is transferred to the nmi handler. the nmi handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. the detection circuit is enabled by setting the cval bit in the main oscillator control (moscctl) register. the main oscillator verification error is indicated in the main oscillator fail status ( moscfail) bit in the reset cause (resc) register. the main oscillator verification circuit action is described in more detail in main oscillator verification circuit on page 195. 5.2.4 power control the stellaris microcontroller provides an integrated ldo regulator that is used to provide power to the majority of the microcontroller's internal logic. figure 5-4 shows the power architecture. an external regulator may be used instead of the on-chip ldo, but must meet the requirements in table 23-22 on page 973. regardless of the ldo implementation, the internal ldo requires decoupling capacitors as specified in on-chip low drop-out (ldo) regulator characteristics on page 965. note: vdda must be supplied with 3.3 v, or the microcontroller does not function properly. vdda is the supply for all of the analog circuitry on the device, including the clock circuitry. 187 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 5-4. power architecture 5.2.5 clock control system control determines the control of clocks in this part. 5.2.5.1 fundamental clock sources there are multiple clock sources for use in the microcontroller: precision internal oscillator (piosc). the precision internal oscillator is an on-chip clock source that is the clock source the microcontroller uses during and following por. it does not require the use of any external components and provides a clock that is 16 mhz 1% at room temperature and 3% across temperature. the piosc allows for a reduced system cost in applications that require an accurate clock source. if the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. if the hibernation module clock source is a 32.768-khz oscillator, the precision internal oscillator can be trimmed by software based on a reference clock for increased accuracy. main oscillator (mosc). the main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the osc0 input pin, or an external crystal is connected across the osc0 input and osc1 output pins. if the pll is being used, the crystal value must be one of the supported frequencies between 3.579545 mhz to march 20, 2011 188 texas instruments-advance information system control $ q d o r j & l u f x l w v , 2 % x i i h u v / r z 1 r l v h / ' 2 , q w h u q d o / r j l f d q g 3 / / * 1 ' * 1 ' $ * 1 ' $ 9 ' ' $ 9 ' ' $ 9 ' ' & 9 ' ' & / ' 2 9 * 1 ' * 1 ' * 1 ' 9 ' ' 9 ' ' 16.384 mhz (inclusive). if the pll is not being used, the crystal may be any one of the supported frequencies between 1 mhz to 16.384 mhz. the single-ended clock source range is from dc through the specified speed of the microcontroller. the supported crystals are listed in the xtal bit field in the rcc register (see page 211). internal 30-khz oscillator. the internal 30-khz oscillator provides an operational frequency of 30 khz 50%. it is intended for use during deep-sleep power-saving modes. this power-savings mode benefits from reduced internal switching and also allows the mosc to be powered down. hibernation module clock source. the hibernation module can be clocked in one of two ways. the first way is a 4.194304-mhz crystal connected to the xosc0 and xosc1 pins. this clock signal is divided by 128 internally to produce the 32.768-khz clock reference. the second way is a 32.768-khz oscillator connected to the xosc0 pin. the 32.768-khz oscillator can be used for the system clock, thus eliminating the need for an additional crystal or oscillator. the hibernation module clock source is intended to provide the system with a real-time clock source and may also provide an accurate source of deep-sleep or hibernate mode power savings. the internal system clock (sysclk), is derived from any of the above sources plus two others: the output of the main internal pll and the precision internal oscillator divided by four (4 mhz 1%). the frequency of the pll clock reference must be in the range of 3.579545 mhz to 16.384 mhz (inclusive). table 5-4 on page 189 shows how the various clock sources can be used in a system. table 5-4. clock source options used as sysclk? drive pll? clock source bypass = 1, oscsrc = 0x1 yes bypass = 0, oscsrc = 0x1 yes precision internal oscillator bypass = 1, oscsrc = 0x2 yes - no precision internal oscillator divide by 4 (4 mhz 1%) bypass = 1, oscsrc = 0x0 yes bypass = 0, oscsrc = 0x0 yes main oscillator bypass = 1, oscsrc = 0x3 yes - no internal 30-khz oscillator bypass = 1, oscsrc2 = 0x7 yes - no hibernation module 32.768-khz oscillator - no - no hibernation module 4.194304-mhz crystal 5.2.5.2 clock configuration the run-mode clock configuration (rcc) and run-mode clock configuration 2 (rcc2) registers provide control for the system clock. the rcc2 register is provided to extend fields that offer additional encodings over the rcc register. when used, the rcc2 register field values are used by the logic over the corresponding field in the rcc register. in particular, rcc2 provides for a larger assortment of clock configuration options. these registers control the following clock functionality: source of clocks in sleep and deep-sleep modes system clock derived from pll or other clock source enabling/disabling of oscillators and pll clock divisors 189 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller crystal input selection figure 5-5 shows the logic for the main clock tree. the peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. when the pll is enabled, the adc clock signal is automatically divided down to 16 mhz from the pll output for proper adc operation. the pwm clock signal is a synchronous divide of the system clock to provide the pwm circuit with more range (set with pwmdiv in rcc). note: when the adc module is in operation, the system clock must be at least 16 mhz. march 20, 2011 190 texas instruments-advance information system control figure 5-5. main clock tree note: the figure above shows all features available on all stellaris? tempest-class microcontrollers. not all peripherals may be available on this device. using the sysdiv and sysdiv2 fields in the rcc register, the sysdiv field specifies which divisor is used to generate the system clock from either the pll output or the oscillator source (depending on how the bypass bit in this register 191 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 0 d l q 2 6 & 3 u h f l v l r q , q w h u q d o 2 6 & 0 + ] , q w h u q d o 2 6 & n + ] 3 : 5 ' 1 $ ' & & o r f n 6 \ v w h p & o r f n 0 2 6 & ' , 6 d , 2 6 & ' , 6 d 6 < 6 ' , 9 h 8 6 ( 6 < 6 ' , 9 d g 3 : 0 ' : d 8 6 ( 3 : 0 ' , 9 d 3 : 0 & o r f n + l e h u q d w l r q 2 6 & n + ] 2 6 & 6 5 & e g % < 3 $ 6 6 e g ; 7 $ / d 3 : 5 ' 1 e 8 6 % 3 / / 0 + ] 8 6 % & o r f n ; 7 $ / d 8 6 % 3 : 5 ' 1 f 5 ; , 1 7 5 ; ) 5 $ & , 6 5 h f h l y h 0 & / . , 6 7 u d q v p l w 0 & / . 3 / / 0 + ] 7 ; , 1 7 7 ; ) 5 $ & d & r q w u r o s u r y l g h g e \ 5 & & u h j l v w h u e l w i l h o g e & r q w u r o s u r y l g h g e \ 5 & & u h j l v w h u e l w i l h o g r u 5 & & u h j l v w h u e l w i l h o g l i r y h u u l g g h q z l w k 5 & & u h j l v w h u e l w usercc 2 . c . control provided by rcc 2 register bit/field. d . also may be controlled by dslpclkcf hen in deep sleep mode. e . control provided by rcc register sysdiv field, rcc 2 register sysdiv 2 field if overridden ith usercc 2 bit, or [ sysdiv 2 , sysdiv 2 lsb ] if both usercc 2 and div 400 bits are set. div400 c is configured). when using the pll, the vco frequency of 400 mhz is predivided by 2 before the divisor is applied. table 5-5 shows how the sysdiv encoding affects the system clock frequency, depending on whether the pll is used ( bypass =0) or another clock source is used (bypass=1). the divisor is equivalent to the sysdiv encoding plus 1. for a list of possible clock sources, see table 5-4 on page 189. table 5-5. possible system clock frequencies using the sysdiv field stellarisware parameter a frequency ( bypass=1) frequency ( bypass=0) divisor sysdiv sysctl_sysdiv_1 b clock source frequency/2 reserved /1 0x0 sysctl_sysdiv_2 clock source frequency/2 reserved /2 0x1 sysctl_sysdiv_3 clock source frequency/3 66.67 mhz /3 0x2 sysctl_sysdiv_4 clock source frequency/4 50 mhz /4 0x3 sysctl_sysdiv_5 clock source frequency/5 40 mhz /5 0x4 sysctl_sysdiv_6 clock source frequency/6 33.33 mhz /6 0x5 sysctl_sysdiv_7 clock source frequency/7 28.57 mhz /7 0x6 sysctl_sysdiv_8 clock source frequency/8 25 mhz /8 0x7 sysctl_sysdiv_9 clock source frequency/9 22.22 mhz /9 0x8 sysctl_sysdiv_10 clock source frequency/10 20 mhz /10 0x9 sysctl_sysdiv_11 clock source frequency/11 18.18 mhz /11 0xa sysctl_sysdiv_12 clock source frequency/12 16.67 mhz /12 0xb sysctl_sysdiv_13 clock source frequency/13 15.38 mhz /13 0xc sysctl_sysdiv_14 clock source frequency/14 14.29 mhz /14 0xd sysctl_sysdiv_15 clock source frequency/15 13.33 mhz /15 0xe sysctl_sysdiv_16 clock source frequency/16 12.5 mhz (default) /16 0xf a. this parameter is used in functions such as sysctlclockset() in the stellaris peripheral driver library. b. sysctl_sysdiv_1 does not set the usesysdiv bit. as a result, using this parameter without enabling the pll results in the system clock having the same frequency as the clock source. the sysdiv2 field in the rcc2 register is 2 bits wider than the sysdiv field in the rcc register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved deep sleep power consumption. when using the pll, the vco frequency of 400 mhz is predivided by 2 before the divisor is applied. the divisor is equivalent to the sysdiv2 encoding plus 1. table 5-6 shows how the sysdiv2 encoding affects the system clock frequency, depending on whether the pll is used ( bypass2 =0) or another clock source is used (bypass2 =1). for a list of possible clock sources, see table 5-4 on page 189. table 5-6. examples of possible system clock frequencies using the sysdiv2 field stellarisware parameter a frequency ( bypass2=1) frequency (bypass2=0) divisor sysdiv2 sysctl_sysdiv_1 b clock source frequency/2 reserved /1 0x00 sysctl_sysdiv_2 clock source frequency/2 reserved /2 0x01 sysctl_sysdiv_3 clock source frequency/3 66.67 mhz /3 0x02 sysctl_sysdiv_4 clock source frequency/4 50 mhz /4 0x03 sysctl_sysdiv_5 clock source frequency/5 40 mhz /5 0x09 ... ... ...... ... sysctl_sysdiv_10 clock source frequency/10 20 mhz /10 0x09 ... ... ...... ... march 20, 2011 192 texas instruments-advance information system control table 5-6. examples of possible system clock frequencies using the sysdiv2 field (continued) stellarisware parameter a frequency ( bypass2=1) frequency (bypass2=0) divisor sysdiv2 sysctl_sysdiv_64 clock source frequency/64 3.125 mhz /64 0x3f a. this parameter is used in functions such as sysctlclockset() in the stellaris peripheral driver library. b. sysctl_sysdiv_1 does not set the usesysdiv bit. as a result, using this parameter without enabling the pll results in the system clock having the same frequency as the clock source. to allow for additional frequency choices when using the pll, the div400 bit is provided along with the sysdiv2lsb bit. when the div400 bit is set, bit 22 becomes the lsb for sysdiv2 . in this situation, the divisor is equivalent to the ( sysdiv2 encoding with sysdiv2lsb appended) plus one. table 5-7 shows the frequency choices when div400 is set. when the div400 bit is clear, sysdiv2lsb is ignored, and the system clock frequency is determined as shown in table 5-6 on page 192. table 5-7. examples of possible system clock frequencies with div400=1 stellarisware parameter b frequency ( bypass2=0) a divisor sysdiv2lsb sysdiv2 - reserved /2 reserved 0x00 - reserved /3 0 0x01 - reserved /4 1 sysctl_sysdiv_2_5 80 mhz /5 0 0x02 sysctl_sysdiv_3 66.67 mhz /6 1 - reserved /7 0 0x03 sysctl_sysdiv_4 50 mhz /8 1 sysctl_sysdiv_4_5 44.44 mhz /9 0 0x04 sysctl_sysdiv_5 40 mhz /10 1 ... ... ... ... ... sysctl_sysdiv_63_5 3.15 mhz /127 0 0x3f sysctl_sysdiv_64 3.125 mhz /128 1 a. note that div400 and sysdiv2lsb are only valid when bypass2=0. b. this parameter is used in functions such as sysctlclockset() in the stellaris peripheral driver library. 5.2.5.3 precision internal oscillator operation (piosc) the microcontroller powers up with the piosc running. if another clock source is desired, the piosc must remain enabled as it is used for internal functions. the piosc can only be disabled during deep-sleep mode. it can be powered down by setting the ioscdis bit in the rcc register. the piosc generates a 16-mhz clock with a 1% accuracy at room temperatures. across the extended temperature range, the accuracy is 3%. at the factory, the piosc is set to 16 mhz at room temperature, however, the frequency can be trimmed for other voltage or temperature conditions using software in one of three ways: default calibration: clear the uten bit and set the update bit in the precision internal oscillator calibration (piosccal) register. user-defined calibration: the user can program the ut value to adjust the piosc frequency. as the ut value increases, the generated period increases. to commit a new ut value, first set the 193 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller uten bit, then program the ut field, and then set the update bit. the adjustment finishes within a few clock periods and is glitch free. automatic calibration using the enable 32.768-khz oscillator from the hibernation module: set the cal bit; the results of the calibration are shown in the result field in the precision internal oscillator statistic (pioscstat) register. after calibration is complete, the piosc is trimmed using trimmed value returned in the ct field. 5.2.5.4 crystal configuration for the main oscillator (mosc) the main oscillator supports the use of a select number of crystals. if the main oscillator is used by the pll as a reference clock, the supported range of crystals is 3.579545 to 16.384 mhz, otherwise, the range of supported crystals is 1 to 16.384 mhz. the xtal bit in the rcc register (see page 211) describes the available crystal choices and default programming values. software configures the rcc register xtal field with the crystal number. if the pll is used in the design, the xtal field value is internally translated to the pll settings. 5.2.5.5 main pll frequency configuration the main pll is disabled by default during power-on reset and is enabled later by software if required. software specifies the output divisor to set the system clock frequency and enables the main pll to drive the output. the pll operates at 400 mhz, but is divided by two prior to the application of the output divisor, unless the div400 bit in the rcc2 register is set. to configure the piosc to be the clock source for the main pll, program the oscrc2 field in the run-mode clock configuration 2 (rcc2) register to be 0x1. if the main oscillator provides the clock reference to the main pll, the translation provided by hardware and used to program the pll is available for software in the xtal to pll translation (pllcfg) register (see page 215). the internal translation provides a translation within 1% of the targeted pll vco frequency. table 23-14 on page 971 shows the actual pll frequency and error for a given crystal choice. the crystal value field ( xtal ) in the run-mode clock configuration (rcc) register (see page 211) describes the available crystal choices and default programming of the pllcfg register. any time the xtal field changes, the new settings are translated and the internal pll settings are updated. 5.2.5.6 pll modes normal: the pll multiplies the input clock reference and drives the output. power-down: most of the pll internal circuitry is disabled and the pll does not drive the output. the modes are programmed using the rcc/ rcc2 register fields (see page 211 and page 218). 5.2.5.7 pll operation if a pll configuration is changed, the pll output frequency is unstable until it reconverges (relocks) to the new setting. the time between the configuration change and relock is t ready (see table 23-13 on page 971). during the relock time, the affected pll is not usable as a clock reference. the pll is changed by one of the following: change to the xtal value in the rcc registerwrites of the same value do not cause a relock. march 20, 2011 194 texas instruments-advance information system control change in the pll from power-down to normal mode. a counter clocked by the system clock is used to measure the t ready requirement. if the system clock is the main oscillator and it is running off an 8.192 mhz or slower external oscillator clock, the down counter is set to 0x1200 (that is, ~600 s at an 8.192 mhz). if the system clock is running off the piosc or an external oscillator clock that is faster than 8.192 mhz, the down counter is set to 0x2400. hardware is provided to keep the pll from being used as a system clock until the t ready condition is met after one of the two changes above. it is the user's responsibility to have a stable clock source (like the main oscillator) before the rcc/ rcc2 register is switched to use the pll. if the main pll is enabled and the system clock is switched to use the pll in one step, the system control hardware continues to clock the microcontroller from the oscillator selected by the rcc/ rcc2 register until the main pll is stable (t ready time met), after which it changes to the pll. software can use many methods to ensure that the system is clocked from the main pll, including periodically polling the plllris bit in the raw interrupt status (ris) register, and enabling the pll lock interrupt. 5.2.5.8 main oscillator verification circuit the clock control includes circuitry to ensure that the main oscillator is running at the appropriate frequency. the circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals. the detection circuit is enabled using the cval bit in the main oscillator control (moscctl) register. if this circuit is enabled and detects an error, the following sequence is performed by the hardware: 1. the moscfail bit in the reset cause (resc) register is set. 2. if the internal oscillator (piosc) is disabled, it is enabled. 3. the system clock is switched from the main oscillator to the piosc. 4. an internal power-on reset is initiated that lasts for 32 piosc periods. 5. reset is de-asserted and the processor is directed to the nmi handler during the reset sequence. if the moscim bit in the moscctl register is set, then the following sequence is performed by the hardware: 1. the system clock is switched from the main oscillator to the piosc. 2. the mofris bit in the ris register is set to indicate a mosc failure. 5.2.6 system control for power-savings purposes, the rcgcn , scgcn , and dcgcn registers control the clock gating logic for each peripheral or block in the system while the microcontroller is in run, sleep, and deep-sleep mode, respectively. these registers are located in the system control register map starting at offsets 0x600, 0x700, and 0x800, respectively. there must be a delay of 3 system clocks after a peripheral module clock is enabled in the rcgc register before any module registers are accessed. there are four levels of operation for the microcontroller defined as: run mode 195 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller sleep mode deep-sleep mode hibernation mode the following sections describe the different modes in detail. caution C if the cortex-m3 debug access port (dap) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their run mode confguration. the dap is usually enabled by software tools accessing the jtag or swd interface when debugging or fash programming. if this condition occurs, a hard fault is triggered when software accesses a peripheral with an invalid clock. a software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a wfi (wait for interrupt) instruction. this stalls the execution of any code that accesses a peripheral register that might cause a fault. this loop can be removed for production software as the dap is most likely not enabled during normal execution. because the dap is disabled by default (power on reset), the user can also power cycle the device. the dap is not enabled unless it is enabled through the jtag or swd interface. 5.2.6.1 run mode in run mode, the microcontroller actively executes code. run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the rcgcn registers. the system clock can be any of the available clock sources including the pll. 5.2.6.2 sleep mode in sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. sleep mode is entered by the cortex-m3 core executing a wfi (wait for interrupt) instruction. any properly configured interrupt event in the system brings the processor back into run mode. see power management on page 97 for more details. peripherals are clocked that are enabled in the scgcn registers when auto-clock gating is enabled (see the rcc register) or the rcgcn registers when the auto-clock gating is disabled. the system clock has the same source and frequency as that during run mode. 5.2.6.3 deep-sleep mode in deep-sleep mode, the clock frequency of the active peripherals may change (depending on the run mode clock configuration) in addition to the processor clock being stopped. an interrupt returns the microcontroller to run mode from one of the sleep modes; the sleep modes are entered on request from the code. deep-sleep mode is entered by first setting the sleepdeep bit in the system control (sysctrl) register (see page 140) and then executing a wfi instruction. any properly configured interrupt event in the system brings the processor back into run mode. see power management on page 97 for more details. the cortex-m3 processor core and the memory subsystem are not clocked in deep-sleep mode. peripherals are clocked that are enabled in the dcgcn registers when auto-clock gating is enabled (see the rcc register) or the rcgcn registers when auto-clock gating is disabled. the system clock source is specified in the dslpclkcfg register. when the dslpclkcfg register is used, the internal oscillator source is powered up, if necessary, and other clocks are powered down. if the pll is running at the time of the wfi instruction, hardware powers the pll down and overrides march 20, 2011 196 texas instruments-advance information system control the sysdiv field of the active rcc/ rcc2 register, to be determined by the dsdivoride setting in the dslpclkcfg register, up to /16 or /64 respectively. when the deep-sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of deep-sleep mode before enabling the clocks that had been stopped during the deep-sleep duration. if the piosc is used as the pll reference clock source, it may continue to provide the clock during deep-sleep. see page 222. 5.2.6.4 hibernation mode in this mode, the power supplies are turned off to the main part of the microcontroller and only the hibernation module's circuitry is active. an external wake event or rtc event is required to bring the microcontroller back to run mode. the cortex-m3 processor and peripherals outside of the hibernation module see a normal "power on" sequence and the processor starts running code. software can determine if the microcontroller has been restarted from hibernate mode by inspecting the hibernation module registers. for more information on the operation of hibernation mode, see hibernation module on page 282. 5.3 initialization and configuration the pll is configured using direct register writes to the rcc/ rcc2 register. if the rcc2 register is being used, the usercc2 bit must be set and the appropriate rcc2 bit/field is used. the steps required to successfully change the pll-based system clock are: 1. bypass the pll and system clock divider by setting the bypass bit and clearing the usesys bit in the rcc register, thereby configuring the microcontroller to run off a raw clock source and allowing for the new pll configuration to be validated before switching the system clock to the pll. 2. select the crystal value ( xtal ) and oscillator source (oscsrc ), and clear the pwrdn bit in rcc/ rcc2 . setting the xtal field automatically pulls valid pll configuration data for the appropriate crystal, and clearing the pwrdn bit powers and enables the pll and its output. 3. select the desired system divider ( sysdiv ) in rcc/ rcc2 and set the usesys bit in rcc . the sysdiv field determines the system frequency for the microcontroller. 4. wait for the pll to lock by polling the plllris bit in the raw interrupt status (ris ) register. 5. enable use of the pll by clearing the bypass bit in rcc/ rcc2. 5.4 register map table 5-8 on page 198 lists the system control registers, grouped by function. the offset listed is a hexadecimal increment to the register's address, relative to the system control base address of 0x400f.e000. note: spaces in the system control register space that are not used are reserved for future or internal use. software should not modify any reserved memory address. additional flash and rom registers defined in the system control register space are described in the internal memory on page 310. 197 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 5-8. system control register map see page description reset type name offset 200 device identification 0 - ro did0 0x000 229 device identification 1 - ro did1 0x004 231 device capabilities 0 0x005f.001f ro dc0 0x008 232 device capabilities 1 - ro dc1 0x010 234 device capabilities 2 0x130f.5337 ro dc2 0x014 236 device capabilities 3 0xbfff.8fff ro dc3 0x018 238 device capabilities 4 0x0004.f1ff ro dc4 0x01c 240 device capabilities 5 0x0f30.003f ro dc5 0x020 242 device capabilities 6 0x0000.0000 ro dc6 0x024 243 device capabilities 7 0xffff.ffff ro dc7 0x028 247 device capabilities 8 adc channels 0xffff.ffff ro dc8 0x02c 202 brown-out reset control 0x0000.7ffd r/w pborctl 0x030 275 software reset control 0 0x00000000 r/w srcr0 0x040 277 software reset control 1 0x00000000 r/w srcr1 0x044 280 software reset control 2 0x00000000 r/w srcr2 0x048 203 raw interrupt status 0x0000.0000 ro ris 0x050 205 interrupt mask control 0x0000.0000 r/w imc 0x054 207 masked interrupt status and clear 0x0000.0000 r/w1c misc 0x058 209 reset cause - r/w resc 0x05c 211 run-mode clock configuration 0x078e.3ad1 r/w rcc 0x060 215 xtal to pll translation - ro pllcfg 0x064 216 gpio high-performance bus control 0x0000.0000 r/w gpiohbctl 0x06c 218 run-mode clock configuration 2 0x07c0.6810 r/w rcc2 0x070 221 main oscillator control 0x0000.0000 r/w moscctl 0x07c 252 run mode clock gating control register 0 0x00000040 r/w rcgc0 0x100 260 run mode clock gating control register 1 0x00000000 r/w rcgc1 0x104 269 run mode clock gating control register 2 0x00000000 r/w rcgc2 0x108 255 sleep mode clock gating control register 0 0x00000040 r/w scgc0 0x110 263 sleep mode clock gating control register 1 0x00000000 r/w scgc1 0x114 271 sleep mode clock gating control register 2 0x00000000 r/w scgc2 0x118 258 deep sleep mode clock gating control register 0 0x00000040 r/w dcgc0 0x120 266 deep-sleep mode clock gating control register 1 0x00000000 r/w dcgc1 0x124 march 20, 2011 198 texas instruments-advance information system control table 5-8. system control register map (continued) see page description reset type name offset 273 deep sleep mode clock gating control register 2 0x00000000 r/w dcgc2 0x128 222 deep sleep clock configuration 0x0780.0000 r/w dslpclkcfg 0x144 224 precision internal oscillator calibration 0x0000.0000 r/w piosccal 0x150 226 precision internal oscillator statistics 0x0000.0040 ro pioscstat 0x154 227 i2s mclk configuration 0x0000.0000 r/w i2smclkcfg 0x170 249 device capabilities 9 adc digital comparators 0x00ff.00ff ro dc9 0x190 251 non-volatile memory information 0x0000.0001 ro nvmstat 0x1a0 5.5 register descriptions all addresses given are relative to the system control base address of 0x400f.e000. 199 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: device identification 0 (did0), offset 0x000 this register identifies the version of the microcontroller. each microcontroller is uniquely identified by the combined values of the class field in the did0 register and the partno field in the did1 register. device identification 0 (did0) base 0x400f.e000 offset 0x000 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 class reserved ver reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 minor major ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - - - - - - - - - - reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 did0 version this field defines the did0 register format version. the version number is numeric. the value of the ver field is encoded as follows (all other encodings are reserved): description value second version of the did0 register format. 0x1 0x1 ro ver 30:28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 27:24 device class the class field value identifies the internal design from which all mask sets are generated for all microcontrollers in a particular product line. the class field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the major or minor fields require differentiation from prior microcontrollers. the value of the class field is encoded as follows (all other encodings are reserved): description value stellaris? tempest-class microcontrollers 0x04 0x04 ro class 23:16 march 20, 2011 200 texas instruments-advance information system control description reset type name bit/field major revision this field specifies the major revision number of the microcontroller. the major revision reflects changes to base layers of the design. the major revision number is indicated in the part number as a letter (a for first revision, b for second, and so on). this field is encoded as follows: description value revision a (initial device) 0x0 revision b (first base layer revision) 0x1 revision c (second base layer revision) 0x2 and so on. - ro major 15:8 minor revision this field specifies the minor revision number of the microcontroller. the minor revision reflects changes to the metal layers of the design. the minor field value is reset when the major field is changed. this field is numeric and is encoded as follows: description value initial device, or a major revision update. 0x0 first metal layer change. 0x1 second metal layer change. 0x2 and so on. - ro minor 7:0 201 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: brown-out reset control (pborctl), offset 0x030 this register is responsible for controlling reset conditions after initial power-on reset. brown-out reset control (pborctl) base 0x400f.e000 offset 0x030 type r/w, reset 0x0000.7ffd 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved borior reserved ro r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 bor interrupt or reset description value a brown out event causes an interrupt to be generated to the interrupt controller. 0 a brown out event causes a reset of the microcontroller. 1 0 r/w borior 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 march 20, 2011 202 texas instruments-advance information system control register 3: raw interrupt status (ris), offset 0x050 this register indicates the status for system control raw interrupts. an interrupt is sent to the interrupt controller if the corresponding bit in the interrupt mask control (imc) register is set. writing a 1 to the corresponding bit in the masked interrupt status and clear (misc) register clears an interrupt status bit. raw interrupt status (ris) base 0x400f.e000 offset 0x050 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved borris reserved plllris reserved moscpupris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 mosc power up raw interrupt status description value sufficient time has passed for the mosc to reach the expected frequency. the value for this power-up time is indicated by t mosc_settle . 1 sufficient time has not passed for the mosc to reach the expected frequency. 0 this bit is cleared by writing a 1 to the moscpupmis bit in the misc register. 0 ro moscpupris 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 pll lock raw interrupt status description value the pll timer has reached t ready indicating that sufficient time has passed for the pll to lock. 1 the pll timer has not reached t ready . 0 this bit is cleared by writing a 1 to the plllmis bit in the misc register. 0 ro plllris 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 5:2 203 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field brown-out reset raw interrupt status description value a brown-out condition is currently active. 1 a brown-out condition is not currently active. 0 note the borior bit in the pborctl register must be cleared to cause an interrupt due to a brown out event. this bit is cleared by writing a 1 to the bormis bit in the misc register. 0 ro borris 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 march 20, 2011 204 texas instruments-advance information system control register 4: interrupt mask control (imc), offset 0x054 this register contains the mask bits for system control raw interrupts. a raw interrupt, indicated by a bit being set in the raw interrupt status (ris) register, is sent to the interrupt controller if the corresponding bit in this register is set. interrupt mask control (imc) base 0x400f.e000 offset 0x054 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved borim reserved plllim reserved moscpupim reserved ro r/w ro ro ro ro r/w ro r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 mosc power up interrupt mask description value an interrupt is sent to the interrupt controller when the moscpupris bit in the ris register is set. 1 the moscpupris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w moscpupim 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 pll lock interrupt mask description value an interrupt is sent to the interrupt controller when the plllris bit in the ris register is set. 1 the plllris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w plllim 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 5:2 205 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field brown-out reset interrupt mask description value an interrupt is sent to the interrupt controller when the borris bit in the ris register is set. 1 the borris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w borim 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 march 20, 2011 206 texas instruments-advance information system control register 5: masked interrupt status and clear (misc), offset 0x058 on a read, this register gives the current masked status value of the corresponding interrupt in the raw interrupt status (ris) register. all of the bits are r/w1c, thus writing a 1 to a bit clears the corresponding raw interrupt bit in the ris register (see page 203). masked interrupt status and clear (misc) base 0x400f.e000 offset 0x058 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved bormis reserved plllmis reserved moscpupmis reserved ro r/w1c ro ro ro ro r/w1c ro r/w1c ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 mosc power up masked interrupt status description value when read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the mosc pll to lock. writing a 1 to this bit clears it and also the moscpupris bit in the ris register. 1 when read, a 0 indicates that sufficient time has not passed for the mosc pll to lock. a write of 0 has no effect on the state of this bit. 0 0 r/w1c moscpupmis 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 pll lock masked interrupt status description value when read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the pll to lock. writing a 1 to this bit clears it and also the plllris bit in the ris register. 1 when read, a 0 indicates that sufficient time has not passed for the pll to lock. a write of 0 has no effect on the state of this bit. 0 0 r/w1c plllmis 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 5:2 207 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field bor masked interrupt status description value when read, a 1 indicates that an unmasked interrupt was signaled because of a brown-out condition. writing a 1 to this bit clears it and also the borris bit in the ris register. 1 when read, a 0 indicates that a brown-out condition has not occurred. a write of 0 has no effect on the state of this bit. 0 0 r/w1c bormis 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 march 20, 2011 208 texas instruments-advance information system control register 6: reset cause (resc), offset 0x05c this register is set with the reset cause after reset. the bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than por in the resc register are cleared. reset cause (resc) base 0x400f.e000 offset 0x05c type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 moscfail reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ext por bor wdt0 sw wdt1 reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type - - - - - - 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 mosc failure reset description value when read, this bit indicates that the mosc circuit was enabled for clock validation and failed, generating a reset event. 1 when read, this bit indicates that a mosc failure has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w moscfail 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:6 watchdog timer 1 reset description value when read, this bit indicates that watchdog timer 1 timed out and generated a reset. 1 when read, this bit indicates that watchdog timer 1 has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w wdt1 5 209 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field software reset description value when read, this bit indicates that a software reset has caused a reset event. 1 when read, this bit indicates that a software reset has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w sw 4 watchdog timer 0 reset description value when read, this bit indicates that watchdog timer 0 timed out and generated a reset. 1 when read, this bit indicates that watchdog timer 0 has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w wdt0 3 brown-out reset description value when read, this bit indicates that a brown-out reset has caused a reset event. 1 when read, this bit indicates that a brown-out reset has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w bor 2 power-on reset description value when read, this bit indicates that a power-on reset has caused a reset event. 1 when read, this bit indicates that a power-on reset has not generated a reset. writing a 0 to this bit clears it. 0 - r/w por 1 external reset description value when read, this bit indicates that an external reset ( rst assertion) has caused a reset event. 1 when read, this bit indicates that an external reset ( rst assertion) has not caused a reset event since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w ext 0 march 20, 2011 210 texas instruments-advance information system control register 7: run-mode clock configuration (rcc), offset 0x060 the bits in this register configure the system clock and oscillators. run-mode clock configuration (rcc) base 0x400f.e000 offset 0x060 type r/w, reset 0x078e.3ad1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pwmdiv usepwmdiv reserved usesysdiv sysdiv acg reserved ro r/w r/w r/w r/w ro r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 moscdis ioscdis reserved oscsrc xtal bypass reserved pwrdn reserved r/w r/w ro ro r/w r/w r/w r/w r/w r/w r/w r/w ro r/w ro ro type 1 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:28 auto clock gating this bit specifies whether the system uses the sleep-mode clock gating control (scgcn) registers and deep-sleep-mode clock gating control (dcgcn) registers if the microcontroller enters a sleep or deep-sleep mode (respectively). description value the scgcn or dcgcn registers are used to control the clocks distributed to the peripherals when the microcontroller is in a sleep mode. the scgcn and dcgcn registers allow unused peripherals to consume less power when the microcontroller is in a sleep mode. 1 the run-mode clock gating control (rcgcn) registers are used when the microcontroller enters a sleep mode. 0 the rcgcn registers are always used to control the clocks in run mode. 0 r/w acg 27 system clock divisor specifies which divisor is used to generate the system clock from either the pll output or the oscillator source (depending on how the bypass bit in this register is configured). see table 5-5 on page 192 for bit encodings. if the sysdiv value is less than minsysdiv (see page 232), and the pll is being used, then the minsysdiv value is used as the divisor. if the pll is not being used, the sysdiv value can be less than minsysdiv. 0xf r/w sysdiv 26:23 211 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field enable system clock divider description value the system clock divider is the source for the system clock. the system clock divider is forced to be used when the pll is selected as the source. if the usercc2 bit in the rcc2 register is set, then the sysdiv2 field in the rcc2 register is used as the system clock divider rather than the sysdiv field in this register. 1 the system clock is used undivided. 0 0 r/w usesysdiv 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 21 enable pwm clock divisor description value the pwm clock divider is the source for the pwm clock. 1 the system clock is the source for the pwm clock. 0 note that when the pwm divisor is used, it is applied to the clock for both pwm modules. 0 r/w usepwmdiv 20 pwm unit clock divisor this field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the pwm module. the rising edge of this clock is synchronous with the system clock. divisor value /20x0 /40x1 /80x2 /160x3 /320x4 /640x5 /640x6 /64 (default) 0x7 0x7 r/w pwmdiv 19:17 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 16:14 pll power down description value the pll is powered down. care must be taken to ensure that another clock source is functioning and that the bypass bit is set before setting this bit. 1 the pll is operating normally. 0 1 r/w pwrdn 13 march 20, 2011 212 texas instruments-advance information system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 ro reserved 12 pll bypass description value the system clock is derived from the osc source and divided by the divisor specified by sysdiv. 1 the system clock is the pll output clock divided by the divisor specified by sysdiv. 0 see table 5-5 on page 192 for programming guidelines. note: the adc must be clocked from the pll or directly from a 16-mhz clock source to operate properly. 1 r/w bypass 11 crystal value this field specifies the crystal value attached to the main oscillator. the encoding for this field is provided below. depending on the crystal used, the pll frequency may not be exactly 400 mhz, see table 23-14 on page 971 for more information. crystal frequency (mhz) using the pll crystal frequency (mhz) not using the pll value reserved 1.000 mhz 0x00 reserved 1.8432 mhz 0x01 reserved 2.000 mhz 0x02 reserved 2.4576 mhz 0x03 3.579545 mhz 0x04 3.6864 mhz 0x05 4 mhz 0x06 4.096 mhz 0x07 4.9152 mhz 0x08 5 mhz 0x09 5.12 mhz 0x0a 6 mhz (reset value) 0x0b 6.144 mhz 0x0c 7.3728 mhz 0x0d 8 mhz 0x0e 8.192 mhz 0x0f 10.0 mhz 0x10 12.0 mhz 0x11 12.288 mhz 0x12 13.56 mhz 0x13 14.31818 mhz 0x14 16.0 mhz 0x15 16.384 mhz 0x16 0x0b r/w xtal 10:6 213 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field oscillator source selects the input source for the osc. the values are: input source value mosc main oscillator 0x0 piosc precision internal oscillator (default) 0x1 piosc/4 precision internal oscillator / 4 0x2 30 khz 30-khz internal oscillator 0x3 for additional oscillator sources, see the rcc2 register. 0x1 r/w oscsrc 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 precision internal oscillator disable description value the precision internal oscillator (piosc) is disabled. 1 the precision internal oscillator is enabled. 0 0 r/w ioscdis 1 main oscillator disable description value the main oscillator is disabled (default). 1 the main oscillator is enabled. 0 1 r/w moscdis 0 march 20, 2011 214 texas instruments-advance information system control register 8: xtal to pll translation (pllcfg), offset 0x064 this register provides a means of translating external crystal frequencies into the appropriate pll settings. this register is initialized during the reset sequence and updated anytime that the xtal field changes in the run-mode clock configuration (rcc) register (see page 211). the pll frequency is calculated using the pllcfg field values, as follows: pllfreq = oscfreq * f / (r + 1) xtal to pll translation (pllcfg) base 0x400f.e000 offset 0x064 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r f reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - - - - - - - - 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:14 pll f value this field specifies the value supplied to the plls f input. - ro f 13:5 pll r value this field specifies the value supplied to the plls r input. - ro r 4:0 215 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 9: gpio high-performance bus control (gpiohbctl), offset 0x06c this register controls which internal bus is used to access each gpio port. when a bit is clear, the corresponding gpio port is accessed across the legacy advanced peripheral bus (apb) bus and through the apb memory aperture. when a bit is set, the corresponding port is accessed across the advanced high-performance bus (ahb) bus and through the ahb memory aperture. each gpio port can be individually configured to use ahb or apb, but may be accessed only through one aperture. the ahb bus provides better back-to-back access performance than the apb bus. the address aperture in the memory map changes for the ports that are enabled for ahb access (see table 9-7 on page 415). gpio high-performance bus control (gpiohbctl) base 0x400f.e000 offset 0x06c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 porta portb portc portd porte portf portg porth portj reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:9 port j advanced high-performance bus this bit defines the memory aperture for port j. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portj 8 port h advanced high-performance bus this bit defines the memory aperture for port h. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w porth 7 port g advanced high-performance bus this bit defines the memory aperture for port g. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portg 6 march 20, 2011 216 texas instruments-advance information system control description reset type name bit/field port f advanced high-performance bus this bit defines the memory aperture for port f. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portf 5 port e advanced high-performance bus this bit defines the memory aperture for port e. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w porte 4 port d advanced high-performance bus this bit defines the memory aperture for port d. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portd 3 port c advanced high-performance bus this bit defines the memory aperture for port c. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portc 2 port b advanced high-performance bus this bit defines the memory aperture for port b. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portb 1 port a advanced high-performance bus this bit defines the memory aperture for port a. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w porta 0 217 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 10: run-mode clock configuration 2 (rcc2), offset 0x070 this register overrides the rcc equivalent register fields, as shown in table 5-9, when the usercc2 bit is set, allowing the extended capabilities of the rcc2 register to be used while also providing a means to be backward-compatible to previous parts. each rcc2 field that supersedes an rcc field is located at the same lsb bit position; however, some rcc2 fields are larger than the corresponding rcc field. table 5-9. rcc2 fields that override rcc fields overrides rcc field rcc2 field... sysdiv , bits[26:23] sysdiv2 , bits[28:23] pwrdn , bit[13] pwrdn2 , bit[13] bypass , bit[11] bypass2 , bit[11] oscsrc , bits[5:4] oscsrc2 , bits[6:4] run-mode clock configuration 2 (rcc2) base 0x400f.e000 offset 0x070 type r/w, reset 0x07c0.6810 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved sysdiv2lsb sysdiv2 reserved div400 usercc2 ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w ro r/w r/w type 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved oscsrc2 reserved bypass2 reserved pwrdn2 reserved ro ro ro ro r/w r/w r/w ro ro ro ro r/w ro r/w ro ro type 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 reset description reset type name bit/field use rcc2 description value the rcc2 register fields override the rcc register fields. 1 the rcc register fields are used, and the fields in rcc2 are ignored. 0 0 r/w usercc2 31 divide pll as 400 mhz vs. 200 mhz this bit, along with the sysdiv2lsb bit, allows additional frequency choices. description value append the sysdiv2lsb bit to the sysdiv2 field to create a 7 bit divisor using the 400 mhz pll output, see table 5-7 on page 193. 1 use sysdiv2 as is and apply to 200 mhz predivided pll output. see table 5-6 on page 192 for programming guidelines. 0 0 r/w div400 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 29 march 20, 2011 218 texas instruments-advance information system control description reset type name bit/field system clock divisor 2 specifies which divisor is used to generate the system clock from either the pll output or the oscillator source (depending on how the bypass2 bit is configured). sysdiv2 is used for the divisor when both the usesysdiv bit in the rcc register and the usercc2 bit in this register are set. see table 5-6 on page 192 for programming guidelines. 0x0f r/w sysdiv2 28:23 additional lsb for sysdiv2 when div400 is set, this bit becomes the lsb of sysdiv2 . if div400 is clear, this bit is not used. see table 5-6 on page 192 for programming guidelines. this bit can only be set or cleared when div400 is set. 1 r/w sysdiv2lsb 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 21:14 power-down pll 2 description value the pll is powered down. 1 the pll operates normally. 0 1 r/w pwrdn2 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12 pll bypass 2 description value the system clock is derived from the osc source and divided by the divisor specified by sysdiv2. 1 the system clock is the pll output clock divided by the divisor specified by sysdiv2. 0 see table 5-6 on page 192 for programming guidelines. note: the adc must be clocked from the pll or directly from a 16-mhz clock source to operate properly. 1 r/w bypass2 11 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 10:7 219 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field oscillator source 2 selects the input source for the osc. the values are: description value mosc main oscillator 0x0 piosc precision internal oscillator 0x1 piosc/4 precision internal oscillator / 4 0x2 30 khz 30-khz internal oscillator 0x3 reserved 0x4-0x6 32.768 khz 32.768-khz external oscillator 0x7 0x1 r/w oscsrc2 6:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 march 20, 2011 220 texas instruments-advance information system control register 11: main oscillator control (moscctl), offset 0x07c this register provides the ability to enable the mosc clock verification circuit. when enabled, this circuit monitors the frequency of the mosc to verify that the oscillator is operating within specified limits. if the clock goes invalid after being enabled, the microcontroller issues a power-on reset and reboots to the nmi handler. main oscillator control (moscctl) base 0x400f.e000 offset 0x07c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cval reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 clock validation for mosc description value the mosc monitor circuit is enabled. 1 the mosc monitor circuit is disabled. 0 0 r/w cval 0 221 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: deep sleep clock configuration (dslpclkcfg), offset 0x144 this register provides configuration information for the hardware control of deep sleep mode. deep sleep clock configuration (dslpclkcfg) base 0x400f.e000 offset 0x144 type r/w, reset 0x0780.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved dsdivoride reserved ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w ro ro ro type 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved dsoscsrc reserved ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:29 divider field override if deep-sleep mode is enabled when the pll is running, the pll is disabled. this 6-bit field contains a system divider field that overrides the sysdiv field in the rcc register or the sysdiv2 field in the rcc2 register during deep sleep. this divider is applied to the source selected by the dsoscsrc field. description value /10x0 /20x1 /30x2 /40x3 ...... /640x3f 0x0f r/w dsdivoride 28:23 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 22:7 march 20, 2011 222 texas instruments-advance information system control description reset type name bit/field clock source specifies the clock source during deep-sleep mode. description value mosc use the main oscillator as the source. 0x0 note: if the piosc is being used as the clock reference for the pll, the piosc is the clock source instead of mosc in deep-sleep mode. piosc use the precision internal 16-mhz oscillator as the source. 0x1 reserved 0x2 30 khz use the 30-khz internal oscillator as the source. 0x3 reserved 0x4-0x6 32.768 khz use the hibernation module 32.768-khz external oscillator as the source. 0x7 0x0 r/w dsoscsrc 6:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 223 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 13: precision internal oscillator calibration (piosccal), offset 0x150 this register provides the ability to update or recalibrate the precision internal oscillator. note that a 32.768-khz oscillator must be used as the hibernation module clock source for the user to be able to calibrate the piosc. precision internal oscillator calibration (piosccal) base 0x400f.e000 offset 0x150 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved uten ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ut reserved update cal reserved r/w r/w r/w r/w r/w r/w r/w ro r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field use user trim value description value the trim value in bits[6:0] of this register are used for any update trim operation. 1 the factory calibration value is used for an update trim operation. 0 0 r/w uten 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 30:10 start calibration description value starts a new calibration of the piosc. results are in the pioscstat register. the resulting trim value from the operation is active in the piosc after the calibration completes. the result overrides any previous update trim operation whether the calibration passes or fails. 1 no action. 0 this bit is auto-cleared after it is set. 0 r/w cal 9 update trim description value updates the piosc trim value with the ut bit or the dt bit in the pioscstat register. used with uten. 1 no action. 0 this bit is auto-cleared after the update. 0 r/w update 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 march 20, 2011 224 texas instruments-advance information system control description reset type name bit/field user trim value user trim value that can be loaded into the piosc. refer to main pll frequency configuration on page 194 for more information on calibrating the piosc. 0x0 r/w ut 6:0 225 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 14: precision internal oscillator statistics (pioscstat), offset 0x154 this register provides the user information on the piosc calibration. note that a 32.768-khz oscillator must be used as the hibernation module clock source for the user to be able to calibrate the piosc. precision internal oscillator statistics (pioscstat) base 0x400f.e000 offset 0x154 type ro, reset 0x0000.0040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dt reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ct reserved result reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 default trim value this field contains the default trim value. this value is loaded into the piosc after every full power-up. - ro dt 22:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:10 calibration result description value calibration has not been attempted. 0x0 the last calibration operation completed to meet 1% accuracy. 0x1 the last calibration operation failed to meet 1% accuracy. 0x2 reserved 0x3 0 ro result 9:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 calibration trim value this field contains the trim value from the last calibration operation. after factory calibration ct and dt are the same. 0x40 ro ct 6:0 march 20, 2011 226 texas instruments-advance information system control register 15: i 2 s mclk configuration (i2smclkcfg), offset 0x170 this register configures the receive and transmit fractional clock dividers for the for the i 2 s master transmit and receive clocks (i2s0txmclk and i2s0rxmclk). varying the integer and fractional inputs for the clocks allows greater accuracy in hitting the target i 2 s clock frequencies. refer to clock control on page 756 for combinations of the txi and txf bits and the rxi and rxf bits that provide mclk frequencies within acceptable error limits. i2s mclk configuration (i2smclkcfg) base 0x400f.e000 offset 0x170 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rxf rxi reserved rxen r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txf txi reserved txen r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field rx clock enable description value the i 2 s receive clock generator is enabled. 1 the i 2 s receive clock generator is disabled. if the rxslv bit in the i 2 s module configuration (i2scfg) register is set, then the i2s0rxmclk must be externally generated. 0 0 r/w rxen 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 30 rx clock integer input this field contains the integer input for the receive clock generator. 0x0 r/w rxi 29:20 rx clock fractional input this field contains the fractional input for the receive clock generator. 0x0 r/w rxf 19:16 tx clock enable description value the i 2 s transmit clock generator is enabled. 1 the i 2 s transmit clock generator is disabled. if the txslv bit in the i 2 s module configuration (i2scfg) register is set, then the i2s0txmclk must be externally generated. 0 0 r/w txen 15 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 14 227 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field tx clock integer input this field contains the integer input for the transmit clock generator. 0x00 r/w txi 13:4 tx clock fractional input this field contains the fractional input for the transmit clock generator. 0x0 r/w txf 3:0 march 20, 2011 228 texas instruments-advance information system control register 16: device identification 1 (did1), offset 0x004 this register identifies the device family, part number, temperature range, and package type. each microcontroller is uniquely identified by the combined values of the class field in the did0 register and the partno field in the did1 register. device identification 1 (did1) base 0x400f.e000 offset 0x004 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 partno fam ver ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 1 1 0 1 0 0 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 qual rohs pkg temp reserved pincount ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - 1 - - - - - 0 0 0 0 0 0 1 0 reset description reset type name bit/field did1 version this field defines the did1 register format version. the version number is numeric. the value of the ver field is encoded as follows (all other encodings are reserved): description value second version of the did1 register format. 0x1 0x1 ro ver 31:28 family this field provides the family identification of the device within the luminary micro product portfolio. the value is encoded as follows (all other encodings are reserved): description value stellaris family of microcontollers, that is, all devices with external part numbers starting with lm3s. 0x0 0x0 ro fam 27:24 part number this field provides the part number of the device within the family. the value is encoded as follows (all other encodings are reserved): description value lm3s1p51 0xb2 0xb2 ro partno 23:16 package pin count this field specifies the number of pins on the device package. the value is encoded as follows (all other encodings are reserved): description value 100-pin package 0x2 0x2 ro pincount 15:13 229 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:8 temperature range this field specifies the temperature rating of the device. the value is encoded as follows (all other encodings are reserved): description value commercial temperature range (0c to 70c) 0x0 industrial temperature range (-40c to 85c) 0x1 extended temperature range (-40c to 105c) 0x2 - ro temp 7:5 package type this field specifies the package type. the value is encoded as follows (all other encodings are reserved): description value soic package 0x0 lqfp package 0x1 bga package 0x2 - ro pkg 4:3 rohs-compliance this bit specifies whether the device is rohs-compliant. a 1 indicates the part is rohs-compliant. 1 ro rohs 2 qualification status this field specifies the qualification status of the device. the value is encoded as follows (all other encodings are reserved): description value engineering sample (unqualified) 0x0 pilot production (unqualified) 0x1 fully qualified 0x2 - ro qual 1:0 march 20, 2011 230 texas instruments-advance information system control register 17: device capabilities 0 (dc0), offset 0x008 this register is predefined by the part and can be used to verify features. device capabilities 0 (dc0) base 0x400f.e000 offset 0x008 type ro, reset 0x005f.001f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sramsz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 flashsz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field sram size indicates the size of the on-chip sram memory. description value 24 kb of sram 0x005f 0x005f ro sramsz 31:16 flash size indicates the size of the on-chip flash memory. description value 64 kb of flash 0x001f 0x001f ro flashsz 15:0 231 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 18: device capabilities 1 (dc1), offset 0x010 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 1 (dc1) base 0x400f.e000 offset 0x010 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved wdt1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 jtag swd swo wdt0 pll tempsns hib mpu maxadc0spd maxadc1spd minsysdiv ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 - - - - reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 watchdog timer1 present when set, indicates that watchdog timer 1 is present. 1 ro wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:21 pwm module present when set, indicates that the pwm module is present. 1 ro pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 adc module 1 present when set, indicates that adc module 1 is present. 1 ro adc1 17 adc module 0 present when set, indicates that adc module 0 is present 1 ro adc0 16 system clock divider minimum 4-bit divider value for system clock. the reset value is hardware-dependent. see the rcc register for how to change the system clock divisor using the sysdiv bit. description value specifies an 80-mhz cpu clock with a pll divider of 2.5. 0x1 specifies a 66.67-mhz cpu clock with a pll divider of 3. 0x2 specifies a 50-mhz cpu clock with a pll divider of 4. 0x3 specifies a 25-mhz clock with a pll divider of 8. 0x7 specifies a 20-mhz clock with a pll divider of 10. 0x9 - ro minsysdiv 15:12 march 20, 2011 232 texas instruments-advance information system control description reset type name bit/field max adc1 speed this field indicates the maximum rate at which the adc samples data. description value 1m samples/second 0x3 0x3 ro maxadc1spd 11:10 max adc0 speed this field indicates the maximum rate at which the adc samples data. description value 1m samples/second 0x3 0x3 ro maxadc0spd 9:8 mpu present when set, indicates that the cortex-m3 memory protection unit (mpu) module is present. see the "cortex-m3 peripherals" chapter for details on the mpu. 1 ro mpu 7 hibernation module present when set, indicates that the hibernation module is present. 1 ro hib 6 temp sensor present when set, indicates that the on-chip temperature sensor is present. 1 ro tempsns 5 pll present when set, indicates that the on-chip phase locked loop (pll) is present. 1 ro pll 4 watchdog timer 0 present when set, indicates that watchdog timer 0 is present. 1 ro wdt0 3 swo trace port present when set, indicates that the serial wire output (swo) trace port is present. 1 ro swo 2 swd present when set, indicates that the serial wire debugger (swd) is present. 1 ro swd 1 jtag present when set, indicates that the jtag debugger interface is present. 1 ro jtag 0 233 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 19: device capabilities 2 (dc2), offset 0x014 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 2 (dc2) base 0x400f.e000 offset 0x014 type ro, reset 0x130f.5337 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 reserved i2s0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 i2s module 0 present when set, indicates that i2s module 0 is present. 1 ro i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 analog comparator 1 present when set, indicates that analog comparator 1 is present. 1 ro comp1 25 analog comparator 0 present when set, indicates that analog comparator 0 is present. 1 ro comp0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer module 3 present when set, indicates that general-purpose timer module 3 is present. 1 ro timer3 19 timer module 2 present when set, indicates that general-purpose timer module 2 is present. 1 ro timer2 18 timer module 1 present when set, indicates that general-purpose timer module 1 is present. 1 ro timer1 17 timer module 0 present when set, indicates that general-purpose timer module 0 is present. 1 ro timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 march 20, 2011 234 texas instruments-advance information system control description reset type name bit/field i2c module 1 present when set, indicates that i2c module 1 is present. 1 ro i2c1 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c module 0 present when set, indicates that i2c module 0 is present. 1 ro i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei module 1 present when set, indicates that qei module 1 is present. 1 ro qei1 9 qei module 0 present when set, indicates that qei module 0 is present. 1 ro qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi module 1 present when set, indicates that ssi module 1 is present. 1 ro ssi1 5 ssi module 0 present when set, indicates that ssi module 0 is present. 1 ro ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart module 2 present when set, indicates that uart module 2 is present. 1 ro uart2 2 uart module 1 present when set, indicates that uart module 1 is present. 1 ro uart1 1 uart module 0 present when set, indicates that uart module 0 is present. 1 ro uart0 0 235 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 20: device capabilities 3 (dc3), offset 0x018 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 3 (dc3) base 0x400f.e000 offset 0x018 type ro, reset 0xbfff.8fff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0ain0 adc0ain1 adc0ain2 adc0ain3 adc0ain4 adc0ain5 adc0ain6 adc0ain7 ccp0 ccp1 ccp2 ccp3 ccp4 ccp5 reserved 32khz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 c0minus c0plus c0o c1minus c1plus c1o reserved pwmfault ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 reset description reset type name bit/field 32khz input clock available when set, indicates an even ccp pin is present and can be used as a 32-khz input clock. 1 ro 32khz 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 30 ccp5 pin present when set, indicates that capture/compare/pwm pin 5 is present. 1 ro ccp5 29 ccp4 pin present when set, indicates that capture/compare/pwm pin 4 is present. 1 ro ccp4 28 ccp3 pin present when set, indicates that capture/compare/pwm pin 3 is present. 1 ro ccp3 27 ccp2 pin present when set, indicates that capture/compare/pwm pin 2 is present. 1 ro ccp2 26 ccp1 pin present when set, indicates that capture/compare/pwm pin 1 is present. 1 ro ccp1 25 ccp0 pin present when set, indicates that capture/compare/pwm pin 0 is present. 1 ro ccp0 24 adc module 0 ain7 pin present when set, indicates that adc module 0 input pin 7 is present. 1 ro adc0ain7 23 adc module 0 ain6 pin present when set, indicates that adc module 0 input pin 6 is present. 1 ro adc0ain6 22 adc module 0 ain5 pin present when set, indicates that adc module 0 input pin 5 is present. 1 ro adc0ain5 21 adc module 0 ain4 pin present when set, indicates that adc module 0 input pin 4 is present. 1 ro adc0ain4 20 march 20, 2011 236 texas instruments-advance information system control description reset type name bit/field adc module 0 ain3 pin present when set, indicates that adc module 0 input pin 3 is present. 1 ro adc0ain3 19 adc module 0 ain2 pin present when set, indicates that adc module 0 input pin 2 is present. 1 ro adc0ain2 18 adc module 0 ain1 pin present when set, indicates that adc module 0 input pin 1 is present. 1 ro adc0ain1 17 adc module 0 ain0 pin present when set, indicates that adc module 0 input pin 0 is present. 1 ro adc0ain0 16 pwm fault pin present when set, indicates that a pwm fault pin is present. see dc5 for specific fault pins on this device. 1 ro pwmfault 15 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 14:12 c1o pin present when set, indicates that the analog comparator 1 output pin is present. 1 ro c1o 11 c1+ pin present when set, indicates that the analog comparator 1 (+) input pin is present. 1 ro c1plus 10 c1- pin present when set, indicates that the analog comparator 1 (-) input pin is present. 1 ro c1minus 9 c0o pin present when set, indicates that the analog comparator 0 output pin is present. 1 ro c0o 8 c0+ pin present when set, indicates that the analog comparator 0 (+) input pin is present. 1 ro c0plus 7 c0- pin present when set, indicates that the analog comparator 0 (-) input pin is present. 1 ro c0minus 6 pwm5 pin present when set, indicates that the pwm pin 5 is present. 1 ro pwm5 5 pwm4 pin present when set, indicates that the pwm pin 4 is present. 1 ro pwm4 4 pwm3 pin present when set, indicates that the pwm pin 3 is present. 1 ro pwm3 3 pwm2 pin present when set, indicates that the pwm pin 2 is present. 1 ro pwm2 2 pwm1 pin present when set, indicates that the pwm pin 1 is present. 1 ro pwm1 1 pwm0 pin present when set, indicates that the pwm pin 0 is present. 1 ro pwm0 0 237 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 21: device capabilities 4 (dc4), offset 0x01c this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 4 (dc4) base 0x400f.e000 offset 0x01c type ro, reset 0x0004.f1ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pical reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved rom udma ccp6 ccp7 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:19 piosc calibrate when set, indicates that the piosc can be calibrated by software. 1 ro pical 18 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 17:16 ccp7 pin present when set, indicates that capture/compare/pwm pin 7 is present. 1 ro ccp7 15 ccp6 pin present when set, indicates that capture/compare/pwm pin 6 is present. 1 ro ccp6 14 micro-dma module present when set, indicates that the micro-dma module present. 1 ro udma 13 internal code rom present when set, indicates that internal code rom is present. 1 ro rom 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:9 gpio port j present when set, indicates that gpio port j is present. 1 ro gpioj 8 gpio port h present when set, indicates that gpio port h is present. 1 ro gpioh 7 gpio port g present when set, indicates that gpio port g is present. 1 ro gpiog 6 march 20, 2011 238 texas instruments-advance information system control description reset type name bit/field gpio port f present when set, indicates that gpio port f is present. 1 ro gpiof 5 gpio port e present when set, indicates that gpio port e is present. 1 ro gpioe 4 gpio port d present when set, indicates that gpio port d is present. 1 ro gpiod 3 gpio port c present when set, indicates that gpio port c is present. 1 ro gpioc 2 gpio port b present when set, indicates that gpio port b is present. 1 ro gpiob 1 gpio port a present when set, indicates that gpio port a is present. 1 ro gpioa 0 239 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 22: device capabilities 5 (dc5), offset 0x020 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 5 (dc5) base 0x400f.e000 offset 0x020 type ro, reset 0x0f30.003f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pwmesync pwmeflt reserved pwmfault0 pwmfault1 pwmfault2 pwmfault3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:28 pwm fault 3 pin present when set, indicates that the pwm fault 3 pin is present. 1 ro pwmfault3 27 pwm fault 2 pin present when set, indicates that the pwm fault 2 pin is present. 1 ro pwmfault2 26 pwm fault 1 pin present when set, indicates that the pwm fault 1 pin is present. 1 ro pwmfault1 25 pwm fault 0 pin present when set, indicates that the pwm fault 0 pin is present. 1 ro pwmfault0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:22 pwm extended fault active when set, indicates that the pwm extended fault feature is active. 1 ro pwmeflt 21 pwm extended sync active when set, indicates that the pwm extended sync feature is active. 1 ro pwmesync 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:6 pwm5 pin present when set, indicates that the pwm pin 5 is present. 1 ro pwm5 5 pwm4 pin present when set, indicates that the pwm pin 4 is present. 1 ro pwm4 4 march 20, 2011 240 texas instruments-advance information system control description reset type name bit/field pwm3 pin present when set, indicates that the pwm pin 3 is present. 1 ro pwm3 3 pwm2 pin present when set, indicates that the pwm pin 2 is present. 1 ro pwm2 2 pwm1 pin present when set, indicates that the pwm pin 1 is present. 1 ro pwm1 1 pwm0 pin present when set, indicates that the pwm pin 0 is present. 1 ro pwm0 0 241 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 23: device capabilities 6 (dc6), offset 0x024 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 6 (dc6) base 0x400f.e000 offset 0x024 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:0 march 20, 2011 242 texas instruments-advance information system control register 24: device capabilities 7 (dc7), offset 0x028 this register is predefined by the part and can be used to verify udma channel features. a 1 indicates the channel is available on this device; a 0 that the channel is only available on other devices in the family. most channels have primary and secondary assignments. if the primary function is not available on this microcontroller, the secondary function becomes the primary function. if the secondary function is not available, the primary function is the only option. device capabilities 7 (dc7) base 0x400f.e000 offset 0x028 type ro, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dmach16 dmach17 dmach18 dmach19 dmach20 dmach21 dmach22 dmach23 dmach24 dmach25 dmach26 dmach27 dmach28 dmach29 dmach30 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dmach0 dmach1 dmach2 dmach3 dmach4 dmach5 dmach6 dmach7 dmach8 dmach9 dmach10 dmach11 dmach12 dmach13 dmach14 dmach15 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field reserved reserved for udma channel 31. 1 ro reserved 31 sw when set, indicates udma channel 30 is available for software transfers. 1 ro dmach30 30 i2s0_tx / can1_tx when set, indicates udma channel 29 is available and connected to the transmit path of i2s module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of can module 1 transmit. 1 ro dmach29 29 i2s0_rx / can1_rx when set, indicates udma channel 28 is available and connected to the receive path of i2s module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of can module 1 receive. 1 ro dmach28 28 can1_tx / adc1_ss3 when set, indicates udma channel 27 is available and connected to the transmit path of can module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of adc module 1 sample sequencer 3. 1 ro dmach27 27 can1_rx / adc1_ss2 when set, indicates udma channel 26 is available and connected to the receive path of can module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of adc module 1 sample sequencer 2. 1 ro dmach26 26 243 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ssi1_tx / adc1_ss1 when set, indicates udma channel 25 is available and connected to the transmit path of ssi module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of adc module 1 sample sequencer 1. 1 ro dmach25 25 ssi1_rx / adc1_ss0 when set, indicates udma channel 24 is available and connected to the receive path of ssi module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of adc module 1 sample sequencer 0. 1 ro dmach24 24 uart1_tx / can2_tx when set, indicates udma channel 23 is available and connected to the transmit path of uart module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of can module 2 transmit. 1 ro dmach23 23 uart1_rx / can2_rx when set, indicates udma channel 22 is available and connected to the receive path of uart module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of can module 2 receive. 1 ro dmach22 22 timer1b / epi0_wfifo when set, indicates udma channel 21 is available and connected to timer 1b.if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of epi module write fifo (wrifo). 1 ro dmach21 21 timer1a / epi0_nbrfifo when set, indicates udma channel 20 is available and connected to timer 1a. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of epi module 0 non-blocking read fifo (nbrfifo). 1 ro dmach20 20 timer0b / timer1b when set, indicates udma channel 19 is available and connected to timer 0b. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 1b. 1 ro dmach19 19 timer0a / timer1a when set, indicates udma channel 18 is available and connected to timer 0a. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 1a. 1 ro dmach18 18 adc0_ss3 when set, indicates udma channel 17 is available and connected to adc module 0 sample sequencer 3. 1 ro dmach17 17 adc0_ss2 when set, indicates udma channel 16 is available and connected to adc module 0 sample sequencer 2. 1 ro dmach16 16 march 20, 2011 244 texas instruments-advance information system control description reset type name bit/field adc0_ss1 / timer2b when set, indicates udma channel 15 is available and connected to adc module 0 sample sequencer 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2b. 1 ro dmach15 15 adc0_ss0 / timer2a when set, indicates udma channel 14 is available and connected to adc module 0 sample sequencer 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2a. 1 ro dmach14 14 can0_tx / uart2_tx when set, indicates udma channel 13 is available and connected to the transmit path of can module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 2 transmit. 1 ro dmach13 13 can0_rx / uart2_rx when set, indicates udma channel 12 is available and connected to the receive path of can module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 2 receive. 1 ro dmach12 12 ssi0_tx / ssi1_tx when set, indicates udma channel 11 is available and connected to the transmit path of ssi module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of ssi module 1 transmit. 1 ro dmach11 11 ssi0_rx / ssi1_rx when set, indicates udma channel 10 is available and connected to the receive path of ssi module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of ssi module 1 receive. 1 ro dmach10 10 uart0_tx / uart1_tx when set, indicates udma channel 9 is available and connected to the transmit path of uart module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the seondary channel assignment of uart module 1 transmit. 1 ro dmach9 9 uart0_rx / uart1_rx when set, indicates udma channel 8 is available and connected to the receive path of uart module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 1 receive. 1 ro dmach8 8 eth_tx / timer2b when set, indicates udma channel 7 is available and connected to the transmit path of the ethernet module. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2b. 1 ro dmach7 7 eth_rx / timer2a when set, indicates udma channel 6 is available and connected to the receive path of the ethernet module. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2a. 1 ro dmach6 6 245 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field usb_ep3_tx / timer2b when set, indicates udma channel 5 is available and connected to the transmit path of usb endpoint 3. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2b. 1 ro dmach5 5 usb_ep3_rx / timer2a when set, indicates udma channel 4 is available and connected to the receive path of usb endpoint 3. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2a. 1 ro dmach4 4 usb_ep2_tx / timer3b when set, indicates udma channel 3 is available and connected to the transmit path of usb endpoint 2. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 3b. 1 ro dmach3 3 usb_ep2_rx / timer3a when set, indicates udma channel 2 is available and connected to the receive path of usb endpoint 2. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 3a. 1 ro dmach2 2 usb_ep1_tx / uart2_tx when set, indicates udma channel 1 is available and connected to the transmit path of usb endpoint 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 2 transmit. 1 ro dmach1 1 usb_ep1_rx / uart2_rx when set, indicates udma channel 0 is available and connected to the receive path of usb endpoint 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 2 receive. 1 ro dmach0 0 march 20, 2011 246 texas instruments-advance information system control register 25: device capabilities 8 adc channels (dc8), offset 0x02c this register is predefined by the part and can be used to verify features. device capabilities 8 adc channels (dc8) base 0x400f.e000 offset 0x02c type ro, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc1ain0 adc1ain1 adc1ain2 adc1ain3 adc1ain4 adc1ain5 adc1ain6 adc1ain7 adc1ain8 adc1ain9 adc1ain10 adc1ain11 adc1ain12 adc1ain13 adc1ain14 adc1ain15 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adc0ain0 adc0ain1 adc0ain2 adc0ain3 adc0ain4 adc0ain5 adc0ain6 adc0ain7 adc0ain8 adc0ain9 adc0ain10 adc0ain11 adc0ain12 adc0ain13 adc0ain14 adc0ain15 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field adc module 1 ain15 pin present when set, indicates that adc module 1 input pin 15 is present. 1 ro adc1ain15 31 adc module 1 ain14 pin present when set, indicates that adc module 1 input pin 14 is present. 1 ro adc1ain14 30 adc module 1 ain13 pin present when set, indicates that adc module 1 input pin 13 is present. 1 ro adc1ain13 29 adc module 1 ain12 pin present when set, indicates that adc module 1 input pin 12 is present. 1 ro adc1ain12 28 adc module 1 ain11 pin present when set, indicates that adc module 1 input pin 11 is present. 1 ro adc1ain11 27 adc module 1 ain10 pin present when set, indicates that adc module 1 input pin 10 is present. 1 ro adc1ain10 26 adc module 1 ain9 pin present when set, indicates that adc module 1 input pin 9 is present. 1 ro adc1ain9 25 adc module 1 ain8 pin present when set, indicates that adc module 1 input pin 8 is present. 1 ro adc1ain8 24 adc module 1 ain7 pin present when set, indicates that adc module 1 input pin 7 is present. 1 ro adc1ain7 23 adc module 1 ain6 pin present when set, indicates that adc module 1 input pin 6 is present. 1 ro adc1ain6 22 adc module 1 ain5 pin present when set, indicates that adc module 1 input pin 5 is present. 1 ro adc1ain5 21 adc module 1 ain4 pin present when set, indicates that adc module 1 input pin 4 is present. 1 ro adc1ain4 20 adc module 1 ain3 pin present when set, indicates that adc module 1 input pin 3 is present. 1 ro adc1ain3 19 247 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field adc module 1 ain2 pin present when set, indicates that adc module 1 input pin 2 is present. 1 ro adc1ain2 18 adc module 1 ain1 pin present when set, indicates that adc module 1 input pin 1 is present. 1 ro adc1ain1 17 adc module 1 ain0 pin present when set, indicates that adc module 1 input pin 0 is present. 1 ro adc1ain0 16 adc module 0 ain15 pin present when set, indicates that adc module 0 input pin 15 is present. 1 ro adc0ain15 15 adc module 0 ain14 pin present when set, indicates that adc module 0 input pin 14 is present. 1 ro adc0ain14 14 adc module 0 ain13 pin present when set, indicates that adc module 0 input pin 13 is present. 1 ro adc0ain13 13 adc module 0 ain12 pin present when set, indicates that adc module 0 input pin 12 is present. 1 ro adc0ain12 12 adc module 0 ain11 pin present when set, indicates that adc module 0 input pin 11 is present. 1 ro adc0ain11 11 adc module 0 ain10 pin present when set, indicates that adc module 0 input pin 10 is present. 1 ro adc0ain10 10 adc module 0 ain9 pin present when set, indicates that adc module 0 input pin 9 is present. 1 ro adc0ain9 9 adc module 0 ain8 pin present when set, indicates that adc module 0 input pin 8 is present. 1 ro adc0ain8 8 adc module 0 ain7 pin present when set, indicates that adc module 0 input pin 7 is present. 1 ro adc0ain7 7 adc module 0 ain6 pin present when set, indicates that adc module 0 input pin 6 is present. 1 ro adc0ain6 6 adc module 0 ain5 pin present when set, indicates that adc module 0 input pin 5 is present. 1 ro adc0ain5 5 adc module 0 ain4 pin present when set, indicates that adc module 0 input pin 4 is present. 1 ro adc0ain4 4 adc module 0 ain3 pin present when set, indicates that adc module 0 input pin 3 is present. 1 ro adc0ain3 3 adc module 0 ain2 pin present when set, indicates that adc module 0 input pin 2 is present. 1 ro adc0ain2 2 adc module 0 ain1 pin present when set, indicates that adc module 0 input pin 1 is present. 1 ro adc0ain1 1 adc module 0 ain0 pin present when set, indicates that adc module 0 input pin 0 is present. 1 ro adc0ain0 0 march 20, 2011 248 texas instruments-advance information system control register 26: device capabilities 9 adc digital comparators (dc9), offset 0x190 this register is predefined by the part and can be used to verify features. device capabilities 9 adc digital comparators (dc9) base 0x400f.e000 offset 0x190 type ro, reset 0x00ff.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc1dc0 adc1dc1 adc1dc2 adc1dc3 adc1dc4 adc1dc5 adc1dc6 adc1dc7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adc0dc0 adc0dc1 adc0dc2 adc0dc3 adc0dc4 adc0dc5 adc0dc6 adc0dc7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:24 adc1 dc7 present when set, indicates that adc module 1 digital comparator 7 is present. 1 ro adc1dc7 23 adc1 dc6 present when set, indicates that adc module 1 digital comparator 6 is present. 1 ro adc1dc6 22 adc1 dc5 present when set, indicates that adc module 1 digital comparator 5 is present. 1 ro adc1dc5 21 adc1 dc4 present when set, indicates that adc module 1 digital comparator 4 is present. 1 ro adc1dc4 20 adc1 dc3 present when set, indicates that adc module 1 digital comparator 3 is present. 1 ro adc1dc3 19 adc1 dc2 present when set, indicates that adc module 1 digital comparator 2 is present. 1 ro adc1dc2 18 adc1 dc1 present when set, indicates that adc module 1 digital comparator 1 is present. 1 ro adc1dc1 17 adc1 dc0 present when set, indicates that adc module 1 digital comparator 0 is present. 1 ro adc1dc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:8 adc0 dc7 present when set, indicates that adc module 0 digital comparator 7 is present. 1 ro adc0dc7 7 adc0 dc6 present when set, indicates that adc module 0 digital comparator 6 is present. 1 ro adc0dc6 6 249 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field adc0 dc5 present when set, indicates that adc module 0 digital comparator 5 is present. 1 ro adc0dc5 5 adc0 dc4 present when set, indicates that adc module 0 digital comparator 4 is present. 1 ro adc0dc4 4 adc0 dc3 present when set, indicates that adc module 0 digital comparator 3 is present. 1 ro adc0dc3 3 adc0 dc2 present when set, indicates that adc module 0 digital comparator 2 is present. 1 ro adc0dc2 2 adc0 dc1 present when set, indicates that adc module 0 digital comparator 1 is present. 1 ro adc0dc1 1 adc0 dc0 present when set, indicates that adc module 0 digital comparator 0 is present. 1 ro adc0dc0 0 march 20, 2011 250 texas instruments-advance information system control register 27: non-volatile memory information (nvmstat), offset 0x1a0 this register is predefined by the part and can be used to verify features. non-volatile memory information (nvmstat) base 0x400f.e000 offset 0x1a0 type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fwb reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:1 32 word flash write buffer active when set, indicates that the 32 word flash memory write buffer feature is active. 1 ro fwb 0 251 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 28: run mode clock gating control register 0 (rcgc0), offset 0x100 this register controls the clock gating logic in normal run mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 0 (rcgc0) base 0x400f.e000 offset 0x100 type r/w, reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved wdt1 reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wdt0 reserved hib reserved maxadc0spd maxadc1spd reserved ro ro ro r/w ro ro r/w ro r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 wdt1 clock gating control this bit controls the clock gating for the watchdog timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 march 20, 2011 252 texas instruments-advance information system control description reset type name bit/field adc1 clock gating control this bit controls the clock gating for sar adc module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc1 17 adc0 clock gating control this bit controls the clock gating for adc module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:12 adc1 sample speed this field sets the rate at which adc module 1 samples data. you cannot set the rate higher than the maximum rate. you can set the sample rate by setting the maxadc1spd bit as follows (all other encodings are reserved): description value 1m samples/second 0x3 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadc1spd 11:10 adc0 sample speed this field sets the rate at which adc0 samples data. you cannot set the rate higher than the maximum rate. you can set the sample rate by setting the maxadc0spd bit as follows (all other encodings are reserved): description value 1m samples/second 0x3 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadc0spd 9:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hib clock gating control this bit controls the clock gating for the hibernation module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 1 r/w hib 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 253 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field wdt0 clock gating control this bit controls the clock gating for the watchdog timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt0 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 march 20, 2011 254 texas instruments-advance information system control register 29: sleep mode clock gating control register 0 (scgc0), offset 0x110 this register controls the clock gating logic in sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 0 (scgc0) base 0x400f.e000 offset 0x110 type r/w, reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved wdt1 reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wdt0 reserved hib reserved maxadc0spd maxadc1spd reserved ro ro ro r/w ro ro r/w ro r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 wdt1 clock gating control this bit controls the clock gating for watchdog timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 255 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field adc1 clock gating control this bit controls the clock gating for adc module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc1 17 adc0 clock gating control this bit controls the clock gating for adc module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:12 adc1 sample speed this field sets the rate at which adc module 1 samples data. you cannot set the rate higher than the maximum rate. you can set the sample rate by setting the maxadc1spd bit as follows (all other encodings are reserved): description value 1m samples/second 0x3 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadc1spd 11:10 adc0 sample speed this field sets the rate at which adc module 0 samples data. you cannot set the rate higher than the maximum rate. you can set the sample rate by setting the maxadc0spd bit as follows (all other encodings are reserved): description value 1m samples/second 0x3 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadc0spd 9:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hib clock gating control this bit controls the clock gating for the hibernation module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 1 r/w hib 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 march 20, 2011 256 texas instruments-advance information system control description reset type name bit/field wdt0 clock gating control this bit controls the clock gating for the watchdog timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt0 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 257 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 30: deep sleep mode clock gating control register 0 (dcgc0), offset 0x120 this register controls the clock gating logic in deep-sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 0 (dcgc0) base 0x400f.e000 offset 0x120 type r/w, reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved wdt1 reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wdt0 reserved hib reserved ro ro ro r/w ro ro r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 wdt1 clock gating control this bit controls the clock gating for the watchdog timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 march 20, 2011 258 texas instruments-advance information system control description reset type name bit/field adc1 clock gating control this bit controls the clock gating for adc module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc1 17 adc0 clock gating control this bit controls the clock gating for adc module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:7 hib clock gating control this bit controls the clock gating for the hibernation module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 1 r/w hib 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt0 clock gating control this bit controls the clock gating for the watchdog timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt0 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 259 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 31: run mode clock gating control register 1 (rcgc1), offset 0x104 this register controls the clock gating logic in normal run mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 1 (rcgc1) base 0x400f.e000 offset 0x104 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 reserved i2s0 reserved r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved r/w r/w r/w ro r/w r/w ro ro r/w r/w ro ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 i2s0 clock gating this bit controls the clock gating for i2s module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp0 24 march 20, 2011 260 texas instruments-advance information system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer 3 clock gating control this bit controls the clock gating for general-purpose timer module 3. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer3 19 timer 2 clock gating control this bit controls the clock gating for general-purpose timer module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer2 18 timer 1 clock gating control this bit controls the clock gating for general-purpose timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer1 17 timer 0 clock gating control this bit controls the clock gating for general-purpose timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c1 clock gating control this bit controls the clock gating for i2c module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c1 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei1 9 261 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi1 clock gating control this bit controls the clock gating for ssi module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi1 5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart2 clock gating control this bit controls the clock gating for uart module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart2 2 uart1 clock gating control this bit controls the clock gating for uart module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart1 1 uart0 clock gating control this bit controls the clock gating for uart module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart0 0 march 20, 2011 262 texas instruments-advance information system control register 32: sleep mode clock gating control register 1 (scgc1), offset 0x114 this register controls the clock gating logic in sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 1 (scgc1) base 0x400f.e000 offset 0x114 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 reserved i2s0 reserved r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved r/w r/w r/w ro r/w r/w ro ro r/w r/w ro ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 i2s0 clock gating this bit controls the clock gating for i2s module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp0 24 263 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer 3 clock gating control this bit controls the clock gating for general-purpose timer module 3. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer3 19 timer 2 clock gating control this bit controls the clock gating for general-purpose timer module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer2 18 timer 1 clock gating control this bit controls the clock gating for general-purpose timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer1 17 timer 0 clock gating control this bit controls the clock gating for general-purpose timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c1 clock gating control this bit controls the clock gating for i2c module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c1 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei1 9 march 20, 2011 264 texas instruments-advance information system control description reset type name bit/field qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi1 clock gating control this bit controls the clock gating for ssi module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi1 5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart2 clock gating control this bit controls the clock gating for uart module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart2 2 uart1 clock gating control this bit controls the clock gating for uart module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart1 1 uart0 clock gating control this bit controls the clock gating for uart module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart0 0 265 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 33: deep-sleep mode clock gating control register 1 (dcgc1), offset 0x124 this register controls the clock gating logic in deep-sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep-sleep mode clock gating control register 1 (dcgc1) base 0x400f.e000 offset 0x124 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 reserved i2s0 reserved r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved r/w r/w r/w ro r/w r/w ro ro r/w r/w ro ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 i2s0 clock gating this bit controls the clock gating for i2s module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp0 24 march 20, 2011 266 texas instruments-advance information system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer 3 clock gating control this bit controls the clock gating for general-purpose timer module 3. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer3 19 timer 2 clock gating control this bit controls the clock gating for general-purpose timer module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer2 18 timer 1 clock gating control this bit controls the clock gating for general-purpose timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer1 17 timer 0 clock gating control this bit controls the clock gating for general-purpose timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c1 clock gating control this bit controls the clock gating for i2c module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c1 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei1 9 267 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi1 clock gating control this bit controls the clock gating for ssi module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi1 5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart2 clock gating control this bit controls the clock gating for uart module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart2 2 uart1 clock gating control this bit controls the clock gating for uart module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart1 1 uart0 clock gating control this bit controls the clock gating for uart module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart0 0 march 20, 2011 268 texas instruments-advance information system control register 34: run mode clock gating control register 2 (rcgc2), offset 0x108 this register controls the clock gating logic in normal run mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 2 (rcgc2) base 0x400f.e000 offset 0x108 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved udma reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:14 micro-dma clock gating control this bit controls the clock gating for micro-dma. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w udma 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 port j clock gating control this bit controls the clock gating for port j. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioj 8 port h clock gating control this bit controls the clock gating for port h. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioh 7 269 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field port g clock gating control this bit controls the clock gating for port g. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiog 6 port f clock gating control this bit controls the clock gating for port f. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiof 5 port e clock gating control port e clock gating control. this bit controls the clock gating for port e. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioe 4 port d clock gating control port d clock gating control. this bit controls the clock gating for port d. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiob 1 port a clock gating control this bit controls the clock gating for port a. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioa 0 march 20, 2011 270 texas instruments-advance information system control register 35: sleep mode clock gating control register 2 (scgc2), offset 0x118 this register controls the clock gating logic in sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 2 (scgc2) base 0x400f.e000 offset 0x118 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved udma reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:14 micro-dma clock gating control this bit controls the clock gating for micro-dma. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w udma 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 port j clock gating control this bit controls the clock gating for port j. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioj 8 port h clock gating control this bit controls the clock gating for port h. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioh 7 271 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field port g clock gating control this bit controls the clock gating for port g. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiog 6 port f clock gating control this bit controls the clock gating for port f. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiof 5 port e clock gating control port e clock gating control. this bit controls the clock gating for port e. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioe 4 port d clock gating control port d clock gating control. this bit controls the clock gating for port d. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiob 1 port a clock gating control this bit controls the clock gating for port a. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioa 0 march 20, 2011 272 texas instruments-advance information system control register 36: deep sleep mode clock gating control register 2 (dcgc2), offset 0x128 this register controls the clock gating logic in deep-sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 2 (dcgc2) base 0x400f.e000 offset 0x128 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved udma reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:14 micro-dma clock gating control this bit controls the clock gating for micro-dma. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w udma 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 port j clock gating control this bit controls the clock gating for port j. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioj 8 port h clock gating control this bit controls the clock gating for port h. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioh 7 273 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field port g clock gating control this bit controls the clock gating for port g. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiog 6 port f clock gating control this bit controls the clock gating for port f. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiof 5 port e clock gating control port e clock gating control. this bit controls the clock gating for port e. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioe 4 port d clock gating control port d clock gating control. this bit controls the clock gating for port d. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiob 1 port a clock gating control this bit controls the clock gating for port a. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioa 0 march 20, 2011 274 texas instruments-advance information system control register 37: software reset control 0 (srcr0), offset 0x040 this register allows individual modules to be reset. writes to this register are masked by the bits in the device capabilities 1 (dc1) register. software reset control 0 (srcr0) base 0x400f.e000 offset 0x040 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved wdt1 reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wdt0 reserved hib reserved ro ro ro r/w ro ro r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 wdt1 reset control when this bit is set, watchdog timer module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:21 pwm reset control when this bit is set, pwm module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 adc1 reset control when this bit is set, adc module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w adc1 17 adc0 reset control when this bit is set, adc module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w adc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:7 275 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field hib reset control when this bit is set, the hibernation module is reset. all internal data is lost and the registers are returned to their reset states.this bit must be manually cleared after being set. 0 r/w hib 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt0 reset control when this bit is set, watchdog timer module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w wdt0 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 march 20, 2011 276 texas instruments-advance information system control register 38: software reset control 1 (srcr1), offset 0x044 this register allows individual modules to be reset. writes to this register are masked by the bits in the device capabilities 2 (dc2) register. software reset control 1 (srcr1) base 0x400f.e000 offset 0x044 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 reserved i2s0 reserved r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved r/w r/w r/w ro r/w r/w ro ro r/w r/w ro ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 i2s0 reset control when this bit is set, i2s module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 analog comp 1 reset control when this bit is set, analog comparator module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w comp1 25 analog comp 0 reset control when this bit is set, analog comparator module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w comp0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer 3 reset control timer 3 reset control. when this bit is set, general-purpose timer module 3 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w timer3 19 timer 2 reset control when this bit is set, general-purpose timer module 2 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w timer2 18 277 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field timer 1 reset control when this bit is set, general-purpose timer module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w timer1 17 timer 0 reset control when this bit is set, general-purpose timer module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c1 reset control when this bit is set, i2c module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w i2c1 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c0 reset control when this bit is set, i2c module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei1 reset control when this bit is set, qei module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w qei1 9 qei0 reset control when this bit is set, qei module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi1 reset control when this bit is set, ssi module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w ssi1 5 ssi0 reset control when this bit is set, ssi module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 march 20, 2011 278 texas instruments-advance information system control description reset type name bit/field uart2 reset control when this bit is set, uart module 2 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w uart2 2 uart1 reset control when this bit is set, uart module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w uart1 1 uart0 reset control when this bit is set, uart module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w uart0 0 279 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 39: software reset control 2 (srcr2), offset 0x048 this register allows individual modules to be reset. writes to this register are masked by the bits in the device capabilities 4 (dc4) register. software reset control 2 (srcr2) base 0x400f.e000 offset 0x048 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved udma reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:14 micro-dma reset control when this bit is set, udma module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w udma 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 port j reset control when this bit is set, port j module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioj 8 port h reset control when this bit is set, port h module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioh 7 port g reset control when this bit is set, port g module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpiog 6 port f reset control when this bit is set, port f module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpiof 5 port e reset control when this bit is set, port e module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioe 4 march 20, 2011 280 texas instruments-advance information system control description reset type name bit/field port d reset control when this bit is set, port d module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpiod 3 port c reset control when this bit is set, port c module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioc 2 port b reset control when this bit is set, port b module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpiob 1 port a reset control when this bit is set, port a module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioa 0 281 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 hibernation module the hibernation module manages removal and restoration of power to provide a means for reducing power consumption. when the processor and peripherals are idle, power can be completely removed with only the hibernation module remaining powered. power can be restored based on an external signal or at a certain time using the built-in real-time clock (rtc). the hibernation module can be independently supplied from a battery or an auxiliary power supply. the hibernation module has the following features: 32-bit real-time counter (rtc) C two 32-bit rtc match registers for timed wake-up and interrupt generation C rtc predivider trim for making fine adjustments to the clock rate two mechanisms for power control C system power control using discrete external regulator C on-chip power control using internal switches under register control dedicated pin for waking using an external signal rtc operational and hibernation memory valid as long as v bat is valid low-battery detection, signaling, and interrupt generation clock source from a 32.768-khz external oscillator or a 4.194304-mhz crystal; 32.768-khz external oscillator can be used for main controller clock 64 32-bit words of non-volatile memory to save state during hibernation programmable interrupts for rtc match, external wake, and low battery events march 20, 2011 282 texas instruments-advance information hibernation module 6.1 block diagram figure 6-1. hibernation module block diagram 6.2 signal description table 6-1 on page 283 and table 6-2 on page 284 list the external signals of the hibernation module and describe the function of each. these signals have dedicated functions and are not alternate functions for any gpio signals. table 6-1. signals for hibernate (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name an output that indicates the processor is in hibernate mode. od o fixed 51 hib power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply. power - fixed 55 vbat an external input that brings the processor out of hibernate mode when asserted. ttl i fixed 50 wake hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.194304-mhz crystal or a 32.768-khz oscillator for the hibernation module rtc. see the clksel bit in the hibctl register. analog i fixed 52 xosc0 283 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller + , % , 0 + , % 5 , 6 + , % 0 , 6 + , % , & + , % 5 7 & 7 3 u h ' l y l g h u ; 2 6 & ; 2 6 & + , % & 7 / & / . ( 1 + , % & 7 / & / . 6 ( / + , % 5 7 & & + , % 5 7 & / ' + , % 5 7 & 0 + , % 5 7 & 0 5 7 & , q w h u u x s w v 3 r z h u 6 h t x h q f h / r j l f / r z % d w w h u \ ' h w h f w / 2 : % $ 7 9 % $ 7 + , % & 7 / / 2 : % $ 7 ( 1 + , % & 7 / 3 : 5 & 8 7 + , % & 7 / ( ; 7 : ( 1 + , % & 7 / 5 7 & : ( 1 + , % & 7 / 9 $ % 2 5 7 1 r q 9 r o d w l o h 0 h p r u \ z r u g v + , % ' $ 7 $ + , % & 7 / + , % 5 ( 4 : $ . ( + , % & o r f n 6 r x u f h i r u 6 \ v w h p & o r f n , q w h u u x s w v w r & 3 8 + , % & 7 / 5 7 & ( 1 0 $ 7 & + table 6-1. signals for hibernate (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name hibernation module oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed 53 xosc1 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 6-2. signals for hibernate (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name an output that indicates the processor is in hibernate mode. od o fixed m12 hib power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply. power - fixed l12 vbat an external input that brings the processor out of hibernate mode when asserted. ttl i fixed m10 wake hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.194304-mhz crystal or a 32.768-khz oscillator for the hibernation module rtc. see the clksel bit in the hibctl register. analog i fixed k11 xosc0 hibernation module oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed k12 xosc1 a. the ttl designation indicates the pin has ttl-compatible voltage levels. 6.3 functional description important: the hibernate module must have either the rtc function or the external wake function enabled to ensure proper operation of the microcontroller. see initialization on page 289. the hibernation module provides two mechanisms for power control: the first mechanism controls the power to the microcontroller with a control signal ( hib ) that signals an external voltage regulator to turn on or off. the second mechanism uses internal switches to control power to the cortex-m3 as well as to most analog and digital functions while retaining i/o pin power (vdd3on mode). the hibernation module power source is determined dynamically. the supply voltage of the hibernation module is the larger of the main voltage source (v dd ) or the battery/auxilliary voltage source (v bat ). the hibernation module also has an independent clock source to maintain a real-time clock (rtc) when the system clock is powered down. once in hibernation, the module signals an external voltage regulator to turn the power back on when an external pin ( wake ) is asserted or when the internal rtc reaches a certain value. the hibernation module can also detect when the battery voltage is low and optionally prevent hibernation when this occurs. when waking from hibernation, the hib signal is deasserted. the return of v dd causes a por to be executed. the time from when the wake signal is asserted to when code begins execution is equal to the wake-up time (t wake_to_hib ) plus the power-on reset time (t irpor ). march 20, 2011 284 texas instruments-advance information hibernation module 6.3.1 register access timing because the hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. the delay time is t hib_reg_access , therefore software must guarantee that this delay is inserted between back-to-back writes to certain hibernation registers or between a write followed by a read to those same registers. software may make use of the wrc bit in the hibernation control (hibctl) register to ensure that the required timing gap has elapsed. this bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. software should poll hibctl for wrc=1 prior to accessing any affected register. the following registers are subject to this timing restriction: hibernation rtc counter (hibrtcc) hibernation rtc match 0 (hibrtcm0) hibernation rtc match 1 (hibrtcm1) hibernation rtc load (hibrtcld) hibernation rtc trim (hibrtct) hibernation data (hibdata) back-to-back reads from hibernation module registers have no timing restrictions. reads are performed at the full peripheral clock rate. 6.3.2 hibernation clock source in systems where the hibernation module is used to put the microcontroller into hibernation, the module must be clocked by an external source that is independent from the main system clock, even if the rtc feature is not used. an external oscillator or crystal is used for this purpose. to use a crystal, a 4.194304-mhz crystal is connected to the xosc0 and xosc1 pins. this clock signal is divided by 128 internally to produce a 32.768-khz hibernation clock reference. alternatively, a 32.768-khz oscillator can be connected to the xosc0 pin, leaving xosc1 unconnected. care must be taken that the voltage amplitude of the 32.768-khz oscillator is less than v bat , otherwise, the hibernation module may draw power from the oscillator and not v bat during hibernation. see figure 6-2 on page 286 and figure 6-3 on page 286. note that these diagrams only show the connection to the hibernation pins and not to the full system. see hibernation module on page 978 for specific values. the hibernation clock source is enabled by setting the clk32en bit of the hibctl register. the type of clock source is selected by clearing the clksel bit for a 4.194304-mhz crystal and setting the clksel bit for a 32.768-khz oscillator. if a crystal is used for the clock source, the software must leave a delay of t xosc_settle after writing to the clk32en bit and before any other accesses to the hibernation module registers. the delay allows the crystal to power up and stabilize. if an oscillator is used for the clock source, no delay is needed. 285 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 6-2. using a crystal as the hibernation clock source note: x 1 = crystal frequency is f xosc_xtal . c 1,2 = capacitor value derived from crystal vendor load capacitance specifications. r l = load resistor is r xosc_load . r pu1 = pull-up resistor 1 (value and voltage source (v bat or input voltage) determined by regulator or switch enable input characteristics). r pu2 = pull-up resistor 2 is 1 m see hibernation module on page 978 for specific parameter values. figure 6-3. using a dedicated oscillator as the hibernation clock source with vdd3on mode note: r pu = pull-up resistor is 1 m if the application does not require the use of the hibernation module, the xosc0 and xosc1 can remain unconnected and v bat should be connected to v dd . in this situation, the hib bit in the run mode clock gating control register 0 (rcgc0) register must be cleared, disabling the system clock to the hibernation module and hibernation module registers are not accessible. march 20, 2011 286 texas instruments-advance information hibernation module 2 s h q g u d l q h [ w h u q d o z d n h x s f l u f x l w 9 % d w w h u \ * 1 ' 6 w h o o d u l v ? 0 l f u r f r q w u r o o h u , q s x w 9 r o w d j h 5 h j x o d w r u & o r f n 6 r x u f h i ( ; 7 b 2 6 & 1 & ; 2 6 & ; 2 6 & 9 ' ' + , % : $ . ( 9 % $ 7 2 8 7 , 1 5 3 8 2 s h q g u d l q h [ w h u q d o z d n h x s f l u f x l w 9 % d w w h u \ * 1 ' & & 5 / ; 9 % $ 7 ( 1 , q s x w 9 r o w d j h 5 h j x o d w r u r u 6 z l w f k ; 2 6 & ; 2 6 & 9 ' ' + , % : $ . ( 2 8 7 , 1 6 w h o o d u l v ? 0 l f u r f r q w u r o o h u 5 3 8 5 3 8 6.3.2.1 special considerations when using a 4.194304-mhz crystal for some 4.194304-mhz crystals, the manufacturer-recommended crystal value may be outside of the capabilities of the hibernate module oscillator. if the crystal manufacturer's recommended load capacitance is used, the hibernate oscillator may fail to start. for a parallel-resonant oscillator circuit, the total load capacitance c l (as specified by the manufacturer) is calculated as follows: c l = (c 1 * c 2 ) / (c 1 + c 2 ) + c s the internal oscillator was designed for a typical c 1 and c 2 of 16 pf ( c 1 and c 2 are specified as 12 pf minimum and 22 pf maximum). using 2 pf for stray capacitance ( c s ) and the typical value of 16 pf for c 1 and c 2 , the formula above shows that the selected crystal should have a c l specification of about 10 pf. if the crystal has a c l specification higher than 13 pf or lower than 8 pf, or if c s is substantially different from 2 pf, then the oscillator frequency may be outside of the specified accuracy. the crystal manufacturer can provide this error information. 6.3.3 battery management important: system-level factors may affect the accuracy of the low battery detect circuit. the designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. the hibernation module can be independently powered by a battery or an auxiliary power source. the module can monitor the voltage level of the battery and detect when the voltage drops below v lowbat . the module can also be configured so that it does not go into hibernate mode if the battery voltage drops below this threshold. battery voltage is not measured while in hibernate mode. the hibernation module can be configured to detect a low battery condition by setting the lowbaten bit of the hibctl register. in this configuration, the lowbat bit of the hibernation raw interrupt status (hibris) register is set when the battery level is low. if the vabort bit in the hibctl register is also set, then the module is prevented from entering hibernation mode when a low battery is detected. the module can also be configured to generate an interrupt for the low-battery condition (see interrupts and status on page 289). note that the hibernation module draws power from whichever source (v bat or v dd ) has the higher voltage. therefore, it is important to design the circuit to ensure that v dd is higher that v bat under nominal conditions or else the hibernation module draws power from the battery even when v dd is available. 6.3.4 real-time clock the hibernation module includes a 32-bit counter that increments once per second with the proper configuration (see hibernation clock source on page 285). the 32.768-khz clock signal, either directly from the 32.768-khz oscillator or from the 4.194304-mhz crystal divided by 128, is fed into a predivider register that counts down the 32.768-khz clock ticks to achieve a once per second clock rate for the rtc. the rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register, hibrtct . this register has a nominal value of 0x7fff, and is used for one second out of every 64 seconds to divide the input clock. this configuration allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7fff. the predivider trim should be adjusted up from 0x7fff in order to slow down the rtc rate and down from 0x7fff in order to speed up the rtc rate. 287 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller the hibernation module includes two 32-bit match registers that are compared to the value of the rtc counter. the match registers can be used to wake the processor from hibernation mode or to generate an interrupt to the processor if it is not in hibernation. the rtc must be enabled with the rtcen bit of the hibctl register. the value of the rtc can be set at any time by writing to the hibrtcld register. the predivider trim can be adjusted by reading and writing the hibrtct register. the predivider uses this register once every 64 seconds to adjust the clock rate. the two match registers can be set by writing to the hibrtcm0 and hibrtcm1 registers. the rtc can be configured to generate interrupts by using the interrupt registers (see interrupts and status on page 289). 6.3.5 non-volatile memory the hibernation module contains 64 32-bit words of memory that are powered from the battery or auxiliary power supply and therefore retained during hibernation. the processor software can save state information in this memory prior to hibernation and recover the state upon waking. the non-volatile memory can be accessed through the hibdata registers. 6.3.6 power control using hib important: the hibernation module requires special system implementation considerations when using hib to control power, as it is intended to power-down all other sections of the microcontroller. all system signals and power supplies that connect to the chip must be driven to 0 v dc or powered down with the same regulator controlled by hib . see hibernation module on page 978 for more details. the hibernation module controls power to the microcontroller through the use of the hib pin which is intended to be connected to the enable signal of the external regulator(s) providing 3.3 v to the microcontroller and other circuits. when the hib signal is asserted by the hibernation module, the external regulator is turned off and no longer powers the microcontroller and any parts of the system that are powered by the regulator. the hibernation module remains powered from the v bat supply (which could be a battery or an auxiliary power source) until a wake event. power to the microcontroller is restored by deasserting the hib signal, which causes the external regulator to turn power back on to the chip. 6.3.7 power control using vdd3on mode the hibernation module may also be configured to cut power to all internal modules. while in this state, all pins are configured as inputs. in the vdd3on mode, the regulator should maintain 3.3 v power to the microcontroller during hibernate. this power control mode is enabled by setting the vdd3on bit in hibctl . 6.3.8 initiating hibernate prior to initiating hibernation, a wake-up condition must be configured, either from the external wake pin, or by using an rtc match. hibernation mode is initiated when the hibreq bit of the hibctl register is set. if a flash memory write operation is in progress, an interlock feature holds off the transition into hibernation mode until the write has completed. the hibernation module is configured to wake from the external wake pin by setting the pinwen bit of the hibctl register. it is configured to wake from rtc match by setting the rtcwen bit. either one or both of these bits must be set prior to going into hibernation. note that the wake pin uses the hibernation module's internal power supply as the logic 1 reference. march 20, 2011 288 texas instruments-advance information hibernation module upon either external wake-up or rtc match, the hibernation module delays coming out of hibernation until v dd is above the minimum specified voltage, see table 23-2 on page 964. when the hibernation module wakes, the microcontroller performs a normal power-on reset. software can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see interrupts and status on page 289) and by looking for state data in the non-volatile memory (see non-volatile memory on page 288). 6.3.9 interrupts and status the hibernation module can generate interrupts when the following conditions occur: assertion of wake pin rtc match low battery detected all of the interrupts are ored together before being sent to the interrupt controller, so the hibernate module can only generate a single interrupt request to the controller at any given time. the software interrupt handler can service multiple interrupt events by reading the hibernation masked interrupt status (hibmis) register. software can also read the status of the hibernation module at any time by reading the hibris register which shows all of the pending events. this register can be used after waking from hibernation to see if the wake condition was caused by the wake signal or the rtc match. the events that can trigger an interrupt are configured by setting the appropriate bits in the hibernation interrupt mask (hibim) register. pending interrupts can be cleared by writing the corresponding bit in the hibernation interrupt clear (hibic) register. 6.4 initialization and configuration the hibernation module has several different configurations. the following sections show the recommended programming sequence for various scenarios. the examples below assume that a 32.768-khz oscillator is used, and thus always set the clksel bit of the hibctl register. if a 4.194304-mhz crystal is used instead, then the clksel bit remains cleared. because the hibernation module runs at 32.768 khz and is asynchronous to the rest of the microcontroller, which is run off the system clock, software must allow a delay of t hib_reg_access after writes to certain registers (see register access timing on page 285). the registers that require a delay are listed in a note in register map on page 292 as well as in each register description. 6.4.1 initialization the hibernation module comes out of reset with the system clock enabled to the module, but if the system clock to the module has been disabled, then it must be re-enabled, even if the rtc feature is not used. see page 252. if a 4.194304-mhz crystal is used as the hibernation module clock source, perform the following steps: 1. write 0x40 to the hibctl register at offset 0x10 to enable the crystal and select the divide-by-128 input path. 2. wait until the wc interrupt in the hibmis register has been triggered before performing any other operations with the hibernation module. 289 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller if a 32.678-khz single-ended oscillator is used as the hibernation module clock source, then perform the following steps: 1. write 0x44 to the hibctl register at offset 0x10 to enable the oscillator input and bypass the on-chip oscillator. 2. no delay is necessary. the above steps are only necessary when the entire system is initialized for the first time. if the microcontroller has been in hibernation, then the hibernation module has already been powered up and the above steps are not necessary. the software can detect that the hibernation module and clock are already powered by examining the clk32en bit of the hibctl register. table 6-3 on page 290 illustrates how the clocks function with various bit setting both in normal operation and in hibernation. table 6-3. hibernation module clock operation result hibernation result normal operation rtcen clksel rtcwen pinwen clk32en hibernation module disabled hibernation module disabled xx x x 0 no hibernation rtc match capability enabled. module clocked from 4.184304-mhz crystal. 10 0 0 1 no hibernation rtc match capability enabled. module clocked from 32.768-khz oscillator. 11 0 0 1 rtc match for wake-up event module clocked from selected source 1x 1 0 1 clock is powered down during hibernation and powered up again on external wake-up event. module clocked from selected source 0x 0 1 1 clock is powered up during hibernation for rtc. wake up on external event. module clocked from selected source 1x 0 1 1 rtc match or external wake-up event, whichever occurs first. module clocked from selected source 1x 1 1 1 6.4.2 rtc match functionality (no hibernation) use the following steps to implement the rtc match functionality of the hibernation module: 1. write the required rtc match value to one of the hibrtcmn registers at offset 0x004 or 0x008. 2. write the required rtc load value to the hibrtcld register at offset 0x00c. 3. set the required rtc match interrupt mask in the rtcalt0 and rtcalt1 bits (bits 1:0) in the hibim register at offset 0x014. 4. write 0x0000.0041 to the hibctl register at offset 0x010 to enable the rtc to begin counting. 6.4.3 rtc match/wake-up from hibernation use the following steps to implement the rtc match and wake-up functionality of the hibernation module: 1. write the required rtc match value to the hibrtcmn registers at offset 0x004 or 0x008. march 20, 2011 290 texas instruments-advance information hibernation module 2. write the required rtc load value to the hibrtcld register at offset 0x00c. 3. write any data to be retained during power cut to the hibdata register at offsets 0x030-0x12c. 4. set the rtc match wake-up and start the hibernation sequence by writing 0x0000.004f to the hibctl register at offset 0x010. 6.4.4 external wake-up from hibernation use the following steps to implement the hibernation module with the external wake pin as the wake-up source for the microcontroller: 1. write any data to be retained during power cut to the hibdata register at offsets 0x030-0x12c. 2. enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the hibctl register at offset 0x010. note that in this mode, if the rtc is disabled, then the hibernation clock source is powered down during hibernation mode and is powered up again on the external wake event to save power during hibernation. if the rtc is enabled before hibernation, it continues to operate during hibernation. 6.4.5 rtc or external wake-up from hibernation 1. write the required rtc match value to the hibrtcmn registers at offset 0x004 or 0x008. 2. write the required rtc load value to the hibrtcld register at offset 0x00c. 3. write any data to be retained during power cut to the hibdata register at offsets 0x030-0x12c. 4. set the rtc match/external wake-up and start the hibernation sequence by writing 0x0000.005f to the hibctl register at offset 0x010. 6.4.6 register reset the hibernation module handles resets according to the following conditions: cold reset when the hibernation module has no externally applied voltage and detects a change to either v dd or v bat , it resets all hibernation module registers to the value in table 6-4 on page 292. reset during hibernation module disable when the module has either not been enabled or has been disabled by software, the reset is passed through to the hibernation module circuitry, and the internal state of the module is reset. non-volatile memory contents are not reset to zero and contents after reset are indeterminate. reset while hibernation module is in hibernation mode while in hibernation mode, or while transitioning from hibernation mode to run mode, the reset generated by the por circuitry of the microcontroller is suppressed, and the state of the hibernation module's registers is unaffected. reset while hibernation module is in normal mode 291 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller while in normal mode (not hibernating), any reset is suppressed if either the rtcen or the pinwen bit is set in the hibctl register, and the content/state of the control and data registers is unaffected. software must initialize any control or data registers in this condition. therefore, software is the only mechanism to set or clear the clk32en bit and real-time clock operation, or to clear contents of the data memory. the only state that must be cleared by a reset operation while not in hibernation mode is any state that prevents software from managing the interface. note: if v dd drops below operational range while in normal mode (not hibernating), all hibernation module registers are reset to the value in table 6-4 on page 292, regardless of whether the proper voltage is applied to v bat . 6.5 register map table 6-4 on page 292 lists the hibernation registers. all addresses given are relative to the hibernation module base address at 0x400f.c000. note that the system clock to the hibernation module must be enabled before the registers can be programmed (see page 252). there must be a delay of 3 system clocks after the hibernation module clock is enabled before any hibernation module registers are accessed. note: hibrtcc , hibrtcm0 , hibrtcm1 , hibrtcld , hibrtct , and hibdata are on the hibernation module clock domain and have special timing requirements. software should make use of the wrc bit in the hibctl register to ensure that the required timing gap has elapsed. if the wrc bit is clear, any attempted write access is ignored. see register access timing on page 285. important: reset values apply only to a cold reset. once configured, the hibernate module ignores any system reset, other than power on reset, as long as v bat is present. table 6-4. hibernation module register map see page description reset type name offset 294 hibernation rtc counter 0x0000.0000 ro hibrtcc 0x000 295 hibernation rtc match 0 0xffff.ffff r/w hibrtcm0 0x004 296 hibernation rtc match 1 0xffff.ffff r/w hibrtcm1 0x008 297 hibernation rtc load 0xffff.ffff r/w hibrtcld 0x00c 298 hibernation control 0x8000.0000 r/w hibctl 0x010 301 hibernation interrupt mask 0x0000.0000 r/w hibim 0x014 303 hibernation raw interrupt status 0x0000.0000 ro hibris 0x018 305 hibernation masked interrupt status 0x0000.0000 ro hibmis 0x01c 307 hibernation interrupt clear 0x0000.0000 r/w1c hibic 0x020 308 hibernation rtc trim 0x0000.7fff r/w hibrtct 0x024 309 hibernation data - r/w hibdata 0x030- 0x12c march 20, 2011 292 texas instruments-advance information hibernation module 6.6 register descriptions the remainder of this section lists and describes the hibernation module registers, in numerical order by address offset. 293 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: hibernation rtc counter (hibrtcc), offset 0x000 this register is the current 32-bit value of the rtc counter. note: hibrtcc , hibrtcm0 , hibrtcm1 , hibrtcld , hibrtct , and hibdata are on the hibernation module clock domain and have special timing requirements. software should make use of the wrc bit in the hibctl register to ensure that the required timing gap has elapsed. if the wrc bit is clear, any attempted write access is ignored. see register access timing on page 285. hibernation rtc counter (hibrtcc) base 0x400f.c000 offset 0x000 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtcc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field rtc counter a read returns the 32-bit counter value, which represents the seconds elapsed since the rtc was enabled. this register is read-only. to change the value, use the hibrtcld register. 0x0000.0000 ro rtcc 31:0 march 20, 2011 294 texas instruments-advance information hibernation module register 2: hibernation rtc match 0 (hibrtcm0), offset 0x004 this register is the 32-bit match 0 register for the rtc counter. note: hibrtcc , hibrtcm0 , hibrtcm1 , hibrtcld , hibrtct , and hibdata are on the hibernation module clock domain and have special timing requirements. software should make use of the wrc bit in the hibctl register to ensure that the required timing gap has elapsed. if the wrc bit is clear, any attempted write access is ignored. see register access timing on page 285. hibernation rtc match 0 (hibrtcm0) base 0x400f.c000 offset 0x004 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtcm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field rtc match 0 a write loads the value into the rtc match register. a read returns the current match value. 0xffff.ffff r/w rtcm0 31:0 295 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 3: hibernation rtc match 1 (hibrtcm1), offset 0x008 this register is the 32-bit match 1 register for the rtc counter. note: hibrtcc , hibrtcm0 , hibrtcm1 , hibrtcld , hibrtct , and hibdata are on the hibernation module clock domain and have special timing requirements. software should make use of the wrc bit in the hibctl register to ensure that the required timing gap has elapsed. if the wrc bit is clear, any attempted write access is ignored. see register access timing on page 285. hibernation rtc match 1 (hibrtcm1) base 0x400f.c000 offset 0x008 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtcm1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcm1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field rtc match 1 a write loads the value into the rtc match register. a read returns the current match value. 0xffff.ffff r/w rtcm1 31:0 march 20, 2011 296 texas instruments-advance information hibernation module register 4: hibernation rtc load (hibrtcld), offset 0x00c this register is used to load a 32-bit value loaded into the rtc counter. the load occurs immediately upon this register being written. note: hibrtcc , hibrtcm0 , hibrtcm1 , hibrtcld , hibrtct , and hibdata are on the hibernation module clock domain and have special timing requirements. software should make use of the wrc bit in the hibctl register to ensure that the required timing gap has elapsed. if the wrc bit is clear, any attempted write access is ignored. see register access timing on page 285. hibernation rtc load (hibrtcld) base 0x400f.c000 offset 0x00c type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtcld r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcld r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field rtc load a write loads the current value into the rtc counter ( rtcc). a read returns the 32-bit load value. 0xffff.ffff r/w rtcld 31:0 297 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 5: hibernation control (hibctl), offset 0x010 this register is the control register for the hibernation module. this register must be written last before a hibernate event is issued. writes to other registers after the hibreq bit is set are not guaranteed to complete before hibernation is entered. hibernation control (hibctl) base 0x400f.c000 offset 0x010 type r/w, reset 0x8000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wrc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcen hibreq clksel rtcwen pinwen lowbaten clk32en vabort vdd3on reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field write complete/capable description value the interface is processing a prior write and is busy. any write operation that is attempted while wrc is 0 results in undetermined behavior. 0 the interface is ready to accept a write. 1 software must poll this bit between write requests and defer writes until wrc =1 to ensure proper operation. the bit name wrc means "write complete," which is the normal use of the bit (between write accesses). however, because the bit is set out-of-reset, the name can also mean "write capable" which simply indicates that the interface may be written to by software. this difference may be exploited by software at reset time to detect which method of programming is appropriate: 0 = software delay loops required; 1 = wrc paced available. 1 ro wrc 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 30:9 vdd powered description value the internal switches control the power to the on-chip modules (vdd3on mode). 1 the internal switches are not used. the hib signal should be used to control an external switch or regulator. 0 note that regardless of the status of the vdd3on bit, the hib signal is asserted during hibernate mode. thus, when vdd3on is set, the hib signal should not be connected to the 3.3v regulator, and the 3.3v power source should remain connected. 0 r/w vdd3on 8 march 20, 2011 298 texas instruments-advance information hibernation module description reset type name bit/field power cut abort enable description value when this bit is set, the battery voltage level is checked before entering hibernation. if v bat is less than v lowbat , the microcontroller does not go into hibernation. 1 the microcontroller goes into hibernation regardless of the voltage level of the battery. 0 0 r/w vabort 7 clocking enable this bit must be enabled to use the hibernation module. description value the hibernation module clock source is enabled. 1 the hibernation module clock source is disabled. 0 0 r/w clk32en 6 low battery monitoring enable description value low battery voltage detection is enabled. when this bit is set, the battery voltage level is checked before entering hibernation. if v bat is less than v lowbat , the lowbat bit in the hibris register is set. 1 low battery monitoring is disabled. 0 0 r/w lowbaten 5 external wake pin enable description value an assertion of the wake pin takes the microcontroller out of hibernation. 1 the status of the wake pin has no effect on hibernation. 0 0 r/w pinwen 4 rtc wake-up enable description value an rtc match event (the value the hibrtcc register matches the value of the hibrtcm0 or hibrtcm1 register) takes the microcontroller out of hibernation. 1 an rtc match event has no effect on hibernation. 0 0 r/w rtcwen 3 hibernation module clock select description value use raw output. use this value for a 32.768-khz oscillator. 1 use divide-by-128 output. use this value for a 4.194304-mhz crystal. 0 0 r/w clksel 2 299 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field hibernation request description value set this bit to initiate hibernation. 1 no hibernation request. 0 after a wake-up event, this bit is automatically cleared by hardware. 0 r/w hibreq 1 rtc timer enable description value the hibernation module rtc is enabled. the rtc remains active during hibernation. 1 the hibernation module rtc is disabled. when this bit is clear and pinwen is set, enabling an external wake event, the rtc stops during hibernation to save power. 0 0 r/w rtcen 0 march 20, 2011 300 texas instruments-advance information hibernation module register 6: hibernation interrupt mask (hibim), offset 0x014 this register is the interrupt mask register for the hibernation module interrupt sources. each bit in this register masks the corresponding bit in the hibernation raw interrupt status (hibris) register. if a bit is unmasked, the interrupt is sent to the interrupt controller. if the bit is masked, the interrupt is not sent to the interrupt controller. hibernation interrupt mask (hibim) base 0x400f.c000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcalt0 rtcalt1 lowbat extw reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 external wake-up interrupt mask description value an interrupt is sent to the interrupt controller when the extw bit in the hibris register is set. 1 the extw interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w extw 3 low battery voltage interrupt mask description value an interrupt is sent to the interrupt controller when the lowbat bit in the hibris register is set. 1 the lowbat interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w lowbat 2 rtc alert 1 interrupt mask description value an interrupt is sent to the interrupt controller when the rtcalt1 bit in the hibris register is set. 1 the rtcalt1 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w rtcalt1 1 301 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field rtc alert 0 interrupt mask description value an interrupt is sent to the interrupt controller when the rtcalt0 bit in the hibris register is set. 1 the rtcalt0 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w rtcalt0 0 march 20, 2011 302 texas instruments-advance information hibernation module register 7: hibernation raw interrupt status (hibris), offset 0x018 this register is the raw interrupt status for the hibernation module interrupt sources. each bit can be masked by clearing the corresponding bit in the hibim register. when a bit is masked, the interrupt is not sent to the interrupt controller. bits in this register are cleared by writing a 1 to the corresponding bit in the hibernation interrupt clear (hibic) register or by entering hibernation. hibernation raw interrupt status (hibris) base 0x400f.c000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcalt0 rtcalt1 lowbat extw reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 external wake-up raw interrupt status description value the wake pin has been asserted. 1 the wake pin has not been asserted. 0 this bit is cleared by writing a 1 to the extw bit in the hibic register. 0 ro extw 3 low battery voltage raw interrupt status description value the battery voltage dropped below v lowbat . 1 the battery voltage has not dropped below v lowbat . 0 this bit is cleared by writing a 1 to the lowbat bit in the hibic register. 0 ro lowbat 2 rtc alert 1 raw interrupt status description value the value of the hibrtcc register matches the value in the hibrtcm1 register. 1 no match 0 this bit is cleared by writing a 1 to the rtcalt1 bit in the hibic register. 0 ro rtcalt1 1 303 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field rtc alert 0 raw interrupt status description value the value of the hibrtcc register matches the value in the hibrtcm0 register. 1 no match 0 this bit is cleared by writing a 1 to the rtcalt0 bit in the hibic register. 0 ro rtcalt0 0 march 20, 2011 304 texas instruments-advance information hibernation module register 8: hibernation masked interrupt status (hibmis), offset 0x01c this register is the masked interrupt status for the hibernation module interrupt sources. bits in this register are the and of the corresponding bits in the hibris and hibim registers. when both corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt controller. hibernation masked interrupt status (hibmis) base 0x400f.c000 offset 0x01c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcalt0 rtcalt1 lowbat extw reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 external wake-up masked interrupt status description value an unmasked interrupt was signaled due to a wake pin assertion. 1 an external wake-up interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the extw bit in the hibic register. 0 ro extw 3 low battery voltage masked interrupt status description value an unmasked interrupt was signaled due to a low battery voltage condition. 1 a low battery voltage interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the lowbat bit in the hibic register. 0 ro lowbat 2 rtc alert 1 masked interrupt status description value an unmasked interrupt was signaled due to an rtc match. 1 an rtc match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the rtcalt1 bit in the hibic register. 0 ro rtcalt1 1 305 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field rtc alert 0 masked interrupt status description value an unmasked interrupt was signaled due to an rtc match. 1 an rtc match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the rtcalt0 bit in the hibic register. 0 ro rtcalt0 0 march 20, 2011 306 texas instruments-advance information hibernation module register 9: hibernation interrupt clear (hibic), offset 0x020 this register is the interrupt write-one-to-clear register for the hibernation module interrupt sources. writing a 1 to a bit clears the corresponding interrupt in the hibris register. hibernation interrupt clear (hibic) base 0x400f.c000 offset 0x020 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtcalt0 rtcalt1 lowbat extw reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 external wake-up masked interrupt clear writing a 1 to this bit clears the extw bit in the hibris and hibmis registers. reads return an indeterminate value. 0 r/w1c extw 3 low battery voltage masked interrupt clear writing a 1 to this bit clears the lowbat bit in the hibris and hibmis registers. reads return an indeterminate value. 0 r/w1c lowbat 2 rtc alert1 masked interrupt clear writing a 1 to this bit clears the rtcalt1 bit in the hibris and hibmis registers. reads return an indeterminate value. 0 r/w1c rtcalt1 1 rtc alert0 masked interrupt clear writing a 1 to this bit clears the rtcalt0 bit in the hibris and hibmis registers. reads return an indeterminate value. 0 r/w1c rtcalt0 0 307 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 10: hibernation rtc trim (hibrtct), offset 0x024 this register contains the value that is used to trim the rtc clock predivider. it represents the computed underflow value that is used during the trim cycle. it is represented as 0x7fff n clock cycles, where n is the number of clock cycles to add or subtract every 63 seconds. note: hibrtcc , hibrtcm0 , hibrtcm1 , hibrtcld , hibrtct , and hibdata are on the hibernation module clock domain and have special timing requirements. software should make use of the wrc bit in the hibctl register to ensure that the required timing gap has elapsed. if the wrc bit is clear, any attempted write access is ignored. see register access timing on page 285. hibernation rtc trim (hibrtct) base 0x400f.c000 offset 0x024 type r/w, reset 0x0000.7fff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 trim r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 rtc trim value this value is loaded into the rtc predivider every 64 seconds. it is used to adjust the rtc rate to account for drift and inaccuracy in the clock source. compensation can be adjusted by software by moving the default value of 0x7fff up or down. moving the value up slows down the rtc and moving the value down speeds up the rtc. 0x7fff r/w trim 15:0 march 20, 2011 308 texas instruments-advance information hibernation module register 11: hibernation data (hibdata), offset 0x030-0x12c this address space is implemented as a 64x32-bit memory (256 bytes). it can be loaded by the system processor in order to store any non-volatile state data and does not lose power during a power cut operation. note: hibrtcc , hibrtcm0 , hibrtcm1 , hibrtcld , hibrtct , and hibdata are on the hibernation module clock domain and have special timing requirements. software should make use of the wrc bit in the hibctl register to ensure that the required timing gap has elapsed. if the wrc bit is clear, any attempted write access is ignored. see register access timing on page 285. hibernation data (hibdata) base 0x400f.c000 offset 0x030-0x12c type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field hibernation module nv data - r/w rtd 31:0 309 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 7 internal memory the lm3s1p51 microcontroller comes with 24 kb of bit-banded sram, internal rom,and 64 kb of flash memory. the flash memory controller provides a user-friendly interface, making flash memory programming a simple task. flash memory protection can be applied to the flash memory on a 2-kb block basis. 7.1 block diagram figure 7-1 on page 310 illustrates the internal memory blocks and control logic. the dashed boxes in the figure indicate registers residing in the system control module. figure 7-1. internal memory block diagram 7.2 functional description this section describes the functionality of the sram, rom, and flash memories. note: the dma controller can transfer data to and from the on-chip sram. however, because the flash memory and rom are located on a separate internal bus, it is not possible to transfer data from the flash memory or rom with the dma controller. march 20, 2011 310 texas instruments-advance information internal memory 5 2 0 & r q w u r o 5 0 & 7 / 5 2 0 $ u u d \ ) o d v k & r q w u r o ) o d v k : u l w h % x i i h u ) 0 $ ) 0 ' ) & , 0 ) & 0 , 6 & ) o d v k $ u u d \ & r u w h [ 0 % u l g j h 6 5 $ 0 $ u u d \ 6 \ v w h p % x v , f r g h % x v ' f r g h % x v ) o d v k 3 u r w h f w l r q ) 0 3 5 ( ) 0 3 3 ( ) o d v k 7 l p l q j 8 6 ( & 5 / ) o d v k 3 u r w h f w l r q ) 0 3 5 ( q ) 0 3 3 ( q 8 v h u 5 h j l v w h u v % 2 2 7 & ) * 8 6 ( 5 b 5 ( * 8 6 ( 5 b 5 ( * 8 6 ( 5 b 5 ( * 8 6 ( 5 b 5 ( * ) 0 & ) & 5 , 6 ) 0 & ) : % 9 $ / ) : % q z r u g v 7.2.1 sram the internal sram of the stellaris ? devices is located at address 0x2000.0000 of the device memory map. to reduce the number of time consuming read-modify-write (rmw) operations, arm provides bit-banding technology in the processor. with a bit-band-enabled processor, certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. the bit-band base is located at address 0x2200.0000. the bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) for example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000c with the alias address calculated, an instruction performing a read/write to address 0x2202.000c allows direct access to only bit 3 of the byte at address 0x2000.1000. for details about bit-banding, see bit-banding on page 84. note: the sram is implemented using two 32-bit wide sram banks (separate sram arrays). the banks are partitioned such that one bank contains all even words (the even bank) and the other contains all odd words (the odd bank). a write access that is followed immediately by a read access to the same bank incurs a stall of a single clock cycle. however, a write to one bank followed by a read of the other bank can occur in successive clock cycles without incurring any delay. 7.2.2 rom the internal rom of the stellaris device is located at address 0x0100.0000 of the device memory map. detailed information on the rom contents can be found in the stellaris? rom users guide . the rom contains the following components: stellaris boot loader and vector table stellaris peripheral driver library (driverlib) release for product-specific peripherals and interfaces advanced encryption standard (aes) cryptography tables cyclic redundancy check (crc) error detection functionality the boot loader is used as an initial program loader (when the flash memory is empty) as well as an application-initiated firmware upgrade mechanism (by calling back to the boot loader). the peripheral driver library apis in rom can be called by applications, reducing flash memory requirements and freeing the flash memory to be used for other purposes (such as additional features in the application). advance encryption standard (aes) is a publicly defined encryption standard used by the u.s. government and cyclic redundancy check (crc) is a technique to validate a span of data has the same contents as when previously checked. 7.2.2.1 boot loader overview the stellaris boot loader is used to download code to the flash memory of a device without the use of a debug interface. when the core is reset, the user has the opportunity to direct the core to execute the rom boot loader or the application in flash memory by using any gpio signal in ports a-h as configured in the boot configuration (bootcfg) register. 311 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller at reset, the rom is mapped over the flash memory so that the rom boot sequence is always executed. the boot sequence executed from rom is as follows: 1. the ba bit (below) is cleared such that rom is mapped to 0x01xx.xxxx and flash memory is mapped to address 0x0. 2. the bootcfg register is read. if the en bit is clear, the status of the specified gpio pin is compared with the specified polarity. if the status matches the specified polarity, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 3. if the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xffff.ffff, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 4. if there is data at address 0x0000.0004 that is not 0xffff.ffff, the stack pointer ( sp ) is loaded from flash memory at address 0x0000.0000 and the program counter ( pc ) is loaded from address 0x0000.0004. the user application begins executing. the boot loader uses a simple packet interface to provide synchronous communication with the device. the speed of the boot loader is determined by the internal oscillator (piosc) frequency as it does not enable the pll. the following serial interfaces can be used: uart0 ssi0 i 2 c0 for simplicity, both the data format and communication protocol are identical for all serial interfaces. see the stellaris? boot loader user's guide for information on the boot loader software. 7.2.2.2 stellaris peripheral driver library the stellaris peripheral driver library contains a file called driverlib/rom.h that assists with calling the peripheral driver library functions in the rom. the detailed description of each function is available in the stellaris? rom users guide . see the "using the rom" chapter of the stellaris? peripheral driver library user's guide for more details on calling the rom functions and using driverlib/rom.h. a table at the beginning of the rom points to the entry points for the apis that are provided in the rom. accessing the api through these tables provides scalability; while the api locations may change in future versions of the rom, the api tables will not. the tables are split into two levels; the main table contains one pointer per peripheral which points to a secondary table that contains one pointer per api that is associated with that peripheral. the main table is located at 0x0100.0010, right after the cortex-m3 vector table in the rom. driverlib functions are described in detail in the stellaris? peripheral driver library user's guide . additional apis are available for graphics and usb functions, but are not preloaded into rom. the stellaris graphics library provides a set of graphics primitives and a widget set for creating graphical user interfaces on stellaris microcontroller-based boards that have a graphical display (for more information, see the stellaris? graphics library user's guide ). march 20, 2011 312 texas instruments-advance information internal memory 7.2.2.3 advanced encryption standard (aes) cryptography tables aes is a strong encryption method with reasonable performance and size. aes is fast in both hardware and software, is fairly easy to implement, and requires little memory. aes is ideal for applications that can use pre-arranged keys, such as setup during manufacturing or configuration. four data tables used by the xyssl aes implementation are provided in the rom. the first is the forward s-box substitution table, the second is the reverse s-box substitution table, the third is the forward polynomial table, and the final is the reverse polynomial table. see the stellaris? rom users guide for more information on aes. 7.2.2.4 cyclic redundancy check (crc) error detection the crc technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that flash memory contents have not been changed, and for other cases where the data needs to be validated. a crc is preferred over a simple checksum (e.g. xor all bits) because it catches changes more readily. see the stellaris? rom users guide for more information on crc. 7.2.3 flash memory at system clock speeds of 50 mhz and below, the flash memory is read in a single cycle. the flash memory is organized as a set of 1-kb blocks that can be individually erased. an individual 32-bit word can be programmed to change bits from 1 to 0. in addition, a write buffer provides the ability to concurrently program 32 continuous words in flash memory. erasing a block causes the entire contents of the block to be reset to all 1s. the 1-kb blocks are paired into sets of 2-kb blocks that can be individually protected. the protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. caution C the stellaris flash memory array has ecc which uses a test port into the flash memory to continually scan the array for ecc errors and to correct any that are detected. this operation is transparent to the microcontroller. the bist must scan the entire memory array occasionally to ensure integrity, taking about ve minutes to do so. in systems where the microcontroller is frequently powered for less than ve minutes, power should be removed from the microcontroller in a controlled manner to ensure proper operation. this controlled manner can either be through entering hibernation mode or software can request permission to power down the part using the usdreq elw lq wk odvk rqwuro ujlvwu dqg zdlw wr uly dq dnqrzogj iurp wk usdack elw sulru wr uprylqj srzu i wk plurrqwuroou lv srzug grzq xvlqj wklv rqwuroog pwkrg wk qjlq nsv wudn ri zku lw zdv lq wk ppru duud dqg lw dozdv vdqv wk rpsow duud diwu dq djjujdw ri y plqxwv srzugrq ujdugovv ri wk qxpeu ri lqwuyqlqj srzu ov i wk plurrqwuroou lv srzug grzq eiru y plqxwv ri elqj srzug xs vwduwv djdlq iurp zkuyu lw oiw rii eiru wk odvw rqwuroog srzugrzq ru iurp li wku qyu zdv d rqwuroog srzu grzq q rdvlrqdo vkruw srzu grzq lv qrw d rquq exw wk plurrqwuroou vkrxog qrw dozdv e srzug grzq iutxqwo lq dq xqrqwuroog pdqqu k plurrqwuroou dq e srzuog dv iutxqwo dv qvvdu li lw lv srzuggrzq lq d rqwuroog pdqqu 7.2.3.1 prefetch buffer the flash memory controller has a prefetch buffer that is automatically used when the cpu frequency is greater than 50 mhz. in this mode, the flash memory operates at half of the system clock. the prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait states while code is executing linearly. the fetch buffer includes a branch speculation mechanism 313 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller that recognizes a branch and avoids extra wait states by not reading the next word pair. also, short loop branches often stay in the buffer. as a result, some branches can be executed with no wait states. other branches incur a single wait state. 7.2.3.2 flash memory protection the user is provided two forms of flash memory protection per 2-kb flash memory block in one pair of 32-bit wide registers. the policy for each protection form is controlled by individual bits (per policy per block) in the fmppen and fmpren registers. flash memory protection program enable (fmppen) : if a bit is set, the corresponding block may be programmed (written) or erased. if a bit is cleared, the corresponding block may not be changed. flash memory protection read enable (fmpren) : if a bit is set, the corresponding block may be executed or read by software or debuggers. if a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. the policies may be combined as shown in table 7-1 on page 314. table 7-1. flash memory protection policy combinations protection fmpren fmppen execute-only protection. the block may only be executed and may not be written or erased. this mode is used to protect code. 0 0 the block may be written, erased or executed, but not read. this combination is unlikely to be used. 0 1 read-only protection. the block may be read or executed but may not be written or erased. this mode is used to lock the block from further modification while allowing any read or execute access. 1 0 no protection. the block may be written, erased, executed or read. 1 1 a flash memory access that attempts to read a read-protected block ( fmpren bit is set) is prohibited and generates a bus fault. a flash memory access that attempts to program or erase a program-protected block ( fmppen bit is set) is prohibited and can optionally generate an interrupt (by setting the amask bit in the flash controller interrupt mask (fcim) register) to alert software developers of poorly behaving software during the development and debug phases. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. these settings create a policy of open access and programmability. the register bits may be changed by clearing the specific register bit. the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the changes are committed using the flash memory control (fmc) register. details on programming these bits are discussed in nonvolatile register programming on page 317. 7.2.3.3 interrupts the flash memory controller can generate interrupts when the following conditions are observed: programming interrupt - signals when a program or erase action is complete. access interrupt - signals when a program or erase action has been attempted on a 2-kb block of memory that is protected by its corresponding fmppen bit. march 20, 2011 314 texas instruments-advance information internal memory the interrupt events that can trigger a controller-level interrupt are defined in the flash controller masked interrupt status (fcmis) register (see page 325) by setting the corresponding mask bits. if interrupts are not used, the raw interrupt status is always visible via the flash controller raw interrupt status (fcris) register (see page 324). interrupts are always cleared (for both the fcmis and fcris registers) by writing a 1 to the corresponding bit in the flash controller masked interrupt status and clear (fcmisc) register (see page 326). 7.2.3.4 flash memory programming the stellaris devices provide a user-friendly interface for flash memory programming. all erase/program operations are handled via three registers: flash memory address (fma) , flash memory data (fmd) , and flash memory control (fmc) . note that if the debug capabilities of the microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be performed in order to reactivate the debug module. see recovering a "locked" microcontroller on page 175. during a flash memory operation (write, page erase, or mass erase) access to the flash memory is inhibited. as a result, instruction and literal fetches are held off until the flash memory operation is complete. if instruction execution is required during a flash memory operation, the code that is executing must be placed in sram and executed from there while the flash operation is in progress. caution C the flash memory is divided into sectors of electrically separated address ranges of 4 kb each, aligned on 4 kb boundaries. erase/program operations on a 1-kb page have an electrical effect on the other three 1-kb pages within the sector. a specifc 1-kb page must be erased after 6 total erase/program cycles occur to the other pages within its 4-kb sector. the following sequence of operations on a 4-kb sector of flash memory (page 0..3) provides an example: page 3 is erase and programmed with values. page 0, page 1, and page 2 are erased and then programmed with values. at this point page 3 has been affected by 3 erase/program cycles. page 0, page 1, and page 2 are again erased and then programmed with values. at this point page 3 has been affected by 6 erase/program cycles. if the contents of page 3 must continue to be valid, page 3 must be erased and reprogrammed before any other page in this sector has another erase or program operation. to program a 32-bit word 1. write source data to the fmd register. 2. write the target address to the fma register. 3. write the flash memory write key and the write bit (a value of 0xa442.0001) to the fmc register. 4. poll the fmc register until the write bit is cleared. important: to ensure proper operation, two writes to the same word must be separated by an erase. the following two sequences are allowed: 315 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller erase -> program value -> program 0x0000.0000 erase -> program value -> erase the following sequence is not allowed: erase -> program value -> program value to perform an erase of a 1-kb page 1. write the page address to the fma register. 2. write the flash memory write key and the erase bit (a value of 0xa442.0002) to the fmc register. 3. poll the fmc register until the erase bit is cleared or, alternatively, enable the programming interrupt using the pmask bit in the fcim register. to perform a mass erase of the flash memory 1. write the flash memory write key and the merase bit (a value of 0xa442.0004) to the fmc register. 2. poll the fmc register until the merase bit is cleared or, alternatively, enable the programming interrupt using the pmask bit in the fcim register. 7.2.3.5 32-word flash memory write buffer a 32-word write buffer provides the capability to perform faster write accesses to the flash memory by concurrently programing 32 words with a single buffered flash memory write operation. the buffered flash memory write operation takes the same amount of time as the single word write operation controlled by bit 0 in the fmc register. the data for the buffered write is written to the flash write buffer (fwbn) registers. the registers are 32-word aligned with flash memory, and therefore the register fwb0 corresponds with the address in fma where bits [6:0] of fma are all 0. fwb1 corresponds with the address in fma + 0x4 and so on. only the fwbn registers that have been updated since the previous buffered flash memory write operation are written. the flash write buffer valid (fwbval) register shows which registers have been written since the last buffered flash memory write operation. this register contains a bit for each of the 32 fwbn registers, where bit[n] of fwbval corresponds to fwbn . the fwbn register has been updated if the corresponding bit in the fwbval register is set. to program 32 words with a single buffered flash memory write operation 1. write the source data to the fwbn registers. 2. write the target address to the fma register. this must be a 32-word aligned address (that is, bits [6:0] in fma must be 0s). 3. write the flash memory write key and the wrbuf bit (a value of 0xa442.0001) to the fmc2 register. 4. poll the fmc2 register until the wrbuf bit is cleared or wait for the pmis interrupt to be signaled. march 20, 2011 316 texas instruments-advance information internal memory 7.2.3.6 nonvolatile register programming this section discusses how to update registers that are resident within the flash memory itself. these registers exist in a separate space from the main flash memory array and are not affected by an erase or mass erase operation. the bits in these registers can be changed from 1 to 0 with a write operation. the register contents are unaffected by any reset condition except power-on reset, which returns the register contents to 0xffff.ffff. by committing the register values using the comt bit in the fmc register, the register contents become nonvolatile and are therefore retained following power cycling. once the register contents are committed, the only way to restore the factory default values is to perform the sequence described in recovering a "locked" microcontroller on page 175. with the exception of the boot configuration (bootcfg) register, the settings in these registers can be tested before committing them to flash memory. for the bootcfg register, the data to be written is loaded into the fmd register before it is committed. the fmd register is read only and does not allow the bootcfg operation to be tried before committing it to nonvolatile memory. important: the flash memory resident registers can only have bits changed from 1 to 0 by user programming and can only be committed once. after being committed, these registers can only be restored to their factory default values only by performing the sequence described in recovering a "locked" microcontroller on page 175. the mass erase of the main flash memory array caused by the sequence is performed prior to restoring these registers. in addition, the user_reg0 , user_reg1 , user_reg2 , user_reg3 , and bootcfg registers each use bit 31 ( nw ) to indicate that they have not been committed and bits in the register may be changed from 1 to 0. table 7-2 on page 317 provides the fma address required for commitment of each of the registers and the source of the data to be written when the fmc register is written with a value of 0xa442.0008. after writing the comt bit, the user may poll the fmc register to wait for the commit operation to complete. table 7-2. user-programmable flash memory resident registers data source fma value register to be committed fmpre0 0x0000.0000 fmpre0 fmppe0 0x0000.0001 fmppe0 user_reg0 0x8000.0000 user_reg0 user_reg1 0x8000.0001 user_reg1 user_reg2 0x8000.0002 user_reg2 user_reg3 0x8000.0003 user_reg3 fmd 0x7510.0000 bootcfg 7.3 register map table 7-3 on page 318 lists the rom controller register and the flash memory and control registers. the offset listed is a hexadecimal increment to the register's address. the fma , fmd , fmc , fcris , fcim , fcmisc , fmc2 , fwbval , and fwbn register offsets are relative to the flash memory control base address of 0x400f.d000. the rom and flash memory protection register offsets are relative to the system control base address of 0x400f.e000. 317 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 7-3. flash register map see page description reset type name offset flash memory registers (flash control offset) 319 flash memory address 0x0000.0000 r/w fma 0x000 320 flash memory data 0x0000.0000 r/w fmd 0x004 321 flash memory control 0x0000.0000 r/w fmc 0x008 324 flash controller raw interrupt status 0x0000.0000 ro fcris 0x00c 325 flash controller interrupt mask 0x0000.0000 r/w fcim 0x010 326 flash controller masked interrupt status and clear 0x0000.0000 r/w1c fcmisc 0x014 327 flash memory control 2 0x0000.0000 r/w fmc2 0x020 328 flash write buffer valid 0x0000.0000 r/w fwbval 0x030 329 flash control 0x0000.0000 r/w fctl 0x0f8 330 flash write buffer n 0x0000.0000 r/w fwbn 0x100 - 0x17c memory registers (system control offset) 331 rom control - r/w1c rmctl 0x0f0 332 flash memory protection read enable 0 0xffff.ffff r/w fmpre0 0x130 332 flash memory protection read enable 0 0xffff.ffff r/w fmpre0 0x200 333 flash memory protection program enable 0 0xffff.ffff r/w fmppe0 0x134 333 flash memory protection program enable 0 0xffff.ffff r/w fmppe0 0x400 334 boot configuration 0xffff.fffe r/w bootcfg 0x1d0 336 user register 0 0xffff.ffff r/w user_reg0 0x1e0 337 user register 1 0xffff.ffff r/w user_reg1 0x1e4 338 user register 2 0xffff.ffff r/w user_reg2 0x1e8 339 user register 3 0xffff.ffff r/w user_reg3 0x1ec 340 flash memory protection read enable 1 0x0000.0000 r/w fmpre1 0x204 341 flash memory protection read enable 2 0x0000.0000 r/w fmpre2 0x208 342 flash memory protection read enable 3 0x0000.0000 r/w fmpre3 0x20c 343 flash memory protection program enable 1 0x0000.0000 r/w fmppe1 0x404 344 flash memory protection program enable 2 0x0000.0000 r/w fmppe2 0x408 345 flash memory protection program enable 3 0x0000.0000 r/w fmppe3 0x40c 7.4 flash memory register descriptions (flash control offset) this section lists and describes the flash memory registers, in numerical order by address offset. registers in this section are relative to the flash control base address of 0x400f.d000. march 20, 2011 318 texas instruments-advance information internal memory register 1: flash memory address (fma), offset 0x000 during a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. during erase operations, this register contains a 1 kb-aligned cpu byte address and specifies which block is erased. note that the alignment requirements must be met by software or the results of the operation are unpredictable. flash memory address (fma) base 0x400f.d000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:16 address offset address offset in flash memory where operation is performed, except for nonvolatile registers (see nonvolatile register programming on page 317 for details on values for this field). 0x0 r/w offset 15:0 319 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: flash memory data (fmd), offset 0x004 this register contains the data to be written during the programming cycle or read during the read cycle. note that the contents of this register are undefined for a read access of an execute-only block. this register is not used during erase cycles. flash memory data (fmd) base 0x400f.d000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field data value data value for write operation. 0x0000.0000 r/w data 31:0 march 20, 2011 320 texas instruments-advance information internal memory register 3: flash memory control (fmc), offset 0x008 when this register is written, the flash memory controller initiates the appropriate access cycle for the location specified by the flash memory address (fma) register (see page 319). if the access is a write access, the data contained in the flash memory data (fmd) register (see page 320) is written to the specified address. this register must be the final register written and initiates the memory operation. the four control bits in the lower byte of this register are used to initiate memory operations. care must be taken not to set multiple control bits as the results of such an operation are unpredictable. caution C if any of bits [15:4] are written to 1, the device may become inoperable. these bits should always be written to 0. in all registers, the value of a reserved bit should be preserved across a read-modify-write operation. flash memory control (fmc) base 0x400f.d000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wrkey wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 write erase merase comt reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash memory write key this field contains a write key, which is used to minimize the incidence of accidental flash memory writes. the value 0xa442 must be written into this field for a flash memory write to occur. writes to the fmc register without this wrkey value are ignored. a read of this field returns the value 0. 0x0000 wo wrkey 31:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:4 321 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field commit register value this bit is used to commit writes to flash-memory-resident registers and to monitor the progress of that process. description value set this bit to commit (write) the register value to a flash-memory-resident register. when read, a 1 indicates that the previous commit access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous commit access is complete. 0 see nonvolatile register programming on page 317 for more information on programming flash-memory-resident registers. 0 r/w comt 3 mass erase flash memory this bit is used to mass erase the flash main memory and to monitor the progress of that process. description value set this bit to erase the flash main memory. when read, a 1 indicates that the previous mass erase access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous mass erase access is complete. 0 for information on erase time, see flash memory characteristics on page 965. 0 r/w merase 2 erase a page of flash memory this bit is used to erase a page of flash memory and to monitor the progress of that process. description value set this bit to erase the flash memory page specified by the contents of the fma register. when read, a 1 indicates that the previous page erase access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous page erase access is complete. 0 for information on erase time, see flash memory characteristics on page 965. 0 r/w erase 1 march 20, 2011 322 texas instruments-advance information internal memory description reset type name bit/field write a word into flash memory this bit is used to write a word into flash memory and to monitor the progress of that process. description value set this bit to write the data stored in the fmd register into the flash memory location specified by the contents of the fma register. when read, a 1 indicates that the write update access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous write update access is complete. 0 for information on programming time, see flash memory characteristics on page 965. 0 r/w write 0 323 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: flash controller raw interrupt status (fcris), offset 0x00c this register indicates that the flash memory controller has an interrupt condition. an interrupt is sent to the interrupt controller only if the corresponding fcim register bit is set. flash controller raw interrupt status (fcris) base 0x400f.d000 offset 0x00c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 aris pris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 programming raw interrupt status this bit provides status on programming cycles which are write or erase actions generated through the fmc or fmc2 register bits (see page 321 and page 327). description value the programming or erase cycle has completed. 1 the programming or erase cycle has not completed. 0 this status is sent to the interrupt controller when the pmask bit in the fcim register is set. this bit is cleared by writing a 1 to the pmisc bit in the fcmisc register. 0 ro pris 1 access raw interrupt status description value a program or erase action was attempted on a block of flash memory that contradicts the protection policy for that block as set in the fmppen registers. 1 no access has tried to improperly program or erase the flash memory. 0 this status is sent to the interrupt controller when the amask bit in the fcim register is set. this bit is cleared by writing a 1 to the amisc bit in the fcmisc register. 0 ro aris 0 march 20, 2011 324 texas instruments-advance information internal memory register 5: flash controller interrupt mask (fcim), offset 0x010 this register controls whether the flash memory controller generates interrupts to the controller. flash controller interrupt mask (fcim) base 0x400f.d000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 amask pmask reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 programming interrupt mask this bit controls the reporting of the programming raw interrupt status to the interrupt controller. description value an interrupt is sent to the interrupt controller when the pris bit is set. 1 the pris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w pmask 1 access interrupt mask this bit controls the reporting of the access raw interrupt status to the interrupt controller. description value an interrupt is sent to the interrupt controller when the aris bit is set. 1 the aris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w amask 0 325 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 6: flash controller masked interrupt status and clear (fcmisc), offset 0x014 this register provides two functions. first, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. second, it serves as the method to clear the interrupt reporting. flash controller masked interrupt status and clear (fcmisc) base 0x400f.d000 offset 0x014 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 amisc pmisc reserved r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 programming masked interrupt status and clear description value when read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. writing a 1 to this bit clears pmisc and also the pris bit in the fcris register (see page 324). 1 when read, a 0 indicates that a programming cycle complete interrupt has not occurred. a write of 0 has no effect on the state of this bit. 0 0 r/w1c pmisc 1 access masked interrupt status and clear description value when read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of flash memory that contradicts the protection policy for that block as set in the fmppen registers. writing a 1 to this bit clears amisc and also the aris bit in the fcris register (see page 324). 1 when read, a 0 indicates that no improper accesses have occurred. a write of 0 has no effect on the state of this bit. 0 0 r/w1c amisc 0 march 20, 2011 326 texas instruments-advance information internal memory register 7: flash memory control 2 (fmc2), offset 0x020 when this register is written, the flash memory controller initiates the appropriate access cycle for the location specified by the flash memory address (fma) register (see page 319). if the access is a write access, the data contained in the flash write buffer (fwb) registers is written. this register must be the final register written as it initiates the memory operation. flash memory control 2 (fmc2) base 0x400f.d000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wrkey wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wrbuf reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash memory write key this field contains a write key, which is used to minimize the incidence of accidental flash memory writes. the value 0xa442 must be written into this field for a write to occur. writes to the fmc2 register without this wrkey value are ignored. a read of this field returns the value 0. 0x0000 wo wrkey 31:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:1 buffered flash memory write this bit is used to start a buffered write to flash memory. description value set this bit to write the data stored in the fwbn registers to the location specified by the contents of the fma register. when read, a 1 indicates that the previous buffered flash memory write access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous buffered flash memory write access is complete. 0 for information on programming time, see flash memory characteristics on page 965. 0 r/w wrbuf 0 327 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 8: flash write buffer valid (fwbval), offset 0x030 this register provides a bitwise status of which fwbn registers have been written by the processor since the last write of the flash memory write buffer. the entries with a 1 are written on the next write of the flash memory write buffer. this register is cleared after the write operation by hardware. a protection violation on the write operation also clears this status. software can program the same 32 words to various flash memory locations by setting the fwb[n] bits after they are cleared by the write operation. the next write operation then uses the same data as the previous one. in addition, if a fwbn register change should not be written to flash memory, software can clear the corresponding fwb[n] bit to preserve the existing data when the next write operation occurs. flash write buffer valid (fwbval) base 0x400f.d000 offset 0x030 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fwb[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fwb[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash memory write buffer description value the corresponding fwbn register has been updated since the last buffer write operation and is ready to be written to flash memory. 1 the corresponding fwbn register has no new data to be written. 0 bit 0 corresponds to fwb0 , offset 0x100, and bit 31 corresponds to fwb31 , offset 0x13c. 0x0 r/w fwb[n] 31:0 march 20, 2011 328 texas instruments-advance information internal memory register 9: flash control (fctl), offset 0x0f8 this register is used to ensure that the microcontroller is powered down in a controlled fashion in systems where power is cycled more frequently than once every five minutes. the usdreq bit should be set to indicate that power is going to be turned off. software should poll the usdack bit to determine when it is acceptable to power down. note that this power-down process is not required if the microcontroller enters hibernation mode prior to power being removed. flash control (fctl) base 0x400f.d000 offset 0x0f8 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usdreq usdack reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 user shut down acknowledge description value the microcontroller can be powered down. 1 the microcontroller cannot yet be powered down. 0 this bit should be set within 50 ms of setting the usdreq bit. 0 ro usdack 1 user shut down request description value requests permission to power down the microcontroller. 1 no effect. 0 0 r/w usdreq 0 329 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 10: flash write buffer n (fwbn), offset 0x100 - 0x17c these 32 registers hold the contents of the data to be written into the flash memory on a buffered flash memory write operation. the offset selects one of the 32-bit registers. only fwbn registers that have been updated since the preceding buffered flash memory write operation are written into the flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or 2 words. the fwbn registers are written into the flash memory with the fwb0 register corresponding to the address contained in fma . fwb1 is written to the address fma +0x4 etc. note that only data bits that are 0 result in the flash memory being modified. a data bit that is 1 leaves the content of the flash memory bit at its previous value. flash write buffer n (fwbn) base 0x400f.d000 offset 0x100 - 0x17c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field data data to be written into the flash memory. 0x0000.0000 r/w data 31:0 7.5 memory register descriptions (system control offset) the remainder of this section lists and describes the registers that reside in the system control address space, in numerical order by address offset. registers in this section are relative to the system control base address of 0x400f.e000. march 20, 2011 330 texas instruments-advance information internal memory register 11: rom control (rmctl), offset 0x0f0 this register provides control of the rom controller state. this register offset is relative to the system control base address of 0x400f.e000. at reset, the rom is mapped over the flash memory so that the rom boot sequence is always executed. the boot sequence executed from rom is as follows: 1. the ba bit (below) is cleared such that rom is mapped to 0x01xx.xxxx and flash memory is mapped to address 0x0. 2. the bootcfg register is read. if the en bit is clear, the status of the specified gpio pin is compared with the specified polarity. if the status matches the specified polarity, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 3. if the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xffff.ffff, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 4. if there is data at address 0x0000.0004 that is not 0xffff.ffff, the stack pointer ( sp ) is loaded from flash memory at address 0x0000.0000 and the program counter ( pc ) is loaded from address 0x0000.0004. the user application begins executing. rom control (rmctl) base 0x400f.e000 offset 0x0f0 type r/w1c, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ba reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 boot alias description value the microcontroller's rom appears at address 0x0. 1 the flash memory is at address 0x0. 0 this bit is cleared by writing a 1 to this bit position. 1 r/w1c ba 0 331 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: flash memory protection read enable 0 (fmpre0), offset 0x130 and 0x200 note: this register is aliased for backwards compatability. note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. for additional information, see the "flash memory protection" section. flash memory protection read enable 0 (fmpre0) base 0x400f.e000 offset 0x130 and 0x200 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in the table flash protection policy combinations. description value bits [31:0] each enable protection on a 2-kb block of flash memory up to the total of 64 kb. 0xffffffff 0xffffffff r/w read_enable 31:0 march 20, 2011 332 texas instruments-advance information internal memory register 13: flash memory protection program enable 0 (fmppe0), offset 0x134 and 0x400 note: this register is aliased for backwards compatability. note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. for additional information, see the "flash memory protection" section. flash memory protection program enable 0 (fmppe0) base 0x400f.e000 offset 0x134 and 0x400 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in the table flash protection policy combinations. description value bits [31:0] each enable protection on a 2-kb block of flash memory up to the total of 64 kb. 0xffffffff 0xffffffff r/w prog_enable 31:0 333 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 14: boot configuration (bootcfg), offset 0x1d0 note: offset is relative to system control base address of 0x400fe000. this register provides configuration of a gpio pin to enable the rom boot loader as well as a write-once mechanism to disable external debugger access to the device. upon reset, the user has the opportunity to direct the core to execute the rom boot loader or the application in flash memory by using any gpio signal from ports a-h as configured by the bits in this register. if the en bit is set or the specified pin does not have the required polarity, the system control module checks address 0x000.0004 to see if the flash memory has a valid reset vector. if the data at address 0x0000.0004 is 0xffff.ffff, then it is assumed that the flash memory has not yet been programmed, and the core executes the rom boot loader. the dbg0 bit (bit 0) is set to 0 from the factory and the dbg1 bit (bit 1) is set to 1, which enables external debuggers. clearing the dbg1 bit disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. the nw bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. prior to being committed, bits can only be changed from 1 to 0. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. boot configuration (bootcfg) base 0x400f.e000 offset 0x1d0 type r/w, reset 0xffff.fffe 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved nw ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dbg0 dbg1 reserved en pol pin port r/w r/w ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w type 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x7fff ro reserved 30:16 march 20, 2011 334 texas instruments-advance information internal memory description reset type name bit/field boot gpio port this field selects the port of the gpio port pin that enables the rom boot loader at reset. description value port a 0x0 port b 0x1 port c 0x2 port d 0x3 port e 0x4 port f 0x5 port g 0x6 port h 0x7 0x7 r/w port 15:13 boot gpio pin this field selects the pin number of the gpio port pin that enables the rom boot loader at reset. description value pin 0 0x0 pin 1 0x1 pin 2 0x2 pin 3 0x3 pin 4 0x4 pin 5 0x5 pin 6 0x6 pin 7 0x7 0x7 r/w pin 12:10 boot gpio polarity when set, this bit selects a high level for the gpio port pin to enable the rom boot loader at reset. when clear, this bit selects a low level for the gpio port pin. 0x1 r/w pol 9 boot gpio enable clearing this bit enables the use of a gpio pin to enable the rom boot loader at reset. when this bit is set, the contents of address 0x0000.0004 are checked to see if the flash memory has been programmed. if the contents are not 0xffff.ffff, the core executes out of flash memory. if the flash has not been programmed, the core executes out of rom. 0x1 r/w en 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x3f ro reserved 7:2 debug control 1 the dbg1 bit must be 1 and dbg0 must be 0 for debug to be available. 1 r/w dbg1 1 debug control 0 the dbg1 bit must be 1 and dbg0 must be 0 for debug to be available. 0x0 r/w dbg0 0 335 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 15: user register 0 (user_reg0), offset 0x1e0 note: offset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be committed once. bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. prior to being committed, bits can only be changed from 1 to 0. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag section. user register 0 (user_reg0) base 0x400f.e000 offset 0x1e0 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be committed once. 0x7fffffff r/w data 30:0 march 20, 2011 336 texas instruments-advance information internal memory register 16: user register 1 (user_reg1), offset 0x1e4 note: offset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be written once. bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. user register 1 (user_reg1) base 0x400f.e000 offset 0x1e4 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be committed once. 0x7fffffff r/w data 30:0 337 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 17: user register 2 (user_reg2), offset 0x1e8 note: offset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be written once. bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. user register 2 (user_reg2) base 0x400f.e000 offset 0x1e8 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be committed once. 0x7fffffff r/w data 30:0 march 20, 2011 338 texas instruments-advance information internal memory register 18: user register 3 (user_reg3), offset 0x1ec note: offset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be written once. bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. user register 3 (user_reg3) base 0x400f.e000 offset 0x1ec type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be committed once. 0x7fffffff r/w data 30:0 339 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 19: flash memory protection read enable 1 (fmpre1), offset 0x204 note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. if the flash memory size on the device is less than 64 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see the "flash memory protection" section. flash memory protection read enable 1 (fmpre1) base 0x400f.e000 offset 0x204 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in the table flash protection policy combinations. description value bits [31:0] each enable protection on a 2-kb block of flash memory in memory range from 65 to 128 kb. 0x00000000 0x00000000 r/w read_enable 31:0 march 20, 2011 340 texas instruments-advance information internal memory register 20: flash memory protection read enable 2 (fmpre2), offset 0x208 note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. if the flash memory size on the device is less than 128 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see the "flash memory protection" section. flash memory protection read enable 2 (fmpre2) base 0x400f.e000 offset 0x208 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in the table flash protection policy combinations. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 129 to 192 kb. 0x00000000 0x00000000 r/w read_enable 31:0 341 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 21: flash memory protection read enable 3 (fmpre3), offset 0x20c note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see the "flash memory protection" section. flash memory protection read enable 3 (fmpre3) base 0x400f.e000 offset 0x20c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in the table flash protection policy combinations. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 193 to 256 kb. 0x00000000 0x00000000 r/w read_enable 31:0 march 20, 2011 342 texas instruments-advance information internal memory register 22: flash memory protection program enable 1 (fmppe1), offset 0x404 note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. if the flash memory size on the device is less than 64 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see the "flash memory protection" section. flash memory protection program enable 1 (fmppe1) base 0x400f.e000 offset 0x404 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in the table flash protection policy combinations. description value bits [31:0] each enable protection on a 2-kb block of flash memory in memory range from 65 to 128 kb. 0x00000000 0x00000000 r/w prog_enable 31:0 343 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 23: flash memory protection program enable 2 (fmppe2), offset 0x408 note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. if the flash memory size on the device is less than 128 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see the "flash memory protection" section. flash memory protection program enable 2 (fmppe2) base 0x400f.e000 offset 0x408 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in the table flash protection policy combinations. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 129 to 192 kb. 0x00000000 0x00000000 r/w prog_enable 31:0 march 20, 2011 344 texas instruments-advance information internal memory register 24: flash memory protection program enable 3 (fmppe3), offset 0x40c note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the "recover locked device" sequence detailed in the jtag chapter. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see the "flash memory protection" section. flash memory protection program enable 3 (fmppe3) base 0x400f.e000 offset 0x40c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in the table flash protection policy combinations. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 193 to 256 kb. 0x00000000 0x00000000 r/w prog_enable 31:0 345 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 8 micro direct memory access (dma) the lm3s1p51 microcontroller includes a direct memory access (dma) controller, known as micro-dma (dma). the dma controller provides a way to offload data transfer tasks from the cortex ? -m3 processor, allowing for more efficient use of the processor and the available bus bandwidth. the dma controller can perform transfers between memory and peripherals. it has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. the dma controller provides the following features: arm ? primecell ? 32-channel configurable dma controller support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes C basic for simple transfer scenarios C ping-pong for continuous data flow C scatter-gather for a programmable list of arbitrary transfers initiated from a single request highly flexible and configurable channel operation C independently configured and operated channels C dedicated channels for supported on-chip modules C primary and secondary channel assignments C one channel each for receive and transmit path for bidirectional modules C dedicated channel for software-initiated transfers C per-channel configurable priority scheme C optional software-initiated requests for any channel two levels of priority design optimizations for improved bus access performance between dma controller and the processor core C dma controller access is subordinate to core access C ram striping C peripheral bus segmentation data sizes of 8, 16, and 32 bits transfer size is programmable in binary steps from 1 to 1024 source and destination address increment size of byte, half-word, word, or no increment maskable peripheral requests march 20, 2011 346 texas instruments-advance information micro direct memory access (dma) 8.1 block diagram figure 8-1. dma block diagram 8.2 functional description the dma controller is a flexible and highly configurable dma controller designed to work efficiently with the microcontroller's cortex-m3 processor core. it supports multiple data sizes and address increment schemes, multiple levels of priority among dma channels, and several transfer modes to allow for sophisticated programmed data transfers. the dma controller's usage of the bus is always subordinate to the processor core, so it never holds up a bus transaction by the processor. because the dma controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free, with no impact on the rest of the system. the bus architecture has been optimized to greatly enhance the ability of the processor core and the dma controller to efficiently share the on-chip bus, thus improving performance. the optimizations include ram striping and peripheral bus segmentation, which in many cases allow both the processor core and the dma controller to access the bus and perform simultaneous data transfers. the dma controller can transfer data to and from the on-chip sram. however, because the flash memory and rom are located on a separate internal bus, it is not possible to transfer data from the flash memory or rom with the dma controller. each peripheral function that is supported has a dedicated channel on the dma controller that can be configured independently. the dma controller implements a unique configuration method using channel control structures that are maintained in system memory by the processor. while simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the dma controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. the dma controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral. each channel also has a configurable arbitration size. the arbitration size is the number of items that are transferred in a burst before the dma controller rearbitrates for channel priority. using the 347 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 \ v w h p 0 h p r u \ & + & r q w u r o 7 d e o h 7 u d q v i h u % x i i h u v 8 v h g e \ ? ' 0 $ x ' 0 $ & r q w u r o o h u ? ? ? ' 0 $ 6 5 & ( 1 ' 3 ' 0 $ ' 6 7 ( 1 ' 3 ' 0 $ & + & 7 5 / ' 0 $ 6 5 & ( 1 ' 3 ' 0 $ ' 6 7 ( 1 ' 3 ' 0 $ & + & 7 5 / ' 0 $ h u u r u 3 h u l s k h u d o ' 0 $ & k d q q h o 3 h u l s k h u d o ' 0 $ & k d q q h o 1 ? ? ? ' 0 $ 6 7 $ 7 ' 0 $ & ) * ' 0 $ & 7 / % $ 6 ( ' 0 $ $ / 7 % $ 6 ( ' 0 $ : $ , 7 6 7 $ 7 ' 0 $ 6 : 5 ( 4 ' 0 $ 8 6 ( % 8 5 6 7 6 ( 7 ' 0 $ 8 6 ( % 8 5 6 7 & / 5 ' 0 $ 5 ( 4 0 $ 6 . 6 ( 7 ' 0 $ 5 ( 4 0 $ 6 . & / 5 ' 0 $ ( 1 $ 6 ( 7 ' 0 $ ( 1 $ & / 5 ' 0 $ $ / 7 6 ( 7 ' 0 $ $ / 7 & / 5 ' 0 $ 3 5 , 2 6 ( 7 ' 0 $ 3 5 , 2 & / 5 ' 0 $ ( 5 5 & / 5 u h t x h v w g r q h u h t x h v w g r q h * h q h u d o 3 h u l s k h u d o 1 5 h j l v w h u v 1 h v w h g 9 h f w r u h g , q w h u u x s w & r q w u r o o h u 1 9 , & $ 5 0 & r u w h [ 0 , 5 4 u h t x h v w g r q h ' 0 $ & + $ 6 * 1 arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a dma service request. 8.2.1 channel assignments dma channels 0-31 are assigned to peripherals according to the following table. the dma channel assignment (dmachasgn) register (see page 394) can be used to specify the primary or secondary assignment. if the primary function is not available on this microcontroller, the secondary function becomes the primary function. if the secondary function is not available, the primary function is the only option. note: channels noted in the table as "available for software" may be assigned to peripherals in the future. however, they are currently available for software use. channel 30 is dedicated for software use. because of the way the dma controller interacts with peripherals, the dma channel for the peripheral must be enabled in order for the dma controller to be able to read and write the peripheral registers, even if a different dma channel is used to perform the dma transfer. to minimize confusion and chance of software errors, it is best practice to use a peripheral's dma channel for performing all dma transfers for that peripheral, even if it is processor-triggered and using auto mode, which could be considered a software transfer. note that if the software channel is used, interrupts occur on the dedicated dma interrupt vector. if the peripheral channel is used, then the interrupt occurs on the interrupt vector for the peripheral. table 8-1. dma channel assignments secondary assignment primary assignment dma channel uart2 receive available for software 0 uart2 transmit available for software 1 general-purpose timer 3a available for software 2 general-purpose timer 3b available for software 3 general-purpose timer 2a available for software 4 general-purpose timer 2b available for software 5 general-purpose timer 2a available for software 6 general-purpose timer 2b available for software 7 uart1 receive uart0 receive 8 uart1 transmit uart0 transmit 9 ssi1 receive ssi0 receive 10 ssi1 transmit ssi0 transmit 11 uart2 receive available for software 12 uart2 transmit available for software 13 general-purpose timer 2a adc0 sample sequencer 0 14 general-purpose timer 2b adc0 sample sequencer 1 15 available for software adc0 sample sequencer 2 16 available for software adc0 sample sequencer 3 17 general-purpose timer 1a general-purpose timer 0a 18 general-purpose timer 1b general-purpose timer 0b 19 available for software general-purpose timer 1a 20 available for software general-purpose timer 1b 21 march 20, 2011 348 texas instruments-advance information micro direct memory access (dma) table 8-1. dma channel assignments (continued) secondary assignment primary assignment dma channel available for software uart1 receive 22 available for software uart1 transmit 23 adc1 sample sequencer 0 ssi1 receive 24 adc1 sample sequencer 1 ssi1 transmit 25 adc1 sample sequencer 2 available for software 26 adc1 sample sequencer 3 available for software 27 available for software i 2 s0 receive 28 available for software i 2 s0 transmit 29 dedicated for software use 30 reserved 31 8.2.2 priority the dma controller assigns priority to each channel based on the channel number and the priority level bit for the channel. channel number 0 has the highest priority and as the channel number increases, the priority of a channel decreases. each channel has a priority level bit to provide two levels of priority: default priority and high priority. if the priority level bit is set, then that channel has higher priority than all other channels at default priority. if multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels. the priority bit for a channel can be set using the dma channel priority set (dmaprioset) register and cleared with the dma channel priority clear (dmaprioclr) register. 8.2.3 arbitration size when a dma channel requests a transfer, the dma controller arbitrates among all the channels making a request and services the dma channel with the highest priority. once a transfer begins, it continues for a selectable number of transfers before rearbitrating among the requesting channels again. the arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers. after the dma controller transfers the number of items specified by the arbitration size, it then checks among all the channels making a request and services the channel with the highest priority. if a lower priority dma channel uses a large arbitration size, the latency for higher priority channels is increased because the dma controller completes the lower priority burst before checking for higher priority requests. therefore, lower priority channels should not use a large arbitration size for best response on high priority channels. the arbitration size can also be thought of as a burst size. it is the maximum number of items that are transferred at any one time in a burst. here, the term arbitration refers to determination of dma channel priority, not arbitration for the bus. when the dma controller arbitrates for the bus, the processor always takes priority. furthermore, the dma controller is held off whenever the processor must perform a bus transaction on the same bus, even in the middle of a burst transfer. 8.2.4 request types the dma controller responds to two types of requests from a peripheral: single or burst. each peripheral may support either or both types of requests. a single request means that the peripheral is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items. 349 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller the dma controller responds differently depending on whether the peripheral is making a single request or a burst request. if both are asserted, and the dma channel has been set up for a burst transfer, then the burst request takes precedence. see table 8-2 on page 350, which shows how each peripheral supports the two request types. table 8-2. request type support burst request signal single request signal peripheral sequencer ie bit none adc none raw interrupt pulse general-purpose timer fifo service request none i 2 s tx fifo service request none i 2 s rx tx fifo level (fixed at 4) tx fifo not full ssi tx rx fifo level (fixed at 4) rx fifo not empty ssi rx tx fifo level (configurable) tx fifo not full uart tx rx fifo level (configurable) rx fifo not empty uart rx 8.2.4.1 single request when a single request is detected, and not a burst request, the dma controller transfers one item and then stops to wait for another request. 8.2.4.2 burst request when a burst request is detected, the dma controller transfers the number of items that is the lesser of the arbitration size or the number of items remaining in the transfer. therefore, the arbitration size should be the same as the number of data items that the peripheral can accommodate when making a burst request. for example, the uart generates a burst request based on the fifo trigger level. in this case, the arbitration size should be set to the amount of data that the fifo can transfer when the trigger level is reached. a burst transfer runs to completion once it is started, and cannot be interrupted, even by a higher priority channel. burst transfers complete in a shorter time than the same number of non-burst transfers. it may be desirable to use only burst transfers and not allow single transfers. for example, perhaps the nature of the data is such that it only makes sense when transferred together as a single unit rather than one piece at a time. the single request can be disabled by using the dma channel useburst set (dmauseburstset) register. by setting the bit for a channel in this register, the dma controller only responds to burst requests for that channel. 8.2.5 channel configuration the dma controller uses an area of system memory to store a set of channel control structures in a table. the control table may have one or two entries for each dma channel. each entry in the table structure contains source and destination pointers, transfer size, and transfer mode. the control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary. table 8-3 on page 351 shows the layout in memory of the channel control table. each channel may have one or two control structures in the control table: a primary control structure and an optional alternate control structure. the table is organized so that all of the primary entries are in the first half of the table, and all the alternate structures are in the second half of the table. the primary entry is used for simple transfer modes where transfers can be reconfigured and restarted after each transfer is complete. in this case, the alternate control structures are not used and therefore only the first half of the table must be allocated in memory; the second half of the control table is not march 20, 2011 350 texas instruments-advance information micro direct memory access (dma) necessary, and that memory can be used for something else. if a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table. any unused memory in the control table may be used by the application. this includes the control structures for any channels that are unused by the application as well as the unused control word for each channel. table 8-3. control structure memory map channel offset 0, primary 0x0 1, primary 0x10 ... ... 31, primary 0x1f0 0, alternate 0x200 1, alternate 0x210 ... ... 31, alternate 0x3f0 table 8-4 shows an individual control structure entry in the control table. each entry is aligned on a 16-byte boundary. the entry contains four long words: the source end pointer, the destination end pointer, the control word, and an unused entry. the end pointers point to the ending address of the transfer and are inclusive. if the source or destination is non-incrementing (as for a peripheral register), then the pointer should point to the transfer address. table 8-4. channel control structure description offset source end pointer 0x000 destination end pointer 0x004 control word 0x008 unused 0x00c the control word contains the following fields: source and destination data sizes source and destination address increment size number of transfers before bus arbitration total number of items to transfer useburst flag transfer mode the control word and each field are described in detail in dma channel control structure on page 368. the dma controller updates the transfer size and transfer mode fields as the transfer is performed. at the end of a transfer, the transfer size indicates 0, and the transfer mode indicates "stopped." because the control word is modified by the dma controller, it must be 351 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller reconfigured before each new transfer. the source and destination end pointers are not modified, so they can be left unchanged if the source or destination addresses remain the same. prior to starting a transfer, a dma channel must be enabled by setting the appropriate bit in the dma channel enable set (dmaenaset) register. a channel can be disabled by setting the channel bit in the dma channel enable clear (dmaenaclr) register. at the end of a complete dma transfer, the controller automatically disables the channel. 8.2.6 transfer modes the dma controller supports several transfer modes. two of the modes support simple one-time transfers. several complex modes support a continuous flow of data. 8.2.6.1 stop mode while stop is not actually a transfer mode, it is a valid value for the mode field of the control word. when the mode field has this value, the dma controller does not perform any transfers and disables the channel if it is enabled. at the end of a transfer, the dma controller updates the control word to set the mode to stop. 8.2.6.2 basic mode in basic mode, the dma controller performs transfers as long as there are more items to transfer, and a transfer request is present. this mode is used with peripherals that assert a dma request signal whenever the peripheral is ready for a data transfer. basic mode should not be used in any situation where the request is momentary even though the entire transfer should be completed. for example, a software-initiated transfer creates a momentary request, and in basic mode, only the number of transfers specified by the arbsize field in the dma channel control word (dmachctl) register is transferred on a software request, even if there is more data to transfer. when all of the items have been transferred using basic mode, the dma controller sets the mode for that channel to stop. 8.2.6.3 auto mode auto mode is similar to basic mode, except that once a transfer request is received, the transfer runs to completion, even if the dma request is removed. this mode is suitable for software-triggered transfers. generally, auto mode is not used with a peripheral. when all the items have been transferred using auto mode, the dma controller sets the mode for that channel to stop. 8.2.6.4 ping-pong ping-pong mode is used to support a continuous data flow to or from a peripheral. to use ping-pong mode, both the primary and alternate data structures must be implemented. both structures are set up by the processor for data transfer between memory and a peripheral. the transfer is started using the primary control structure. when the transfer using the primary control structure is complete, the dma controller reads the alternate control structure for that channel to continue the transfer. each time this happens, an interrupt is generated, and the processor can reload the control structure for the just-completed transfer. data flow can continue indefinitely this way, using the primary and alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. refer to figure 8-2 on page 353 for an example showing operation in ping-pong mode. march 20, 2011 352 texas instruments-advance information micro direct memory access (dma) figure 8-2. example of ping-pong dma transaction 8.2.6.5 memory scatter-gather memory scatter-gather mode is a complex mode used when data must be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. for example, a gather dma operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. 353 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller $ o w h u q d w h 6 w u x f w x u h 3 u l p d u \ 6 w u x f w x u h 3 u l p d u \ 6 w u x f w x u h $ o w h u q d w h 6 w u x f w x u h w u d q v i h u f r q w l q x h v x v l q j d o w h u q d w h % 8 ) ) ( 5 % % 8 ) ) ( 5 $ d d d d d d d d in memory scatter-gather mode, the primary control structure is used to program the alternate control structure from a table in memory. the table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. the mode of each control word must be set to scatter-gather mode. each entry in the table is copied in turn to the alternate structure where it is then executed. the dma controller alternates between using the primary control structure to copy the next transfer instruction from the list and then executing the new transfer instruction. the end of the list is marked by programming the control word for the last entry to use auto transfer mode. once the last transfer is performed using auto mode, the dma controller stops. a completion interrupt is generated only after the last transfer. it is possible to loop the list by having the last entry copy the primary control structure to point back to the beginning of the list (or to a new list). it is also possible to trigger a set of other channels to perform a transfer, either directly, by programming a write to the software trigger for another channel, or indirectly, by causing a peripheral action that results in a dma request. by programming the dma controller using this method, a set of arbitrary transfers can be performed based on a single dma request. refer to figure 8-3 on page 355 and figure 8-4 on page 356, which show an example of operation in memory scatter-gather mode. this example shows a gather operation, where data in three separate buffers in memory is copied together into one buffer. figure 8-3 on page 355 shows how the application sets up a dma task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. the primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. figure 8-4 on page 356 shows the sequence as the dma controller performs the three sets of copy operations. first, using the primary control structure, the dma controller loads the alternate control structure with task a. it then performs the copy operation specified by task a, copying the data from the source buffer a to the destination buffer. next, the dma controller again uses the primary control structure to load task b into the alternate control structure, and then performs the b operation with the alternate control structure. the process is repeated for task c. march 20, 2011 354 texas instruments-advance information micro direct memory access (dma) figure 8-3. memory scatter-gather, setup and configuration 355 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 1 2 7 ( 6 $ s s o l f d w l r q k d v d q h h g w r f r s \ g d w d l w h p v i u r p w k u h h v h s d u d w h o r f d w l r q v l q p h p r u \ l q w r r q h f r p e l q h g e x i i h u $ s s o l f d w l r q v h w v x s ? ' 0 $ 3 w d v n o l v w l q p h p r u \ z k l f k f r q w d l q v w k h s r l q w h u v d q g f r q w u r o f r q i l j x u d w l r q i r u w k u h h ? ' 0 $ f r s \ 3 w d v n v $ s s o l f d w l r q v h w v x s w k h f k d q q h o s u l p d u \ f r q w u r o v w u x f w x u h w r f r s \ h d f k w d v n f r q i l j x u d w l r q r q h d w d w l p h w r w k h d o w h u q d w h f r q w u r o v w u x f w x u h z k h u h l w l v h [ h f x w h g e \ w k h ? ' 0 $ f r q w u r o o h u & : 2 5 ' 6 6 5 & $ : 2 5 ' 6 6 5 & % 6 5 & ' 6 7 , 7 ( 0 6 8 q x v h g 6 5 & ' 6 7 , 7 ( 0 6 : 2 5 ' 6 5 & & ' ( 6 7 $ ' ( 6 7 % ' ( 6 7 & ' 6 7 $ % 3 7 $ 6 . $ 3 7 $ 6 . % 3 7 $ 6 . & 6 5 & ' 6 7 , 7 ( 0 6 6 5 & ' 6 7 , 7 ( 0 6 q 7 d v n / l v w l q 0 h p r u \ 6 r x u f h d q g ' h v w l q d w l r q % x i i h u l q 0 h p r u \ & k d q q h o & r q w u r o 7 d e o h l q 0 h p r u \ & k d q q h o 3 u l p d u \ & r q w u r o 6 w u x f w x u h & k d q q h o $ o w h u q d w h & r q w u r o 6 w u x f w x u h 8 q x v h g , 7 ( 0 6 6 5 & 8 q x v h g figure 8-4. memory scatter-gather, dma copy sequence march 20, 2011 356 texas instruments-advance information micro direct memory access (dma) 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 3 5 , $ / 7 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 7 d v n / l v w l q 0 h p r u \ ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 7 $ 6 . % 7 $ 6 . & 3 5 , $ / 7 6 5 & % 6 5 & & ' ( 6 7 % ' ( 6 7 & 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n $ f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u $ w r w k h g h v w l q d w l r q e x i i h u 7 d v n / l v w l q 0 h p r u \ ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n % f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u % w r w k h g h v w l q d w l r q e x i i h u ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n & f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u & w r w k h g h v w l q d w l r q e x i i h u 3 5 , $ / 7 7 d v n / l v w l q 0 h p r u \ 7 $ 6 . $ 7 $ 6 . % 7 $ 6 . $ 7 $ 6 . & 6 5 & $ 6 5 & & ' ( 6 7 $ ' ( 6 7 & 6 5 & $ 6 5 & % ' ( 6 7 $ ' ( 6 7 % 7 $ 6 . $ 7 $ 6 . % 6 5 & $ 7 $ 6 . & 6 5 & & ' ( 6 7 & 6 5 & % ' ( 6 7 % ' ( 6 7 $ 8.2.6.6 peripheral scatter-gather peripheral scatter-gather mode is very similar to memory scatter-gather, except that the transfers are controlled by a peripheral making a dma request. upon detecting a request from the peripheral, the dma controller uses the primary control structure to copy one entry from the list to the alternate control structure and then performs the transfer. at the end of this transfer, the next transfer is started only if the peripheral again asserts a dma request. the dma controller continues to perform transfers from the list only when the peripheral is making a request, until the last transfer is complete. a completion interrupt is generated only after the last transfer. by using this method, the dma controller can transfer data to or from a peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data. refer to figure 8-5 on page 358 and figure 8-6 on page 359, which show an example of operation in peripheral scatter-gather mode. this example shows a gather operation, where data from three separate buffers in memory is copied to a single peripheral data register. figure 8-5 on page 358 shows how the application sets up a dma task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. the primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. figure 8-6 on page 359 shows the sequence as the dma controller performs the three sets of copy operations. first, using the primary control structure, the dma controller loads the alternate control structure with task a. it then performs the copy operation specified by task a, copying the data from the source buffer a to the peripheral data register. next, the dma controller again uses the primary control structure to load task b into the alternate control structure, and then performs the b operation with the alternate control structure. the process is repeated for task c. 357 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 8-5. peripheral scatter-gather, setup and configuration march 20, 2011 358 texas instruments-advance information micro direct memory access (dma) & : 2 5 ' 6 6 5 & $ : 2 5 ' 6 6 5 & % : 2 5 ' 6 5 & & $ % 6 5 & ' 6 7 , 7 ( 0 6 6 5 & ' 6 7 , 7 ( 0 6 q 7 d v n / l v w l q 0 h p r u \ 6 r x u f h % x i i h u l q 0 h p r u \ & k d q q h o & r q w u r o 7 d e o h l q 0 h p r u \ & k d q q h o 3 u l p d u \ & r q w u r o 6 w u x f w x u h & k d q q h o $ o w h u q d w h & r q w u r o 6 w u x f w x u h ' ( 6 7 3 h u l s k h u d o ' d w d 5 h j l v w h u 6 5 & ' 6 7 , 7 ( 0 6 8 q x v h g 6 5 & ' 6 7 , 7 ( 0 6 ' 6 7 3 7 $ 6 . $ 3 7 $ 6 . % 3 7 $ 6 . & 8 q x v h g , 7 ( 0 6 6 5 & 8 q x v h g 1 2 7 ( 6 $ s s o l f d w l r q k d v d q h h g w r f r s \ g d w d l w h p v i u r p w k u h h v h s d u d w h o r f d w l r q v l q p h p r u \ l q w r d s h u l s k h u d o g d w d u h j l v w h u $ s s o l f d w l r q v h w v x s ? ' 0 $ 3 w d v n o l v w l q p h p r u \ z k l f k f r q w d l q v w k h s r l q w h u v d q g f r q w u r o f r q i l j x u d w l r q i r u w k u h h ? ' 0 $ f r s \ 3 w d v n v $ s s o l f d w l r q v h w v x s w k h f k d q q h o s u l p d u \ f r q w u r o v w u x f w x u h w r f r s \ h d f k w d v n f r q i l j x u d w l r q r q h d w d w l p h w r w k h d o w h u q d w h f r q w u r o v w u x f w x u h z k h u h l w l v h [ h f x w h g e \ w k h ? ' 0 $ f r q w u r o o h u figure 8-6. peripheral scatter-gather, dma copy sequence 359 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 5 & & 7 $ 6 . $ 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 3 5 , $ / 7 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 7 d v n / l v w l q 0 h p r u \ ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 7 $ 6 . % 7 $ 6 . & 3 5 , $ / 7 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n $ f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u $ w r w k h s h u l s k h u d o g d w d u h j l v w h u 7 d v n / l v w l q 0 h p r u \ ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n % f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u % w r w k h s h u l s k h u d o g d w d u h j l v w h u ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n & f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u & w r w k h s h u l s k h u d o g d w d u h j l v w h u 3 5 , $ / 7 7 d v n / l v w l q 0 h p r u \ 7 $ 6 . $ 7 $ 6 . % 7 $ 6 . $ 7 $ 6 . & 3 h u l s k h u d o ' d w d 5 h j l v w h u 6 5 & % 6 5 & & 3 h u l s k h u d o ' d w d 5 h j l v w h u 6 5 & $ 6 5 & & 3 h u l s k h u d o ' d w d 5 h j l v w h u 6 5 & $ 6 5 & % 7 $ 6 . % 7 $ 6 . & 6 5 & % 6 5 & $ 8.2.7 transfer size and increment the dma controller supports transfer data sizes of 8, 16, or 32 bits. the source and destination data size must be the same for any given transfer. the source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment. the source and destination address increment values can be set independently, and it is not necessary for the address increment to match the data size as long as the increment is the same or larger than the data size. for example, it is possible to perform a transfer using 8-bit data size, but using an address increment of full words (4 bytes). the data to be transferred must be aligned in memory according to the data size (8, 16, or 32 bits). table 8-5 shows the configuration to read from a peripheral that supplies 8-bit data. table 8-5. dma read example: 8-bit peripheral configuration field 8 bits source data size 8 bits destination data size no increment source address increment byte destination address increment peripheral read fifo register source end pointer end of the data buffer in memory destination end pointer 8.2.8 peripheral interface each peripheral that supports dma has a single request and/or burst request signal that is asserted when the peripheral is ready to transfer data (see table 8-2 on page 350). the request signal can be disabled or enabled using the dma channel request mask set (dmareqmaskset) and dma channel request mask clear (dmareqmaskclr) registers. the dma request signal is disabled, or masked, when the channel request mask bit is set. when the request is not masked, the dma channel is configured correctly and enabled, and the peripheral asserts the request signal, the dma controller begins the transfer. note: when using dma to transfer data to and from a peripheral, the peripheral must disable all interrupts to the nvic. when a dma transfer is complete, the dma controller generates an interrupt, see interrupts and errors on page 361 for more information. for more information on how a specific peripheral interacts with the dma controller, refer to the dma operation section in the chapter that discusses that peripheral. 8.2.9 software request one dma channel is dedicated to software-initiated transfers. this channel also has a dedicated interrupt to signal completion of a dma transfer. a transfer is initiated by software by first configuring and enabling the transfer, and then issuing a software request using the dma channel software request (dmaswreq) register. for software-based transfers, the auto transfer mode should be used. it is possible to initiate a transfer on any channel using the dmaswreq register. if a request is initiated by software using a peripheral dma channel, then the completion interrupt occurs on the interrupt vector for the peripheral instead of the software interrupt vector. any channel may be used for software requests as long as the corresponding peripheral is not using dma for data transfer. march 20, 2011 360 texas instruments-advance information micro direct memory access (dma) 8.2.10 interrupts and errors when a dma transfer is complete, the dma controller generates a completion interrupt on the interrupt vector of the peripheral. therefore, if dma is used to transfer data for a peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed to handle the dma transfer completion interrupt. if the transfer uses the software dma channel, then the completion interrupt occurs on the dedicated software dma interrupt vector (see table 8-6 on page 361). when dma is enabled for a peripheral, the dma controller stops the normal transfer interrupts for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's interrupt registers). thus, when a large amount of data is transferred using dma, instead of receiving multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt when the transfer is complete. unmasked peripheral error interrupts continue to be sent to the interrupt controller. if the dma controller encounters a bus or memory protection error as it attempts to perform a data transfer, it disables the dma channel that caused the error and generates an interrupt on the dma error interrupt vector. the processor can read the dma bus error clear (dmaerrclr) register to determine if an error is pending. the errclr bit is set if an error occurred. the error can be cleared by writing a 1 to the errclr bit. table 8-6 shows the dedicated interrupt assignments for the dma controller. table 8-6. dma interrupt assignments assignment interrupt dma software channel transfer 46 dma error 47 8.3 initialization and configuration 8.3.1 module initialization before the dma controller can be used, it must be enabled in the system control block and in the peripheral. the location of the channel control structure must also be programmed. the following steps should be performed one time during system initialization: 1. the dma peripheral must be enabled in the system control block. to do this, set the udma bit of the system control rcgc2 register (see page 269). 2. enable the dma controller by setting the masteren bit of the dma configuration (dmacfg) register. 3. program the location of the channel control table by writing the base address of the table to the dma channel control base pointer (dmactlbase) register. the base address must be aligned on a 1024-byte boundary. 8.3.2 configuring a memory-to-memory transfer dma channel 30 is dedicated for software-initiated transfers. however, any channel can be used for software-initiated, memory-to-memory transfer if the associated peripheral is not being used. 361 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 8.3.2.1 configure the channel attributes first, configure the channel attributes: 1. program bit 30 of the dma channel priority set (dmaprioset) or dma channel priority clear (dmaprioclr) registers to set the channel to high priority or default priority. 2. set bit 30 of the dma channel primary alternate clear (dmaaltclr) register to select the primary channel control structure for this transfer. 3. set bit 30 of the dma channel useburst clear (dmauseburstclr) register to allow the dma controller to respond to single and burst requests. 4. set bit 30 of the dma channel request mask clear (dmareqmaskclr) register to allow the dma controller to recognize requests for this channel. 8.3.2.2 configure the channel control structure now the channel control structure must be configured. this example transfers 256 words from one memory buffer to another. channel 30 is used for a software transfer, and the control structure for channel 30 is at offset 0x1e0 of the channel control table. the channel control structure for channel 30 is located at the offsets shown in table 8-7. table 8-7. channel control structure offsets for channel 30 description offset channel 30 source end pointer control table base + 0x1e0 channel 30 destination end pointer control table base + 0x1e4 channel 30 control word control table base + 0x1e8 configure the source and destination the source and destination end pointers must be set to the last address for the transfer (inclusive). 1. program the source end pointer at offset 0x1e0 to the address of the source buffer + 0x3fc. 2. program the destination end pointer at offset 0x1e4 to the address of the destination buffer + 0x3fc. the control word at offset 0x1e8 must be programmed according to table 8-8. table 8-8. channel control word configuration for memory transfer example description value bits field in dmachctl 32-bit destination address increment 2 31:30 dstinc 32-bit destination data size 2 29:28 dstsize 32-bit source address increment 2 27:26 srcinc 32-bit source data size 2 25:24 srcsize reserved 0 23:18 reserved arbitrates after 8 transfers 3 17:14 arbsize transfer 256 items 255 13:4 xfersize n/a for this transfer type 0 3 nxtuseburst use auto-request transfer mode 2 2:0 xfermode march 20, 2011 362 texas instruments-advance information micro direct memory access (dma) 8.3.2.3 start the transfer now the channel is configured and is ready to start. 1. enable the channel by setting bit 30 of the dma channel enable set (dmaenaset) register. 2. issue a transfer request by setting bit 30 of the dma channel software request (dmaswreq) register. the dma transfer begins. if the interrupt is enabled, then the processor is notified by interrupt when the transfer is complete. if needed, the status can be checked by reading bit 30 of the dmaenaset register. this bit is automatically cleared when the transfer is complete. the status can also be checked by reading the xfermode field of the channel control word at offset 0x1e8. this field is automatically cleared at the end of the transfer. 8.3.3 configuring a peripheral for simple transmit this example configures the dma controller to transmit a buffer of data to a peripheral. the peripheral has a transmit fifo with a trigger level of 4. the example peripheral uses dma channel 7. 8.3.3.1 configure the channel attributes first, configure the channel attributes: 1. configure bit 7 of the dma channel priority set (dmaprioset) or dma channel priority clear (dmaprioclr) registers to set the channel to high priority or default priority. 2. set bit 7 of the dma channel primary alternate clear (dmaaltclr) register to select the primary channel control structure for this transfer. 3. set bit 7 of the dma channel useburst clear (dmauseburstclr) register to allow the dma controller to respond to single and burst requests. 4. set bit 7 of the dma channel request mask clear (dmareqmaskclr) register to allow the dma controller to recognize requests for this channel. 8.3.3.2 configure the channel control structure this example transfers 64 bytes from a memory buffer to the peripheral's transmit fifo register using dma channel 7. the control structure for channel 7 is at offset 0x070 of the channel control table. the channel control structure for channel 7 is located at the offsets shown in table 8-9. table 8-9. channel control structure offsets for channel 7 description offset channel 7 source end pointer control table base + 0x070 channel 7 destination end pointer control table base + 0x074 channel 7 control word control table base + 0x078 configure the source and destination the source and destination end pointers must be set to the last address for the transfer (inclusive). because the peripheral pointer does not change, it simply points to the peripheral's data register. 1. program the source end pointer at offset 0x070 to the address of the source buffer + 0x3f. 363 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 2. program the destination end pointer at offset 0x074 to the address of the peripheral's transmit fifo register. the control word at offset 0x078 must be programmed according to table 8-10. table 8-10. channel control word configuration for peripheral transmit example description value bits field in dmachctl destination address does not increment 3 31:30 dstinc 8-bit destination data size 0 29:28 dstsize 8-bit source address increment 0 27:26 srcinc 8-bit source data size 0 25:24 srcsize reserved 0 23:18 reserved arbitrates after 4 transfers 2 17:14 arbsize transfer 64 items 63 13:4 xfersize n/a for this transfer type 0 3 nxtuseburst use basic transfer mode 1 2:0 xfermode note: in this example, it is not important if the peripheral makes a single request or a burst request. because the peripheral has a fifo that triggers at a level of 4, the arbitration size is set to 4. if the peripheral does make a burst request, then 4 bytes are transferred, which is what the fifo can accommodate. if the peripheral makes a single request (if there is any space in the fifo), then one byte is transferred at a time. if it is important to the application that transfers only be made in bursts, then the channel useburst set[7] bit should be set in the dma channel useburst set (dmauseburstset) register. 8.3.3.3 start the transfer now the channel is configured and is ready to start. 1. enable the channel by setting bit 7 of the dma channel enable set (dmaenaset) register. the dma controller is now configured for transfer on channel 7. the controller makes transfers to the peripheral whenever the peripheral asserts a dma request. the transfers continue until the entire buffer of 64 bytes has been transferred. when that happens, the dma controller disables the channel and sets the xfermode field of the channel control word to 0 (stopped). the status of the transfer can be checked by reading bit 7 of the dma channel enable set (dmaenaset) register. this bit is automatically cleared when the transfer is complete. the status can also be checked by reading the xfermode field of the channel control word at offset 0x078. this field is automatically cleared at the end of the transfer. if peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when the entire transfer is complete. 8.3.4 configuring a peripheral for ping-pong receive this example configures the dma controller to continuously receive 8-bit data from a peripheral into a pair of 64-byte buffers. the peripheral has a receive fifo with a trigger level of 8. the example peripheral uses dma channel 8. 8.3.4.1 configure the channel attributes first, configure the channel attributes: march 20, 2011 364 texas instruments-advance information micro direct memory access (dma) 1. configure bit 8 of the dma channel priority set (dmaprioset) or dma channel priority clear (dmaprioclr) registers to set the channel to high priority or default priority. 2. set bit 8 of the dma channel primary alternate clear (dmaaltclr) register to select the primary channel control structure for this transfer. 3. set bit 8 of the dma channel useburst clear (dmauseburstclr) register to allow the dma controller to respond to single and burst requests. 4. set bit 8 of the dma channel request mask clear (dmareqmaskclr) register to allow the dma controller to recognize requests for this channel. 8.3.4.2 configure the channel control structure this example transfers bytes from the peripheral's receive fifo register into two memory buffers of 64 bytes each. as data is received, when one buffer is full, the dma controller switches to use the other. to use ping-pong buffering, both primary and alternate channel control structures must be used. the primary control structure for channel 8 is at offset 0x080 of the channel control table, and the alternate channel control structure is at offset 0x280. the channel control structures for channel 8 are located at the offsets shown in table 8-11. table 8-11. primary and alternate channel control structure offsets for channel 8 description offset channel 8 primary source end pointer control table base + 0x080 channel 8 primary destination end pointer control table base + 0x084 channel 8 primary control word control table base + 0x088 channel 8 alternate source end pointer control table base + 0x280 channel 8 alternate destination end pointer control table base + 0x284 channel 8 alternate control word control table base + 0x288 configure the source and destination the source and destination end pointers must be set to the last address for the transfer (inclusive). because the peripheral pointer does not change, it simply points to the peripheral's data register. both the primary and alternate sets of pointers must be configured. 1. program the primary source end pointer at offset 0x080 to the address of the peripheral's receive buffer. 2. program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer a + 0x3f. 3. program the alternate source end pointer at offset 0x280 to the address of the peripheral's receive buffer. 4. program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer b + 0x3f. the primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially programmed the same way. 1. program the primary channel control word at offset 0x088 according to table 8-12. 365 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 2. program the alternate channel control word at offset 0x288 according to table 8-12. table 8-12. channel control word configuration for peripheral ping-pong receive example description value bits field in dmachctl 8-bit destination address increment 0 31:30 dstinc 8-bit destination data size 0 29:28 dstsize source address does not increment 3 27:26 srcinc 8-bit source data size 0 25:24 srcsize reserved 0 23:18 reserved arbitrates after 8 transfers 3 17:14 arbsize transfer 64 items 63 13:4 xfersize n/a for this transfer type 0 3 nxtuseburst use ping-pong transfer mode 3 2:0 xfermode note: in this example, it is not important if the peripheral makes a single request or a burst request. because the peripheral has a fifo that triggers at a level of 8, the arbitration size is set to 8. if the peripheral does make a burst request, then 8 bytes are transferred, which is what the fifo can accommodate. if the peripheral makes a single request (if there is any data in the fifo), then one byte is transferred at a time. if it is important to the application that transfers only be made in bursts, then the channel useburst set[8] bit should be set in the dma channel useburst set (dmauseburstset) register. 8.3.4.3 configure the peripheral interrupt an interrupt handler should be configured when using dma ping-pong mode, it is best to use an interrupt handler. however, the ping-pong mode can be configured without interrupts by polling. the interrupt handler is triggered after each buffer is complete. 1. configure and enable an interrupt handler for the peripheral. 8.3.4.4 enable the dma channel now the channel is configured and is ready to start. 1. enable the channel by setting bit 8 of the dma channel enable set (dmaenaset) register. 8.3.4.5 process interrupts the dma controller is now configured and enabled for transfer on channel 8. when the peripheral asserts the dma request signal, the dma controller makes transfers into buffer a using the primary channel control structure. when the primary transfer to buffer a is complete, it switches to the alternate channel control structure and makes transfers into buffer b. at the same time, the primary channel control word mode field is configured to indicate stopped, and an interrupt is when an interrupt is triggered, the interrupt handler must determine which buffer is complete and process the data or set a flag that the data must be processed by non-interrupt buffer processing code. then the next buffer transfer must be set up. in the interrupt handler: 1. read the primary channel control word at offset 0x088 and check the xfermode field. if the field is 0, this means buffer a is complete. if buffer a is complete, then: march 20, 2011 366 texas instruments-advance information micro direct memory access (dma) a. process the newly received data in buffer a or signal the buffer processing code that buffer a has data available. b. reprogram the primary channel control word at offset 0x88 according to table 8-12 on page 366. 2. read the alternate channel control word at offset 0x288 and check the xfermode field. if the field is 0, this means buffer b is complete. if buffer b is complete, then: a. process the newly received data in buffer b or signal the buffer processing code that buffer b has data available. b. reprogram the alternate channel control word at offset 0x288 according to table 8-12 on page 366. 8.3.5 configuring channel assignments channel assignments for each dma channel can be changed using the dmachasgn register. each bit represents a dma channel. if the bit is set, then the secondary function is used for the channel. refer to table 8-1 on page 348 for channel assignments. for example, to use ssi1 receive on channel 8 instead of uart0, set bit 8 of the dmachasgn register. 8.4 register map table 8-13 on page 367 lists the dma channel control structures and registers. the channel control structure shows the layout of one entry in the channel control table. the channel control table is located in system memory, and the location is determined by the application, that is, the base address is n/a (not applicable). in the table below, the offset for the channel control structures is the offset from the entry in the channel control table. see channel configuration on page 350 and table 8-3 on page 351 for a description of how the entries in the channel control table are located in memory. the dma register addresses are given as a hexadecimal increment, relative to the dma base address of 0x400f.f000. note that the dma module clock must be enabled before the registers can be programmed (see page 269). there must be a delay of 3 system clocks after the dma module clock is enabled before any dma module registers are accessed. table 8-13. dma register map see page description reset type name offset dma channel control structure (offset from channel control table base) 369 dma channel source address end pointer - r/w dmasrcendp 0x000 370 dma channel destination address end pointer - r/w dmadstendp 0x004 371 dma channel control word - r/w dmachctl 0x008 dma registers (offset from dma base address) 376 dma status 0x001f.0000 ro dmastat 0x000 378 dma configuration - wo dmacfg 0x004 379 dma channel control base pointer 0x0000.0000 r/w dmactlbase 0x008 367 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 8-13. dma register map (continued) see page description reset type name offset 380 dma alternate channel control base pointer 0x0000.0200 ro dmaaltbase 0x00c 381 dma channel wait-on-request status 0xffff.ffc0 ro dmawaitstat 0x010 382 dma channel software request - wo dmaswreq 0x014 383 dma channel useburst set 0x0000.0000 r/w dmauseburstset 0x018 384 dma channel useburst clear - wo dmauseburstclr 0x01c 385 dma channel request mask set 0x0000.0000 r/w dmareqmaskset 0x020 386 dma channel request mask clear - wo dmareqmaskclr 0x024 387 dma channel enable set 0x0000.0000 r/w dmaenaset 0x028 388 dma channel enable clear - wo dmaenaclr 0x02c 389 dma channel primary alternate set 0x0000.0000 r/w dmaaltset 0x030 390 dma channel primary alternate clear - wo dmaaltclr 0x034 391 dma channel priority set 0x0000.0000 r/w dmaprioset 0x038 392 dma channel priority clear - wo dmaprioclr 0x03c 393 dma bus error clear 0x0000.0000 r/w dmaerrclr 0x04c 394 dma channel assignment 0x0000.0000 r/w dmachasgn 0x500 399 dma peripheral identification 4 0x0000.0004 ro dmaperiphid4 0xfd0 395 dma peripheral identification 0 0x0000.0030 ro dmaperiphid0 0xfe0 396 dma peripheral identification 1 0x0000.00b2 ro dmaperiphid1 0xfe4 397 dma peripheral identification 2 0x0000.000b ro dmaperiphid2 0xfe8 398 dma peripheral identification 3 0x0000.0000 ro dmaperiphid3 0xfec 400 dma primecell identification 0 0x0000.000d ro dmapcellid0 0xff0 401 dma primecell identification 1 0x0000.00f0 ro dmapcellid1 0xff4 402 dma primecell identification 2 0x0000.0005 ro dmapcellid2 0xff8 403 dma primecell identification 3 0x0000.00b1 ro dmapcellid3 0xffc 8.5 dma channel control structure the dma channel control structure holds the transfer settings for a dma channel. each channel has two control structures, which are located in a table in system memory. refer to channel configuration on page 350 for an explanation of the channel control table and the channel control structure. the channel control structure is one entry in the channel control table. each channel has a primary and alternate structure. the primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. the alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. march 20, 2011 368 texas instruments-advance information micro direct memory access (dma) register 1: dma channel source address end pointer (dmasrcendp), offset 0x000 dma channel source address end pointer (dmasrcendp) is part of the channel control structure and is used to specify the source address for a dma transfer. the dma controller can transfer data to and from the on-chip sram. however, because the flash memory and rom are located on a separate internal bus, it is not possible to transfer data from the flash memory or rom with the dma controller. note: the offset specified is from the base address of the control structure in system memory, not the dma module base address. dma channel source address end pointer (dmasrcendp) base n/a offset 0x000 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field source address end pointer this field points to the last address of the dma transfer source (inclusive). if the source address is not incrementing (the srcinc field in the dmachctl register is 0x3), then this field points at the source location itself (such as a peripheral data register). - r/w addr 31:0 369 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: dma channel destination address end pointer (dmadstendp), offset 0x004 dma channel destination address end pointer (dmadstendp) is part of the channel control structure and is used to specify the destination address for a dma transfer. note: the offset specified is from the base address of the control structure in system memory, not the dma module base address. dma channel destination address end pointer (dmadstendp) base n/a offset 0x004 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field destination address end pointer this field points to the last address of the dma transfer destination (inclusive). if the destination address is not incrementing (the dstinc field in the dmachctl register is 0x3), then this field points at the destination location itself (such as a peripheral data register). - r/w addr 31:0 march 20, 2011 370 texas instruments-advance information micro direct memory access (dma) register 3: dma channel control word (dmachctl), offset 0x008 dma channel control word (dmachctl) is part of the channel control structure and is used to specify parameters of a dma transfer. note: the offset specified is from the base address of the control structure in system memory, not the dma module base address. dma channel control word (dmachctl) base n/a offset 0x008 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 arbsize reserved srcsize srcinc dstsize dstinc r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 xfermode nxtuseburst xfersize arbsize r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field destination address increment this field configures the destination address increment. the address increment value must be equal or greater than the value of the destination size ( dstsize). description value byte increment by 8-bit locations 0x0 half-word increment by 16-bit locations 0x1 word increment by 32-bit locations 0x2 no increment address remains set to the value of the destination address end pointer ( dmadstendp ) for the channel 0x3 - r/w dstinc 31:30 destination data size this field configures the destination item data size. note: dstsize must be the same as srcsize. description value byte 8-bit data size 0x0 half-word 16-bit data size 0x1 word 32-bit data size 0x2 reserved 0x3 - r/w dstsize 29:28 371 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field source address increment this field configures the source address increment. the address increment value must be equal or greater than the value of the source size ( srcsize). description value byte increment by 8-bit locations 0x0 half-word increment by 16-bit locations 0x1 word increment by 32-bit locations 0x2 no increment address remains set to the value of the source address end pointer ( dmasrcendp ) for the channel 0x3 - r/w srcinc 27:26 source data size this field configures the source item data size. note: dstsize must be the same as srcsize. description value byte 8-bit data size. 0x0 half-word 16-bit data size. 0x1 word 32-bit data size. 0x2 reserved 0x3 - r/w srcsize 25:24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. - r/w reserved 23:18 march 20, 2011 372 texas instruments-advance information micro direct memory access (dma) description reset type name bit/field arbitration size this field configures the number of transfers that can occur before the dma controller re-arbitrates. the possible arbitration rate configurations represent powers of 2 and are shown below. description value 1 transfer arbitrates after each dma transfer 0x0 2 transfers 0x1 4 transfers 0x2 8 transfers 0x3 16 transfers 0x4 32 transfers 0x5 64 transfers 0x6 128 transfers 0x7 256 transfers 0x8 512 transfers 0x9 1024 transfers in this configuration, no arbitration occurs during the dma transfer because the maximum transfer size is 1024. 0xa-0xf - r/w arbsize 17:14 transfer size (minus 1) this field configures the total number of items to transfer. the value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). the maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. the transfer size is the number of items, not the number of bytes. if the data size is 32 bits, then this value is the number of 32-bit words to transfer. the dma controller updates this field immediately prior to entering the arbitration process, so it contains the number of outstanding items that is necessary to complete the dma cycle. - r/w xfersize 13:4 next useburst this field controls whether the useburst set[n] bit is automatically set for the last transfer of a peripheral scatter-gather operation. normally, for the last transfer, if the number of remaining items to transfer is less than the arbitration size, the dma controller uses single transfers to complete the transaction. if this bit is set, then the controller uses a burst transfer to complete the last transfer. - r/w nxtuseburst 3 373 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field dma transfer mode this field configures the operating mode of the dma cycle. refer to transfer modes on page 352 for a detailed explanation of transfer modes. because this register is in system ram, it has no reset value. therefore, this field should be initialized to 0 before the channel is enabled. description value stop 0x0 basic 0x1 auto-request 0x2 ping-pong 0x3 memory scatter-gather 0x4 alternate memory scatter-gather 0x5 peripheral scatter-gather 0x6 alternate peripheral scatter-gather 0x7 - r/w xfermode 2:0 xfermode bit field values. stop channel is stopped or configuration data is invalid. no more transfers can occur. basic for each trigger (whether from a peripheral or a software request), the dma controller performs the number of transfers specified by the arbsize field. auto-request the initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of xfersize items without any further requests. ping-pong this mode uses both the primary and alternate control structures for this channel. when the number of transfers specified by the xfersize field have completed for the current control structure (primary or alternate), the dma controller switches to the other one. these switches continue until one of the control structures is not set to ping-pong mode. at that point, the dma controller stops. an interrupt is generated on completion of the transfers configured by each control structure. see ping-pong on page 352. memory scatter-gather when using this mode, the primary control structure for the channel is configured to allow a list of operations (tasks) to be performed. the source address pointer specifies the start of a table of tasks to be copied to the alternate control structure for this channel. the xfermode field for the alternate control structure should be configured to 0x5 (alternate memory scatter-gather) to perform the task. when the task completes, the dma switches back to the primary channel control structure, which then copies the next task to the alternate control structure. this process continues until the table of tasks is empty. the last task must have an xfermode value other than 0x5. note that for continuous operation, the last task can update the primary channel control structure back to the start of the list or to another list. see memory scatter-gather on page 353. march 20, 2011 374 texas instruments-advance information micro direct memory access (dma) alternate memory scatter-gather this value must be used in the alternate channel control data structure when the dma controller operates in memory scatter-gather mode. peripheral scatter-gather this value must be used in the primary channel control data structure when the dma controller operates in peripheral scatter-gather mode. in this mode, the dma controller operates exactly the same as in memory scatter-gather mode, except that instead of performing the number of transfers specified by the xfersize field in the alternate control structure at one time, the dma controller only performs the number of transfers specified by the arbsize field per trigger; see basic mode for details. see peripheral scatter-gather on page 357. alternate peripheral scatter-gather this value must be used in the alternate channel control data structure when the dma controller operates in peripheral scatter-gather mode. 8.6 dma register descriptions the register addresses given are relative to the dma base address of 0x400f.f000. 375 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: dma status (dmastat), offset 0x000 the dma status (dmastat) register returns the status of the dma controller. you cannot read this register when the dma controller is in the reset state. dma status (dmastat) base 0x400f.f000 offset 0x000 type ro, reset 0x001f.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dmachans reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 masten reserved state reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:21 available dma channels minus 1 this field contains a value equal to the number of dma channels the dma controller is configured to use, minus one. the value of 0x1f corresponds to 32 dma channels. 0x1f ro dmachans 20:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:8 control state machine status this field shows the current status of the control state machine. status can be one of the following. description value idle 0x0 reading channel controller data. 0x1 reading source end pointer. 0x2 reading destination end pointer. 0x3 reading source data. 0x4 writing destination data. 0x5 waiting for dma request to clear. 0x6 writing channel controller data. 0x7 stalled 0x8 done 0x9 undefined 0xa-0xf 0x0 ro state 7:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 march 20, 2011 376 texas instruments-advance information micro direct memory access (dma) description reset type name bit/field master enable status description value the dma controller is disabled. 0 the dma controller is enabled. 1 0 ro masten 0 377 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 5: dma configuration (dmacfg), offset 0x004 the dmacfg register controls the configuration of the dma controller. dma configuration (dmacfg) base 0x400f.f000 offset 0x004 type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 masten reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. - wo reserved 31:1 controller master enable description value disables the dma controller. 0 enables dma controller. 1 - wo masten 0 march 20, 2011 378 texas instruments-advance information micro direct memory access (dma) register 6: dma channel control base pointer (dmactlbase), offset 0x008 the dmactlbase register must be configured so that the base pointer points to a location in system memory. the amount of system memory that must be assigned to the dma controller depends on the number of dma channels used and whether the alternate channel control data structure is used. see channel configuration on page 350 for details about the channel control table. the base address must be aligned on a 1024-byte boundary. this register cannot be read when the dma controller is in the reset state. dma channel control base pointer (dmactlbase) base 0x400f.f000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved addr ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel control base address this field contains the pointer to the base address of the channel control table. the base address must be 1024-byte aligned. 0x0000.00 r/w addr 31:10 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 9:0 379 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 7: dma alternate channel control base pointer (dmaaltbase), offset 0x00c the dmaaltbase register returns the base address of the alternate channel control data. this register removes the necessity for application software to calculate the base address of the alternate channel control structures. this register cannot be read when the dma controller is in the reset state. dma alternate channel control base pointer (dmaaltbase) base 0x400f.f000 offset 0x00c type ro, reset 0x0000.0200 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 reset description reset type name bit/field alternate channel address pointer this field provides the base address of the alternate channel control structures. 0x0000.0200 ro addr 31:0 march 20, 2011 380 texas instruments-advance information micro direct memory access (dma) register 8: dma channel wait-on-request status (dmawaitstat), offset 0x010 this read-only register indicates that the dma channel is waiting on a request. a peripheral can hold off the dma from performing a single request until the peripheral is ready for a burst request to enhance the dma performance. the use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. this register cannot be read when the dma controller is in the reset state. dma channel wait-on-request status (dmawaitstat) base 0x400f.f000 offset 0x010 type ro, reset 0xffff.ffc0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 waitreq[n] ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 waitreq[n] ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field channel [n] wait status these bits provide the channel wait-on-request status. bit 0 corresponds to channel 0. description value the corresponding channel is waiting on a request. 1 the corresponding channel is not waiting on a request. 0 0xffff.ffc0 ro waitreq[n] 31:0 381 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 9: dma channel software request (dmaswreq), offset 0x014 each bit of the dmaswreq register represents the corresponding dma channel. setting a bit generates a request for the specified dma channel. dma channel software request (dmaswreq) base 0x400f.f000 offset 0x014 type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 swreq[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 swreq[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] software request these bits generate software requests. bit 0 corresponds to channel 0. description value generate a software request for the corresponding channel. 1 no request generated. 0 these bits are automatically cleared when the software request has been completed. - wo swreq[n] 31:0 march 20, 2011 382 texas instruments-advance information micro direct memory access (dma) register 10: dma channel useburst set (dmauseburstset), offset 0x018 each bit of the dmauseburstset register represents the corresponding dma channel. setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. reading the register returns the status of useburst. if the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding set[n] bit is cleared after completing the final transfer. if there are fewer items remaining to transfer than the arbitration (burst) size, the dma controller automatically clears the corresponding set[n ] bit, allowing the remaining items to transfer using single requests. in order to resume transfers using burst requests, the corresponding bit must be set again. a bit should not be set if the corresponding peripheral does not support the burst request model. refer to request types on page 349 for more details about request types. dma channel useburst set (dmauseburstset) base 0x400f.f000 offset 0x018 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] useburst set description value dma channel [n] responds to single or burst requests. 0 dma channel [n] responds only to burst requests. 1 bit 0 corresponds to channel 0. this bit is automatically cleared as described above. a bit can also be manually cleared by setting the corresponding clr[n] bit in the dmauseburstclr register. 0x0000.0000 r/w set[n] 31:0 383 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 11: dma channel useburst clear (dmauseburstclr), offset 0x01c each bit of the dmauseburstclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmauseburstset register. dma channel useburst clear (dmauseburstclr) base 0x400f.f000 offset 0x01c type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] useburst clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmauseburstset register meaning that dma channel [n] responds to single and burst requests. 1 - wo clr[n] 31:0 march 20, 2011 384 texas instruments-advance information micro direct memory access (dma) register 12: dma channel request mask set (dmareqmaskset), offset 0x020 each bit of the dmareqmaskset register represents the corresponding dma channel. setting a bit disables dma requests for the channel. reading the register returns the request mask status. when a dma channel's request is masked, that means the peripheral can no longer request dma transfers. the channel can then be used for software-initiated transfers. dma channel request mask set (dmareqmaskset) base 0x400f.f000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] request mask set description value the peripheral associated with channel [n] is enabled to request dma transfers. 0 the peripheral associated with channel [n] is not able to request dma transfers. channel [n] may be used for software-initiated transfers. 1 bit 0 corresponds to channel 0. a bit can only be cleared by setting the corresponding clr[n] bit in the dmareqmaskclr register. 0x0000.0000 r/w set[n] 31:0 385 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 13: dma channel request mask clear (dmareqmaskclr), offset 0x024 each bit of the dmareqmaskclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmareqmaskset register. dma channel request mask clear (dmareqmaskclr) base 0x400f.f000 offset 0x024 type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] request mask clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmareqmaskset register meaning that the peripheral associated with channel [n] is enabled to request dma transfers. 1 - wo clr[n] 31:0 march 20, 2011 386 texas instruments-advance information micro direct memory access (dma) register 14: dma channel enable set (dmaenaset), offset 0x028 each bit of the dmaenaset register represents the corresponding dma channel. setting a bit enables the corresponding dma channel. reading the register returns the enable status of the channels. if a channel is enabled but the request mask is set ( dmareqmaskset ), then the channel can be used for software-initiated transfers. dma channel enable set (dmaenaset) base 0x400f.f000 offset 0x028 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] enable set description value dma channel [n] is disabled. 0 dma channel [n] is enabled. 1 bit 0 corresponds to channel 0. a bit can only be cleared by setting the corresponding clr[n] bit in the dmaenaclr register. 0x0000.0000 r/w set[n] 31:0 387 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 15: dma channel enable clear (dmaenaclr), offset 0x02c each bit of the dmaenaclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmaenaset register. dma channel enable clear (dmaenaclr) base 0x400f.f000 offset 0x02c type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field clear channel [n] enable clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmaenaset register meaning that channel [n] is disabled for dma transfers. 1 note: the controller disables a channel when it completes the dma cycle. - wo clr[n] 31:0 march 20, 2011 388 texas instruments-advance information micro direct memory access (dma) register 16: dma channel primary alternate set (dmaaltset), offset 0x030 each bit of the dmaaltset register represents the corresponding dma channel. setting a bit configures the dma channel to use the alternate control data structure. reading the register returns the status of which control data structure is in use for the corresponding dma channel. dma channel primary alternate set (dmaaltset) base 0x400f.f000 offset 0x030 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] alternate set description value dma channel [n] is using the primary control structure. 0 dma channel [n] is using the alternate control structure. 1 bit 0 corresponds to channel 0. a bit can only be cleared by setting the corresponding clr[n] bit in the dmaaltclr register. note: for ping-pong and scatter-gather cycle types, the dma controller automatically sets these bits to select the alternate channel control data structure. 0x0000.0000 r/w set[n] 31:0 389 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 17: dma channel primary alternate clear (dmaaltclr), offset 0x034 each bit of the dmaaltclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmaaltset register. dma channel primary alternate clear (dmaaltclr) base 0x400f.f000 offset 0x034 type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] alternate clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmaaltset register meaning that channel [n] is using the primary control structure. 1 note: for ping-pong and scatter-gather cycle types, the dma controller automatically sets these bits to select the alternate channel control data structure. - wo clr[n] 31:0 march 20, 2011 390 texas instruments-advance information micro direct memory access (dma) register 18: dma channel priority set (dmaprioset), offset 0x038 each bit of the dmaprioset register represents the corresponding dma channel. setting a bit configures the dma channel to have a high priority level. reading the register returns the status of the channel priority mask. dma channel priority set (dmaprioset) base 0x400f.f000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] priority set description value dma channel [n] is using the default priority level. 0 dma channel [n] is using a high priority level. 1 bit 0 corresponds to channel 0. a bit can only be cleared by setting the corresponding clr[n] bit in the dmaprioclr register. 0x0000.0000 r/w set[n] 31:0 391 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 19: dma channel priority clear (dmaprioclr), offset 0x03c each bit of the dmaprioclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmaprioset register. dma channel priority clear (dmaprioclr) base 0x400f.f000 offset 0x03c type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] priority clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmaprioset register meaning that channel [n] is using the default priority level. 1 - wo clr[n] 31:0 march 20, 2011 392 texas instruments-advance information micro direct memory access (dma) register 20: dma bus error clear (dmaerrclr), offset 0x04c the dmaerrclr register is used to read and clear the dma bus error status. the error status is set if the dma controller encountered a bus error while performing a transfer. if a bus error occurs on a channel, that channel is automatically disabled by the dma controller. the other channels are unaffected. dma bus error clear (dmaerrclr) base 0x400f.f000 offset 0x04c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 errclr reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 dma bus error status description value no bus error is pending. 0 a bus error is pending. 1 this bit is cleared by writing a 1 to it. 0 r/w1c errclr 0 393 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 21: dma channel assignment (dmachasgn), offset 0x500 each bit of the dmachasgn register represents the corresponding dma channel. setting a bit selects the secondary channel assignment as specified in table 8-1 on page 348. dma channel assignment (dmachasgn) base 0x400f.f000 offset 0x500 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 chasgn[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 chasgn[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] assignment select description value use the primary channel assignment. 0 use the secondary channel assignment. 1 - r/w chasgn[n] 31:0 march 20, 2011 394 texas instruments-advance information micro direct memory access (dma) register 22: dma peripheral identification 0 (dmaperiphid0), offset 0xfe0 the dmaperiphidn registers are hard-coded, and the fields within the registers determine the reset values. dma peripheral identification 0 (dmaperiphid0) base 0x400f.f000 offset 0xfe0 type ro, reset 0x0000.0030 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x30 ro pid0 7:0 395 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 23: dma peripheral identification 1 (dmaperiphid1), offset 0xfe4 the dmaperiphidn registers are hard-coded, and the fields within the registers determine the reset values. dma peripheral identification 1 (dmaperiphid1) base 0x400f.f000 offset 0xfe4 type ro, reset 0x0000.00b2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0xb2 ro pid1 7:0 march 20, 2011 396 texas instruments-advance information micro direct memory access (dma) register 24: dma peripheral identification 2 (dmaperiphid2), offset 0xfe8 the dmaperiphidn registers are hard-coded, and the fields within the registers determine the reset values. dma peripheral identification 2 (dmaperiphid2) base 0x400f.f000 offset 0xfe8 type ro, reset 0x0000.000b 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x0b ro pid2 7:0 397 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 25: dma peripheral identification 3 (dmaperiphid3), offset 0xfec the dmaperiphidn registers are hard-coded and the fields within the registers determine the reset values. dma peripheral identification 3 (dmaperiphid3) base 0x400f.f000 offset 0xfec type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x00 ro pid3 7:0 march 20, 2011 398 texas instruments-advance information micro direct memory access (dma) register 26: dma peripheral identification 4 (dmaperiphid4), offset 0xfd0 the dmaperiphidn registers are hard-coded, and the fields within the registers determine the reset values. dma peripheral identification 4 (dmaperiphid4) base 0x400f.f000 offset 0xfd0 type ro, reset 0x0000.0004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register can be used by software to identify the presence of this peripheral. 0x04 ro pid4 7:0 399 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 27: dma primecell identification 0 (dmapcellid0), offset 0xff0 the dmapcellidn registers are hard-coded, and the fields within the registers determine the reset values. dma primecell identification 0 (dmapcellid0) base 0x400f.f000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 march 20, 2011 400 texas instruments-advance information micro direct memory access (dma) register 28: dma primecell identification 1 (dmapcellid1), offset 0xff4 the dmapcellidn registers are hard-coded, and the fields within the registers determine the reset values. dma primecell identification 1 (dmapcellid1) base 0x400f.f000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 401 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 29: dma primecell identification 2 (dmapcellid2), offset 0xff8 the dmapcellidn registers are hard-coded, and the fields within the registers determine the reset values. dma primecell identification 2 (dmapcellid2) base 0x400f.f000 offset 0xff8 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 dma primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 march 20, 2011 402 texas instruments-advance information micro direct memory access (dma) register 30: dma primecell identification 3 (dmapcellid3), offset 0xffc the dmapcellidn registers are hard-coded, and the fields within the registers determine the reset values. dma primecell identification 3 (dmapcellid3) base 0x400f.f000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 dma primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 403 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 9 general-purpose input/outputs (gpios) the gpio module is composed of nine physical gpio blocks, each corresponding to an individual gpio port (port a, port b, port c, port d, port e, port f, port g, port h, port j). the gpio module supports up to 67 programmable input/output pins, depending on the peripherals being used. the gpio module has the following features: up to 67 gpios, depending on configuration highly flexible pin muxing allows use as gpio or one of several peripheral functions 5-v-tolerant in input configuration fast toggle capable of a change every two clock cycles two means of port access: either advanced high-performance bus (ahb) with better back-to-back access performance, or the legacy advanced peripheral bus (apb) for backwards-compatibility with existing code programmable control for gpio interrupts C interrupt generation masking C edge-triggered on rising, falling, or both C level-sensitive on high or low values bit masking in both read and write operations through address lines can be used to initiate an adc sample sequence pins configured as digital inputs are schmitt-triggered programmable control for gpio pad configuration C weak pull-up or pull-down resistors C 2-ma, 4-ma, and 8-ma pad drive for digital communication; up to four pads can be configured with an 18-ma pad drive for high-current applications C slew rate control for the 8-ma drive C open drain enables C digital input enables 9.1 signal description gpio signals have alternate hardware functions. table 9-2 on page 405 and table 9-3 on page 407 list the gpio pins and their analog and digital alternate functions. the ainx and vrefa analog signals are not 5-v tolerant and go through an isolation circuit before reaching their circuitry. these signals are configured by clearing the corresponding den bit in the gpio digital enable (gpioden) register and setting the corresponding amsel bit in the gpio analog mode select (gpioamsel) register. other analog signals are 5-v tolerant and are connected directly to their circuitry ( c0-, march 20, 2011 404 texas instruments-advance information general-purpose input/outputs (gpios) c0+, c1-, c1+ ). these signals are configured by clearing the den bit in the gpio digital enable (gpioden) register. the digital alternate hardware functions are enabled by setting the appropriate bit in the gpio alternate function select (gpioafsel) and gpioden registers and configuring the pmcx bit field in the gpio port control (gpiopctl) register to the numeric encoding shown in the table below. note that each pin must be programmed individually; no type of grouping is implied by the columns in the table. table entries that are shaded gray are the default values for the corresponding gpio pin. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the four jtag/swd pins (shown in the table below). a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 9-1. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 1 0 uart0 pa[1:0] 0x1 0 0 1 0 ssi0 pa[5:2] 0x1 0 0 1 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] table 9-2. gpio pins and alternate functions (100lqfp) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1rx i2c1scl ------ u0rx -26 pa0 -- u1tx i2c1sda ------ u0tx -27 pa1 -- i2s0rxsd ---- pwm4 -- ssi0clk -28 pa2 -- i2s0rxmclk ---- pwm5 -- ssi0fss -29 pa3 -- i2s0txsck ------- ssi0rx -30 pa4 -- i2s0txws ------- ssi0tx -31 pa5 -- u1cts --- pwm4 pwm0 - ccp1 i2c1scl -34 pa6 -- u1dcd - ccp3 - pwm5 pwm1 - ccp4 i2c1sda -35 pa7 ------ u1rx -- pwm2 ccp0 -66 pb0 ------ u1tx ccp1 - pwm3 ccp2 -67 pb1 ------ ccp0 ccp3 - idx0 i2c0scl -72 pb2 ------- fault3 - fault0 i2c0sda -65 pb3 ---- u1rx idx0 - u2rx --- ain10 c0- 92 pb4 ---- u1tx ccp2 - ccp0 ccp6 ccp5 c0o ain11 c1- 91 pb5 -- i2s0txsck -- ccp5 idx0 fault1 c0o ccp7 ccp1 vrefa c0+ 90 pb6 ------- nmi ----89 pb7 -------- tck swclk ---80 pc0 -------- tms swdio ---79 pc1 405 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 9-2. gpio pins and alternate functions (100lqfp) (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -------- tdi ---78 pc2 -------- tdo swo ---77 pc3 -- ccp1 -- ccp4 ccp2 -- pha0 ccp5 -25 pc4 ------ ccp3 fault2 c0o c1o ccp1 c1+ 24 pc5 ----- ccp0 u1rx -- phb0 ccp3 -23 pc6 ---- c1o - u1tx ccp0 - phb0 ccp4 -22 pc7 -- u1cts i2s0rxsck - ccp6 u1rx u2rx idx0 - pwm0 ain15 10 pd0 phb1 ccp2 u1dcd i2s0rxws - ccp7 u1tx u2tx pha0 - pwm1 ain14 11 pd1 ------- ccp5 pwm2 ccp6 u1rx ain13 12 pd2 ------- ccp0 pwm3 ccp7 u1tx ain12 13 pd3 -- u1ri i2s0rxsd ----- ccp3 ccp0 ain7 97 pd4 -- u2rx i2s0rxmclk ----- ccp4 ccp2 ain6 98 pd5 -- u2tx i2s0txsck ------ fault0 ain5 99 pd6 -- u1dtr i2s0txws ---- ccp1 c0o idx0 ain4 100 pd7 -------- ccp3 ssi1clk pwm4 -74 pe0 ------ ccp6 ccp2 fault0 ssi1fss pwm5 -75 pe1 ------ ccp2 pha0 phb1 ssi1rx ccp4 ain9 95 pe2 ------ ccp7 phb0 pha1 ssi1tx ccp1 ain8 96 pe3 -- i2s0txws -- ccp2 u2tx fault0 -- ccp3 ain3 6 pe4 -- i2s0txsd ------- ccp5 ain2 5 pe5 -- u1cts ------ c1o pwm4 ain1 2 pe6 -- u1dcd ------- pwm5 ain0 1 pe7 -- u1dsr i2s0txsd ---- pwm0 phb0 --47 pf0 - ccp3 u1rts i2s0txmclk ---- pwm1 idx1 --61 pf1 -- ssi1clk ---- pwm2 - pwm4 --60 pf2 -- ssi1fss ---- pwm3 - pwm5 --59 pf3 -- ssi1rx ---- fault0 - c0o ccp0 -58 pf4 -- ssi1tx ------ c1o ccp2 -46 pf5 - u1rts i2s0txmclk ---- pha0 -- ccp1 -43 pf6 -- fault1 ---- phb0 -- ccp4 -42 pf7 ------- pwm4 i2c1scl pwm0 u2rx -19 pg0 ------- pwm5 i2c1sda pwm1 u2tx -18 pg1 -- i2s0rxsd idx1 --- fault0 -- pwm0 -17 pg2 -- i2s0rxmclk fault0 --- fault2 -- pwm1 -16 pg3 - u1ri ----- fault1 -- ccp3 -41 pg4 - u1dtr i2s0rxsck --- fault1 idx0 -- ccp5 -40 pg5 - u1ri i2s0rxws fault1 ------ pha1 -37 pg6 --- ccp5 ------ phb1 -36 pg7 -- pwm4 ------ pwm2 ccp6 -86 ph0 march 20, 2011 406 texas instruments-advance information general-purpose input/outputs (gpios) table 9-2. gpio pins and alternate functions (100lqfp) (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- pwm5 ------ pwm3 ccp7 -85 ph1 ------- fault3 - c1o idx1 -84 ph2 --------- fault0 phb0 -83 ph3 ssi1clk -----------76 ph4 ssi1fss fault2 ----------63 ph5 ssi1rx pwm4 ----------62 ph6 ssi1tx pwm5 ----------15 ph7 i2c1scl pwm0 ----------14 pj0 i2c1sda pwm1 ----------87 pj1 - fault0 ccp0 ---------39 pj2 a. the digital signals that are shaded gray are the power-on default values for the corresponding gpio pin. table 9-3. gpio pins and alternate functions (108bga) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1rx i2c1scl ------ u0rx -l3 pa0 -- u1tx i2c1sda ------ u0tx -m3 pa1 -- i2s0rxsd ---- pwm4 -- ssi0clk -m4 pa2 -- i2s0rxmclk ---- pwm5 -- ssi0fss -l4 pa3 -- i2s0txsck ------- ssi0rx -l5 pa4 -- i2s0txws ------- ssi0tx -m5 pa5 -- u1cts --- pwm4 pwm0 - ccp1 i2c1scl -l6 pa6 -- u1dcd - ccp3 - pwm5 pwm1 - ccp4 i2c1sda -m6 pa7 ------ u1rx -- pwm2 ccp0 -e12 pb0 ------ u1tx ccp1 - pwm3 ccp2 -d12 pb1 ------ ccp0 ccp3 - idx0 i2c0scl -a11 pb2 ------- fault3 - fault0 i2c0sda -e11 pb3 ---- u1rx idx0 - u2rx --- ain10 c0- a6 pb4 ---- u1tx ccp2 - ccp0 ccp6 ccp5 c0o ain11 c1- b7 pb5 -- i2s0txsck -- ccp5 idx0 fault1 c0o ccp7 ccp1 vrefa c0+ a7 pb6 ------- nmi ----a8 pb7 -------- tck swclk ---a9 pc0 -------- tms swdio ---b9 pc1 -------- tdi ---b8 pc2 -------- tdo swo ---a10 pc3 -- ccp1 -- ccp4 ccp2 -- pha0 ccp5 -l1 pc4 407 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 9-3. gpio pins and alternate functions (108bga) (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 ------ ccp3 fault2 c0o c1o ccp1 c1+ m1 pc5 ----- ccp0 u1rx -- phb0 ccp3 -m2 pc6 ---- c1o - u1tx ccp0 - phb0 ccp4 -l2 pc7 -- u1cts i2s0rxsck - ccp6 u1rx u2rx idx0 - pwm0 ain15 g1 pd0 phb1 ccp2 u1dcd i2s0rxws - ccp7 u1tx u2tx pha0 - pwm1 ain14 g2 pd1 ------- ccp5 pwm2 ccp6 u1rx ain13 h2 pd2 ------- ccp0 pwm3 ccp7 u1tx ain12 h1 pd3 -- u1ri i2s0rxsd ----- ccp3 ccp0 ain7 b5 pd4 -- u2rx i2s0rxmclk ----- ccp4 ccp2 ain6 c6 pd5 -- u2tx i2s0txsck ------ fault0 ain5 a3 pd6 -- u1dtr i2s0txws ---- ccp1 c0o idx0 ain4 a2 pd7 -------- ccp3 ssi1clk pwm4 -b11 pe0 ------ ccp6 ccp2 fault0 ssi1fss pwm5 -a12 pe1 ------ ccp2 pha0 phb1 ssi1rx ccp4 ain9 a4 pe2 ------ ccp7 phb0 pha1 ssi1tx ccp1 ain8 b4 pe3 -- i2s0txws -- ccp2 u2tx fault0 -- ccp3 ain3 b2 pe4 -- i2s0txsd ------- ccp5 ain2 b3 pe5 -- u1cts ------ c1o pwm4 ain1 a1 pe6 -- u1dcd ------- pwm5 ain0 b1 pe7 -- u1dsr i2s0txsd ---- pwm0 phb0 --m9 pf0 - ccp3 u1rts i2s0txmclk ---- pwm1 idx1 --h12 pf1 -- ssi1clk ---- pwm2 - pwm4 --j11 pf2 -- ssi1fss ---- pwm3 - pwm5 --j12 pf3 -- ssi1rx ---- fault0 - c0o ccp0 -l9 pf4 -- ssi1tx ------ c1o ccp2 -l8 pf5 - u1rts i2s0txmclk ---- pha0 -- ccp1 -m8 pf6 -- fault1 ---- phb0 -- ccp4 -k4 pf7 ------- pwm4 i2c1scl pwm0 u2rx -k1 pg0 ------- pwm5 i2c1sda pwm1 u2tx -k2 pg1 -- i2s0rxsd idx1 --- fault0 -- pwm0 -j1 pg2 -- i2s0rxmclk fault0 --- fault2 -- pwm1 -j2 pg3 - u1ri ----- fault1 -- ccp3 -k3 pg4 - u1dtr i2s0rxsck --- fault1 idx0 -- ccp5 -m7 pg5 - u1ri i2s0rxws fault1 ------ pha1 -l7 pg6 --- ccp5 ------ phb1 -c10 pg7 -- pwm4 ------ pwm2 ccp6 -c9 ph0 -- pwm5 ------ pwm3 ccp7 -c8 ph1 ------- fault3 - c1o idx1 -d11 ph2 --------- fault0 phb0 -d10 ph3 ssi1clk -----------b10 ph4 march 20, 2011 408 texas instruments-advance information general-purpose input/outputs (gpios) table 9-3. gpio pins and alternate functions (108bga) (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 ssi1fss fault2 ----------f10 ph5 ssi1rx pwm4 ----------g3 ph6 ssi1tx pwm5 ----------h3 ph7 i2c1scl pwm0 ----------f3 pj0 i2c1sda pwm1 ----------b6 pj1 - fault0 ccp0 ---------k6 pj2 a. the digital signals that are shaded gray are the power-on default values for the corresponding gpio pin. 9.2 functional description each gpio port is a separate hardware instantiation of the same physical block (see figure 9-1 on page 409 and figure 9-2 on page 410). the lm3s1p51 microcontroller contains nineports and thus nine of these physical gpio blocks. note that not all pins may be implemented on every block. some gpio pins can function as i/o signals for the on-chip peripheral modules. for information on which gpio pins are used for alternate hardware functions, refer to table 21-5 on page 925. figure 9-1. digital i/o pads 409 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 3 d g & r q w u r o & r p p l w & r q w u r o 0 r g h & r q w u r o * 3 , 2 $ ) 6 ( / ' d w d & r q w u r o , q w h u u x s w & r q w u r o 0 8 ; 0 8 ; ' ( 0 8 ; ' l j l w d o , 2 3 d g , g h q w l i l f d w l r q 5 h j l v w h u v * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' 3 d g , q s x w 3 d g 2 x w s x w ( q d e o h * 3 , 2 / 2 & . * 3 , 2 & 5 * 3 , 2 ' $ 7 $ * 3 , 2 ' , 5 * 3 , 2 , 6 * 3 , 2 , % ( * 3 , 2 , ( 9 * 3 , 2 , 0 * 3 , 2 5 , 6 * 3 , 2 0 , 6 * 3 , 2 , & 5 * 3 , 2 ' 5 5 * 3 , 2 ' 5 5 * 3 , 2 ' 5 5 * 3 , 2 6 / 5 * 3 , 2 3 8 5 * 3 , 2 3 ' 5 * 3 , 2 2 ' 5 * 3 , 2 ' ( 1 $ o w h u q d w h , q s x w $ o w h u q d w h 2 x w s x w $ o w h u q d w h 2 x w s x w ( q d e o h , q w h u u x s w * 3 , 2 , q s x w * 3 , 2 2 x w s x w * 3 , 2 2 x w s x w ( q d e o h 3 d g 2 x w s x w 3 d f n d j h , 2 3 l q 0 8 ; 3 h u l s k 3 h u l s k 3 h u l s k q 3 r u w & r q w u r o * 3 , 2 3 & 7 / figure 9-2. analog/digital i/o pads 9.2.1 data control the data control registers allow software to configure the operational modes of the gpios. the data direction register configures the gpio as an input or an output while the data register either captures incoming data or drives it out to the pads. caution C it is possible to create a software sequence that prevents the debugger from connecting to the stellaris ? microcontroller. if the program code loaded into fash immediately changes the jtag pins to their gpio functionality, the debugger may not have enough time to connect and halt the controller before the jtag pin functionality switches. as a result, the debugger may be locked out of the part. this issue can be avoided with a software routine that restores jtag functionality based on an external or software trigger. 9.2.1.1 data direction operation the gpio direction (gpiodir) register (see page 419) is used to configure each individual pin as an input or output. when the data direction bit is cleared, the gpio is configured as an input, and the corresponding data register bit captures and stores the value on the gpio port. when the data direction bit is set, the gpio is configured as an output, and the corresponding data register bit is driven out on the gpio port. march 20, 2011 410 texas instruments-advance information general-purpose input/outputs (gpios) 3 d g & r q w u r o ' d w d & r q w u r o * 3 , 2 , q s x w * 3 , 2 2 x w s x w * 3 , 2 2 x w s x w ( q d e o h , q w h u u x s w & r q w u r o , q w h u u x s w 0 8 ; 0 8 ; * 3 , 2 ' 5 5 * 3 , 2 ' 5 5 * 3 , 2 ' 5 5 * 3 , 2 6 / 5 * 3 , 2 3 8 5 * 3 , 2 3 ' 5 * 3 , 2 2 ' 5 * 3 , 2 ' ( 1 * 3 , 2 $ 0 6 ( / * 3 , 2 , ( 9 * 3 , 2 , 6 * 3 , 2 , % ( * 3 , 2 , 0 * 3 , 2 5 , 6 * 3 , 2 0 , 6 * 3 , 2 , & 5 * 3 , 2 ' $ 7 $ * 3 , 2 ' , 5 , g h q w l i l f d w l r q 5 h j l v w h u v * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' $ q d o r j & l u f x l w u \ i r u * 3 , 2 s l q v w k d w f r q q h f w w r w k h $ ' & l q s x w 0 8 ; $ ' & , v r o d w l r q & l u f x l w 3 d g 2 x w s x w ( q d e o h 3 d f n d j h , 2 3 l q 3 d g , q s x w 3 d g 2 x w s x w $ q d o r j ' l j l w d o , 2 3 d g & r p p l w & r q w u r o 0 r g h & r q w u r o * 3 , 2 $ ) 6 ( / * 3 , 2 / 2 & . * 3 , 2 & 5 $ o w h u q d w h , q s x w $ o w h u q d w h 2 x w s x w $ o w h u q d w h 2 x w s x w ( q d e o h 0 8 ; 3 h u l s k 3 h u l s k 3 h u l s k q 3 r u w & r q w u r o * 3 , 2 3 & 7 / ' ( 0 8 ; 9.2.1.2 data register operation to aid in the efficiency of software, the gpio ports allow for the modification of individual bits in the gpio data (gpiodata) register (see page 418) by using bits [9:2] of the address bus as a mask. in this manner, software drivers can modify individual gpio pins in a single instruction without affecting the state of the other pins. this method is more efficient than the conventional method of performing a read-modify-write operation to set or clear an individual gpio pin. to implement this feature, the gpiodata register covers 256 locations in the memory map. during a write, if the address bit associated with that data bit is set, the value of the gpiodata register is altered. if the address bit is cleared, the data bit is left unchanged. for example, writing a value of 0xeb to the address gpiodata + 0x098 has the results shown in figure 9-3, where u indicates that data is unchanged by the write. figure 9-3. gpiodata write example during a read, if the address bit associated with the data bit is set, the value is read. if the address bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual value. for example, reading address gpiodata + 0x0c4 yields as shown in figure 9-4. figure 9-4. gpiodata read example 9.2.2 interrupt control the interrupt capabilities of each gpio port are controlled by a set of seven registers. these registers are used to select the source of the interrupt, its polarity, and the edge properties. when one or more gpio inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire gpio port. for edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. for a level-sensitive interrupt, the external source must hold the level constant for the interrupt to be recognized by the controller. three registers define the edge or sense that causes interrupts: gpio interrupt sense (gpiois) register (see page 420) 411 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 5 h w x u q h g 9 d o x h * 3 , 2 ' $ 7 $ [ & $ ' ' 5 > @ x x x x x * 3 , 2 ' $ 7 $ [ ( % [ $ ' ' 5 > @ gpio interrupt both edges (gpioibe) register (see page 421) gpio interrupt event (gpioiev) register (see page 422) interrupts are enabled/disabled via the gpio interrupt mask (gpioim) register (see page 423). when an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the gpio raw interrupt status (gpioris) and gpio masked interrupt status (gpiomis) registers (see page 424 and page 425). as the name implies, the gpiomis register only shows interrupt conditions that are allowed to be passed to the interrupt controller. the gpioris register indicates that a gpio pin meets the conditions for an interrupt, but has not necessarily been sent to the interrupt controller. interrupts are cleared by writing a 1 to the appropriate bit of the gpio interrupt clear (gpioicr) register (see page 427). when programming the interrupt control registers ( gpiois , gpioibe , or gpioiev ), the interrupts should be masked ( gpioim cleared). writing any value to an interrupt control register can generate a spurious interrupt if the corresponding bits are enabled. 9.2.2.1 adc trigger source in addition to providing gpio functionality, pb4 can also be used as an external trigger for the adc. if pb4 is configured as a non-masked interrupt pin (the appropriate bit of gpioim is set), an interrupt for port b is generated, and an external trigger signal is sent to the adc. if the adc event multiplexer select (adcemux) register is configured to use the external trigger, an adc conversion is initiated. see page 563. if no other port b pins are being used to generate interrupts, the interrupt 0-31 set enable (en0) register can disable the port b interrupts, and the adc interrupt can be used to read back the converted data. otherwise, the port b interrupt handler must ignore and clear interrupts on pb4 and wait for the adc interrupt, or the adc interrupt must be disabled in the en0 register and the port b interrupt handler must poll the adc registers until the conversion is completed. see page 118 for more information. 9.2.3 mode control the gpio pins can be controlled by either software or hardware. software control is the default for most signals and corresponds to the gpio mode, where the gpiodata register is used to read or write the corresponding pins. when hardware control is enabled via the gpio alternate function select (gpioafsel) register (see page 428), the pin state is controlled by its alternate function (that is, the peripheral). further pin muxing options are provided through the gpio port control (gpiopctl) register which selects one of several peripheral functions for each gpio. for information on the configuration options, refer to table 21-5 on page 925. note: if any pin is to be used as an adc input, the appropriate bit in the gpioamsel register must be set to disable the analog isolation circuit. 9.2.4 commit control the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7 ) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 428), gpio pull up select (gpiopur) register (see page 434), gpio pull-down select (gpiopdr) register (see page 436), and gpio digital enable (gpioden) register (see march 20, 2011 412 texas instruments-advance information general-purpose input/outputs (gpios) page 439) are not committed to storage unless the gpio lock (gpiolock) register (see page 441) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 442) have been set. 9.2.5 pad control the pad control registers allow software to configure the gpio pads based on the application requirements. the pad control registers include the gpiodr2r , gpiodr4r , gpiodr8r , gpioodr , gpiopur , gpiopdr , gpioslr , and gpioden registers. these registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable for each gpio. for special high-current applications, the gpio output buffers may be used with the following restrictions. with the gpio pins configured as 8-ma output drivers, a total of four gpio outputs may be used to sink current loads up to 18 ma each. at 18-ma sink current loading, the v ol value is specified as 1.2 v. the high-current gpio package pins must be selected such that there are only a maximum of two per side of the physical package or bga pin group with the total number of high-current gpio outputs not exceeding four for the entire package. 9.2.6 identification the identification registers configured at reset allow software to detect and identify the module as a gpio block. the identification registers include the gpioperiphid0 -gpioperiphid7 registers as well as the gpiopcellid0 -gpiopcellid3 registers. 9.3 initialization and configuration the gpio modules may be accessed via two different memory apertures. the legacy aperture, the advanced peripheral bus (apb), is backwards-compatible with previous stellaris parts. the other aperture, the advanced high-performance bus (ahb), offers the same register map but provides better back-to-back access performance than the apb bus. these apertures are mutually exclusive. the aperture enabled for a given gpio port is controlled by the appropriate bit in the gpiohbctl register (see page 216). to use the pins in a particular gpio port, the clock for the port must be enabled by setting the appropriate gpio port bit field ( gpion ) in the rcgc2 register (see page 269). when the internal por signal is asserted and until otherwise configured, all gpio pins are configured to be undriven (tristate): gpioafsel =0, gpioden =0, gpiopdr =0, and gpiopur =0, except for the pins shown in table 9-1 on page 405. table 9-4 on page 413 shows all possible configurations of the gpio pads and the control register settings required to achieve them. table 9-5 on page 414 shows how a rising edge interrupt is configured for pin 2 of a gpio port. table 9-4. gpio pad configuration examples gpio register bit value a configuration slr dr8r dr4r dr2r pdr pur den odr dir afsel x x x x ? ? 1 0 0 0 digital input (gpio) ? ? ? ? ? ? 1 0 1 0 digital output (gpio) ? ? ? ? x x 1 1 1 0 open drain output (gpio) ? ? ? ? x x 1 1 x 1 open drain input/output (i 2 c) x x x x ? ? 1 0 x 1 digital input (timer ccp) 413 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 9-4. gpio pad configuration examples (continued) gpio register bit value a configuration slr dr8r dr4r dr2r pdr pur den odr dir afsel x x x x ? ? 1 0 x 1 digital input (qei) ? ? ? ? ? ? 1 0 x 1 digital output (pwm) ? ? ? ? ? ? 1 0 x 1 digital output (timer pwm) ? ? ? ? ? ? 1 0 x 1 digital input/output (ssi) ? ? ? ? ? ? 1 0 x 1 digital input/output (uart) x x x x 0 0 0 0 0 0 analog input (comparator) ? ? ? ? ? ? 1 0 x 1 digital output (comparator) a. x=ignored (dont care bit) ?=can be either 0 or 1, depending on the configuration table 9-5. gpio interrupt configuration example pin 2 bit value a desired interrupt event trigger register 0 1 2 3 4 5 6 7 x x 0 x x x x x 0=edge 1=level gpiois x x 0 x x x x x 0=single edge 1=both edges gpioibe x x 1 x x x x x 0=low level, or falling edge 1=high level, or rising edge gpioiev 0 0 1 0 0 0 0 0 0=masked 1=not masked gpioim a. x=ignored (dont care bit) 9.4 register map table 9-7 on page 415 lists the gpio registers. each gpio port can be accessed through one of two bus apertures. the legacy aperture, the advanced peripheral bus (apb), is backwards-compatible with previous stellaris parts. the other aperture, the advanced high-performance bus (ahb), offers the same register map but provides better back-to-back access performance than the apb bus. important: the gpio registers in this chapter are duplicated in each gpio block; however, depending on the block, all eight bits may not be connected to a gpio pad. in those cases, writing to unconnected bits has no effect, and reading unconnected bits returns no meaningful data. the offset listed is a hexadecimal increment to the registers address, relative to that gpio ports base address: gpio port a (apb): 0x4000.4000 gpio port a (ahb): 0x4005.8000 gpio port b (apb): 0x4000.5000 march 20, 2011 414 texas instruments-advance information general-purpose input/outputs (gpios) gpio port b (ahb): 0x4005.9000 gpio port c (apb): 0x4000.6000 gpio port c (ahb): 0x4005.a000 gpio port d (apb): 0x4000.7000 gpio port d (ahb): 0x4005.b000 gpio port e (apb): 0x4002.4000 gpio port e (ahb): 0x4005.c000 gpio port f (apb): 0x4002.5000 gpio port f (ahb): 0x4005.d000 gpio port g (apb): 0x4002.6000 gpio port g (ahb): 0x4005.e000 gpio port h (apb): 0x4002.7000 gpio port h (ahb): 0x4005.f000 gpio port j (apb): 0x4003.d000 gpio port j (ahb): 0x4006.0000 note that each gpio module clock must be enabled before the registers can be programmed (see page 269). there must be a delay of 3 system clocks after the gpio module clock is enabled before any gpio module registers are accessed. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the four jtag/swd pins (shown in the table below). a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 9-6. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 1 0 uart0 pa[1:0] 0x1 0 0 1 0 ssi0 pa[5:2] 0x1 0 0 1 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] the default register type for the gpiocr register is ro for all gpio pins with the exception of the nmi pin and the four jtag/swd pins ( pb7 and pc[3:0] ). these five pins are the only gpios that are protected by the gpiocr register. because of this, the register type for gpio port b7 and gpio port c[3:0] is r/w. the default reset value for the gpiocr register is 0x0000.00ff for all gpio pins, with the exception of the nmi pin and the four jtag/swd pins ( pb7 and pc[3:0] ). to ensure that the jtag port is not accidentally programmed as gpio pins, the pc[3:0] pins default to non-committable. similarly, to ensure that the nmi pin is not accidentally programmed as a gpio pin, the pb7 pin defaults to non-committable. because of this, the default reset value of gpiocr for gpio port b is 0x0000.007f while the default reset value of gpiocr for port c is 0x0000.00f0. table 9-7. gpio register map see page description reset type name offset 418 gpio data 0x0000.0000 r/w gpiodata 0x000 419 gpio direction 0x0000.0000 r/w gpiodir 0x400 415 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 9-7. gpio register map (continued) see page description reset type name offset 420 gpio interrupt sense 0x0000.0000 r/w gpiois 0x404 421 gpio interrupt both edges 0x0000.0000 r/w gpioibe 0x408 422 gpio interrupt event 0x0000.0000 r/w gpioiev 0x40c 423 gpio interrupt mask 0x0000.0000 r/w gpioim 0x410 424 gpio raw interrupt status 0x0000.0000 ro gpioris 0x414 425 gpio masked interrupt status 0x0000.0000 ro gpiomis 0x418 427 gpio interrupt clear 0x0000.0000 w1c gpioicr 0x41c 428 gpio alternate function select - r/w gpioafsel 0x420 430 gpio 2-ma drive select 0x0000.00ff r/w gpiodr2r 0x500 431 gpio 4-ma drive select 0x0000.0000 r/w gpiodr4r 0x504 432 gpio 8-ma drive select 0x0000.0000 r/w gpiodr8r 0x508 433 gpio open drain select 0x0000.0000 r/w gpioodr 0x50c 434 gpio pull-up select - r/w gpiopur 0x510 436 gpio pull-down select 0x0000.0000 r/w gpiopdr 0x514 438 gpio slew rate control select 0x0000.0000 r/w gpioslr 0x518 439 gpio digital enable - r/w gpioden 0x51c 441 gpio lock 0x0000.0001 r/w gpiolock 0x520 442 gpio commit - - gpiocr 0x524 444 gpio analog mode select 0x0000.0000 r/w gpioamsel 0x528 446 gpio port control - r/w gpiopctl 0x52c 448 gpio peripheral identification 4 0x0000.0000 ro gpioperiphid4 0xfd0 449 gpio peripheral identification 5 0x0000.0000 ro gpioperiphid5 0xfd4 450 gpio peripheral identification 6 0x0000.0000 ro gpioperiphid6 0xfd8 451 gpio peripheral identification 7 0x0000.0000 ro gpioperiphid7 0xfdc 452 gpio peripheral identification 0 0x0000.0061 ro gpioperiphid0 0xfe0 453 gpio peripheral identification 1 0x0000.0000 ro gpioperiphid1 0xfe4 454 gpio peripheral identification 2 0x0000.0018 ro gpioperiphid2 0xfe8 455 gpio peripheral identification 3 0x0000.0001 ro gpioperiphid3 0xfec 456 gpio primecell identification 0 0x0000.000d ro gpiopcellid0 0xff0 457 gpio primecell identification 1 0x0000.00f0 ro gpiopcellid1 0xff4 458 gpio primecell identification 2 0x0000.0005 ro gpiopcellid2 0xff8 459 gpio primecell identification 3 0x0000.00b1 ro gpiopcellid3 0xffc march 20, 2011 416 texas instruments-advance information general-purpose input/outputs (gpios) 9.5 register descriptions the remainder of this section lists and describes the gpio registers, in numerical order by address offset. 417 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: gpio data (gpiodata), offset 0x000 the gpiodata register is the data register. in software control mode, values written in the gpiodata register are transferred onto the gpio port pins if the respective pins have been configured as outputs through the gpio direction (gpiodir) register (see page 419). in order to write to gpiodata , the corresponding bits in the mask, resulting from the address bus bits [9:2], must be set. otherwise, the bit values remain unchanged by the write. similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. bits that are set in the address mask cause the corresponding bits in gpiodata to be read, and bits that are clear in the address mask cause the corresponding bits in gpiodata to be read as 0, regardless of their value. a read from gpiodata returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. all bits are cleared by a reset. gpio data (gpiodata) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio data this register is virtually mapped to 256 locations in the address space. to facilitate the reading and writing of data to these registers by independent drivers, the data read from and written to the registers are masked by the eight address lines [9:2]. reads from this register return its current state. writes to this register only affect bits that are not masked by addr[9:2] and are configured as outputs. see data register operation on page 411 for examples of reads and writes. 0x00 r/w data 7:0 march 20, 2011 418 texas instruments-advance information general-purpose input/outputs (gpios) register 2: gpio direction (gpiodir), offset 0x400 the gpiodir register is the data direction register. setting a bit in the gpiodir register configures the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be an input. all bits are cleared by a reset, meaning all gpio pins are inputs by default. gpio direction (gpiodir) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x400 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dir reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio data direction description value corresponding pin is an input. 0 corresponding pins is an output. 1 0x00 r/w dir 7:0 419 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 3: gpio interrupt sense (gpiois), offset 0x404 the gpiois register is the interrupt sense register. setting a bit in the gpiois register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. all bits are cleared by a reset. gpio interrupt sense (gpiois) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x404 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 is reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt sense description value the edge on the corresponding pin is detected (edge-sensitive). 0 the level on the corresponding pin is detected (level-sensitive). 1 0x00 r/w is 7:0 march 20, 2011 420 texas instruments-advance information general-purpose input/outputs (gpios) register 4: gpio interrupt both edges (gpioibe), offset 0x408 the gpioibe register allows both edges to cause interrupts. when the corresponding bit in the gpio interrupt sense (gpiois) register (see page 420) is set to detect edges, setting a bit in the gpioibe register configures the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the gpio interrupt event (gpioiev) register (see page 422). clearing a bit configures the pin to be controlled by the gpioiev register. all bits are cleared by a reset. gpio interrupt both edges (gpioibe) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x408 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ibe reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt both edges description value interrupt generation is controlled by the gpio interrupt event (gpioiev) register (see page 422). 0 both edges on the corresponding pin trigger an interrupt. 1 0x00 r/w ibe 7:0 421 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 5: gpio interrupt event (gpioiev), offset 0x40c the gpioiev register is the interrupt event register. setting a bit in the gpioiev register configures the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the gpio interrupt sense (gpiois) register (see page 420). clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in the gpiois register. all bits are cleared by a reset. gpio interrupt event (gpioiev) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x40c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 iev reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt event description value a falling edge or a low level on the corresponding pin triggers an interrupt. 0 a rising edge or a high level on the corresponding pin triggers an interrupt. 1 0x00 r/w iev 7:0 march 20, 2011 422 texas instruments-advance information general-purpose input/outputs (gpios) register 6: gpio interrupt mask (gpioim), offset 0x410 the gpioim register is the interrupt mask register. setting a bit in the gpioim register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. all bits are cleared by a reset. gpio interrupt mask (gpioim) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x410 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ime reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt mask enable description value the interrupt from the corresponding pin is masked. 0 the interrupt from the corresponding pin is sent to the interrupt controller. 1 0x00 r/w ime 7:0 423 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 7: gpio raw interrupt status (gpioris), offset 0x414 the gpioris register is the raw interrupt status register. a bit in this register is set when an interrupt condition occurs on the corresponding gpio pin. if the corresponding bit in the gpio interrupt mask (gpioim) register (see page 423) is set, the interrupt is sent to the interrupt controller. bits read as zero indicate that corresponding input pins have not initiated an interrupt. a bit in this register can be cleared by writing a 1 to the corresponding bit in the gpio interrupt clear (gpioicr) register. gpio raw interrupt status (gpioris) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x414 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt raw status description value an interrupt condition has occurred on the corresponding pin. 1 an interrupt condition has not occurred on the corresponding pin. 0 a bit is cleared by writing a 1 to the corresponding bit in the gpioicr register. 0x00 ro ris 7:0 march 20, 2011 424 texas instruments-advance information general-purpose input/outputs (gpios) register 8: gpio masked interrupt status (gpiomis), offset 0x418 the gpiomis register is the masked interrupt status register. if a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. if a bit is clear, either no interrupt has been generated, or the interrupt is masked. in addition to providing gpio functionality, pb4 can also be used as an external trigger for the adc. if pb4 is configured as a non-masked interrupt pin (the appropriate bit of gpioim is set), an interrupt for port b is generated, and an external trigger signal is sent to the adc. if the adc event multiplexer select (adcemux) register is configured to use the external trigger, an adc conversion is initiated. see page 563. if no other port b pins are being used to generate interrupts, the interrupt 0-31 set enable (en0) register can disable the port b interrupts, and the adc interrupt can be used to read back the converted data. otherwise, the port b interrupt handler must ignore and clear interrupts on pb4 and wait for the adc interrupt, or the adc interrupt must be disabled in the en0 register and the port b interrupt handler must poll the adc registers until the conversion is completed. see page 118 for more information. gpiomis is the state of the interrupt after masking. gpio masked interrupt status (gpiomis) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x418 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 425 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field gpio masked interrupt status description value an interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. 1 an interrupt condition on the corresponding pin is masked or has not occurred. 0 a bit is cleared by writing a 1 to the corresponding bit in the gpioicr register. 0x00 ro mis 7:0 march 20, 2011 426 texas instruments-advance information general-purpose input/outputs (gpios) register 9: gpio interrupt clear (gpioicr), offset 0x41c the gpioicr register is the interrupt clear register. writing a 1 to a bit in this register clears the corresponding interrupt bit in the gpioris and gpiomis registers. writing a 0 has no effect. gpio interrupt clear (gpioicr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x41c type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ic reserved w1c w1c w1c w1c w1c w1c w1c w1c ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt clear description value the corresponding interrupt is cleared. 1 the corresponding interrupt is unaffected. 0 0x00 w1c ic 7:0 427 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 10: gpio alternate function select (gpioafsel), offset 0x420 the gpioafsel register is the mode control select register. if a bit is clear, the pin is used as a gpio and is controlled by the gpio registers. setting a bit in this register configures the corresponding gpio line to be controlled by an associated peripheral. several possible peripheral functions are multiplexed on each gpio. the gpio port control (gpiopctl) register is used to select one of the possible functions. table 21-5 on page 925 details which functions are muxed on each gpio pin. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in the table below. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the four jtag/swd pins (shown in the table below). a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 9-8. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 1 0 uart0 pa[1:0] 0x1 0 0 1 0 ssi0 pa[5:2] 0x1 0 0 1 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] caution C it is possible to create a software sequence that prevents the debugger from connecting to the stellaris microcontroller. if the program code loaded into fash immediately changes the jtag pins to their gpio functionality, the debugger may not have enough time to connect and halt the controller before the jtag pin functionality switches. as a result, the debugger may be locked out of the part. this issue can be avoided with a software routine that restores jtag functionality based on an external or software trigger. the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7 ) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 428), gpio pull up select (gpiopur) register (see page 434), gpio pull-down select (gpiopdr) register (see page 436), and gpio digital enable (gpioden) register (see page 439) are not committed to storage unless the gpio lock (gpiolock) register (see page 441) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 442) have been set. when using the i 2 c module, in addition to setting the gpioafsel register bits for the i 2 c clock and data pins, the data pins should be set to open drain using the gpio open drain select (gpioodr) register (see examples in initialization and configuration on page 413). march 20, 2011 428 texas instruments-advance information general-purpose input/outputs (gpios) gpio alternate function select (gpioafsel) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x420 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 afsel reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio alternate function select description value the associated pin functions as a gpio and is controlled by the gpio registers. 0 the associated pin functions as a peripheral signal and is controlled by the alternate hardware function. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in table 9-1 on page 405. 1 - r/w afsel 7:0 429 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 11: gpio 2-ma drive select (gpiodr2r), offset 0x500 the gpiodr2r register is the 2-ma drive control register. each gpio signal in the port can be individually configured without affecting the other pads. when setting the drv2 bit for a gpio signal, the corresponding drv4 bit in the gpiodr4r register and drv8 bit in the gpiodr8r register are automatically cleared by hardware. by default, all gpio pins have 2-ma drive. gpio 2-ma drive select (gpiodr2r) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x500 type r/w, reset 0x0000.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 drv2 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 output pad 2-ma drive enable description value the corresponding gpio pin has 2-ma drive. 1 the drive for the corresponding gpio pin is controlled by the gpiodr4r or gpiodr8r register. 0 setting a bit in either the gpiodr4 register or the gpiodr8 register clears the corresponding 2-ma enable bit. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. 0xff r/w drv2 7:0 march 20, 2011 430 texas instruments-advance information general-purpose input/outputs (gpios) register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 the gpiodr4r register is the 4-ma drive control register. each gpio signal in the port can be individually configured without affecting the other pads. when setting the drv4 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and drv8 bit in the gpiodr8r register are automatically cleared by hardware. gpio 4-ma drive select (gpiodr4r) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x504 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 drv4 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 output pad 4-ma drive enable description value the corresponding gpio pin has 4-ma drive. 1 the drive for the corresponding gpio pin is controlled by the gpiodr2r or gpiodr8r register. 0 setting a bit in either the gpiodr2 register or the gpiodr8 register clears the corresponding 4-ma enable bit. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. 0x00 r/w drv4 7:0 431 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 the gpiodr8r register is the 8-ma drive control register. each gpio signal in the port can be individually configured without affecting the other pads. when setting the drv8 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and drv4 bit in the gpiodr4r register are automatically cleared by hardware. the 8-ma setting is also used for high-current operation. note: there is no configuration difference between 8-ma and high-current operation. the additional current capacity results from a shift in the v oh /v ol levels. see recommended dc operating conditions on page 964 for further information. gpio 8-ma drive select (gpiodr8r) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x508 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 drv8 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 output pad 8-ma drive enable description value the corresponding gpio pin has 8-ma drive. 1 the drive for the corresponding gpio pin is controlled by the gpiodr2r or gpiodr4r register. 0 setting a bit in either the gpiodr2 register or the gpiodr4 register clears the corresponding 8-ma enable bit. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. 0x00 r/w drv8 7:0 march 20, 2011 432 texas instruments-advance information general-purpose input/outputs (gpios) register 14: gpio open drain select (gpioodr), offset 0x50c the gpioodr register is the open drain control register. setting a bit in this register enables the open-drain configuration of the corresponding gpio pad. when open-drain mode is enabled, the corresponding bit should also be set in the gpio digital enable (gpioden) register (see page 439). corresponding bits in the drive strength and slew rate control registers ( gpiodr2r , gpiodr4r , gpiodr8r , and gpioslr ) can be set to achieve the desired rise and fall times. the gpio acts as an open-drain input if the corresponding bit in the gpiodir register is cleared. if open drain is selected while the gpio is configured as an input, the gpio will remain an input and the open-drain selection has no effect until the gpio is changed to an output. when using the i 2 c module, in addition to configuring the pin to open drain, the gpio alternate function select (gpioafsel) register bits for the i 2 c clock and data pins should be set (see examples in initialization and configuration on page 413). gpio open drain select (gpioodr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x50c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ode reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 output pad open drain enable description value the corresponding pin is configured as open drain. 1 the corresponding pin is not configured as open drain. 0 0x00 r/w ode 7:0 433 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 15: gpio pull-up select (gpiopur), offset 0x510 the gpiopur register is the pull-up control register. when a bit is set, a weak pull-up resistor on the corresponding gpio signal is enabled. setting a bit in gpiopur automatically clears the corresponding bit in the gpio pull-down select (gpiopdr) register (see page 436). write access to this register is protected with the gpiocr register. bits in gpiocr that are cleared prevent writes to the equivalent bit in this register. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the four jtag/swd pins (shown in the table below). a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 9-9. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 1 0 uart0 pa[1:0] 0x1 0 0 1 0 ssi0 pa[5:2] 0x1 0 0 1 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] note: the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 428), gpio pull up select (gpiopur) register (see page 434), gpio pull-down select (gpiopdr) register (see page 436), and gpio digital enable (gpioden) register (see page 439) are not committed to storage unless the gpio lock (gpiolock) register (see page 441) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 442) have been set. gpio pull-up select (gpiopur) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x510 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pue reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type - - - - - - - - 0 0 0 0 0 0 0 0 reset march 20, 2011 434 texas instruments-advance information general-purpose input/outputs (gpios) description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 pad weak pull-up enable description value the corresponding pin has a weak pull-up resistor. 1 the corresponding pin is not affected. 0 setting a bit in the gpiopdr register clears the corresponding bit in the gpiopur register. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in table 9-1 on page 405. - r/w pue 7:0 435 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 16: gpio pull-down select (gpiopdr), offset 0x514 the gpiopdr register is the pull-down control register. when a bit is set, a weak pull-down resistor on the corresponding gpio signal is enabled. setting a bit in gpiopdr automatically clears the corresponding bit in the gpio pull-up select (gpiopur) register (see page 434). important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the four jtag/swd pins (shown in the table below). a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 9-10. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 1 0 uart0 pa[1:0] 0x1 0 0 1 0 ssi0 pa[5:2] 0x1 0 0 1 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] note: the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 428), gpio pull up select (gpiopur) register (see page 434), gpio pull-down select (gpiopdr) register (see page 436), and gpio digital enable (gpioden) register (see page 439) are not committed to storage unless the gpio lock (gpiolock) register (see page 441) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 442) have been set. gpio pull-down select (gpiopdr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x514 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pde reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset march 20, 2011 436 texas instruments-advance information general-purpose input/outputs (gpios) description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 pad weak pull-down enable description value the corresponding pin has a weak pull-down resistor. 1 the corresponding pin is not affected. 0 setting a bit in the gpiopur register clears the corresponding bit in the gpiopdr register. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. 0x00 r/w pde 7:0 437 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 17: gpio slew rate control select (gpioslr), offset 0x518 the gpioslr register is the slew rate control register. slew rate control is only available when using the 8-ma drive strength option via the gpio 8-ma drive select (gpiodr8r) register (see page 432). gpio slew rate control select (gpioslr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x518 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 srl reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 slew rate limit enable (8-ma drive only) description value slew rate control is enabled for the corresponding pin. 1 slew rate control is disabled for the corresponding pin. 0 0x00 r/w srl 7:0 march 20, 2011 438 texas instruments-advance information general-purpose input/outputs (gpios) register 18: gpio digital enable (gpioden), offset 0x51c note: pins configured as digital inputs are schmitt-triggered. the gpioden register is the digital enable register. by default, all gpio signals except those listed below are configured out of reset to be undriven (tristate). their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the gpio receiver. to use the pin as a digital input or output (either gpio or alternate function), the corresponding gpioden bit must be set. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the four jtag/swd pins (shown in the table below). a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 9-11. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 1 0 uart0 pa[1:0] 0x1 0 0 1 0 ssi0 pa[5:2] 0x1 0 0 1 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] note: the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 428), gpio pull up select (gpiopur) register (see page 434), gpio pull-down select (gpiopdr) register (see page 436), and gpio digital enable (gpioden) register (see page 439) are not committed to storage unless the gpio lock (gpiolock) register (see page 441) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 442) have been set. 439 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller gpio digital enable (gpioden) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x51c type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 den reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 digital enable description value the digital functions for the corresponding pin are disabled. 0 the digital functions for the corresponding pin are enabled. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in table 9-1 on page 405. 1 - r/w den 7:0 march 20, 2011 440 texas instruments-advance information general-purpose input/outputs (gpios) register 19: gpio lock (gpiolock), offset 0x520 the gpiolock register enables write access to the gpiocr register (see page 442). writing 0x4c4f.434b to the gpiolock register unlocks the gpiocr register. writing any other value to the gpiolock register re-enables the locked state. reading the gpiolock register returns the lock status rather than the 32-bit value that was previously written. therefore, when write accesses are disabled, or locked, reading the gpiolock register returns 0x0000.0001. when write accesses are enabled, or unlocked, reading the gpiolock register returns 0x0000.0000. gpio lock (gpiolock) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x520 type r/w, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field gpio lock a write of the value 0x4c4f.434b unlocks the gpio commit (gpiocr) register for write access.a write of any other value or a write to the gpiocr register reapplies the lock, preventing any register updates. a read of this register returns the following values: description value the gpiocr register is locked and may not be modified. 0x1 the gpiocr register is unlocked and may be modified. 0x0 0x0000.0001 r/w lock 31:0 441 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 20: gpio commit (gpiocr), offset 0x524 the gpiocr register is the commit register. the value of the gpiocr register determines which bits of the gpioafsel , gpiopur , gpiopdr , and gpioden registers are committed when a write to these registers is performed. if a bit in the gpiocr register is cleared, the data being written to the corresponding bit in the gpioafsel , gpiopur , gpiopdr , or gpioden registers cannot be committed and retains its previous value. if a bit in the gpiocr register is set, the data being written to the corresponding bit of the gpioafsel , gpiopur , gpiopdr , or gpioden registers is committed to the register and reflects the new value. the contents of the gpiocr register can only be modified if the status in the gpiolock register is unlocked. writes to the gpiocr register are ignored if the status in the gpiolock register is locked. important: this register is designed to prevent accidental programming of the registers that control connectivity to the nmi and jtag/swd debug hardware. by initializing the bits of the gpiocr register to 0 for pb7 and pc[3:0] , the nmi and jtag/swd debug port can only be converted to gpios through a deliberate set of writes to the gpiolock , gpiocr , and the corresponding registers. because this protection is currently only implemented on the nmi and jtag/swd pins on pb7 and pc[3:0] , all of the other bits in the gpiocr registers cannot be written with 0x0. these bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the gpioafsel , gpiopur , gpiopdr , or gpioden register bits of these other pins. gpio commit (gpiocr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x524 type -, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cr reserved - - - - - - - - ro ro ro ro ro ro ro ro type - - - - - - - - 0 0 0 0 0 0 0 0 reset march 20, 2011 442 texas instruments-advance information general-purpose input/outputs (gpios) description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio commit description value the corresponding gpioafsel , gpiopur , gpiopdr , or gpioden bits can be written. 1 the corresponding gpioafsel , gpiopur , gpiopdr , or gpioden bits cannot be written. 0 note: the default register type for the gpiocr register is ro for all gpio pins with the exception of the nmi pin and the four jtag/swd pins ( pb7 and pc[3:0] ). these five pins are the only gpios that are protected by the gpiocr register. because of this, the register type for gpio port b7 and gpio port c[3:0] is r/w. the default reset value for the gpiocr register is 0x0000.00ff for all gpio pins, with the exception of the nmi pin and the four jtag/swd pins ( pb7 and pc[3:0] ). to ensure that the jtag port is not accidentally programmed as gpio pins, the pc[3:0] pins default to non-committable. similarly, to ensure that the nmi pin is not accidentally programmed as a gpio pin, the pb7 pin defaults to non-committable. because of this, the default reset value of gpiocr for gpio port b is 0x0000.007f while the default reset value of gpiocr for port c is 0x0000.00f0. - - cr 7:0 443 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 21: gpio analog mode select (gpioamsel), offset 0x528 important: this register is only valid for ports d and e; the corresponding base addresses for the remaining ports are not valid. if any pin is to be used as an adc input, the appropriate bit in gpioamsel must be set to disable the analog isolation circuit. the gpioamsel register controls isolation circuits to the analog side of a unified i/o pad. because the gpios may be driven by a 5-v source and affect analog operation, analog circuitry requires isolation from the pins when they are not used in their analog function. each bit of this register controls the isolation circuitry for the corresponding gpio signal. for information on which gpio pins can be used for adc functions, refer to table 21-5 on page 925. gpio analog mode select (gpioamsel) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x528 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioamsel reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 march 20, 2011 444 texas instruments-advance information general-purpose input/outputs (gpios) description reset type name bit/field gpio analog mode select description value the analog function of the pin is enabled, the isolation is disabled, and the pin is capable of analog functions. 1 the analog function of the pin is disabled, the isolation is enabled, and the pin is capable of digital functions as specified by the other gpio configuration registers. 0 note: this register and bits are only valid for gpio signals that share analog function through a unified i/o pad. the reset state of this register is 0 for all signals. 0x00 r/w gpioamsel 7:0 445 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 22: gpio port control (gpiopctl), offset 0x52c the gpiopctl register is used in conjunction with the gpioafsel register and selects the specific peripheral signal for each gpio pin when using the alternate function mode. most bits in the gpioafsel register are cleared on reset, therefore most gpio pins are configured as gpios by default. when a bit is set in the gpioafsel register, the corresponding gpio signal is controlled by an associated peripheral. the gpiopctl register selects one out of a set of peripheral functions for each gpio, providing additional flexibility in signal definition. for information on the defined encodings for the bit fields in this register, refer to table 21-5 on page 925. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in the table below. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the four jtag/swd pins (shown in the table below). a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 9-12. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 1 0 uart0 pa[1:0] 0x1 0 0 1 0 ssi0 pa[5:2] 0x1 0 0 1 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] gpio port control (gpiopctl) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x52c type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 pmc4 pmc5 pmc6 pmc7 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pmc0 pmc1 pmc2 pmc3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field port mux control 7 this field controls the configuration for gpio pin 7. - r/w pmc7 31:28 march 20, 2011 446 texas instruments-advance information general-purpose input/outputs (gpios) description reset type name bit/field port mux control 6 this field controls the configuration for gpio pin 6. - r/w pmc6 27:24 port mux control 5 this field controls the configuration for gpio pin 5. - r/w pmc5 23:20 port mux control 4 this field controls the configuration for gpio pin 4. - r/w pmc4 19:16 port mux control 3 this field controls the configuration for gpio pin 3. - r/w pmc3 15:12 port mux control 2 this field controls the configuration for gpio pin 2. - r/w pmc2 11:8 port mux control 1 this field controls the configuration for gpio pin 1. - r/w pmc1 7:4 port mux control 0 this field controls the configuration for gpio pin 0. - r/w pmc0 3:0 447 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 23: gpio peripheral identification 4 (gpioperiphid4), offset 0xfd0 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 4 (gpioperiphid4) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfd0 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [7:0] 0x00 ro pid4 7:0 march 20, 2011 448 texas instruments-advance information general-purpose input/outputs (gpios) register 24: gpio peripheral identification 5 (gpioperiphid5), offset 0xfd4 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 5 (gpioperiphid5) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfd4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [15:8] 0x00 ro pid5 7:0 449 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 25: gpio peripheral identification 6 (gpioperiphid6), offset 0xfd8 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 6 (gpioperiphid6) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfd8 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [23:16] 0x00 ro pid6 7:0 march 20, 2011 450 texas instruments-advance information general-purpose input/outputs (gpios) register 26: gpio peripheral identification 7 (gpioperiphid7), offset 0xfdc the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 7 (gpioperiphid7) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfdc type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [31:24] 0x00 ro pid7 7:0 451 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 27: gpio peripheral identification 0 (gpioperiphid0), offset 0xfe0 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 0 (gpioperiphid0) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfe0 type ro, reset 0x0000.0061 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x61 ro pid0 7:0 march 20, 2011 452 texas instruments-advance information general-purpose input/outputs (gpios) register 28: gpio peripheral identification 1 (gpioperiphid1), offset 0xfe4 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 1 (gpioperiphid1) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfe4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 453 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 29: gpio peripheral identification 2 (gpioperiphid2), offset 0xfe8 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 2 (gpioperiphid2) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfe8 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 march 20, 2011 454 texas instruments-advance information general-purpose input/outputs (gpios) register 30: gpio peripheral identification 3 (gpioperiphid3), offset 0xfec the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 3 (gpioperiphid3) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfec type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 455 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 31: gpio primecell identification 0 (gpiopcellid0), offset 0xff0 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. gpio primecell identification 0 (gpiopcellid0) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 march 20, 2011 456 texas instruments-advance information general-purpose input/outputs (gpios) register 32: gpio primecell identification 1 (gpiopcellid1), offset 0xff4 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. gpio primecell identification 1 (gpiopcellid1) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 457 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 33: gpio primecell identification 2 (gpiopcellid2), offset 0xff8 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. gpio primecell identification 2 (gpiopcellid2) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xff8 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 march 20, 2011 458 texas instruments-advance information general-purpose input/outputs (gpios) register 34: gpio primecell identification 3 (gpiopcellid3), offset 0xffc the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. gpio primecell identification 3 (gpiopcellid3) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 459 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 10 general-purpose timers programmable timers can be used to count or time external events that drive the timer input pins. the stellaris ? general-purpose timer module (gptm) contains four gptm blocks. each gptm block provides two 16-bit timers/counters (referred to as timer a and timer b) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer or one 32-bit real-time clock (rtc). timers can also be used to trigger dma transfers. in addition, timers can be used to trigger analog-to-digital conversions (adc). the adc trigger signals from all of the general-purpose timers are ored together before reaching the adc module, so only one timer should be used to trigger adc events. the gpt module is one timing resource available on the stellaris microcontrollers. other timer resources include the system timer (systick) (see 103) and the pwm timer in the pwm module (see pwm timer on page 805). the general-purpose timer module (gptm) contains four gptm blocks with the following functional options: operating modes: C 16- or 32-bit programmable one-shot timer C 16- or 32-bit programmable periodic timer C 16-bit general-purpose timer with an 8-bit prescaler C 32-bit real-time clock (rtc) when using an external 32.768-khz clock as the input C 16-bit input-edge count- or time-capture modes C 16-bit pwm mode with software-programmable output inversion of the pwm signal count up or down eight capture compare pwm pins (ccp) daisy chaining of timer modules to allow a single timer to initiate multiple timing events adc event trigger user-enabled stalling when the microcontroller asserts cpu halt flag during debug (excluding rtc mode) ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. efficient transfers using micro direct memory access controller (dma) C dedicated channel for each timer C burst request generated on timer interrupt march 20, 2011 460 texas instruments-advance information general-purpose timers 10.1 block diagram in the block diagram, the specific capture compare pwm (ccp) pins available depend on the stellaris device. see table 10-1 on page 461 for the available ccp pins and their timer assignments. figure 10-1. gptm module block diagram table 10-1. available ccp pins odd ccp pin even ccp pin 16-bit up/down counter timer - ccp0 timera timer 0 ccp1 - timerb - ccp2 timera timer 1 ccp3 - timerb - ccp4 timera timer 2 ccp5 - timerb - ccp6 timera timer 3 ccp7 - timerb 10.2 signal description table 10-2 on page 462 and table 10-3 on page 463 list the external signals of the gp timer module and describe the function of each. the gp timer signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these gp timer signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the gp timer function. the number in parentheses is the encoding that must be programmed into 461 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller & o r f n ( g j h ' h w h f w 5 7 & ' l y l g h u & o r f n ( g j h ' h w h f w . + ] r u ( y h q & & 3 3 l q 2 g g & & 3 3 l q 7 $ & r p s d u d w r u 7 % & r p s d u d w r u * 3 7 0 7 % 5 * 3 7 0 7 $ 5 7 l p h u $ , q w h u u x s w 7 l p h u % , q w h u u x s w 6 \ v w h p & o r f n [ ' r z q & r x q w h u 0 r g h v [ ) ) ) ) 8 s & r x q w h u 0 r g h v [ ' r z q & r x q w h u 0 r g h v [ ) ) ) ) 8 s & r x q w h u 0 r g h v ( q ( q , q w h u u x s w & r q i l j * 3 7 0 & ) * * 3 7 0 5 , 6 * 3 7 0 , & 5 * 3 7 0 0 , 6 * 3 7 0 , 0 5 * 3 7 0 & 7 / * 3 7 0 7 $ 9 * 3 7 0 7 % 9 7 l p h u $ ) u h h 5 x q q l q j 9 d o x h 7 l p h u % ) u h h 5 x q q l q j 9 d o x h 7 l p h u $ & r q w u r o * 3 7 0 7 $ 3 0 5 * 3 7 0 7 $ , / 5 * 3 7 0 7 $ 0 $ 7 & + 5 * 3 7 0 7 $ 3 5 * 3 7 0 7 $ 0 5 7 l p h u % & r q w u r o * 3 7 0 7 % 3 0 5 * 3 7 0 7 % , / 5 * 3 7 0 7 % 0 $ 7 & + 5 * 3 7 0 7 % 3 5 * 3 7 0 7 % 0 5 the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the gp timer signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. table 10-2. signals for general-purpose timers (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 0. ttl i/o pd3 (4) pc7 (4) pc6 (6) pj2 (9) pf4 (1) pb0 (1) pb2 (5) pb5 (4) pd4 (1) 13 22 23 39 58 66 72 91 97 ccp0 capture/compare/pwm 1. ttl i/o pc5 (1) pc4 (9) pa6 (2) pf6 (1) pb1 (4) pb6 (1) pe3 (1) pd7 (3) 24 25 34 43 67 90 96 100 ccp1 capture/compare/pwm 2. ttl i/o pe4 (6) pd1 (10) pc4 (5) pf5 (1) pb1 (1) pe1 (4) pb5 (6) pe2 (5) pd5 (1) 6 11 25 46 67 75 91 95 98 ccp2 capture/compare/pwm 3. ttl i/o pe4 (1) pc6 (1) pc5 (5) pa7 (7) pg4 (1) pf1 (10) pb2 (4) pe0 (3) pd4 (2) 6 23 24 35 41 61 72 74 97 ccp3 capture/compare/pwm 4. ttl i/o pc7 (1) pc4 (6) pa7 (2) pf7 (1) pe2 (1) pd5 (2) 22 25 35 42 95 98 ccp4 capture/compare/pwm 5. ttl i/o pe5 (1) pd2 (4) pc4 (1) pg7 (8) pg5 (1) pb6 (6) pb5 (2) 5 12 25 36 40 90 91 ccp5 march 20, 2011 462 texas instruments-advance information general-purpose timers table 10-2. signals for general-purpose timers (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 6. ttl i/o pd0 (6) pd2 (2) pe1 (5) ph0 (1) pb5 (3) 10 12 75 86 91 ccp6 capture/compare/pwm 7. ttl i/o pd1 (6) pd3 (2) ph1 (1) pb6 (2) pe3 (5) 11 13 85 90 96 ccp7 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 10-3. signals for general-purpose timers (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 0. ttl i/o pd3 (4) pc7 (4) pc6 (6) pj2 (9) pf4 (1) pb0 (1) pb2 (5) pb5 (4) pd4 (1) h1 l2 m2 k6 l9 e12 a11 b7 b5 ccp0 capture/compare/pwm 1. ttl i/o pc5 (1) pc4 (9) pa6 (2) pf6 (1) pb1 (4) pb6 (1) pe3 (1) pd7 (3) m1 l1 l6 m8 d12 a7 b4 a2 ccp1 capture/compare/pwm 2. ttl i/o pe4 (6) pd1 (10) pc4 (5) pf5 (1) pb1 (1) pe1 (4) pb5 (6) pe2 (5) pd5 (1) b2 g2 l1 l8 d12 a12 b7 a4 c6 ccp2 capture/compare/pwm 3. ttl i/o pe4 (1) pc6 (1) pc5 (5) pa7 (7) pg4 (1) pf1 (10) pb2 (4) pe0 (3) pd4 (2) b2 m2 m1 m6 k3 h12 a11 b11 b5 ccp3 463 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 10-3. signals for general-purpose timers (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 4. ttl i/o pc7 (1) pc4 (6) pa7 (2) pf7 (1) pe2 (1) pd5 (2) l2 l1 m6 k4 a4 c6 ccp4 capture/compare/pwm 5. ttl i/o pe5 (1) pd2 (4) pc4 (1) pg7 (8) pg5 (1) pb6 (6) pb5 (2) b3 h2 l1 c10 m7 a7 b7 ccp5 capture/compare/pwm 6. ttl i/o pd0 (6) pd2 (2) pe1 (5) ph0 (1) pb5 (3) g1 h2 a12 c9 b7 ccp6 capture/compare/pwm 7. ttl i/o pd1 (6) pd3 (2) ph1 (1) pb6 (2) pe3 (5) g2 h1 c8 a7 b4 ccp7 a. the ttl designation indicates the pin has ttl-compatible voltage levels. 10.3 functional description the main components of each gptm block are two free-running up/down counters (referred to as timer a and timer b), two match registers, two prescaler match registers, two shadow registers, and two load/initialization registers and their associated control functions. the exact functionality of each gptm is controlled by software and configured through the register interface. timer a and timer b can be used individually, in which case they have a 16-bit counting range. in addition, timer a and timer b can be concatenated to provide a 32-bit counting range. note that the prescaler can only be used when the timers are used individually. the available modes for each gptm block are shown in table 10-4 on page 464. note that when counting down, the prescaler acts as a true prescaler and contains the least-significant bits of the count. when counting up, the prescaler acts as a timer extension and holds the most-significant bits of the count. table 10-4. general-purpose timer capabilities prescaler size a counter size count direction timer use mode 8-bit 16-bit up or down individual one-shot - 32-bit up or down concatenated 8-bit 16-bit up or down individual periodic - 32-bit up or down concatenated - 32-bit up concatenated rtc 8-bit 16-bit down individual edge count - 16-bit down individual edge time march 20, 2011 464 texas instruments-advance information general-purpose timers table 10-4. general-purpose timer capabilities (continued) prescaler size a counter size count direction timer use mode - 16-bit down individual pwm a. the prescaler is only available when the timers are used individually software configures the gptm using the gptm configuration (gptmcfg) register (see page 476), the gptm timer a mode (gptmtamr) register (see page 477), and the gptm timer b mode (gptmtbmr) register (see page 479). when in one of the concatentated modes, timer a and timer b can only operate in one mode. however, when configured in an individual mode, timer a and timer b can be independently configured in any combination of the individual modes. 10.3.1 gptm reset conditions after reset has been applied to the gptm module, the module is in an inactive state, and all control registers are cleared and in their default states. counters timer a and timer b are initialized to all 1s, along with their corresponding load registers: the gptm timer a interval load (gptmtailr) register (see page 494) and the gptm timer b interval load (gptmtbilr) register (see page 495) and shadow registers: the gptm timer a value (gptmtav) register (see page 504) and the gptm timer b value (gptmtbv) register (see page 505). the prescale counters are initialized to 0x00: the gptm timer a prescale (gptmtapr) register (see page 498) and the gptm timer b prescale (gptmtbpr) register (see page 499). 10.3.2 timer modes this section describes the operation of the various timer modes. when using timer a and timer b in concatenated mode, only the timer a control and status bits must be used; there is no need to use timer b control and status bits. the gptm is placed into individual mode by writing a value of 0x4 to the gptm configuration (gptmcfg) register (see page 476). in the following sections, the variable " n " is used in bit field and register names to imply either a timer a fun m,kction or a timer b function. the prescaler is only available in the 16-bit one-shot, periodic, and input edge count timer mode. note that when counting down, the prescaler acts as a true prescaler and contains the least-significant bits of the count. when counting up, the prescaler acts as a timer extension and holds the most-significant bits of the count. throughout this section, the timeout event in down-count mode is 0x0 and in up-count mode is the value in the gptm timer n match (gptmtnmatch) and the optional gptm timer n prescale match (gptmtnpmr) registers. 10.3.2.1 one-shot/periodic timer mode the selection of one-shot or periodic mode is determined by the value written to the tnmr field of the gptm timer n mode (gptmtnmr) register (see page 477). the timer is configured to count up or down using the tncdir bit in the gptmtnmr register. when software sets the tnen bit in the gptm control (gptmctl) register (see page 481), the timer begins counting up from 0x0 or down from its preloaded value. alternatively, if the tnwot bit is set in the gptmtnmr register, once the tnen bit is set, the timer waits for a trigger to begin counting (see the section called wait-for-trigger mode on page 466). when the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start value from the gptmtnilr and the gptmtnpr registers on the next cycle. when the timer is counting up and it reaches the timeout event (the value in the gptmtnilr and the gptmtnpr registers), the timer reloads with 0x0. if configured to be a one-shot timer, the timer stops counting and clears the tnen bit in the gptmctl register. if configured as a periodic timer, the timer starts counting again on the next cycle. in periodic, snap-shot mode ( tnsnaps bit in the gptmtnmr register is set), the actual free-running value of the timer at the time-out event is loaded into the 465 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller gptmtnr register. in this manner, software can determine the time elapsed from the interrupt assertion to the isr entry. in addition to reloading the count value, the gptm generates interrupts and triggers when it reaches the time-out event. the gptm sets the tntoris bit in the gptm raw interrupt status (gptmris) register (see page 486), and holds it until it is cleared by writing the gptm interrupt clear (gptmicr) register (see page 492). if the timeout interrupt is enabled in the gptm interrupt mask (gptmimr) register (see page 484), the gptm also sets the tntomis bit in the gptm masked interrupt status (gptmmis) register (see page 489). by setting the tnmie bit in the gptmtamr register, an interrupt can also be generated when the timer value equals the value loaded into the gptm timer n match (gptmtnmatch) and gptm timer n prescale match (gptmtnpmr) registers. this interrupt has the same status, masking, and clearing functions as the timeout interrupt. the adc trigger is enabled by setting the tnote bit in gptmctl . the dma trigger is enabled by configuring and enabling the appropriate dma channel. see channel configuration on page 350. if software updates the gptmtnilr register while the counter is counting down, the counter loads the new value on the next clock cycle and continues counting down from the new value. if software updates the gptmtnilr register while the counter is counting up, the timeout event is changed on the next cycle to the new value. if software updates the gptm timer n value (gptmtnv) register while the counter is counting up or down, the counter loads the new value on the next clock cycle and continues counting from the new value. if software updates the gptmtnmatchr register while the counter is counting, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tnstall bit in the gptmctl register is set, the timer freezes counting while the processor is halted by the debugger. the timer resumes counting when the processor resumes execution. the following table shows a variety of configurations for a 16-bit free-running timer while using the prescaler. all values assume an 80-mhz clock with tc=12.5 ns (clock period). table 10-5. 16-bit timer with prescaler configurations units max time #clock (tc) a prescale ms 0.8192 1 00000000 ms 1.6384 2 00000001 ms 2.4576 3 00000010 -- -- -- ------------ ms 208.0768 254 11111101 ms 208.896 255 11111110 ms 209.7152 256 11111111 a. tc is the clock period. wait-for-trigger mode the wait-for-trigger mode allows daisy chaining of the timer modules such that once configured, a single timer can initiate mulitple timing events using the timer triggers. wait-for-trigger mode is enabled by setting the tnwot bit in the gptmtnmr register. when the tnwot bit is set, timer n+1 does not begin counting until the timer in the previous position in the daisy chain (timer n) reaches its time-out event. the daisy chain is configured such that gptm1 always follows gptm0, gptm2 follows gptm1, and so on. if timer a is in 32-bit mode (controlled by the gptmcfg bit in the gptmcfg register), it triggers timer a in the next module. if timer a is in 16-bit mode, it triggers timer b in the same module, and timer b triggers timer a in the next module. care must be taken that the tawot bit is never set in gptm0. figure 10-2 on page 467 shows how the gptmcfg bit affects the daisy chain. this function is valid for both one-shot and periodic modes. march 20, 2011 466 texas instruments-advance information general-purpose timers figure 10-2. timer daisy chain 10.3.2.2 real-time clock timer mode in real-time clock (rtc) mode, the concatenated versions of the timer a and timer b registers are configured as an up-counter. when rtc mode is selected for the first time after reset, the counter is loaded with a value of 0x1. all subsequent load values must be written to the gptm timer a interval load (gptmtailr) register (see page 494). the input clock on an even ccp input is required to be 32.768 khz in rtc mode. the clock signal is then divided down to a 1-hz rate and is passed along to the input of the counter. when software writes the taen bit in the gptmctl register, the counter starts counting up from its preloaded value of 0x1. when the current count value matches the preloaded value in the gptmtamatchr register, the gptm asserts the rtcris bit in gptmris and continues counting until either a hardware reset, or it is disabled by software (clearing the taen bit). when the timer value reaches the terminal count, the timer rolls over and continues counting up from 0x0. if the rtc interrupt is enabled in gptmimr , the gptm also sets the rtcmis bit in gptmmis and generates a controller interrupt. the status flags are cleared by writing the rtccint bit in gptmicr . in addition to generating interrupts, a dma trigger can be generated. the dma trigger is enabled by configuring and enabling the appropriate dma channel. see channel configuration on page 350. if the tastall and/or tbstall bits in the gptmctl register are set, the timer does not freeze if the rtcen bit is set in gptmctl . 10.3.2.3 input edge-count mode note: for rising-edge detection, the input signal must be high for at least two system clock periods following the rising edge. similarly, for falling-edge detection, the input signal must be low for at least two system clock periods following the falling edge. based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. in edge-count mode, the timer is configured as a 24-bit down-counter including the optional prescaler with the upper count value stored in the gptm timer n prescale (gptmtnpr) register and the lower bits in the gptmtnr register. in this mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. to place the timer in edge-count mode, the tncmr bit of the gptmtnmr register must be cleared. the type of edge that the timer counts is determined by the tnevent fields of the gptmctl register. during initialization, the gptmtnmatchr and gptmtnpmr registers are configured so that the difference between the value in the gptmtnilr and gptmtnpr registers and the gptmtnmatchr and gptmtnpmr registers equals the number of edge events that must be counted. 467 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller * 3 7 l p h u 1 7 l p h u % 7 l p h u $ * 3 7 0 & ) * * 3 7 l p h u 1 7 l p h u % 7 l p h u $ * 3 7 0 & ) * 7 l p h u % $ ' & 7 u l j j h u 7 l p h u $ $ ' & 7 u l j j h u 7 l p h u % $ ' & 7 u l j j h u 7 l p h u $ $ ' & 7 u l j j h u when software writes the tnen bit in the gptm control (gptmctl) register, the timer is enabled for event capture. each input event on the ccp pin decrements the counter by 1 until the event count matches gptmtnmatchr and gptmtnpmr . when the counts match, the gptm asserts the cnmris bit in the gptmris register (and the cnmmis bit, if the interrupt is not masked). in addition to generating interrupts, an adc and/or a dma trigger can be generated. the adc trigger is enabled by setting the tnote bit in gptmctl .the dma trigger is enabled by configuring and enabling the appropriate dma channel. see channel configuration on page 350. after the match value is reached, the counter is then reloaded using the value in gptmtnilr and gptmtnpr registers, and stopped because the gptm automatically clears the tnen bit in the gptmctl register. once the event count has been reached, all further events are ignored until tnen is re-enabled by software. figure 10-3 on page 468 shows how input edge-count mode works. in this case, the timer start value is set to gptmtnilr =0x000a and the match value is set to gptmtnmatchr =0x0006 so that four edge events are counted. the counter is configured to detect both edges of the input signal. note that the last two edges are not counted because the timer automatically clears the tnen bit after the current count matches the value in the gptmtnmatchr register. figure 10-3. input edge-count mode example 10.3.2.4 input edge-time mode note: for rising-edge detection, the input signal must be high for at least two system clock periods following the rising edge. similarly, for falling edge detection, the input signal must be low for at least two system clock periods following the falling edge. based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. the prescaler is not available in 16-bit input edge-time mode. in edge-time mode, the timer is configured as a 16-bit down-counter. in this mode, the timer is initialized to the value loaded in the gptmtnilr register. the timer is capable of capturing three types of events: rising edge, falling edge, or both. the timer is placed into edge-time mode by march 20, 2011 468 texas instruments-advance information general-purpose timers , q s x w 6 l j q d o 7 l p h u v w r s v i o d j v d v v h u w h g 7 l p h u u h o r d g r q q h [ w f \ f o h , j q r u h g , j q r u h g & r x q w [ $ [ [ [ [ setting the tncmr bit in the gptmtnmr register, and the type of event that the timer captures is determined by the tnevent fields of the gptmctl register. when software writes the tnen bit in the gptmctl register, the timer is enabled for event capture. when the selected input event is detected, the current timer counter value is captured in the gptmtnr register and is available to be read by the microcontroller. the gptm then asserts the cneris bit (and the cnemis bit, if the interrupt is not masked). the gptmtnv contains the free-running value of the timer and can be read to determine the time that elapsed between the interrupt assertion and the entry into the isr. in addition to generating interrupts, an adc and/or a dma trigger can be generated. the adc trigger is enabled by setting the tnote bit in gptmctl .the dma trigger is enabled by configuring and enabling the appropriate dma channel. see channel configuration on page 350. after an event has been captured, the timer does not stop counting. it continues to count until the tnen bit is cleared. when the timer reaches the timeout value, it is reloaded with the value from the gptmtnilr register. figure 10-4 on page 469 shows how input edge timing mode works. in the diagram, it is assumed that the start value of the timer is the default value of 0xffff, and the timer is configured to capture rising edge events. each time a rising edge event is detected, the current count value is loaded into the gptmtnr register, and is held there until another rising edge is detected (at which point the new count value is loaded into the gptmtnr register). figure 10-4. 16-bit input edge-time mode example 10.3.2.5 pwm mode note: the prescaler is not available in 16-bit pwm mode. the gptm supports a simple pwm generation mode. in pwm mode, the timer is configured as a 16-bit down-counter with a start value (and thus period) defined by the gptmtnilr register. in this mode, the pwm frequency and period are synchronous events and therefore guaranteed to be glitch free. pwm mode is enabled with the gptmtnmr register by setting the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x1 or 0x2. 469 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller * 3 7 0 7 q 5 < , q s x w 6 l j q d o 7 l p h & r x q w * 3 7 0 7 q 5 ; * 3 7 0 7 q 5 = = ; < [ ) ) ) ) when software writes the tnen bit in the gptmctl register, the counter begins counting down until it reaches the 0x0 state. on the next counter cycle in periodic mode, the counter reloads its start value from the gptmtnilr register and continues counting until disabled by software clearing the tnen bit in the gptmctl register. no interrupts or status bits are asserted in pwm mode. the output pwm signal asserts when the counter is at the value of the gptmtnilr register (its start state), and is deasserted when the counter value equals the value in the gptmtnmatchr register. software has the capability of inverting the output pwm signal by setting the tnpwml bit in the gptmctl register. figure 10-5 on page 470 shows how to generate an output pwm with a 1-ms period and a 66% duty cycle assuming a 50-mhz input clock and tnpwml =0 (duty cycle would be 33% for the tnpwml =1 configuration). for this example, the start value is gptmtnilr =0xc350 and the match value is gptmtnmatchr =0x411a. figure 10-5. 16-bit pwm mode example 10.3.3 dma operation the timers each have a dedicated dma channel and can provide a request signal to the dma controller. the request is a burst type and occurs whenever a timer raw interrupt condition occurs. the arbitration size of the dma transfer should be set to the amount of data that should be transferred whenever a timer event occurs. for example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a periodic timeout at 10 ms. configure the dma transfer for a total of 256 items, with a burst size of 8 items. each time the timer times out, the dma controller transfers 8 items, until all 256 items have been transferred. no other special steps are needed to enable timers for dma operation. refer to micro direct memory access (dma) on page 346 for more details about programming the dma controller. march 20, 2011 470 texas instruments-advance information general-purpose timers 2 x w s x w 6 l j q d o 7 l p h & r x q w * 3 7 0 7 q 5 * 3 7 0 q 0 5 * 3 7 0 7 q 5 * 3 7 0 q 0 5 [ & [ $ 7 q 3 : 0 / 7 q 3 : 0 / 7 q ( 1 v h w 10.3.4 accessing concatenated register values the gptm is placed into concatenated mode by writing a 0x0 or a 0x1 to the gptmcfg bit field in the gptm configuration (gptmcfg) register. in both configurations, certain registers are concatenated to form pseudo 32-bit registers. these registers include: gptm timer a interval load (gptmtailr) register [15:0], see page 494 gptm timer b interval load (gptmtbilr) register [15:0], see page 495 gptm timer a (gptmtar) register [15:0], see page 502 gptm timer b (gptmtbr) register [15:0], see page 503 gptm timer a value (gptmtav) register [15:0], see page 504 gptm timer b value (gptmtbv) register [15:0], see page 505 gptm timer a match (gptmtamatchr) register [15:0], see page 496 gptm timer b match (gptmtbmatchr) register [15:0], see page 497 in the 32-bit modes, the gptm translates a 32-bit write access to gptmtailr into a write access to both gptmtailr and gptmtbilr . the resulting word ordering for such a write operation is: gptmtbilr[15:0]:gptmtailr[15:0] likewise, a 32-bit read access to gptmtar returns the value: gptmtbr[15:0]:gptmtar[15:0] a 32-bit read access to gptmtav returns the value: gptmtbv[15:0]:gptmtav[15:0] 10.4 initialization and configuration to use a gptm, the appropriate timern bit must be set in the rcgc1 register (see page 260). if using any ccp pins, the clock to the appropriate gpio module must be enabled via the rcgc1 register (see page 260). to find out which gpio port to enable, refer to table 21-4 on page 917. configure the pmcn fields in the gpiopctl register to assign the ccp signals to the appropriate pins (see page 446 and table 21-5 on page 925). this section shows module initialization and configuration examples for each of the supported timer modes. 10.4.1 one-shot/periodic timer mode the gptm is configured for one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the tnen bit in the gptmctl register is cleared) before making any changes. 2. write the gptm configuration register (gptmcfg) with a value of 0x0000.0000. 3. configure the tnmr field in the gptm timer n mode register (gptmtnmr) : 471 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller a. write a value of 0x1 for one-shot mode. b. write a value of 0x2 for periodic mode. 4. optionally configure the tnsnaps, tnwot, tnmte , and tncdir bits in the gptmtnmr register to select whether to capture the value of the free-running timer at time-out, use an external trigger to start counting, configure an additional trigger or interrupt, and count up or down. 5. load the start value into the gptm timer n interval load register (gptmtnilr) . 6. if interrupts are required, set the appropriate bits in the gptm interrupt mask register (gptmimr) . 7. set the tnen bit in the gptmctl register to enable the timer and start counting. 8. poll the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the appropriate bit of the gptm interrupt clear register (gptmicr) . if the tnmie bit in the gptmtnmr register is set, the rtcris bit in the gptmris register is set, and the timer continues counting. in one-shot mode, the timer stops counting after the time-out event. to re-enable the timer, repeat the sequence. a timer configured in periodic mode reloads the timer and continues counting after the time-out event. 10.4.2 real-time clock (rtc) mode to use the rtc mode, the timer must have a 32.768-khz input signal on an even ccp input. to enable the rtc feature, follow these steps: 1. ensure the timer is disabled (the taen bit is cleared) before making any changes. 2. write the gptm configuration register (gptmcfg) with a value of 0x0000.0001. 3. write the match value to the gptm timer n match register (gptmtnmatchr) . 4. set/clear the rtcen bit in the gptm control register (gptmctl) as needed. 5. if interrupts are required, set the rtcim bit in the gptm interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. when the timer count equals the value in the gptmtnmatchr register, the gptm asserts the rtcris bit in the gptmris register and continues counting until timer a is disabled or a hardware reset. the interrupt is cleared by writing the rtccint bit in the gptmicr register. 10.4.3 input edge-count mode a timer is configured to input edge-count mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register with a value of 0x0000.0004. 3. in the gptm timer mode (gptmtnmr) register, write the tncmr field to 0x0 and the tnmr field to 0x3. march 20, 2011 472 texas instruments-advance information general-purpose timers 4. configure the type of event(s) that the timer captures by writing the tnevent field of the gptm control (gptmctl) register. 5. if a prescaler is to be used, write the prescale value to the gptm timer n prescale register (gptmtnpr) . 6. load the timer start value into the gptm timer n interval load (gptmtnilr) register. 7. load the event count into the gptm timer n match (gptmtnmatchr) register. 8. if interrupts are required, set the cnmim bit in the gptm interrupt mask (gptmimr) register. 9. set the tnen bit in the gptmctl register to enable the timer and begin waiting for edge events. 10. poll the cnmris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnmcint bit of the gptm interrupt clear (gptmicr) register. when counting down in input edge-count mode, the timer stops after the programmed number of edge events has been detected. to re-enable the timer, ensure that the tnen bit is cleared and repeat step 4 on page 473 through step 9 on page 473. 10.4.4 input edge timing mode a timer is configured to input edge timing mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register with a value of 0x0000.0004. 3. in the gptm timer mode (gptmtnmr) register, write the tncmr field to 0x1 and the tnmr field to 0x3. 4. configure the type of event that the timer captures by writing the tnevent field of the gptm control (gptmctl) register. 5. load the timer start value into the gptm timer n interval load (gptmtnilr) register. 6. if interrupts are required, set the cneim bit in the gptm interrupt mask (gptmimr) register. 7. set the tnen bit in the gptm control (gptmctl) register to enable the timer and start counting. 8. poll the cneris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnecint bit of the gptm interrupt clear (gptmicr) register. the time at which the event happened can be obtained by reading the gptm timer n (gptmtnr) register. in input edge timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the gptmtnilr register. the change takes effect at the next cycle after the write. 10.4.5 pwm mode a timer is configured to pwm mode using the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 473 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 2. write the gptm configuration (gptmcfg) register with a value of 0x0000.0004. 3. in the gptm timer mode (gptmtnmr) register, set the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x2. 4. configure the output state of the pwm signal (whether or not it is inverted) in the tn pwml field of the gptm control (gptmctl) register. 5. load the timer start value into the gptm timer n interval load (gptmtnilr) register. 6. load the gptm timer n match (gptmtnmatchr) register with the match value. 7. set the tnen bit in the gptm control (gptmctl) register to enable the timer and begin generation of the output pwm signal. in pwm timing mode, the timer continues running after the pwm signal has been generated. the pwm period can be adjusted at any time by writing the gptmtnilr register, and the change takes effect at the next cycle after the write. 10.5 register map table 10-6 on page 474 lists the gptm registers. the offset listed is a hexadecimal increment to the registers address, relative to that timers base address: timer 0: 0x4003.0000 timer 1: 0x4003.1000 timer 2: 0x4003.2000 timer 3: 0x4003.3000 note that the gp timer module clock must be enabled before the registers can be programmed (see page 260). there must be a delay of 3 system clocks after the timer module clock is enabled before any timer module registers are accessed. table 10-6. timers register map see page description reset type name offset 476 gptm configuration 0x0000.0000 r/w gptmcfg 0x000 477 gptm timer a mode 0x0000.0000 r/w gptmtamr 0x004 479 gptm timer b mode 0x0000.0000 r/w gptmtbmr 0x008 481 gptm control 0x0000.0000 r/w gptmctl 0x00c 484 gptm interrupt mask 0x0000.0000 r/w gptmimr 0x018 486 gptm raw interrupt status 0x0000.0000 ro gptmris 0x01c 489 gptm masked interrupt status 0x0000.0000 ro gptmmis 0x020 492 gptm interrupt clear 0x0000.0000 w1c gptmicr 0x024 494 gptm timer a interval load 0xffff.ffff r/w gptmtailr 0x028 495 gptm timer b interval load 0x0000.ffff r/w gptmtbilr 0x02c 496 gptm timer a match 0xffff.ffff r/w gptmtamatchr 0x030 march 20, 2011 474 texas instruments-advance information general-purpose timers table 10-6. timers register map (continued) see page description reset type name offset 497 gptm timer b match 0x0000.ffff r/w gptmtbmatchr 0x034 498 gptm timer a prescale 0x0000.0000 r/w gptmtapr 0x038 499 gptm timer b prescale 0x0000.0000 r/w gptmtbpr 0x03c 500 gptm timera prescale match 0x0000.0000 r/w gptmtapmr 0x040 501 gptm timerb prescale match 0x0000.0000 r/w gptmtbpmr 0x044 502 gptm timer a 0xffff.ffff ro gptmtar 0x048 503 gptm timer b 0x0000.ffff ro gptmtbr 0x04c 504 gptm timer a value 0xffff.ffff rw gptmtav 0x050 505 gptm timer b value 0x0000.ffff rw gptmtbv 0x054 10.6 register descriptions the remainder of this section lists and describes the gptm registers, in numerical order by address offset. 475 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: gptm configuration (gptmcfg), offset 0x000 this register configures the global operation of the gptm module. the value written to this register determines whether the gptm is in 32- or 16-bit mode. important: bits in this register should only be changed when the taen and tben bits in the gptmctl register are cleared. gptm configuration (gptmcfg) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gptmcfg reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 gptm configuration the gptmcfg values are defined as follows: description value 32-bit timer configuration. 0x0 32-bit real-time clock (rtc) counter configuration. 0x1 reserved 0x2-0x3 16-bit timer configuration. the function is controlled by bits 1:0 of gptmtamr and gptmtbmr . 0x4 reserved 0x5-0x7 0x0 r/w gptmcfg 2:0 march 20, 2011 476 texas instruments-advance information general-purpose timers register 2: gptm timer a mode (gptmtamr), offset 0x004 this register configures the gptm based on the configuration selected in the gptmcfg register. when in pwm mode, set the taams bit , clear the tacmr bit, and configure the tamr field to 0x1 or 0x2. this register controls the modes for timer a when it is used individually. when timer a and timer b are concatenated, this register controls the modes for both timer a and timer b, and the contents of gptmtbmr are ignored. important: bits in this register should only be changed when the taen bit in the gptmctl register is cleared. gptm timer a mode (gptmtamr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tamr tacmr taams tacdir tamie tawot tasnaps reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gptm timer a snap-shot mode description value snap-shot mode is disabled. 0 if timer a is configured in the periodic mode, the actual free-running value of timer a is loaded at the time-out event into the gptm timer a (gptmtar) register. 1 0 r/w tasnaps 7 gptm timer a wait-on-trigger description value timer a begins counting as soon as it is enabled. 0 if timer a is enabled ( taen is set in the gptmctl register), timer a does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain, see figure 10-2 on page 467. this function is valid for both one-shot and periodic modes. 1 this bit must be clear for gp timer module 0, timer a. 0 r/w tawot 6 477 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field gptm timer a match interrupt enable description value the match interrupt is disabled. 0 an interrupt is generated when the match value in the gptmtamatchr register is reached in the one-shot and periodic modes. 1 0 r/w tamie 5 gptm timer a count direction description value the timer counts down. 0 when in one-shot or periodic mode, the timer counts up. when counting up, the timer starts from a value of 0x0. 1 when in pwm or rtc mode, the status of this bit is ignored. pwm mode always counts down and rtc mode always counts up. 0 r/w tacdir 4 gptm timer a alternate mode select the taams values are defined as follows: description value capture mode is enabled. 0 pwm mode is enabled. 1 note: to enable pwm mode, you must also clear the tacmr bit and configure the tamr field to 0x1 or 0x2. 0 r/w taams 3 gptm timer a capture mode the tacmr values are defined as follows: description value edge-count mode 0 edge-time mode 1 0 r/w tacmr 2 gptm timer a mode the tamr values are defined as follows: description value reserved 0x0 one-shot timer mode 0x1 periodic timer mode 0x2 capture mode 0x3 the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register. 0x0 r/w tamr 1:0 march 20, 2011 478 texas instruments-advance information general-purpose timers register 3: gptm timer b mode (gptmtbmr), offset 0x008 this register configures the gptm based on the configuration selected in the gptmcfg register. when in pwm mode, set the tbams bit, clear the tbcmr bit, and configure the tbmr field to 0x1 or 0x2. this register controls the modes for timer b when it is used individually. when timer a and timer b are concatenated, this register is ignored and gptmtbmr controls the modes for both timer a and timer b. important: bits in this register should only be changed when the tben bit in the gptmctl register is cleared. gptm timer b mode (gptmtbmr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbmr tbcmr tbams tbcdir tbmie tbwot tbsnaps reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gptm timer b snap-shot mode description value snap-shot mode is disabled. 0 if timer b is configured in the periodic mode, the actual free-running value of timer b is loaded at the time-out event into the gptm timer b (gptmtbr) register. 1 0 r/w tbsnaps 7 gptm timer b wait-on-trigger description value timer b begins counting as soon as it is enabled. 0 if timer b is enabled ( tben is set in the gptmctl register), timer b does not begin counting until it receives an it receives a trigger from the timer in the previous position in the daisy chain, see figure 10-2 on page 467. this function is valid for both one-shot and periodic modes. 1 0 r/w tbwot 6 479 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field gptm timer b match interrupt enable description value the match interrupt is disabled. 0 an interrupt is generated when the match value in the gptmtbmatchr register is reached in the one-shot and periodic modes. 1 0 r/w tbmie 5 gptm timer b count direction description value the timer counts down. 0 when in one-shot or periodic mode, the timer counts up. when counting up, the timer starts from a value of 0x0. 1 when in pwm or rtc mode, the status of this bit is ignored. pwm mode always counts down and rtc mode always counts up. 0 r/w tbcdir 4 gptm timer b alternate mode select the tbams values are defined as follows: description value capture mode is enabled. 0 pwm mode is enabled. 1 note: to enable pwm mode, you must also clear the tbcmr bit and configure the tbmr field to 0x1 or 0x2. 0 r/w tbams 3 gptm timer b capture mode the tbcmr values are defined as follows: description value edge-count mode 0 edge-time mode 1 0 r/w tbcmr 2 gptm timer b mode the tbmr values are defined as follows: description value reserved 0x0 one-shot timer mode 0x1 periodic timer mode 0x2 capture mode 0x3 the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register. 0x0 r/w tbmr 1:0 march 20, 2011 480 texas instruments-advance information general-purpose timers register 4: gptm control (gptmctl), offset 0x00c this register is used alongside the gptmcfg and gmtmtnmr registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. the output trigger can be used to initiate transfers on the adc module. important: bits in this register should only be changed when the tnen bit for the respective timer is cleared. gptm control (gptmctl) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 taen tastall taevent rtcen taote tapwml reserved tben tbstall tbevent reserved tbote tbpwml reserved r/w r/w r/w r/w r/w r/w r/w ro r/w r/w r/w r/w ro r/w r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:15 gptm timer b pwm output level the tbpwml values are defined as follows: description value output is unaffected. 0 output is inverted. 1 0 r/w tbpwml 14 gptm timer b output trigger enable the tbote values are defined as follows: description value the output timer b adc trigger is disabled. 0 the output timer b adc trigger is enabled. 1 in addition, the adc must be enabled and the timer selected as a trigger source with the emn bit in the adcemux register (see page 563). 0 r/w tbote 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12 481 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field gptm timer b event mode the tbevent values are defined as follows: description value positive edge 0x0 negative edge 0x1 reserved 0x2 both edges 0x3 0x0 r/w tbevent 11:10 gptm timer b stall enable the tbstall values are defined as follows: description value timer b continues counting while the processor is halted by the debugger. 0 timer b freezes counting while the processor is halted by the debugger. 1 if the processor is executing normally, the tbstall bit is ignored. 0 r/w tbstall 9 gptm timer b enable the tben values are defined as follows: description value timer b is disabled. 0 timer b is enabled and begins counting or the capture logic is enabled based on the gptmcfg register. 1 0 r/w tben 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 gptm timer a pwm output level the tapwml values are defined as follows: description value output is unaffected. 0 output is inverted. 1 0 r/w tapwml 6 gptm timer a output trigger enable the taote values are defined as follows: description value the output timer a adc trigger is disabled. 0 the output timer a adc trigger is enabled. 1 in addition, the adc must be enabled and the timer selected as a trigger source with the emn bit in the adcemux register (see page 563). 0 r/w taote 5 march 20, 2011 482 texas instruments-advance information general-purpose timers description reset type name bit/field gptm rtc enable the rtcen values are defined as follows: description value rtc counting is disabled. 0 rtc counting is enabled. 1 0 r/w rtcen 4 gptm timer a event mode the taevent values are defined as follows: description value positive edge 0x0 negative edge 0x1 reserved 0x2 both edges 0x3 0x0 r/w taevent 3:2 gptm timer a stall enable the tastall values are defined as follows: description value timer a continues counting while the processor is halted by the debugger. 0 timer a freezes counting while the processor is halted by the debugger. 1 if the processor is executing normally, the tastall bit is ignored. 0 r/w tastall 1 gptm timer a enable the taen values are defined as follows: description value timer a is disabled. 0 timer a is enabled and begins counting or the capture logic is enabled based on the gptmcfg register. 1 0 r/w taen 0 483 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 5: gptm interrupt mask (gptmimr), offset 0x018 this register allows software to enable/disable gptm controller-level interrupts. setting a bit enables the corresponding interrupt, while clearing a bit disables it. gptm interrupt mask (gptmimr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x018 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tatoim camim caeim rtcim tamim reserved tbtoim cbmim cbeim tbmim reserved r/w r/w r/w r/w r/w ro ro ro r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 gptm timer b mode match interrupt mask the tbmim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tbmim 11 gptm capture b event interrupt mask the cbeim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w cbeim 10 gptm capture b match interrupt mask the cbmim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w cbmim 9 march 20, 2011 484 texas instruments-advance information general-purpose timers description reset type name bit/field gptm timer b time-out interrupt mask the tbtoim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tbtoim 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 gptm timer a mode match interrupt mask the tamim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tamim 4 gptm rtc interrupt mask the rtcim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w rtcim 3 gptm capture a event interrupt mask the caeim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w caeim 2 gptm capture a match interrupt mask the camim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w camim 1 gptm timer a time-out interrupt mask the tatoim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tatoim 0 485 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 6: gptm raw interrupt status (gptmris), offset 0x01c this register shows the state of the gptm's internal interrupt signal. these bits are set whether or not the interrupt is masked in the gptmimr register. each bit can be cleared by writing a 1 to its corresponding bit in gptmicr . gptm raw interrupt status (gptmris) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x01c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tatoris camris caeris rtcris tamris reserved tbtoris cbmris cberis tbmris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 gptm timer b mode match raw interrupt description value the tbmie bit is set in the gptmtbmr register, and the match value in the gptmtbmatchr register has been reached when in the one-shot and periodic modes. 1 the match value has not been reached. 0 this bit is cleared by writing a 1 to the tbmcint bit in the gptmicr register. 0 ro tbmris 11 gptm capture b event raw interrupt description value the capture b event has occurred. 1 the capture b event has not occurred. 0 this bit is cleared by writing a 1 to the cbecint bit in the gptmicr register. 0 ro cberis 10 gptm capture b match raw interrupt description value the capture b match has occurred. 1 the capture b match has not occurred. 0 this bit is cleared by writing a 1 to the cbmcint bit in the gptmicr register. 0 ro cbmris 9 march 20, 2011 486 texas instruments-advance information general-purpose timers description reset type name bit/field gptm timer b time-out raw interrupt description value timer b has timed out. 1 timer b has not timed out. 0 this bit is cleared by writing a 1 to the tbtocint bit in the gptmicr register. 0 ro tbtoris 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 gptm timer a mode match raw interrupt description value the tamie bit is set in the gptmtamr register, and the match value in the gptmtamatchr register has been reached when in the one-shot and periodic modes. 1 the match value has not been reached. 0 this bit is cleared by writing a 1 to the tamcint bit in the gptmicr register. 0 ro tamris 4 gptm rtc raw interrupt description value the rtc event has occurred. 1 the rtc event has not occurred. 0 this bit is cleared by writing a 1 to the rtccint bit in the gptmicr register. 0 ro rtcris 3 gptm capture a event raw interrupt description value the capture a event has occurred. 1 the capture a event has not occurred. 0 this bit is cleared by writing a 1 to the caecint bit in the gptmicr register. 0 ro caeris 2 gptm capture a match raw interrupt description value the capture a match has occurred. 1 the capture a match has not occurred. 0 this bit is cleared by writing a 1 to the camcint bit in the gptmicr register. 0 ro camris 1 487 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field gptm timer a time-out raw interrupt description value timer a has timed out. 1 timer a has not timed out. 0 this bit is cleared by writing a 1 to the tatocint bit in the gptmicr register. 0 ro tatoris 0 march 20, 2011 488 texas instruments-advance information general-purpose timers register 7: gptm masked interrupt status (gptmmis), offset 0x020 this register show the state of the gptm's controller-level interrupt. if an interrupt is unmasked in gptmimr , and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. all bits are cleared by writing a 1 to the corresponding bit in gptmicr . gptm masked interrupt status (gptmmis) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x020 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tatomis cammis caemis rtcmis tammis reserved tbtomis cbmmis cbemis tbmmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 gptm timer b mode match masked interrupt description value an unmasked timer b mode match interrupt has occurred. 1 a timer b mode match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the tbmcint bit in the gptmicr register. 0 ro tbmmis 11 gptm capture b event masked interrupt description value an unmasked capture b event interrupt has occurred. 1 a capture b event interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the cbecint bit in the gptmicr register. 0 ro cbemis 10 489 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field gptm capture b match masked interrupt description value an unmasked capture b match interrupt has occurred. 1 a capture b mode match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the cbmcint bit in the gptmicr register. 0 ro cbmmis 9 gptm timer b time-out masked interrupt description value an unmasked timer b time-out interrupt has occurred. 1 a timer b time-out interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the tbtocint bit in the gptmicr register. 0 ro tbtomis 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 gptm timer a mode match masked interrupt description value an unmasked timer a mode match interrupt has occurred. 1 a timer a mode match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the tamcint bit in the gptmicr register. 0 ro tammis 4 gptm rtc masked interrupt description value an unmasked rtc event interrupt has occurred. 1 an rtc event interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the rtccint bit in the gptmicr register. 0 ro rtcmis 3 gptm capture a event masked interrupt description value an unmasked capture a event interrupt has occurred. 1 a capture a event interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the caecint bit in the gptmicr register. 0 ro caemis 2 march 20, 2011 490 texas instruments-advance information general-purpose timers description reset type name bit/field gptm capture a match masked interrupt description value an unmasked capture a match interrupt has occurred. 1 a capture a mode match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the camcint bit in the gptmicr register. 0 ro cammis 1 gptm timer a time-out masked interrupt description value an unmasked timer a time-out interrupt has occurred. 1 a timer a time-out interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the tatocint bit in the gptmicr register. 0 ro tatomis 0 491 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 8: gptm interrupt clear (gptmicr), offset 0x024 this register is used to clear the status bits in the gptmris and gptmmis registers. writing a 1 to a bit clears the corresponding bit in the gptmris and gptmmis registers. gptm interrupt clear (gptmicr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x024 type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tatocint camcint caecint rtccint tamcint reserved tbtocint cbmcint cbecint tbmcint reserved w1c w1c w1c w1c w1c ro ro ro w1c w1c w1c w1c ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 gptm timer b mode match interrupt clear writing a 1 to this bit clears the tbmris bit in the gptmris register and the tbmmis bit in the gptmmis register. 0 w1c tbmcint 11 gptm capture b event interrupt clear writing a 1 to this bit clears the cberis bit in the gptmris register and the cbemis bit in the gptmmis register. 0 w1c cbecint 10 gptm capture b match interrupt clear writing a 1 to this bit clears the cbmris bit in the gptmris register and the cbmmis bit in the gptmmis register. 0 w1c cbmcint 9 gptm timer b time-out interrupt clear writing a 1 to this bit clears the tbtoris bit in the gptmris register and the tbtomis bit in the gptmmis register. 0 w1c tbtocint 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 gptm timer a mode match interrupt clear writing a 1 to this bit clears the tamris bit in the gptmris register and the tammis bit in the gptmmis register. 0 w1c tamcint 4 gptm rtc interrupt clear writing a 1 to this bit clears the rtcris bit in the gptmris register and the rtcmis bit in the gptmmis register. 0 w1c rtccint 3 gptm capture a event interrupt clear writing a 1 to this bit clears the caeris bit in the gptmris register and the caemis bit in the gptmmis register. 0 w1c caecint 2 march 20, 2011 492 texas instruments-advance information general-purpose timers description reset type name bit/field gptm capture a match interrupt clear writing a 1 to this bit clears the camris bit in the gptmris register and the cammis bit in the gptmmis register. 0 w1c camcint 1 gptm timer a time-out raw interrupt writing a 1 to this bit clears the tatoris bit in the gptmris register and the tatomis bit in the gptmmis register. 0 w1c tatocint 0 493 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 9: gptm timer a interval load (gptmtailr), offset 0x028 when the timer is counting down, this register is used to load the starting count value into the timer. when the timer is counting up, this register sets the upper bound for the timeout event. when a gptm is configured to one of the 32-bit modes, gptmtailr appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timer b interval load (gptmtbilr) register). in a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of gptmtbilr . gptm timer a interval load (gptmtailr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x028 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tailr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tailr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer a interval load register writing this field loads the counter for timer a. a read returns the current value of gptmtailr . 0xffff.ffff r/w tailr 31:0 march 20, 2011 494 texas instruments-advance information general-purpose timers register 10: gptm timer b interval load (gptmtbilr), offset 0x02c when the timer is counting down, this register is used to load the starting count value into the timer. when the timer is counting up, this register sets the upper bound for the timeout event. when a gptm is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the gptmtailr register. reads from this register return the current value of timer b and writes are ignored. in a 16-bit mode, bits 15:0 are used for the load value. bits 31:16 are reserved in both cases. gptm timer b interval load (gptmtbilr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x02c type r/w, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tbilr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbilr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer b interval load register writing this field loads the counter for timer b. a read returns the current value of gptmtbilr . when a gptm is in 32-bit mode, writes are ignored, and reads return the current value of gptmtbilr . 0x0000.ffff r/w tbilr 31:0 495 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 11: gptm timer a match (gptmtamatchr), offset 0x030 this register is loaded with a match value. interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. in edge-count mode, this register along with gptmtailr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtailr minus this value. in pwm mode, this value along with gptmtailr , determines the duty cycle of the output pwm signal. when a gptm is configured to one of the 32-bit modes, gptmtamatchr appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timer b match (gptmtbmatchr) register). in a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of gptmtbmatchr . gptm timer a match (gptmtamatchr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x030 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tamr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tamr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer a match register this value is compared to the gptmtar register to determine match events. 0xffff.ffff r/w tamr 31:0 march 20, 2011 496 texas instruments-advance information general-purpose timers register 12: gptm timer b match (gptmtbmatchr), offset 0x034 this register is loaded with a match value. interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. in edge-count mode, this register along with gptmtbilr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtbilr minus this value. in pwm mode, this value along with gptmtbilr , determines the duty cycle of the output pwm signal. when a gptm is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the gptmtamatchr register. reads from this register return the current match value of timer b and writes are ignored. in a 16-bit mode, bits 15:0 are used for the match value. bits 31:16 are reserved in both cases. gptm timer b match (gptmtbmatchr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x034 type r/w, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tbmr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbmr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer b match register this value is compared to the gptmtbr register to determine match events. 0x0000.ffff r/w tbmr 31:0 497 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 13: gptm timer a prescale (gptmtapr), offset 0x038 this register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. in edge-count mode, this register is the msb of the 24-bit count value. gptm timer a prescale (gptmtapr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tapsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 gptm timer a prescale the register loads this value on a write. a read returns the current value of the register. refer to table 10-5 on page 466 for more details and an example. 0x00 r/w tapsr 7:0 march 20, 2011 498 texas instruments-advance information general-purpose timers register 14: gptm timer b prescale (gptmtbpr), offset 0x03c this register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. in edge-count mode, this register is the msb of the 24-bit count value. gptm timer b prescale (gptmtbpr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x03c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbpsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 gptm timer b prescale the register loads this value on a write. a read returns the current value of this register. refer to table 10-5 on page 466 for more details and an example. 0x00 r/w tbpsr 7:0 499 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 15: gptm timera prescale match (gptmtapmr), offset 0x040 this register effectively extends the range of gptmtamatchr to 24 bits when operating in 16-bit one-shot or periodic mode. gptm timera prescale match (gptmtapmr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x040 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tapsmr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 gptm timera prescale match this value is used alongside gptmtamatchr to detect timer match events while using a prescaler. 0x00 r/w tapsmr 7:0 march 20, 2011 500 texas instruments-advance information general-purpose timers register 16: gptm timerb prescale match (gptmtbpmr), offset 0x044 this register effectively extends the range of gptmtbmatchr to 24 bits when operating in 16-bit one-shot or periodic mode. gptm timerb prescale match (gptmtbpmr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x044 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbpsmr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 gptm timerb prescale match this value is used alongside gptmtbmatchr to detect timer match events while using a prescaler. 0x00 r/w tbpsmr 7:0 501 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 17: gptm timer a (gptmtar), offset 0x048 this register shows the current value of the timer a counter in all cases except for input edge count and time modes. in the input edge count mode, this register contains the number of edges that have occurred. in the input edge time mode, this register contains the time at which the last edge event took place. also in input edge-count mode, bits 23:16 contain the upper 8 bits of the count. when a gptm is configured to one of the 32-bit modes, gptmtar appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timer b (gptmtbr) register). in the16-bit input edge count, input edge time, and pwm modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. bits 31:24 always read as 0. to read the value of the prescaler in 16-bit one-shot and periodic modes, read bits [23:16] in the gptmtav register. gptm timer a (gptmtar) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x048 type ro, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tar ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tar ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer a register a read returns the current value of the gptm timer a count register , in all cases except for input edge count and time modes. in the input edge count mode, this register contains the number of edges that have occurred. in the input edge time mode, this register contains the time at which the last edge event took place. 0xffff.ffff ro tar 31:0 march 20, 2011 502 texas instruments-advance information general-purpose timers register 18: gptm timer b (gptmtbr), offset 0x04c this register shows the current value of the timer b counter in all cases except for input edge count and time modes. in the input edge count mode, this register contains the number of edges that have occurred. in the input edge time mode, this register contains the time at which the last edge event took place. also in input edge-count mode, bits 23:16 contain the upper 8 bits of the count. when a gptm is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the gptmtar register. reads from this register return the current value of timer b. in a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in input edge count, input edge time, and pwm modes, which is the upper 8 bits of the count. bits 31:24 are reserved in both cases. gptm timer b (gptmtbr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x04c type ro, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tbr ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbr ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer b register a read returns the current value of the gptm timer b count register , in all cases except for input edge count and time modes. in the input edge count mode, this register contains the number of edges that have occurred. in the input edge time mode, this register contains the time at which the last edge event took place. 0x0000.ffff ro tbr 31:0 503 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 19: gptm timer a value (gptmtav), offset 0x050 when read, this register shows the current, free-running value of timer a in all modes. software can use this value to determine the time elapsed between an interrupt and the isr entry. when written, the value written into this register is loaded into the gptmtar register on the next clock cycle. in input edge-count mode, bits 23:16 contain the upper 8 bits of the count. when a gptm is configured to one of the 32-bit modes, gptmtav appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timer b value (gptmtbv) register). in a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. bits 31:24 always read as 0. note: the gptmtav register cannot be written in edge-count mode. gptm timer a value (gptmtav) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x050 type rw, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tav rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tav rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer a value a read returns the current, free-running value of timer a in all modes. when written, the value written into this register is loaded into the gptmtar register on the next clock cycle. 0xffff.ffff rw tav 31:0 march 20, 2011 504 texas instruments-advance information general-purpose timers register 20: gptm timer b value (gptmtbv), offset 0x054 when read, this register shows the current, free-running value of timer b in all modes. software can use this value to determine the time elapsed between an interrupt and the isr entry. when written, the value written into this register is loaded into the gptmtbr register on the next clock cycle. in input edge-count mode, bits 23:16 contain the upper 8 bits of the count. when a gptm is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the gptmtav register. reads from this register return the current free-running value of timer b. in a 16-bit mode, bits 15:0 contain the current, free-running value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. bits 31:24 are reserved in both cases. gptm timer b value (gptmtbv) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x054 type rw, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tbv rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbv rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer b value a read returns the current, free-running value of timer a in all modes. when written, the value written into this register is loaded into the gptmtar register on the next clock cycle. 0x0000.ffff rw tbv 31:0 505 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 11 watchdog timers a watchdog timer can generate an interrupt or a reset when a time-out value is reached. the watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. the lm3s1p51 microcontroller has two watchdog timer modules, one module is clocked by the system clock (watchdog timer 0) and the other is clocked by the piosc (watchdog timer 1). the two modules are identical except that wdt1 is in a different clock domain, and therefore requires synchronizers. as a result, wdt1 has a bit defined in the watchdog timer control (wdtctl) register to indicate when a write to a wdt1 register is complete. software can use this bit to ensure that the previous access has completed before starting the next access. the stellaris ? lm3s1p51 controller has two watchdog timer modules with the following features: 32-bit down counter with a programmable load register separate watchdog clock with an enable programmable interrupt generation logic with interrupt masking lock register protection from runaway software reset generation logic with an enable/disable user-enabled stalling when the microcontroller asserts the cpu halt flag during debug the watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. once the watchdog timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. march 20, 2011 506 texas instruments-advance information watchdog timers 11.1 block diagram figure 11-1. wdt module block diagram 11.2 functional description the watchdog timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. after the first time-out event, the 32-bit counter is re-loaded with the value of the watchdog timer load (wdtload) register, and the timer resumes counting down from that value. once the watchdog timer has been configured, the watchdog timer lock (wdtlock) register is written, which prevents the timer configuration from being inadvertently altered by software. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled by setting the resen bit in the wdtctl register, the watchdog timer asserts its reset signal to the system. if the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the wdtload register, and counting resumes from that value. if wdtload is written with a new value while the watchdog timer counter is counting, then the counter is loaded with the new value and continues counting. 507 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller & r q w u r o & o r f n , q w h u u x s w * h q h u d w l r q : ' 7 & 7 / : ' 7 , & 5 : ' 7 5 , 6 : ' 7 0 , 6 : ' 7 / 2 & . : ' 7 7 ( 6 7 : ' 7 / 2 $ ' : ' 7 9 $ / 8 ( & r p s d u d w r u % l w ' r z q & r x q w h u [ , q w h u u x s w 6 \ v w h p & o r f n 3 , 2 6 & , g h q w l i l f d w l r q 5 h j l v w h u v : ' 7 3 & h o o , ' : ' 7 3 h u l s k , ' : ' 7 3 h u l s k , ' : ' 7 3 & h o o , ' : ' 7 3 h u l s k , ' : ' 7 3 h u l s k , ' : ' 7 3 & h o o , ' : ' 7 3 h u l s k , ' : ' 7 3 h u l s k , ' : ' 7 3 & h o o , ' : ' 7 3 h u l s k , ' : ' 7 3 h u l s k , ' writing to wdtload does not clear an active interrupt. an interrupt must be specifically cleared by writing to the watchdog interrupt clear (wdticr) register. the watchdog module interrupt and reset generation can be enabled or disabled as required. when the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 11.2.1 register access timing because the watchdog timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. software must guarantee that this delay is inserted between back-to-back writes to wdt1 registers or between a write followed by a read to the registers. the timing for back-to-back reads from the wdt1 module has no restrictions. the wrc bit in the watchdog control (wdtctl) register for wdt1 indicates that the required timing gap has elapsed. this bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. software should poll wdtctl for wrc =1 prior to accessing another register. note that wdt0 does not have this restriction as it runs off the system clock. 11.3 initialization and configuration to use the wdt, its peripheral clock must be enabled by setting the wdt bit in the rcgc0 register, see page 252. the watchdog timer is configured using the following sequence: 1. load the wdtload register with the desired timer load value. 2. if wdt1, wait for the wrc bit in the wdtctl register to be set. 3. if the watchdog is configured to trigger system resets, set the resen bit in the wdtctl register. 4. if wdt1, wait for the wrc bit in the wdtctl register to be set. 5. set the inten bit in the wdtctl register to enable the watchdog and lock the control register. if software requires that all of the watchdog registers are locked, the watchdog timer module can be fully locked by writing any value to the wdtlock register. to unlock the watchdog timer, write a value of 0x1acc.e551. 11.4 register map table 11-1 on page 509 lists the watchdog registers. the offset listed is a hexadecimal increment to the registers address, relative to the watchdog timer base address: wdt0: 0x4000.0000 wdt1: 0x4000.1000 note that the watchdog timer module clock must be enabled before the registers can be programmed (see page 252). march 20, 2011 508 texas instruments-advance information watchdog timers table 11-1. watchdog timers register map see page description reset type name offset 510 watchdog load 0xffff.ffff r/w wdtload 0x000 511 watchdog value 0xffff.ffff ro wdtvalue 0x004 512 watchdog control 0x0000.0000 (wdt0) 0x8000.0000 (wdt1) r/w wdtctl 0x008 514 watchdog interrupt clear - wo wdticr 0x00c 515 watchdog raw interrupt status 0x0000.0000 ro wdtris 0x010 516 watchdog masked interrupt status 0x0000.0000 ro wdtmis 0x014 517 watchdog test 0x0000.0000 r/w wdttest 0x418 518 watchdog lock 0x0000.0000 r/w wdtlock 0xc00 519 watchdog peripheral identification 4 0x0000.0000 ro wdtperiphid4 0xfd0 520 watchdog peripheral identification 5 0x0000.0000 ro wdtperiphid5 0xfd4 521 watchdog peripheral identification 6 0x0000.0000 ro wdtperiphid6 0xfd8 522 watchdog peripheral identification 7 0x0000.0000 ro wdtperiphid7 0xfdc 523 watchdog peripheral identification 0 0x0000.0005 ro wdtperiphid0 0xfe0 524 watchdog peripheral identification 1 0x0000.0018 ro wdtperiphid1 0xfe4 525 watchdog peripheral identification 2 0x0000.0018 ro wdtperiphid2 0xfe8 526 watchdog peripheral identification 3 0x0000.0001 ro wdtperiphid3 0xfec 527 watchdog primecell identification 0 0x0000.000d ro wdtpcellid0 0xff0 528 watchdog primecell identification 1 0x0000.00f0 ro wdtpcellid1 0xff4 529 watchdog primecell identification 2 0x0000.0006 ro wdtpcellid2 0xff8 530 watchdog primecell identification 3 0x0000.00b1 ro wdtpcellid3 0xffc 11.5 register descriptions the remainder of this section lists and describes the wdt registers, in numerical order by address offset. 509 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: watchdog load (wdtload), offset 0x000 this register is the 32-bit interval value used by the 32-bit counter. when this register is written, the value is immediately loaded and the counter restarts counting down from the new value. if the wdtload register is loaded with 0x0000.0000, an interrupt is immediately generated. watchdog load (wdtload) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x000 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field watchdog load value 0xffff.ffff r/w wdtload 31:0 march 20, 2011 510 texas instruments-advance information watchdog timers register 2: watchdog value (wdtvalue), offset 0x004 this register contains the current count value of the timer. watchdog value (wdtvalue) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x004 type ro, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtvalue ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtvalue ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field watchdog value current value of the 32-bit down counter. 0xffff.ffff ro wdtvalue 31:0 511 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 3: watchdog control (wdtctl), offset 0x008 this register is the watchdog control register. the watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. when the watchdog interrupt has been enabled by setting the inten bit, all subsequent writes to the inten bit are ignored. the only mechanism that can re-enable writes to this bit is a hardware reset. important: because the watchdog timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. software must guarantee that this delay is inserted between back-to-back writes to wdt1 registers or between a write followed by a read to the registers. the timing for back-to-back reads from the wdt1 module has no restrictions. the wrc bit in the watchdog control (wdtctl) register for wdt1 indicates that the required timing gap has elapsed. this bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. software should poll wdtctl for wrc =1 prior to accessing another register. note that wdt0 does not have this restriction as it runs off the system clock and therefore does not have a wrc bit. watchdog control (wdtctl) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x008 type r/w, reset 0x0000.0000 (wdt0) and 0x8000.0000 (wdt1) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wrc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 inten resen reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field write complete the wrc values are defined as follows: description value a write access to one of the wdt1 registers is in progress. 0 a write access is not in progress, and wdt1 registers can be read or written. 1 note: this bit is reserved for wdt0 and has a reset value of 0. 1 ro wrc 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.000 ro reserved 30:2 march 20, 2011 512 texas instruments-advance information watchdog timers description reset type name bit/field watchdog reset enable the resen values are defined as follows: description value disabled. 0 enable the watchdog module reset output. 1 0 r/w resen 1 watchdog interrupt enable the inten values are defined as follows: description value interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 0 interrupt event enabled. once enabled, all writes are ignored. 1 0 r/w inten 0 513 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: watchdog interrupt clear (wdticr), offset 0x00c this register is the interrupt clear register. a write of any value to this register clears the watchdog interrupt and reloads the 32-bit counter from the wdtload register. value for a read or reset is indeterminate. watchdog interrupt clear (wdticr) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x00c type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtintclr wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtintclr wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field watchdog interrupt clear - wo wdtintclr 31:0 march 20, 2011 514 texas instruments-advance information watchdog timers register 5: watchdog raw interrupt status (wdtris), offset 0x010 this register is the raw interrupt status register. watchdog interrupt events can be monitored via this register if the controller interrupt is masked. watchdog raw interrupt status (wdtris) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x010 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 watchdog raw interrupt status description value a watchdog time-out event has occurred. 1 the watchdog has not timed out. 0 0 ro wdtris 0 515 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 6: watchdog masked interrupt status (wdtmis), offset 0x014 this register is the masked interrupt status register. the value of this register is the logical and of the raw interrupt bit and the watchdog interrupt enable bit. watchdog masked interrupt status (wdtmis) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x014 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 watchdog masked interrupt status description value a watchdog time-out event has been signalled to the interrupt controller. 1 the watchdog has not timed out or the watchdog timer interrupt is masked. 0 0 ro wdtmis 0 march 20, 2011 516 texas instruments-advance information watchdog timers register 7: watchdog test (wdttest), offset 0x418 this register provides user-enabled stalling when the microcontroller asserts the cpu halt flag during debug. watchdog test (wdttest) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x418 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved stall reserved ro ro ro ro ro ro ro ro r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 watchdog stall enable description value if the microcontroller is stopped with a debugger, the watchdog timer stops counting. once the microcontroller is restarted, the watchdog timer resumes counting. 1 the watchdog timer continues counting if the microcontroller is stopped with a debugger. 0 0 r/w stall 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:0 517 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 8: watchdog lock (wdtlock), offset 0xc00 writing 0x1acc.e551 to the wdtlock register enables write access to all other registers. writing any other value to the wdtlock register re-enables the locked state for register writes to all the other registers. reading the wdtlock register returns the lock status rather than the 32-bit value written. therefore, when write accesses are disabled, reading the wdtlock register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). watchdog lock (wdtlock) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xc00 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtlock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtlock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field watchdog lock a write of the value 0x1acc.e551 unlocks the watchdog registers for write access. a write of any other value reapplies the lock, preventing any register updates. a read of this register returns the following values: description value locked 0x0000.0001 unlocked 0x0000.0000 0x0000.0000 r/w wdtlock 31:0 march 20, 2011 518 texas instruments-advance information watchdog timers register 9: watchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 4 (wdtperiphid4) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfd0 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 wdt peripheral id register [7:0] 0x00 ro pid4 7:0 519 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 10: watchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 5 (wdtperiphid5) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfd4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 wdt peripheral id register [15:8] 0x00 ro pid5 7:0 march 20, 2011 520 texas instruments-advance information watchdog timers register 11: watchdog peripheral identification 6 (wdtperiphid6), offset 0xfd8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 6 (wdtperiphid6) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfd8 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 wdt peripheral id register [23:16] 0x00 ro pid6 7:0 521 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: watchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 7 (wdtperiphid7) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfdc type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 wdt peripheral id register [31:24] 0x00 ro pid7 7:0 march 20, 2011 522 texas instruments-advance information watchdog timers register 13: watchdog peripheral identification 0 (wdtperiphid0), offset 0xfe0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 0 (wdtperiphid0) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfe0 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog peripheral id register [7:0] 0x05 ro pid0 7:0 523 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 14: watchdog peripheral identification 1 (wdtperiphid1), offset 0xfe4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 1 (wdtperiphid1) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfe4 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog peripheral id register [15:8] 0x18 ro pid1 7:0 march 20, 2011 524 texas instruments-advance information watchdog timers register 15: watchdog peripheral identification 2 (wdtperiphid2), offset 0xfe8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 2 (wdtperiphid2) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfe8 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog peripheral id register [23:16] 0x18 ro pid2 7:0 525 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 16: watchdog peripheral identification 3 (wdtperiphid3), offset 0xfec the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 3 (wdtperiphid3) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfec type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog peripheral id register [31:24] 0x01 ro pid3 7:0 march 20, 2011 526 texas instruments-advance information watchdog timers register 17: watchdog primecell identification 0 (wdtpcellid0), offset 0xff0 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. watchdog primecell identification 0 (wdtpcellid0) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog primecell id register [7:0] 0x0d ro cid0 7:0 527 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 18: watchdog primecell identification 1 (wdtpcellid1), offset 0xff4 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. watchdog primecell identification 1 (wdtpcellid1) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog primecell id register [15:8] 0xf0 ro cid1 7:0 march 20, 2011 528 texas instruments-advance information watchdog timers register 19: watchdog primecell identification 2 (wdtpcellid2), offset 0xff8 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. watchdog primecell identification 2 (wdtpcellid2) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xff8 type ro, reset 0x0000.0006 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog primecell id register [23:16] 0x06 ro cid2 7:0 529 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 20: watchdog primecell identification 3 (wdtpcellid3 ), offset 0xffc the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. watchdog primecell identification 3 (wdtpcellid3) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog primecell id register [31:24] 0xb1 ro cid3 7:0 march 20, 2011 530 texas instruments-advance information watchdog timers 12 analog-to-digital converter (adc) an analog-to-digital converter (adc) is a peripheral that converts a continuous analog voltage to a discrete digital number. two identical converter modules are included, which share 16 input channels. the stellaris ? adc module features 10-bit conversion resolution and supports 16 input channels, plus an internal temperature sensor. each adc module contains four programmable sequencers allowing the sampling of multiple analog input sources without controller intervention. each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. a digital comparator function is included which allows the conversion value to be diverted to a digital comparator module. each adc module provides eight digital comparators. each digital comparator evaluates the adc conversion value against its two user-defined values to determine the operational range of the signal. the trigger source for adc0 and adc1 may be independent or the two adc modules may operate from the same trigger source and operate on the same or different inputs. a phase shifter can delay the start of sampling by a specified phase angle. when using both adc modules, it is possible to configure the converters to start the conversions coincidentally or within a relative phase from each other, see sample phase control on page 537. the stellaris lm3s1p51 microcontroller provides two adc modules with each having the following features: 16 shared analog input channels single-ended and differential-input configurations on-chip internal temperature sensor maximum sample rate of one million samples/second optional phase shift in sample time programmable from 22.5o to 337.5o four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result fifos flexible trigger control C controller (software) C timers C analog comparators C pwm C gpio hardware averaging of up to 64 samples for improved accuracy digital comparison unit providing eight digital comparators converter uses an internal 3-v reference or an external reference power and ground for the analog circuitry is separate from the digital power and ground 531 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller efficient transfers using micro direct memory access controller (dma) C dedicated channel for each sample sequencer C adc module uses burst requests for dma 12.1 block diagram the stellaris microcontroller contains two identical analog-to-digital converter modules. these two modules, adc0 and adc1, share the same 16 analog input channels. each adc module operates independently and can therefore execute different sample sequences, sample any of the analog input channels at any time, and generate different interrupts and triggers. figure 12-1 on page 532 shows how the two modules are connected to analog inputs and the system bus. figure 12-1. implementation of two adc blocks figure 12-2 on page 533 provides details on the internal configuration of the adc controls and data registers. march 20, 2011 532 texas instruments-advance information analog-to-digital converter (adc) , q s x w & k d q q h o v 7 u l j j h u v , q w h u u x s w v 7 u l j j h u v $ ' & $ ' & , q w h u u x s w v 7 u l j j h u v figure 12-2. adc module block diagram 12.2 signal description table 12-1 on page 533 and table 12-2 on page 534 list the external signals of the adc module and describe the function of each. the adc signals are analog functions for some gpio signals. the column in the table below titled "pin mux/pin assignment" lists the gpio pin placement for the adc signals. the ainx and vrefa analog signals are not 5-v tolerant and go through an isolation circuit before reaching their circuitry. these signals are configured by clearing the corresponding den bit in the gpio digital enable (gpioden) register and setting the corresponding amsel bit in the gpio analog mode select (gpioamsel) register. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. table 12-1. signals for adc (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 0. analog i pe7 1 ain0 analog-to-digital converter input 1. analog i pe6 2 ain1 analog-to-digital converter input 2. analog i pe5 5 ain2 analog-to-digital converter input 3. analog i pe4 6 ain3 analog-to-digital converter input 4. analog i pd7 100 ain4 analog-to-digital converter input 5. analog i pd6 99 ain5 analog-to-digital converter input 6. analog i pd5 98 ain6 analog-to-digital converter input 7. analog i pd4 97 ain7 analog-to-digital converter input 8. analog i pe3 96 ain8 analog-to-digital converter input 9. analog i pe2 95 ain9 533 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller $ q d o r j , q s x w v ainx ) t rigger events ss0 interrupt ss1 interrupt ss2 interrupt ss3 interrupt adcisc adcris adcim interrupt control adcdcisc ss0 ss1 ss2 ss3 comparator pio (pb4) t imer pm comparator pio (pb4) t imer pm comparator pio (pb4) t imer pm comparator pio (pb4) t imer pm adcemu adcpssi control/status adcust a t adcost a t adcactss adcsspri digital comparator adcssopn adcssdcn adcdcctln adcdccmpn analog-to-digital converter hardare a verager adcsac adcssfst a t0 adcssctl0 adcssmu0 sample sequencer 0 adcssfst a t1 adcssctl1 adcssmu1 sample sequencer 1 adcssfst a t2 adcssctl2 adcssmu2 sample sequencer 2 adcssfst a t3 adcssctl3 adcssmu3 sample sequencer 3 pm t rigger dc interrupts internal v oltage ref external v oltage ref ( vrefa ) adcctl adcspc fifo block adcssfifo0 adcssfifo1 adcssfifo2 adcssfifo3 adcdcric table 12-1. signals for adc (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 10. analog i pb4 92 ain10 analog-to-digital converter input 11. analog i pb5 91 ain11 analog-to-digital converter input 12. analog i pd3 13 ain12 analog-to-digital converter input 13. analog i pd2 12 ain13 analog-to-digital converter input 14. analog i pd1 11 ain14 analog-to-digital converter input 15. analog i pd0 10 ain15 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 1023. the vrefa input is limited to the range specified in table 23-29 on page 981. analog i pb6 90 vrefa a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 12-2. signals for adc (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 0. analog i pe7 b1 ain0 analog-to-digital converter input 1. analog i pe6 a1 ain1 analog-to-digital converter input 2. analog i pe5 b3 ain2 analog-to-digital converter input 3. analog i pe4 b2 ain3 analog-to-digital converter input 4. analog i pd7 a2 ain4 analog-to-digital converter input 5. analog i pd6 a3 ain5 analog-to-digital converter input 6. analog i pd5 c6 ain6 analog-to-digital converter input 7. analog i pd4 b5 ain7 analog-to-digital converter input 8. analog i pe3 b4 ain8 analog-to-digital converter input 9. analog i pe2 a4 ain9 analog-to-digital converter input 10. analog i pb4 a6 ain10 analog-to-digital converter input 11. analog i pb5 b7 ain11 analog-to-digital converter input 12. analog i pd3 h1 ain12 analog-to-digital converter input 13. analog i pd2 h2 ain13 analog-to-digital converter input 14. analog i pd1 g2 ain14 analog-to-digital converter input 15. analog i pd0 g1 ain15 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 1023. the vrefa input is limited to the range specified in table 23-29 on page 981. analog i pb6 a7 vrefa a. the ttl designation indicates the pin has ttl-compatible voltage levels. march 20, 2011 534 texas instruments-advance information analog-to-digital converter (adc) 12.3 functional description the stellaris adc collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approaches found on many adc modules. each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the adc to collect data from multiple input sources without having to be re-configured or serviced by the processor. the programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. in addition, the dma can be used to more efficiently move data from the sample sequencers without cpu intervention. 12.3.1 sample sequencers the sampling control and data capture is handled by the sample sequencers. all of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the fifo. table 12-3 on page 535 shows the maximum number of samples that each sequencer can capture and its corresponding fifo depth. each sample that is captured is stored in the fifo. in this implementation, each fifo entry is a 32-bit word, with the lower 10 bits containing the conversion result. table 12-3. samples and fifo depth of sequencers depth of fifo number of samples sequencer 1 1 ss3 4 4 ss2 4 4 ss1 8 8 ss0 for a given sample sequence, each sample is defined by bit fields in the adc sample sequence input multiplexer select (adcssmuxn) and adc sample sequence control (adcssctln) registers, where "n" corresponds to the sequence number. the adcssmuxn fields select the input pin, while the adcssctln fields contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. sample sequencers are enabled by setting the respective asenn bit in the adc active sample sequencer (adcactss) register and should be configured before being enabled. sampling is then initiated by setting the ssn bit in the adc processor sample sequence initiate (adcpssi) register. in addition, sample sequences may be initiated on multiple adc modules simultaneously using the gsync and syncwait bits in the adcpssi register during the configuration of each adc module. for more information on using these bits, refer to page 573. when configuring a sample sequence, multiple uses of the same input pin within the same sequence are allowed. in the adcssctln register, the ien bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. also, the end bit can be set at any point within a sample sequence. for example, if sequencer 0 is used, the end bit can be set in the nibble associated with the fifth sample, allowing sequencer 0 to complete execution of the sample sequence after the fifth sample. after a sample sequence completes execution, the result data can be retrieved from the adc sample sequence result fifo (adcssfifon) registers. the fifos are simple circular buffers that read a single address to "pop" result data. for software debug purposes, the positions of the fifo head and tail pointers are visible in the adc sample sequence fifo status (adcssfstatn) registers along with full and empty status flags. if a write is attempted when the fifo is full, the write does not occur and an overflow condition is indicated. overflow and underflow conditions are monitored using the adcostat and adcustat registers. 535 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 12.3.2 module control outside of the sample sequencers, the remainder of the control logic is responsible for tasks such as: interrupt generation dma operation sequence prioritization trigger configuration comparator configuration external voltage reference sample phase control most of the adc control logic runs at the adc clock rate of 14-18 mhz. the internal adc divider is configured for 16-mhz operation automatically by hardware when the system xtal is selected. 12.3.2.1 interrupts the register configurations of the sample sequencers and digital comparators dictate which events generate raw interrupts, but do not have control over whether the interrupt is actually sent to the interrupt controller. the adc module's interrupt signals are controlled by the state of the mask bits in the adc interrupt mask (adcim) register. interrupt status can be viewed at two locations: the adc raw interrupt status (adcris) register, which shows the raw status of the various interrupt signals; and the adc interrupt status and clear (adcisc) register, which shows active interrupts that are enabled by the adcim register. sequencer interrupts are cleared by writing a 1 to the corresponding in bit in adcisc . digital comparator interrupts are cleared by writing a 1 to the adc digital comparator interrupt status and clear (adcdcisc) register. 12.3.2.2 dma operation dma may be used to increase efficiency by allowing each sample sequencer to operate independently and transfer data without processor intervention or reconfiguration. the adc module provides a request signal from each sample sequencer to the associated dedicated channel of the dma controller. the adc does not support single transfer requests. a burst transfer request is asserted when the interrupt bit for the sample sequence is set ( ie bit in the adcssctln register is set). the arbitration size of the dma transfer must be a power of 2, and the associated ie bits in the addssctln register must be set. for example, if the dma channel of ss0 has an arbitration size of four, the ie3 bit (4th sample) and the ie7 bit (8th sample) must be set. thus the dma request occurs every time 4 samples have been acquired. no other special steps are needed to enable the adc module for dma operation. refer to the micro direct memory access (dma) on page 346 for more details about programming the dma controller. 12.3.2.3 prioritization when sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the adc sample sequencer priority (adcsspri) register. valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. multiple active sample march 20, 2011 536 texas instruments-advance information analog-to-digital converter (adc) sequencer units with the same priority do not provide consistent results, so software must ensure that all active sample sequencer units have a unique priority value. 12.3.2.4 sampling events sample triggering for each sample sequencer is defined in the adc event multiplexer select (adcemux) register. trigger sources include processor (default), analog comparators, an external signal on gpio pb4 , a gp timer, a pwm generator, and continuous sampling. the processor triggers sampling by setting the ssx bits in the adc processor sample sequence initiate (adcpssi) register. care must be taken when using the continuous sampling trigger. if a sequencer's priority is too high, it is possible to starve other lower priority sequencers. generally, a sample sequencer using continuous sampling should be set to the lowest priority. continuous sampling can be used with a digital comparator to cause an interrupt when a particular voltage is seen on an input. 12.3.2.5 sample phase control the trigger source for adc0 and adc1 may be independent or the two adc modules may operate from the same trigger source and operate on the same or different inputs. if the converters are running at the same sample rate, they may be configured to start the conversions coincidentally or with one of 15 different discrete phases relative to each other. the sample time can be delayed from the standard sampling time in 22.5 increments up to 337.5o using the adc sample phase control (adcspc) register. figure 12-3 on page 537 shows an example of various phase relationships at a 1 msps rate. figure 12-3. adc sample phases this feature can be used to double the sampling rate of an input. both adc module 0 and adc module 1 can be programmed to sample the same input. adc module 0 could sample at the standard position (the phase field in the adcspc register is 0x0). adc module 1 can be configured to sample at 180 ( phase = 0x8). the two modules can be be synchronized using the gsync and syncwait bits in the adc processor sample sequence initiate (adcpssi) register. software could then combine the results from the two modules to create a sample rate of two million samples/second at 16 mhz as shown in figure 12-4 on page 538. 537 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller $ ' & 6 d p s o h & o r f n 3 + $ 6 ( [ ? 3 + $ 6 ( [ ? 3 + $ 6 ( [ ( ? 3 + $ 6 ( [ ) ? figure 12-4. doubling the adc sample rate using the adcspc register, adc0 and adc1 may provide a number of interesting applications: coincident sampling of different signals. the sample sequence steps run coincidently in both converters. C adc module 0, adcspc = 0x0, sampling ain0 C adc module 1, adcspc = 0x0, sampling ain1 skewed sampling of the same signal. the sample sequence steps are 1/2 of an adc clock (500 s for a 1ms/s adc) out of phase with each other. this configuration doubles the conversion bandwidth of a single input when software combines the results as shown in figure 12-5 on page 538. C adc module 0, adcspc = 0x0, sampling ain0 C adc module 1, adcspc = 0x8, sampling ain0 figure 12-5. skewed sampling 12.3.3 hardware sample averaging circuit higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer fifo. throughput is decreased proportionally to the march 20, 2011 538 texas instruments-advance information analog-to-digital converter (adc) 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 $ ' & $ ' & 6 $ ' & 6 d p s o h & o r f n * 6 < 1 & $ ' & 3 + $ 6 ( [ ? $ ' & 3 + $ 6 ( [ ? number of samples in the averaging calculation. for example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. by default the averaging circuit is off, and all data from the converter passes through to the sequencer fifo. the averaging hardware is controlled by the adc sample averaging control (adcsac) register (see page 575). a single averaging circuit has been implemented, thus all input channels receive the same amount of averaging whether they are single-ended or differential. figure 12-6 on page 539 shows an example in which the adcsac register is set to 0x2 for 4x hardware oversampling and the ie1 bit is set for the sample sequence, resulting in an interrupt after the second averaged value is stored in the fifo. figure 12-6. sample averaging example 12.3.4 analog-to-digital converter the analog-to-digital converter (adc) module uses a successive approximation register (sar) architecture to deliver a 10-bit, low-power, high-precision conversion value. the successive-approximation algorithm uses a current mode d/a converter to achieve lower settling time, resulting in higher conversion speeds for the a/d converter. in addition, built-in sample-and-hold circuitry with offset-calibration circuitry improves conversion accuracy. the adc must be run from the pll or a 14- to 18-mhz clock source. the adc operates from both the 3.3-v analog and 1.2-v digital power supplies. the adc clock can be configured to reduce power consumption when adc conversions are not required (see system control on page 195). the analog inputs are connected to the adc through custom pads and specially balanced input paths to minimize the distortion on the inputs. detailed information on the adc power supplies and analog inputs can be found in analog-to-digital converter (adc) on page 980. 539 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller $ % & ' $ % & ' , 1 7 12.3.4.1 internal voltage reference the band-gap circuitry generates an internal 3.0 v reference that can be used by the adc to produce a conversion value from the selected analog input. the range of this conversion value is from 0x000 to 0x3ff. this configuration results in a resolution of approximately 2.9 mv per adc code. while the analog input pads can handle voltages beyond this range, the adc conversions saturate in under-voltage and over-voltage cases. figure 12-7 on page 540 shows the adc conversion function of the analog inputs. figure 12-7. internal voltage conversion result 12.3.4.2 external voltage reference the adc can use an external voltage reference to produce the conversion value from the selected analog input by setting the vref bit in the adc control (adcctl) register. the vref bit specifies whether to use the internal or external reference. while the range of the conversion value remains the same (0x000 to 0x3ff), the analog voltage associated with the 0x3ff value corresponds to the value of the voltage when using the 3.0-v setting and three times the voltage when using the 1.0-v setting, resulting in a smaller voltage resolution per adc code. ground is always used as the reference level for the minimum conversion value. analog input voltages above the external voltage reference saturate to 0x3ff while those below 0.0 v continue to saturate at 0x000. the v refa specification defines the useful range for the external voltage reference, see table 23-29 on page 981. care must be taken to supply a reference voltage of acceptable quality. figure 12-8 on page 541 shows the adc conversion function of the analog inputs when using an external voltage reference. the external voltage reference can be more accurate than the internal reference by using a high-precision source or trimming the source. march 20, 2011 540 texas instruments-advance information analog-to-digital converter (adc) [ ) ) 9 , 1 [ ) ) [ ) ) [ ) ) 9 9 9 9 9 , q s x w 6 d w x u d w l r q figure 12-8. external voltage conversion result 12.3.5 differential sampling in addition to traditional single-ended sampling, the adc module supports differential sampling of two analog input channels. to enable differential sampling, software must set the dn bit in the adcssctl0n register in a step's configuration nibble. when a sequence step is configured for differential sampling, the input pair to sample must be configured in the adcssmuxn register. differential pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see table 12-4 on page 541). the adc does not support other differential pairings such as analog input 0 with analog input 3. table 12-4. differential sampling pairs analog inputs differential pair 0 and 1 0 2 and 3 1 4 and 5 2 6 and 7 3 8 and 9 4 10 and 11 5 12 and 13 6 14 and 15 7 the voltage sampled in differential mode is the difference between the odd and even channels: ?v (differential voltage) = v in_even (even channel) C v in_odd (odd channel), therefore: if ?v = 0, then the conversion result = 0x1ff 541 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller [ ) ) 9 , 1 [ ) ) [ ) ) [ ) ) 9 9 ' ' , q s x w 6 d w x u d w l r q 9 5 ( ) $ 9 5 ( ) $ if ?v > 0, then the conversion result > 0x1ff (range is 0x1ffC0x3ff) if ?v < 0, then the conversion result < 0x1ff (range is 0C0x1ff) the differential pairs assign polarities to the analog inputs: the even-numbered input is always positive, and the odd-numbered input is always negative. in order for a valid conversion result to appear, the negative input must be in the range of 1.5 v of the positive input. if an analog input is greater than 3 v or less than 0 v (the valid range for analog inputs), the input voltage is clipped, meaning it appears as either 3 v or 0 v , respectively, to the adc. figure 12-9 on page 542 shows an example of the negative input centered at 1.5 v. in this configuration, the differential range spans from -1.5 v to 1.5 v. figure 12-10 on page 543 shows an example where the negative input is centered at 0.75 v, meaning inputs on the positive input saturate past a differential voltage of -0.75 v because the input voltage is less than 0 v. figure 12-11 on page 543 shows an example of the negative input centered at 2.25 v, where inputs on the positive channel saturate past a differential voltage of 0.75 v since the input voltage would be greater than 3 v. figure 12-9. differential sampling range, v in_odd = 1.5 v march 20, 2011 542 texas instruments-advance information analog-to-digital converter (adc) 9 9 9 9 9 9 9 , 1 b ( 9 ( 1 d dd figure 12-10. differential sampling range, v in_odd = 0.75 v figure 12-11. differential sampling range, v in_odd = 2.25 v 543 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller [ ) ) [ ) ) [ ) ) 9 9 9 9 , 1 b ( 9 ( 1 d $ ' & & r q y h u v l r q 5 h v x o w [ ) ) [ ) ) [ ) ) 9 9 9 9 , 1 b ( 9 ( 1 d 12.3.6 internal temperature sensor the temperature sensor serves two primary purposes: 1) to notify the system that internal temperature is too high or low for reliable operation and 2) to provide temperature measurements for calibration of the hibernate module rtc trim value. the temperature sensor does not have a separate enable, because it also contains the bandgap reference and must always be enabled. the reference is supplied to other analog modules; not just the adc. in addition, the temperature sensor has a second power-down input in the 3.3 v domain which provides control by the hibernation module. the internal temperature sensor provides an analog temperature reading as well as a reference voltage. this reference voltage, senso , is given by the following equation: senso = 2.7 - ((t + 55) / 75) this relation is shown in figure 12-12 on page 544. figure 12-12. internal temperature sensor characteristic the temperature sensor reading can be sampled in a sample sequence by setting the tsn bit in the adcssctln register. the temperature reading from the temperature sensor can also be given as a function of the adc value. the following formula calculates temperature (in ) based on the adc reading: temperature = 147.5 - ((225 adc) / 1023) 12.3.7 digital comparator unit an adc is commonly used to sample an external signal and to monitor its value to ensure that it remains in a given range. to automate this monitoring procedure and reduce the amount of processor march 20, 2011 544 texas instruments-advance information analog-to-digital converter (adc) 6 h q v r u 6 h q v r u 9 7 9 9 9 7 h p s ? & ? & ? & overhead that is required, each module provides eight digital comparators. conversions from the adc that are sent to the digital comparators are compared against the user programmable limits in the adc digital comparator range (adcdccmpn) registers. if the observed signal moves out of the acceptable range, a processor interrupt can be generated and/or a trigger can be sent to the pwm module. the digital comparators four operational modes (once, always, hysteresis once, hysteresis always) can be applied to three separate regions (low band, mid band, high band) as defined by the user. 12.3.7.1 output functions adc conversions can either be stored in the adc sample sequence fifos or compared using the digital comparator resources as defined by the sndcop bits in the adc sample sequence n operation (adcssopn) register. these selected adc conversions are used by their respective digital comparator to monitor the external signal. each comparator has two possible output functions: processor interrupts and triggers. each function has its own state machine to track the monitored signal. even though the interrupt and trigger functions can be enabled individually or both at the same time, the same conversion data is used by each function to determine if the right conditions have been met to assert the associated output. interrupts the digital comparator interrupt function is enabled by setting the cie bit in the adc digital comparator control (adcdcctln) register. this bit enables the interrupt function state machine to start monitoring the incoming adc conversions. when the appropriate set of conditions is met, and the dconssx bit is set in the adcim register, an interrupt is sent to the interrupt controller. triggers the digital comparator trigger function is enabled by setting the cte bit in the adcdcctln register. this bit enables the trigger function state machine to start monitoring the incoming adc conversions. when the appropriate set of conditions is met, the corresponding digital comparator trigger to the pwm module is asserted 12.3.7.2 operational modes four operational modes are provided to support a broad range of applications and multiple possible signaling requirements: always, once, hysteresis always, and hysteresis once. the operational mode is selected using the cim or ctm field in the adcdcctln register. always mode in the always operational mode, the associated interrupt or trigger is asserted whenever the adc conversion value meets its comparison criteria. the result is a string of assertions on the interrupt or trigger while the conversions are within the appropriate range. once mode in the once operational mode, the associated interrupt or trigger is asserted whenever the adc conversion value meets its comparison criteria, and the previous adc conversion value did not. the result is a single assertion of the interrupt or trigger when the conversions are within the appropriate range. 545 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller hysteresis-always mode the hysteresis-always operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. in the hysteresis-always mode, the associated interrupt or trigger is asserted in the following cases: 1) the adc conversion value meets its comparison criteria or 2) a previous adc conversion value has met the comparison criteria, and the hysteresis condition has not been cleared by entering the opposite region. the result is a string of assertions on the interrupt or trigger that continue until the opposite region is entered. hysteresis-once mode the hysteresis-once operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. in the hysteresis-once mode, the associated interrupt or trigger is asserted only when the adc conversion value meets its comparison criteria, the hysteresis condition is clear, and the previous adc conversion did not meet the comparison criteria. the result is a single assertion on the interrupt or trigger. 12.3.7.3 function ranges the two comparison values, comp0 and comp1 , in the adc digital comparator range (adcdccmpn) register effectively break the conversion area into three distinct regions. these regions are referred to as the low-band (less than or equal to comp0 ), mid-band (greater than comp0 but less than or equal to comp1 ), and high-band (greater than comp1 ) regions. comp0 and comp1 may be programmed to the same value, effectively creating two regions, but comp1 must always be greater than or equal to the value of comp0 . a comp1 value that is less than comp0 generates unpredictable results. low-band operation to operate in the low-band region, either the cic field or the ctc field in the adcdcctln register must be programmed to 0x0. this setting causes interrupts or triggers to be generated in the low-band region as defined by the programmed operational mode. an example of the state of the interrupt/trigger signal in the low-band region for each of the operational modes is shown in figure 12-13 on page 547. note that a "0" in a column following the operational mode name (always, once, hysteresis always, and hysteresis once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. march 20, 2011 546 texas instruments-advance information analog-to-digital converter (adc) figure 12-13. low-band operation (cic=0x0 and/or ctc=0x0) mid-band operation to operate in the mid-band region, either the cic field or the ctc field in the adcdcctln register must be programmed to 0x1. this setting causes interrupts or triggers to be generated in the mid-band region according the operation mode. only the always and once operational modes are available in the mid-band region. an example of the state of the interrupt/trigger signal in the mid-band region for each of the allowed operational modes is shown in figure 12-14 on page 548. note that a "0" in a column following the operational mode name (always or once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. 547 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller $ o z d \ v 2 q f h + \ v w h u h v l v $ o z d \ v + \ v w h u h v l v 2 q f h & 2 0 3 & 2 0 3 figure 12-14. mid-band operation (cic=0x1 and/or ctc=0x1) high-band operation to operate in the high-band region, either the cic field or the ctc field in the adcdcctln register must be programmed to 0x3. this setting causes interrupts or triggers to be generated in the high-band region according the operation mode. an example of the state of the interrupt/trigger signal in the high-band region for each of the allowed operational modes is shown in figure 12-15 on page 549. note that a "0" in a column following the operational mode name (always, once, hysteresis always, and hysteresis once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. march 20, 2011 548 texas instruments-advance information analog-to-digital converter (adc) $ o z d \ v 2 q f h + \ v w h u h v l v $ o z d \ v + \ v w h u h v l v 2 q f h & 2 0 3 & 2 0 3 figure 12-15. high-band operation (cic=0x3 and/or ctc=0x3) 12.4 initialization and configuration in order for the adc module to be used, the pll must be enabled and programmed to a supported crystal frequency in the rcc register (see page 211). using unsupported frequencies can cause faulty operation in the adc module. 12.4.1 module initialization initialization of the adc module is a simple process with very few steps: enabling the clock to the adc, disabling the analog isolation circuit associated with all inputs that are to be used, and reconfiguring the sample sequencer priorities (if needed). the initialization sequence for the adc is as follows: 1. enable the adc clock by using the rcgc0 register (see page 252). 2. enable the clock to the appropriate gpio modules via the rcgc2 register (see page 269). to find out which gpio ports to enable, refer to signal description on page 533. 3. set the gpio afsel bits for the adc input pins (see page 428). to determine which gpios to configure, see table 21-4 on page 917. 4. configure the ainx and vrefa signals to be analog inputs by clearing the corresponding den bit in the gpio digital enable (gpioden) register (see page 439). 5. disable the analog isolation circuit for all adc input pins that are to be used by writing a 1 to the appropriate bits of the gpioamsel register (see page 444) in the associated gpio block. 549 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller $ o z d \ v 2 q f h + \ v w h u h v l v $ o z d \ v + \ v w h u h v l v 2 q f h & 2 0 3 & 2 0 3 6. if required by the application, reconfigure the sample sequencer priorities in the adcsspri register. the default configuration has sample sequencer 0 with the highest priority and sample sequencer 3 as the lowest priority. 12.4.2 sample sequencer configuration configuration of the sample sequencers is slightly more complex than the module initialization because each sample sequencer is completely programmable. the configuration for each sample sequencer should be as follows: 1. ensure that the sample sequencer is disabled by clearing the corresponding asenn bit in the adcactss register. programming of the sample sequencers is allowed without having them enabled. disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. configure the trigger event for the sample sequencer in the adcemux register. 3. for each sample in the sample sequence, configure the corresponding input source in the adcssmuxn register. 4. for each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the adcssctln register. when programming the last nibble, ensure that the end bit is set. failure to set the end bit causes unpredictable behavior. 5. if interrupts are to be used, set the corresponding mask bit in the adcim register. 6. enable the sample sequencer logic by setting the corresponding asenn bit in the adcactss register. 12.5 register map table 12-5 on page 550 lists the adc registers. the offset listed is a hexadecimal increment to the registers address, relative to that adc module's base address of: adc0: 0x4003.8000 adc1: 0x4003.9000 note that the adc module clock must be enabled before the registers can be programmed (see page 252). there must be a delay of 3 system clocks after the adc module clock is enabled before any adc module registers are accessed. table 12-5. adc register map see page description reset type name offset 553 adc active sample sequencer 0x0000.0000 r/w adcactss 0x000 554 adc raw interrupt status 0x0000.0000 ro adcris 0x004 556 adc interrupt mask 0x0000.0000 r/w adcim 0x008 558 adc interrupt status and clear 0x0000.0000 r/w1c adcisc 0x00c 561 adc overflow status 0x0000.0000 r/w1c adcostat 0x010 563 adc event multiplexer select 0x0000.0000 r/w adcemux 0x014 march 20, 2011 550 texas instruments-advance information analog-to-digital converter (adc) table 12-5. adc register map (continued) see page description reset type name offset 568 adc underflow status 0x0000.0000 r/w1c adcustat 0x018 569 adc sample sequencer priority 0x0000.3210 r/w adcsspri 0x020 571 adc sample phase control 0x0000.0000 r/w adcspc 0x024 573 adc processor sample sequence initiate - r/w adcpssi 0x028 575 adc sample averaging control 0x0000.0000 r/w adcsac 0x030 576 adc digital comparator interrupt status and clear 0x0000.0000 r/w1c adcdcisc 0x034 578 adc control 0x0000.0000 r/w adcctl 0x038 579 adc sample sequence input multiplexer select 0 0x0000.0000 r/w adcssmux0 0x040 581 adc sample sequence control 0 0x0000.0000 r/w adcssctl0 0x044 584 adc sample sequence result fifo 0 - ro adcssfifo0 0x048 585 adc sample sequence fifo 0 status 0x0000.0100 ro adcssfstat0 0x04c 587 adc sample sequence 0 operation 0x0000.0000 r/w adcssop0 0x050 589 adc sample sequence 0 digital comparator select 0x0000.0000 r/w adcssdc0 0x054 591 adc sample sequence input multiplexer select 1 0x0000.0000 r/w adcssmux1 0x060 592 adc sample sequence control 1 0x0000.0000 r/w adcssctl1 0x064 584 adc sample sequence result fifo 1 - ro adcssfifo1 0x068 585 adc sample sequence fifo 1 status 0x0000.0100 ro adcssfstat1 0x06c 594 adc sample sequence 1 operation 0x0000.0000 r/w adcssop1 0x070 595 adc sample sequence 1 digital comparator select 0x0000.0000 r/w adcssdc1 0x074 591 adc sample sequence input multiplexer select 2 0x0000.0000 r/w adcssmux2 0x080 592 adc sample sequence control 2 0x0000.0000 r/w adcssctl2 0x084 584 adc sample sequence result fifo 2 - ro adcssfifo2 0x088 585 adc sample sequence fifo 2 status 0x0000.0100 ro adcssfstat2 0x08c 594 adc sample sequence 2 operation 0x0000.0000 r/w adcssop2 0x090 595 adc sample sequence 2 digital comparator select 0x0000.0000 r/w adcssdc2 0x094 597 adc sample sequence input multiplexer select 3 0x0000.0000 r/w adcssmux3 0x0a0 598 adc sample sequence control 3 0x0000.0002 r/w adcssctl3 0x0a4 584 adc sample sequence result fifo 3 - ro adcssfifo3 0x0a8 585 adc sample sequence fifo 3 status 0x0000.0100 ro adcssfstat3 0x0ac 599 adc sample sequence 3 operation 0x0000.0000 r/w adcssop3 0x0b0 600 adc sample sequence 3 digital comparator select 0x0000.0000 r/w adcssdc3 0x0b4 601 adc digital comparator reset initial conditions 0x0000.0000 r/w adcdcric 0xd00 551 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 12-5. adc register map (continued) see page description reset type name offset 606 adc digital comparator control 0 0x0000.0000 r/w adcdcctl0 0xe00 606 adc digital comparator control 1 0x0000.0000 r/w adcdcctl1 0xe04 606 adc digital comparator control 2 0x0000.0000 r/w adcdcctl2 0xe08 606 adc digital comparator control 3 0x0000.0000 r/w adcdcctl3 0xe0c 606 adc digital comparator control 4 0x0000.0000 r/w adcdcctl4 0xe10 606 adc digital comparator control 5 0x0000.0000 r/w adcdcctl5 0xe14 606 adc digital comparator control 6 0x0000.0000 r/w adcdcctl6 0xe18 606 adc digital comparator control 7 0x0000.0000 r/w adcdcctl7 0xe1c 609 adc digital comparator range 0 0x0000.0000 r/w adcdccmp0 0xe40 609 adc digital comparator range 1 0x0000.0000 r/w adcdccmp1 0xe44 609 adc digital comparator range 2 0x0000.0000 r/w adcdccmp2 0xe48 609 adc digital comparator range 3 0x0000.0000 r/w adcdccmp3 0xe4c 609 adc digital comparator range 4 0x0000.0000 r/w adcdccmp4 0xe50 609 adc digital comparator range 5 0x0000.0000 r/w adcdccmp5 0xe54 609 adc digital comparator range 6 0x0000.0000 r/w adcdccmp6 0xe58 609 adc digital comparator range 7 0x0000.0000 r/w adcdccmp7 0xe5c 12.6 register descriptions the remainder of this section lists and describes the adc registers, in numerical order by address offset. march 20, 2011 552 texas instruments-advance information analog-to-digital converter (adc) register 1: adc active sample sequencer (adcactss), offset 0x000 this register controls the activation of the sample sequencers. each sample sequencer can be enabled or disabled independently. adc active sample sequencer (adcactss) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 asen0 asen1 asen2 asen3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 adc ss3 enable description value sample sequencer 3 is enabled. 1 sample sequencer 3 is disabled. 0 0 r/w asen3 3 adc ss2 enable description value sample sequencer 2 is enabled. 1 sample sequencer 2 is disabled. 0 0 r/w asen2 2 adc ss1 enable description value sample sequencer 1 is enabled. 1 sample sequencer 1 is disabled. 0 0 r/w asen1 1 adc ss0 enable description value sample sequencer 0 is enabled. 1 sample sequencer 0 is disabled. 0 0 r/w asen0 0 553 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: adc raw interrupt status (adcris), offset 0x004 this register shows the status of the raw interrupt signal of each sample sequencer. these bits may be polled by software to look for interrupt conditions without sending the interrupts to the interrupt controller. adc raw interrupt status (adcris) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 inrdc reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 inr0 inr1 inr2 inr3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 digital comparator raw interrupt status description value at least one bit in the adcdcisc register is set, meaning that a digital comparator interrupt has occurred. 1 all bits in the adcdcisc register are clear. 0 0 ro inrdc 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:4 ss3 raw interrupt status description value a sample has completed conversion and the respective adcssctl3 ien bit is set, enabling a raw interrupt. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in3 bit in the adcisc register. 0 ro inr3 3 ss2 raw interrupt status description value a sample has completed conversion and the respective adcssctl2 ien bit is set, enabling a raw interrupt. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in2 bit in the adcisc register. 0 ro inr2 2 march 20, 2011 554 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field ss1 raw interrupt status description value a sample has completed conversion and the respective adcssctl1 ien bit is set, enabling a raw interrupt. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in1 bit in the adcisc register. 0 ro inr1 1 ss0 raw interrupt status description value a sample has completed conversion and the respective adcssctl0 ien bit is set, enabling a raw interrupt. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in0 bit in the adcisc register. 0 ro inr0 0 555 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 3: adc interrupt mask (adcim), offset 0x008 this register controls whether the sample sequencer and digital comparator raw interrupt signals are sent to the interrupt controller. each raw interrupt signal can be masked independently. only a single dconssn bit should be set at any given time. setting more than one of these bits results in the inrdc bit from the adcris register being masked, and no interrupt is generated on any of the sample sequencer interrupt lines. adc interrupt mask (adcim) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dconss0 dconss1 dconss2 dconss3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mask0 mask1 mask2 mask3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 digital comparator interrupt on ss3 description value the raw interrupt signal from the digital comparators ( inrdc bit in the adcris register) is sent to the interrupt controller on the ss3 interrupt line. 1 the status of the digital comparators does not affect the ss3 interrupt status. 0 0 r/w dconss3 19 digital comparator interrupt on ss2 description value the raw interrupt signal from the digital comparators ( inrdc bit in the adcris register) is sent to the interrupt controller on the ss2 interrupt line. 1 the status of the digital comparators does not affect the ss2 interrupt status. 0 0 r/w dconss2 18 digital comparator interrupt on ss1 description value the raw interrupt signal from the digital comparators ( inrdc bit in the adcris register) is sent to the interrupt controller on the ss1 interrupt line. 1 the status of the digital comparators does not affect the ss1 interrupt status. 0 0 r/w dconss1 17 march 20, 2011 556 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field digital comparator interrupt on ss0 description value the raw interrupt signal from the digital comparators ( inrdc bit in the adcris register) is sent to the interrupt controller on the ss0 interrupt line. 1 the status of the digital comparators does not affect the ss0 interrupt status. 0 0 r/w dconss0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:4 ss3 interrupt mask description value the raw interrupt signal from sample sequencer 3 ( adcris register inr3 bit) is sent to the interrupt controller. 1 the status of sample sequencer 3 does not affect the ss3 interrupt status. 0 0 r/w mask3 3 ss2 interrupt mask description value the raw interrupt signal from sample sequencer 2 ( adcris register inr2 bit) is sent to the interrupt controller. 1 the status of sample sequencer 2 does not affect the ss2 interrupt status. 0 0 r/w mask2 2 ss1 interrupt mask description value the raw interrupt signal from sample sequencer 1 ( adcris register inr1 bit) is sent to the interrupt controller. 1 the status of sample sequencer 1 does not affect the ss1 interrupt status. 0 0 r/w mask1 1 ss0 interrupt mask description value the raw interrupt signal from sample sequencer 0 ( adcris register inr0 bit) is sent to the interrupt controller. 1 the status of sample sequencer 0 does not affect the ss0 interrupt status. 0 0 r/w mask0 0 557 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: adc interrupt status and clear (adcisc), offset 0x00c this register provides the mechanism for clearing sample sequencer interrupt conditions and shows the status of interrupts generated by the sample sequencers and the digital comparators which have been sent to the interrupt controller. when read, each bit field is the logical and of the respective inr and mask bits. sample sequencer interrupts are cleared by writing a 1 to the corresponding bit position. digital comparator interrupts are cleared by writing a 1 to the appropriate bits in the adcdcisc register. if software is polling the adcris instead of generating interrupts, the sample sequence inrn bits are still cleared via the adcisc register, even if the inn bit is not set. adc interrupt status and clear (adcisc) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x00c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dcinss0 dcinss1 dcinss2 dcinss3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in0 in1 in2 in3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 digital comparator interrupt status on ss3 description value both the inrdc bit in the adcris register and the dconss3 bit in the adcim register are set, providing a level-base interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1 to it. clearing this bit also clears the inrdc bit in the adcris register. 0 ro dcinss3 19 digital comparator interrupt status on ss2 description value both the inrdc bit in the adcris register and the dconss2 bit in the adcim register are set, providing a level-base interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1 to it. clearing this bit also clears the inrdc bit in the adcris register. 0 ro dcinss2 18 march 20, 2011 558 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field digital comparator interrupt status on ss1 description value both the inrdc bit in the adcris register and the dconss1 bit in the adcim register are set, providing a level-base interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1 to it. clearing this bit also clears the inrdc bit in the adcris register. 0 ro dcinss1 17 digital comparator interrupt status on ss0 description value both the inrdc bit in the adcris register and the dconss0 bit in the adcim register are set, providing a level-base interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1 to it. clearing this bit also clears the inrdc bit in the adcris register. 0 ro dcinss0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:4 ss3 interrupt status and clear description value both the inr3 bit in the adcris register and the mask3 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inr3 bit in the adcris register. 0 r/w1c in3 3 ss2 interrupt status and clear description value both the inr2 bit in the adcris register and the mask2 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inr2 bit in the adcris register. 0 r/w1c in2 2 559 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ss1 interrupt status and clear description value both the inr1 bit in the adcris register and the mask1 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inr1 bit in the adcris register. 0 r/w1c in1 1 ss0 interrupt status and clear description value both the inr0 bit in the adcris register and the mask0 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inr0 bit in the adcris register. 0 r/w1c in0 0 march 20, 2011 560 texas instruments-advance information analog-to-digital converter (adc) register 5: adc overflow status (adcostat), offset 0x010 this register indicates overflow conditions in the sample sequencer fifos. once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. adc overflow status (adcostat) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x010 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ov0 ov1 ov2 ov3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 ss3 fifo overflow description value the fifo for sample sequencer 3 has hit an overflow condition, meaning that the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped. 1 the fifo has not overflowed. 0 this bit is cleared by writing a 1. 0 r/w1c ov3 3 ss2 fifo overflow description value the fifo for sample sequencer 2 has hit an overflow condition, meaning that the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped. 1 the fifo has not overflowed. 0 this bit is cleared by writing a 1. 0 r/w1c ov2 2 ss1 fifo overflow description value the fifo for sample sequencer 1 has hit an overflow condition, meaning that the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped. 1 the fifo has not overflowed. 0 this bit is cleared by writing a 1. 0 r/w1c ov1 1 561 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ss0 fifo overflow description value the fifo for sample sequencer 0 has hit an overflow condition, meaning that the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped. 1 the fifo has not overflowed. 0 this bit is cleared by writing a 1. 0 r/w1c ov0 0 march 20, 2011 562 texas instruments-advance information analog-to-digital converter (adc) register 6: adc event multiplexer select (adcemux), offset 0x014 the adcemux selects the event (trigger) that initiates sampling for each sample sequencer. each sample sequencer can be configured with a unique trigger source. adc event multiplexer select (adcemux) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 em0 em1 em2 em3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 563 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ss3 trigger select this field selects the trigger source for sample sequencer 3. the valid configurations for this field are: event value processor (default) the trigger is initiated by setting the ssn bit in the adcpssi register. 0x0 analog comparator 0 this trigger is configured by the analog comparator control 0 (acctl0) register (page 798). 0x1 analog comparator 1 this trigger is configured by the analog comparator control 1 (acctl1) register (page 798). 0x2 reserved 0x3 external (gpio pb4) this trigger is connected to the gpio interrupt for pb4 (see adc trigger source on page 412). 0x4 note: pb4 can be used to trigger the adc. however, the pb4/ ain10 pin cannot be used as both a gpio and an analog input. timer in addition, the trigger must be enabled with the tnote bit in the gptmctl register (page 481). 0x5 pwm0 the pwm generator 0 trigger can be configured with the pwm0 interrupt and trigger enable (pwm0inten) register (page 841). 0x6 pwm1 the pwm generator 1 trigger can be configured with the pwm1inten register (page 841). 0x7 pwm2 the pwm generator 2 trigger can be configured with the pwm2inten register (page 841). 0x8 reserved 0x9 reserved 0xa-0xe always (continuously sample) 0xf 0x0 r/w em3 15:12 march 20, 2011 564 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field ss2 trigger select this field selects the trigger source for sample sequencer 2. the valid configurations for this field are: event value processor (default) the trigger is initiated by setting the ssn bit in the adcpssi register. 0x0 analog comparator 0 this trigger is configured by the analog comparator control 0 (acctl0) register (page 798). 0x1 analog comparator 1 this trigger is configured by the analog comparator control 1 (acctl1) register (page 798). 0x2 reserved 0x3 external (gpio pb4) this trigger is connected to the gpio interrupt for pb4 (see adc trigger source on page 412). 0x4 note: pb4 can be used to trigger the adc. however, the pb4/ ain10 pin cannot be used as both a gpio and an analog input. timer in addition, the trigger must be enabled with the tnote bit in the gptmctl register (page 481). 0x5 pwm0 the pwm generator 0 trigger can be configured with the pwm0 interrupt and trigger enable (pwm0inten) register (page 841). 0x6 pwm1 the pwm generator 1 trigger can be configured with the pwm1inten register (page 841). 0x7 pwm2 the pwm generator 2 trigger can be configured with the pwm2inten register (page 841). 0x8 reserved 0x9 reserved 0xa-0xe always (continuously sample) 0xf 0x0 r/w em2 11:8 565 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ss1 trigger select this field selects the trigger source for sample sequencer 1. the valid configurations for this field are: event value processor (default) the trigger is initiated by setting the ssn bit in the adcpssi register. 0x0 analog comparator 0 this trigger is configured by the analog comparator control 0 (acctl0) register (page 798). 0x1 analog comparator 1 this trigger is configured by the analog comparator control 1 (acctl1) register (page 798). 0x2 reserved 0x3 external (gpio pb4) this trigger is connected to the gpio interrupt for pb4 (see adc trigger source on page 412). 0x4 note: pb4 can be used to trigger the adc. however, the pb4/ ain10 pin cannot be used as both a gpio and an analog input. timer in addition, the trigger must be enabled with the tnote bit in the gptmctl register (page 481). 0x5 pwm0 the pwm generator 0 trigger can be configured with the pwm0 interrupt and trigger enable (pwm0inten) register (page 841). 0x6 pwm1 the pwm generator 1 trigger can be configured with the pwm1inten register (page 841). 0x7 pwm2 the pwm generator 2 trigger can be configured with the pwm2inten register (page 841). 0x8 reserved 0x9 reserved 0xa-0xe always (continuously sample) 0xf 0x0 r/w em1 7:4 march 20, 2011 566 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field ss0 trigger select this field selects the trigger source for sample sequencer 0 the valid configurations for this field are: event value processor (default) the trigger is initiated by setting the ssn bit in the adcpssi register. 0x0 analog comparator 0 this trigger is configured by the analog comparator control 0 (acctl0) register (page 798). 0x1 analog comparator 1 this trigger is configured by the analog comparator control 1 (acctl1) register (page 798). 0x2 reserved 0x3 external (gpio pb4) this trigger is connected to the gpio interrupt for pb4 (see adc trigger source on page 412). 0x4 note: pb4 can be used to trigger the adc. however, the pb4/ ain10 pin cannot be used as both a gpio and an analog input. timer in addition, the trigger must be enabled with the tnote bit in the gptmctl register (page 481). 0x5 pwm0 the pwm generator 0 trigger can be configured with the pwm0 interrupt and trigger enable (pwm0inten) register (page 841). 0x6 pwm1 the pwm generator 1 trigger can be configured with the pwm1inten register (page 841). 0x7 pwm2 the pwm generator 2 trigger can be configured with the pwm2inten register (page 841). 0x8 reserved 0x9 reserved 0xa-0xe always (continuously sample) 0xf 0x0 r/w em0 3:0 567 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 7: adc underflow status (adcustat), offset 0x018 this register indicates underflow conditions in the sample sequencer fifos. the corresponding underflow condition is cleared by writing a 1 to the relevant bit position. adc underflow status (adcustat) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x018 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uv0 uv1 uv2 uv3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 ss3 fifo underflow the valid configurations for this field are shown below. this bit is cleared by writing a 1. description value the fifo for the sample sequencer has hit an underflow condition, meaning that the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. 1 the fifo has not underflowed. 0 0 r/w1c uv3 3 ss2 fifo underflow the valid configurations are the same as those for the uv3 field. this bit is cleared by writing a 1. 0 r/w1c uv2 2 ss1 fifo underflow the valid configurations are the same as those for the uv3 field. this bit is cleared by writing a 1. 0 r/w1c uv1 1 ss0 fifo underflow the valid configurations are the same as those for the uv3 field. this bit is cleared by writing a 1. 0 r/w1c uv0 0 march 20, 2011 568 texas instruments-advance information analog-to-digital converter (adc) register 8: adc sample sequencer priority (adcsspri), offset 0x020 this register sets the priority for each of the sample sequencers. out of reset, sequencer 0 has the highest priority, and sequencer 3 has the lowest priority. when reconfiguring sequence priorities, each sequence must have a unique priority for the adc to operate properly. adc sample sequencer priority (adcsspri) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x020 type r/w, reset 0x0000.3210 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ss0 reserved ss1 reserved ss2 reserved ss3 reserved r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro type 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:14 ss3 priority this field contains a binary-encoded value that specifies the priority encoding of sample sequencer 3. a priority encoding of 0x0 is highest and 0x3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. the adc may not operate properly if two or more fields are equal. 0x3 r/w ss3 13:12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 11:10 ss2 priority this field contains a binary-encoded value that specifies the priority encoding of sample sequencer 2. a priority encoding of 0x0 is highest and 0x3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. the adc may not operate properly if two or more fields are equal. 0x2 r/w ss2 9:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 ss1 priority this field contains a binary-encoded value that specifies the priority encoding of sample sequencer 1. a priority encoding of 0x0 is highest and 0x3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. the adc may not operate properly if two or more fields are equal. 0x1 r/w ss1 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 569 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ss0 priority this field contains a binary-encoded value that specifies the priority encoding of sample sequencer 0. a priority encoding of 0x0 is highest and 0x3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. the adc may not operate properly if two or more fields are equal. 0x0 r/w ss0 1:0 march 20, 2011 570 texas instruments-advance information analog-to-digital converter (adc) register 9: adc sample phase control (adcspc), offset 0x024 this register allows the adc module to sample at one of 16 different discrete phases from 0.0 through 337.5. for example, the sample rate could be effectively doubled by sampling a signal using one adc module configured with the standard sample time and the second adc module configured with a 180.0 phase lag. note: care should be taken when the phase field is non-zero, as the resulting delay in sampling the ainx input may result in undesirable system consequences. the time from adc trigger to sample is increased and could make the response time longer than anticipated. the added latency could have ramifications in the system design. designers should carefully consider the impact of this delay. adc sample phase control (adcspc) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 phase reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 571 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field phase difference this field selects the sample phase difference from the standard sample time. description value adc sample lags by 0.0 0x0 adc sample lags by 22.5 0x1 adc sample lags by 45.0 0x2 adc sample lags by 67.5 0x3 adc sample lags by 90.0 0x4 adc sample lags by 112.5 0x5 adc sample lags by 135.0 0x6 adc sample lags by 157.5 0x7 adc sample lags by 180.0 0x8 adc sample lags by 202.5 0x9 adc sample lags by 225.0 0xa adc sample lags by 247.5 0xb adc sample lags by 270.0 0xc adc sample lags by 292.5 0xd adc sample lags by 315.0 0xe adc sample lags by 337.5 0xf 0x0 r/w phase 3:0 march 20, 2011 572 texas instruments-advance information analog-to-digital converter (adc) register 10: adc processor sample sequence initiate (adcpssi), offset 0x028 this register provides a mechanism for application software to initiate sampling in the sample sequencers. sample sequences can be initiated individually or in any combination. when multiple sequences are triggered simultaneously, the priority encodings in adcsspri dictate execution order. this register also provides a means to configure and then initiate concurrent sampling on all adc modules. to do this, the first adc module should be configured. the adcpssi register for that module should then be written. the appropriate ss bits should be set along with the syncwait bit. additional adc modules should then be configured following the same procedure. once the final adc module is configured, its adcpssi register should be written with the appropriate ss bits set along with the gsync bit. all of the adc modules then begin concurrent sampling according to their configuration. adc processor sample sequence initiate (adcpssi) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x028 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved syncwait reserved gsync ro ro ro ro ro ro ro ro ro ro ro r/w ro ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ss0 ss1 ss2 ss3 reserved wo wo wo wo ro ro ro ro ro ro ro ro ro ro ro ro type - - - - 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field global synchronize description value this bit initiates sampling in multiple adc modules at the same time. any adc module that has been initialized by setting an ssn bit and the syncwait bit starts sampling once this bit is written. 1 this bit is cleared once sampling has been initiated. 0 0 r/w gsync 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 30:28 synchronize wait description value this bit allows the sample sequences to be initiated, but delays sampling until the gsync bit is set. 1 sampling begins when a sample sequence has been initiated. 0 0 r/w syncwait 27 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 26:4 573 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ss3 initiate description value begin sampling on sample sequencer 3, if the sequencer is enabled in the adcactss register. 1 no effect. 0 only a write by software is valid; a read of this register returns no meaningful data. - wo ss3 3 ss2 initiate description value begin sampling on sample sequencer 2, if the sequencer is enabled in the adcactss register. 1 no effect. 0 only a write by software is valid; a read of this register returns no meaningful data. - wo ss2 2 ss1 initiate description value begin sampling on sample sequencer 1, if the sequencer is enabled in the adcactss register. 1 no effect. 0 only a write by software is valid; a read of this register returns no meaningful data. - wo ss1 1 ss0 initiate description value begin sampling on sample sequencer 0, if the sequencer is enabled in the adcactss register. 1 no effect. 0 only a write by software is valid; a read of this register returns no meaningful data. - wo ss0 0 march 20, 2011 574 texas instruments-advance information analog-to-digital converter (adc) register 11: adc sample averaging control (adcsac), offset 0x030 this register controls the amount of hardware averaging applied to conversion results. the final conversion result stored in the fifo is averaged from 2 avg consecutive adc samples at the specified adc speed. if avg is 0, the sample is passed directly through without any averaging. if avg=6, then 64 consecutive adc samples are averaged to generate one result in the sequencer fifo. an avg=7 provides unpredictable results. adc sample averaging control (adcsac) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x030 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 avg reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 hardware averaging control specifies the amount of hardware averaging that will be applied to adc samples. the avg field can be any value between 0 and 6. entering a value of 7 creates unpredictable results. description value no hardware oversampling 0x0 2x hardware oversampling 0x1 4x hardware oversampling 0x2 8x hardware oversampling 0x3 16x hardware oversampling 0x4 32x hardware oversampling 0x5 64x hardware oversampling 0x6 reserved 0x7 0x0 r/w avg 2:0 575 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: adc digital comparator interrupt status and clear (adcdcisc), offset 0x034 this register provides status and acknowledgement of digital comparator interrupts. one bit is provided for each comparator. adc digital comparator interrupt status and clear (adcdcisc) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x034 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dcint0 dcint1 dcint2 dcint3 dcint4 dcint5 dcint6 dcint7 reserved r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 digital comparator 7 interrupt status and clear description value digital comparator 7 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint7 7 digital comparator 6 interrupt status and clear description value digital comparator 6 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint6 6 digital comparator 5 interrupt status and clear description value digital comparator 5 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint5 5 march 20, 2011 576 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field digital comparator 4 interrupt status and clear description value digital comparator 4 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint4 4 digital comparator 3 interrupt status and clear description value digital comparator 3 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint3 3 digital comparator 2 interrupt status and clear description value digital comparator 2 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint2 2 digital comparator 1 interrupt status and clear description value digital comparator 1 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint1 1 digital comparator 0 interrupt status and clear description value digital comparator 0 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint0 0 577 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 13: adc control (adcctl), offset 0x038 this register configures the voltage reference. the voltage reference for the conversion can be the internal 3.0-v reference or an external voltage reference in the range of 2.4 v to 3.06 v. adc control (adcctl) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vref reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 voltage reference select description value the external vrefa input is the voltage reference. 1 the internal reference as the voltage reference. 0 0 r/w vref 0 march 20, 2011 578 texas instruments-advance information analog-to-digital converter (adc) register 14: adc sample sequence input multiplexer select 0 (adcssmux0), offset 0x040 this register defines the analog input configuration for each sample in a sequence executed with sample sequencer 0. this register is 32 bits wide and contains information for eight possible samples. adc sample sequence input multiplexer select 0 (adcssmux0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x040 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mux4 mux5 mux6 mux7 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mux0 mux1 mux2 mux3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field 8th sample input select the mux7 field is used during the eighth sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. the value set here indicates the corresponding pin, for example, a value of 0x1 indicates the input is ain1. 0x0 r/w mux7 31:28 7th sample input select the mux6 field is used during the seventh sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux6 27:24 6th sample input select the mux5 field is used during the sixth sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux5 23:20 5th sample input select the mux4 field is used during the fifth sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux4 19:16 4th sample input select the mux3 field is used during the fourth sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux3 15:12 3rd sample input select the mux2 field is used during the third sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux2 11:8 579 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field 2nd sample input select the mux1 field is used during the second sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux1 7:4 1st sample input select the mux0 field is used during the first sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux0 3:0 march 20, 2011 580 texas instruments-advance information analog-to-digital converter (adc) register 15: adc sample sequence control 0 (adcssctl0), offset 0x044 this register contains the configuration information for each sample for a sequence executed with a sample sequencer. when configuring a sample sequence, the end bit must be set for the final sample, whether it be after the first sample, eighth sample, or any sample in between. this register is 32 bits wide and contains information for eight possible samples. adc sample sequence control 0 (adcssctl0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x044 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 d4 end4 ie4 ts4 d5 end5 ie5 ts5 d6 end6 ie6 ts6 d7 end7 ie7 ts7 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field 8th sample temp sensor select description value the temperature sensor is read during the eighth sample of the sample sequence. 1 the input pin specified by the adcssmuxn register is read during the eighth sample of the sample sequence. 0 0 r/w ts7 31 8th sample interrupt enable description value the raw interrupt signal ( inr0 bit) is asserted at the end of the eighth sample's conversion. if the mask0 bit in the adcim register is set, the interrupt is promoted to the interrupt controller. 1 the raw interrupt is not asserted to the interrupt controller. 0 it is legal to have multiple samples within a sequence generate interrupts. 0 r/w ie7 30 8th sample is end of sequence description value the eighth sample is the last sample of the sequence. 1 another sample in the sequence is the final sample. 0 it is possible to end the sequence on any sample position. software must set an endn bit somewhere within the sequence. samples defined after the sample containing a set endn bit are not requested for conversion even though the fields may be non-zero. 0 r/w end7 29 581 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field 8th sample diff input select description value the analog input is differentially sampled. the corresponding adcssmuxn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". 1 the analog inputs are not differentially sampled. 0 because the temperature sensor does not have a differential option, this bit must not be set when the ts7 bit is set. 0 r/w d7 28 7th sample temp sensor select same definition as ts7 but used during the seventh sample. 0 r/w ts6 27 7th sample interrupt enable same definition as ie7 but used during the seventh sample. 0 r/w ie6 26 7th sample is end of sequence same definition as end7 but used during the seventh sample. 0 r/w end6 25 7th sample diff input select same definition as d7 but used during the seventh sample. 0 r/w d6 24 6th sample temp sensor select same definition as ts7 but used during the sixth sample. 0 r/w ts5 23 6th sample interrupt enable same definition as ie7 but used during the sixth sample. 0 r/w ie5 22 6th sample is end of sequence same definition as end7 but used during the sixth sample. 0 r/w end5 21 6th sample diff input select same definition as d7 but used during the sixth sample. 0 r/w d5 20 5th sample temp sensor select same definition as ts7 but used during the fifth sample. 0 r/w ts4 19 5th sample interrupt enable same definition as ie7 but used during the fifth sample. 0 r/w ie4 18 5th sample is end of sequence same definition as end7 but used during the fifth sample. 0 r/w end4 17 5th sample diff input select same definition as d7 but used during the fifth sample. 0 r/w d4 16 4th sample temp sensor select same definition as ts7 but used during the fourth sample. 0 r/w ts3 15 4th sample interrupt enable same definition as ie7 but used during the fourth sample. 0 r/w ie3 14 4th sample is end of sequence same definition as end7 but used during the fourth sample. 0 r/w end3 13 march 20, 2011 582 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field 4th sample diff input select same definition as d7 but used during the fourth sample. 0 r/w d3 12 3rd sample temp sensor select same definition as ts7 but used during the third sample. 0 r/w ts2 11 3rd sample interrupt enable same definition as ie7 but used during the third sample. 0 r/w ie2 10 3rd sample is end of sequence same definition as end7 but used during the third sample. 0 r/w end2 9 3rd sample diff input select same definition as d7 but used during the third sample. 0 r/w d2 8 2nd sample temp sensor select same definition as ts7 but used during the second sample. 0 r/w ts1 7 2nd sample interrupt enable same definition as ie7 but used during the second sample. 0 r/w ie1 6 2nd sample is end of sequence same definition as end7 but used during the second sample. 0 r/w end1 5 2nd sample diff input select same definition as d7 but used during the second sample. 0 r/w d1 4 1st sample temp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. 0 r/w end0 1 1st sample diff input select same definition as d7 but used during the first sample. 0 r/w d0 0 583 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 16: adc sample sequence result fifo 0 (adcssfifo0), offset 0x048 register 17: adc sample sequence result fifo 1 (adcssfifo1), offset 0x068 register 18: adc sample sequence result fifo 2 (adcssfifo2), offset 0x088 register 19: adc sample sequence result fifo 3 (adcssfifo3), offset 0x0a8 important: this register is read-sensitive. see the register description for details. this register contains the conversion results for samples collected with the sample sequencer (the adcssfifo0 register is used for sample sequencer 0, adcssfifo1 for sequencer 1, adcssfifo2 for sequencer 2, and adcssfifo3 for sequencer 3). reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the fifo is empty. if the fifo is not properly handled by software, overflow and underflow conditions are registered in the adcostat and adcustat registers. adc sample sequence result fifo n (adcssfifon) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x048 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - - - - 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:10 conversion result data - ro data 9:0 march 20, 2011 584 texas instruments-advance information analog-to-digital converter (adc) register 20: adc sample sequence fifo 0 status (adcssfstat0), offset 0x04c register 21: adc sample sequence fifo 1 status (adcssfstat1), offset 0x06c register 22: adc sample sequence fifo 2 status (adcssfstat2), offset 0x08c register 23: adc sample sequence fifo 3 status (adcssfstat3), offset 0x0ac this register provides a window into the sample sequencer, providing full/empty status information as well as the positions of the head and tail pointers. the reset value of 0x100 indicates an empty fifo with the head and tail pointers both pointing to index 0. the adcssfstat0 register provides status on fifo0, which has 8 entries; adcssfstat1 on fifo1, which has 4 entries; adcssfstat2 on fifo2, which has 4 entries; and adcssfstat3 on fifo3 which has a single entry. adc sample sequence fifo 0 status (adcssfstat0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x04c type ro, reset 0x0000.0100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tptr hptr empty reserved full reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:13 fifo full description value the fifo is currently full. 1 the fifo is not currently full. 0 0 ro full 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 11:9 fifo empty description value the fifo is currently empty. 1 the fifo is not currently empty. 0 1 ro empty 8 585 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field fifo head pointer this field contains the current "head" pointer index for the fifo, that is, the next entry to be written. valid values are 0x0 - 0x7 for fifo0; 0x0 - 0x3 for fifo1 and fifo2; and 0x0 for fifo3. 0x0 ro hptr 7:4 fifo tail pointer this field contains the current "tail" pointer index for the fifo, that is, the next entry to be read. valid values are 0x0 - 0x7 for fifo0; 0x0 - 0x3 for fifo1 and fifo2; and 0x0 for fifo3. 0x0 ro tptr 3:0 march 20, 2011 586 texas instruments-advance information analog-to-digital converter (adc) register 24: adc sample sequence 0 operation (adcssop0), offset 0x050 this register determines whether the sample from the given conversion on sample sequence 0 is saved in the sample sequence fifo0 or sent to the digital comparator unit. adc sample sequence 0 operation (adcssop0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x050 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 s4dcop reserved s5dcop reserved s6dcop reserved s7dcop reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcop reserved s1dcop reserved s2dcop reserved s3dcop reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:29 sample 7 digital comparator operation description value the eighth sample is sent to the digital comparator unit specified by the s7dcsel bit in the adcssdc0 register, and the value is not written to the fifo. 1 the eighth sample is saved in sample sequence fifo0. 0 0 r/w s7dcop 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 27:25 sample 6 digital comparator operation same definition as s7dcop but used during the seventh sample. 0 r/w s6dcop 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 23:21 sample 5 digital comparator operation same definition as s7dcop but used during the sixth sample. 0 r/w s5dcop 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 19:17 sample 4 digital comparator operation same definition as s7dcop but used during the fifth sample. 0 r/w s4dcop 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:13 587 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field sample 3 digital comparator operation same definition as s7dcop but used during the fourth sample. 0 r/w s3dcop 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 11:9 sample 2 digital comparator operation same definition as s7dcop but used during the third sample. 0 r/w s2dcop 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 sample 1 digital comparator operation same definition as s7dcop but used during the second sample. 0 r/w s1dcop 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 sample 0 digital comparator operation same definition as s7dcop but used during the first sample. 0 r/w s0dcop 0 march 20, 2011 588 texas instruments-advance information analog-to-digital converter (adc) register 25: adc sample sequence 0 digital comparator select (adcssdc0), offset 0x054 this register determines which digital comparator receives the sample from the given conversion on sample sequence 0, if the corresponding sndcop bit in the adcssop0 register is set. adc sample sequence 0 digital comparator select (adcssdc0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x054 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 s4dcsel s5dcsel s6dcsel s7dcsel r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcsel s1dcsel s2dcsel s3dcsel r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field sample 7 digital comparator select when the s7dcop bit in the adcssop0 register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the eighth sample from sample sequencer 0. note: values not listed are reserved. description value digital comparator unit 0 ( adcdccmp0 and adcdcctl0 ) 0x0 digital comparator unit 1 ( adcdccmp1 and adcdcctl1 ) 0x1 digital comparator unit 2 ( adcdccmp2 and adcdcctl2 ) 0x2 digital comparator unit 3 ( adcdccmp3 and adcdcctl3 ) 0x3 digital comparator unit 4 ( adcdccmp4 and adcdcctl4 ) 0x4 digital comparator unit 5 ( adcdccmp5 and adcdcctl5 ) 0x5 digital comparator unit 6 ( adcdccmp6 and adcdcctl6 ) 0x6 digital comparator unit 7 ( adcdccmp7 and adcdcctl7 ) 0x7 0x0 r/w s7dcsel 31:28 sample 6 digital comparator select this field has the same encodings as s7dcsel but is used during the seventh sample. 0x0 r/w s6dcsel 27:24 sample 5 digital comparator select this field has the same encodings as s7dcsel but is used during the sixth sample. 0x0 r/w s5dcsel 23:20 sample 4 digital comparator select this field has the same encodings as s7dcsel but is used during the fifth sample. 0x0 r/w s4dcsel 19:16 sample 3 digital comparator select this field has the same encodings as s7dcsel but is used during the fourth sample. 0x0 r/w s3dcsel 15:12 589 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field sample 2 digital comparator select this field has the same encodings as s7dcsel but is used during the third sample. 0x0 r/w s2dcsel 11:8 sample 1 digital comparator select this field has the same encodings as s7dcsel but is used during the second sample. 0x0 r/w s1dcsel 7:4 sample 0 digital comparator select this field has the same encodings as s7dcsel but is used during the first sample. 0x0 r/w s0dcsel 3:0 march 20, 2011 590 texas instruments-advance information analog-to-digital converter (adc) register 26: adc sample sequence input multiplexer select 1 (adcssmux1), offset 0x060 register 27: adc sample sequence input multiplexer select 2 (adcssmux2), offset 0x080 this register defines the analog input configuration for each sample in a sequence executed with sample sequencer 1 or 2. these registers are 16 bits wide and contain information for four possible samples. see the adcssmux0 register on page 579 for detailed bit descriptions. the adcssmux1 register affects sample sequencer 1 and the adcssmux2 register affects sample sequencer 2. adc sample sequence input multiplexer select 1 (adcssmux1) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x060 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mux0 mux1 mux2 mux3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 4th sample input select 0x0 r/w mux3 15:12 3rd sample input select 0x0 r/w mux2 11:8 2nd sample input select 0x0 r/w mux1 7:4 1st sample input select 0x0 r/w mux0 3:0 591 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 28: adc sample sequence control 1 (adcssctl1), offset 0x064 register 29: adc sample sequence control 2 (adcssctl2), offset 0x084 these registers contain the configuration information for each sample for a sequence executed with sample sequencer 1 or 2. when configuring a sample sequence, the end bit must be set for the final sample, whether it be after the first sample, fourth sample, or any sample in between. these registers are 16-bits wide and contain information for four possible samples. see the adcssctl0 register on page 581 for detailed bit descriptions. the adcssctl1 register configures sample sequencer 1 and the adcssctl2 register configures sample sequencer 2. adc sample sequence control 1 (adcssctl1) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x064 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 4th sample temp sensor select same definition as ts7 but used during the fourth sample. 0 r/w ts3 15 4th sample interrupt enable same definition as ie7 but used during the fourth sample. 0 r/w ie3 14 4th sample is end of sequence same definition as end7 but used during the fourth sample. 0 r/w end3 13 4th sample diff input select same definition as d7 but used during the fourth sample. 0 r/w d3 12 3rd sample temp sensor select same definition as ts7 but used during the third sample. 0 r/w ts2 11 3rd sample interrupt enable same definition as ie7 but used during the third sample. 0 r/w ie2 10 3rd sample is end of sequence same definition as end7 but used during the third sample. 0 r/w end2 9 3rd sample diff input select same definition as d7 but used during the third sample. 0 r/w d2 8 2nd sample temp sensor select same definition as ts7 but used during the second sample. 0 r/w ts1 7 march 20, 2011 592 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field 2nd sample interrupt enable same definition as ie7 but used during the second sample. 0 r/w ie1 6 2nd sample is end of sequence same definition as end7 but used during the second sample. 0 r/w end1 5 2nd sample diff input select same definition as d7 but used during the second sample. 0 r/w d1 4 1st sample temp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. 0 r/w end0 1 1st sample diff input select same definition as d7 but used during the first sample. 0 r/w d0 0 593 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 30: adc sample sequence 1 operation (adcssop1), offset 0x070 register 31: adc sample sequence 2 operation (adcssop2), offset 0x090 this register determines whether the sample from the given conversion on sample sequence n is saved in the sample sequence n fifo or sent to the digital comparator unit. the adcssop1 register controls sample sequencer 1 and the adcssop2 register controls sample sequencer 2. adc sample sequence 1 operation (adcssop1) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x070 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcop reserved s1dcop reserved s2dcop reserved s3dcop reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:13 sample 3 digital comparator operation description value the fourth sample is sent to the digital comparator unit specified by the s3dcsel bit in the adcssdc0n register, and the value is not written to the fifo. 1 the fourth sample is saved in sample sequence fifon. 0 0 r/w s3dcop 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 11:9 sample 2 digital comparator operation same definition as s3dcop but used during the third sample. 0 r/w s2dcop 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 sample 1 digital comparator operation same definition as s3dcop but used during the second sample. 0 r/w s1dcop 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 sample 0 digital comparator operation same definition as s3dcop but used during the first sample. 0 r/w s0dcop 0 march 20, 2011 594 texas instruments-advance information analog-to-digital converter (adc) register 32: adc sample sequence 1 digital comparator select (adcssdc1), offset 0x074 register 33: adc sample sequence 2 digital comparator select (adcssdc2), offset 0x094 these registers determine which digital comparator receives the sample from the given conversion on sample sequence n if the corresponding sndcop bit in the adcssopn register is set. the adcssdc1 register controls the selection for sample sequencer 1 and the adcssdc2 register controls the selection for sample sequencer 2. adc sample sequence 1 digital comparator select (adcssdc1) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x074 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcsel s1dcsel s2dcsel s3dcsel r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 sample 3 digital comparator select when the s3dcop bit in the adcssopn register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the eighth sample from sample sequencer n. note: values not listed are reserved. description value digital comparator unit 0 ( adcdccmp0 and adccctl0 ) 0x0 digital comparator unit 1 ( adcdccmp1 and adccctl1 ) 0x1 digital comparator unit 2 ( adcdccmp2 and adccctl2 ) 0x2 digital comparator unit 3 ( adcdccmp3 and adccctl3 ) 0x3 digital comparator unit 4 ( adcdccmp4 and adccctl4 ) 0x4 digital comparator unit 5 ( adcdccmp5 and adccctl5 ) 0x5 digital comparator unit 6 ( adcdccmp6 and adccctl6 ) 0x6 digital comparator unit 7 ( adcdccmp7 and adccctl7 ) 0x7 0x0 r/w s3dcsel 15:12 sample 2 digital comparator select this field has the same encodings as s3dcsel but is used during the third sample. 0x0 r/w s2dcsel 11:8 595 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field sample 1 digital comparator select this field has the same encodings as s3dcsel but is used during the second sample. 0x0 r/w s1dcsel 7:4 sample 0 digital comparator select this field has the same encodings as s3dcsel but is used during the first sample. 0x0 r/w s0dcsel 3:0 march 20, 2011 596 texas instruments-advance information analog-to-digital converter (adc) register 34: adc sample sequence input multiplexer select 3 (adcssmux3), offset 0x0a0 this register defines the analog input configuration for the sample executed with sample sequencer 3. this register is 4 bits wide and contains information for one possible sample. see the adcssmux0 register on page 579 for detailed bit descriptions. adc sample sequence input multiplexer select 3 (adcssmux3) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x0a0 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mux0 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 1st sample input select 0 r/w mux0 3:0 597 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 35: adc sample sequence control 3 (adcssctl3), offset 0x0a4 this register contains the configuration information for a sample executed with sample sequencer 3. the end0 bit is always set as this sequencer can execute only one sample. this register is 4 bits wide and contains information for one possible sample. see the adcssctl0 register on page 581 for detailed bit descriptions. adc sample sequence control 3 (adcssctl3) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x0a4 type r/w, reset 0x0000.0002 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d0 end0 ie0 ts0 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 1st sample temp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. because this sequencer has only one entry, this bit must be set. 1 r/w end0 1 1st sample diff input select same definition as d7 but used during the first sample. 0 r/w d0 0 march 20, 2011 598 texas instruments-advance information analog-to-digital converter (adc) register 36: adc sample sequence 3 operation (adcssop3), offset 0x0b0 this register determines whether the sample from the given conversion on sample sequence 3 is saved in the sample sequence 3 fifo or sent to the digital comparator unit. adc sample sequence 3 operation (adcssop3) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x0b0 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcop reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 sample 0 digital comparator operation description value the sample is sent to the digital comparator unit specified by the s0dcsel bit in the adcssdc03 register, and the value is not written to the fifo. 1 the sample is saved in sample sequence fifo3. 0 0 r/w s0dcop 0 599 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 37: adc sample sequence 3 digital comparator select (adcssdc3), offset 0x0b4 this register determines which digital comparator receives the sample from the given conversion on sample sequence 3 if the corresponding sndcop bit in the adcssop3 register is set. adc sample sequence 3 digital comparator select (adcssdc3) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x0b4 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcsel reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 sample 0 digital comparator select when the s0dcop bit in the adcssop3 register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the sample from sample sequencer 3. note: values not listed are reserved. description value digital comparator unit 0 ( adcdccmp0 and adccctl0 ) 0x0 digital comparator unit 1 ( adcdccmp1 and adccctl1 ) 0x1 digital comparator unit 2 ( adcdccmp2 and adccctl2 ) 0x2 digital comparator unit 3 ( adcdccmp3 and adccctl3 ) 0x3 digital comparator unit 4 ( adcdccmp4 and adccctl4 ) 0x4 digital comparator unit 5 ( adcdccmp5 and adccctl5 ) 0x5 digital comparator unit 6 ( adcdccmp6 and adccctl6 ) 0x6 digital comparator unit 7 ( adcdccmp7 and adccctl7 ) 0x7 0x0 r/w s0dcsel 3:0 march 20, 2011 600 texas instruments-advance information analog-to-digital converter (adc) register 38: adc digital comparator reset initial conditions (adcdcric), offset 0xd00 this register provides the ability to reset any of the digital comparator interrupt or trigger functions back to their initial conditions. resetting these functions ensures that the data that is being used by the interrupt and trigger functions in the digital comparator unit is not stale. adc digital comparator reset initial conditions (adcdcric) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0xd00 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dctrig0 dctrig1 dctrig2 dctrig3 dctrig4 dctrig5 dctrig6 dctrig7 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dcint0 dcint1 dcint2 dcint3 dcint4 dcint5 dcint6 dcint7 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 digital comparator trigger 7 description value resets the digital comparator 7 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. after setting this bit, software should wait until the bit clears before continuing. 0 r/w dctrig7 23 digital comparator trigger 6 description value resets the digital comparator 6 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig6 22 601 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field digital comparator trigger 5 description value resets the digital comparator 5 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig5 21 digital comparator trigger 4 description value resets the digital comparator 4 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig4 20 digital comparator trigger 3 description value resets the digital comparator 3 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig3 19 digital comparator trigger 2 description value resets the digital comparator 2 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig2 18 march 20, 2011 602 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field digital comparator trigger 1 description value resets the digital comparator 1 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig1 17 digital comparator trigger 0 description value resets the digital comparator 0 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:8 digital comparator interrupt 7 description value resets the digital comparator 7 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint7 7 digital comparator interrupt 6 description value resets the digital comparator 6 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint6 6 603 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field digital comparator interrupt 5 description value resets the digital comparator 5 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint5 5 digital comparator interrupt 4 description value resets the digital comparator 4 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint4 4 digital comparator interrupt 3 description value resets the digital comparator 3 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint3 3 digital comparator interrupt 2 description value resets the digital comparator 2 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint2 2 march 20, 2011 604 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field digital comparator interrupt 1 description value resets the digital comparator 1 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint1 1 digital comparator interrupt 0 description value resets the digital comparator 0 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint0 0 605 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 39: adc digital comparator control 0 (adcdcctl0), offset 0xe00 register 40: adc digital comparator control 1 (adcdcctl1), offset 0xe04 register 41: adc digital comparator control 2 (adcdcctl2), offset 0xe08 register 42: adc digital comparator control 3 (adcdcctl3), offset 0xe0c register 43: adc digital comparator control 4 (adcdcctl4), offset 0xe10 register 44: adc digital comparator control 5 (adcdcctl5), offset 0xe14 register 45: adc digital comparator control 6 (adcdcctl6), offset 0xe18 register 46: adc digital comparator control 7 (adcdcctl7), offset 0xe1c this register provides the comparison encodings that generate an interrupt and/or pwm trigger. see interrupt/adc-trigger selector on page 808 for more information on using the adc digital comparators to trigger a pwm generator. adc digital comparator control 0 (adcdcctl0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0xe00 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cim cic cie reserved ctm ctc cte reserved r/w r/w r/w r/w r/w ro ro ro r/w r/w r/w r/w r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:13 comparison trigger enable description value enables the trigger function state machine. the adc conversion data is used to determine if a trigger should be generated according to the programming of the ctc and ctm fields. 1 disables the trigger function state machine. adc conversion data is ignored by the trigger function. 0 0 r/w cte 12 march 20, 2011 606 texas instruments-advance information analog-to-digital converter (adc) description reset type name bit/field comparison trigger condition this field specifies the operational region in which a trigger is generated when the adc conversion data is compared against the values of comp0 and comp1 . the comp0 and comp1 fields are defined in the adcdccmpx registers. description value low band adc data < comp0 comp1 0x0 mid band comp0 adc data < comp1 0x1 reserved 0x2 high band comp0 comp1 adc data 0x3 0x0 r/w ctc 11:10 comparison trigger mode this field specifies the mode by which the trigger comparison is made. description value always this mode generates a trigger every time the adc conversion data falls within the selected operational region. 0x0 once this mode generates a trigger the first time that the adc conversion data enters the selected operational region. 0x1 hysteresis always this mode generates a trigger when the adc conversion data falls within the selected operational region and continues to generate the trigger until the hysteresis condition is cleared by entering the opposite operational region. note that the hysteresis modes are only defined for ctc encodings of 0x0 and 0x3. 0x2 hysteresis once this mode generates a trigger the first time that the adc conversion data falls within the selected operational region. no additional triggers are generated until the hysteresis condition is cleared by entering the opposite operational region. note that the hysteresis modes are only defined for ctc encodings of 0x0 and 0x3. 0x3 0x0 r/w ctm 9:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 comparison interrupt enable description value enables the comparison interrupt. the adc conversion data is used to determine if an interrupt should be generated according to the programming of the cic and cim fields. 1 disables the comparison interrupt. adc conversion data has no effect on interrupt generation. 0 0 r/w cie 4 607 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field comparison interrupt condition this field specifies the operational region in which an interrupt is generated when the adc conversion data is compared against the values of comp0 and comp1 . the comp0 and comp1 fields are defined in the adcdccmpx registers. description value low band adc data < comp0 comp1 0x0 mid band comp0 adc data < comp1 0x1 reserved 0x2 high band comp0 < comp1 adc data 0x3 0x0 r/w cic 3:2 comparison interrupt mode this field specifies the mode by which the interrupt comparison is made. description value always this mode generates an interrupt every time the adc conversion data falls within the selected operational region. 0x0 once this mode generates an interrupt the first time that the adc conversion data enters the selected operational region. 0x1 hysteresis always this mode generates an interrupt when the adc conversion data falls within the selected operational region and continues to generate the interrupt until the hysteresis condition is cleared by entering the opposite operational region. note that the hysteresis modes are only defined for ctc encodings of 0x0 and 0x3. 0x2 hysteresis once this mode generates an interrupt the first time that the adc conversion data falls within the selected operational region. no additional interrupts are generated until the hysteresis condition is cleared by entering the opposite operational region. note that the hysteresis modes are only defined for ctc encodings of 0x0 and 0x3. 0x3 0x0 r/w cim 1:0 march 20, 2011 608 texas instruments-advance information analog-to-digital converter (adc) register 47: adc digital comparator range 0 (adcdccmp0), offset 0xe40 register 48: adc digital comparator range 1 (adcdccmp1), offset 0xe44 register 49: adc digital comparator range 2 (adcdccmp2), offset 0xe48 register 50: adc digital comparator range 3 (adcdccmp3), offset 0xe4c register 51: adc digital comparator range 4 (adcdccmp4), offset 0xe50 register 52: adc digital comparator range 5 (adcdccmp5), offset 0xe54 register 53: adc digital comparator range 6 (adcdccmp6), offset 0xe58 register 54: adc digital comparator range 7 (adcdccmp7), offset 0xe5c this register defines the comparison values that are used to determine if the adc conversion data falls in the appropriate operating region. note: the value in the comp1 field must be greater than or equal to the value in the comp0 field or unexpected results can occur. adc digital comparator range 0 (adcdccmp0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0xe40 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 comp1 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 comp0 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:26 compare 1 the value in this field is compared against the adc conversion data. the result of the comparison is used to determine if the data lies within the high-band region. note that the value of comp1 must be greater than or equal to the value of comp0. 0x000 r/w comp1 25:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:10 compare 0 the value in this field is compared against the adc conversion data. the result of the comparison is used to determine if the data lies within the low-band region. 0x000 r/w comp0 9:0 609 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 13 universal asynchronous receivers/transmitters (uarts) the stellaris ? lm3s1p51 controller includes three universal asynchronous receiver/transmitter (uart) with the following features: programmable baud-rate generator allowing speeds up to 5 mbps for regular speed (divide by 16) and 10 mbps for high speed (divide by 8) separate 16x8 transmit (tx) and receive (rx) fifos to reduce cpu interrupt service loading programmable fifo length, including 1-byte deep operation providing conventional double-buffered interface fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 standard asynchronous communication bits for start, stop, and parity line-break generation and detection fully programmable serial interface characteristics C 5, 6, 7, or 8 data bits C even, odd, stick, or no-parity bit generation/detection C 1 or 2 stop bit generation irda serial-ir (sir) encoder/decoder providing C programmable use of irda serial infrared (sir) or uart input/output C support of irda sir encoder/decoder functions for data rates up to 115.2 kbps half-duplex C support of normal 3/16 and low-power (1.41-2.23 s) bit durations C programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration support for communication with iso 7816 smart cards full modem handshake support (on uart1) lin protocol support standard fifo-level and end-of-transmission interrupts efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive single request asserted when data is in the fifo; burst request asserted at programmed fifo level march 20, 2011 610 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) C transmit single request asserted when there is space in the fifo; burst request asserted at programmed fifo level 13.1 block diagram figure 13-1. uart module block diagram 13.2 signal description table 13-1 on page 612 and table 13-2 on page 612 list the external signals of the uart module and describe the function of each. the uart signals are alternate functions for some gpio signals and default to be gpio signals at reset, with the exception of the u0rx and u0tx pins which default to the uart function. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these uart signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the uart function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the uart signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. 611 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 7 [ ) , ) 2 [ 5 [ ) , ) 2 [ ' 0 $ & r q w u r o 8 $ 5 7 ' 0 $ & 7 / , g h q w l i l f d w l r q 5 h j l v w h u v 8 $ 5 7 3 & h o o , ' 8 $ 5 7 3 & h o o , ' 8 $ 5 7 3 & h o o , ' 8 $ 5 7 3 & h o o , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' , q w h u u x s w & r q w u r o 8 $ 5 7 ' 5 & r q w u r o 6 w d w x v 7 u d q v p l w w h u z l w k 6 , 5 7 u d q v p l w ( q f r g h u % d x g 5 d w h * h q h u d w r u 5 h f h l y h u z l w k 6 , 5 5 h f h l y h ' h f r g h u 8 q 7 [ 8 q 5 [ ' 0 $ 5 h t x h v w 6 \ v w h p & o r f n , q w h u u x s w 8 $ 5 7 , ) / 6 8 $ 5 7 , 0 8 $ 5 7 0 , 6 8 $ 5 7 5 , 6 8 $ 5 7 , & 5 8 $ 5 7 , % 5 ' 8 $ 5 7 ) % 5 ' 8 $ 5 7 5 6 5 ( & 5 8 $ 5 7 ) 5 8 $ 5 7 / & 5 + 8 $ 5 7 & 7 / 8 $ 5 7 , / 3 5 8 $ 5 7 / & 7 / 8 $ 5 7 / 6 6 8 $ 5 7 / 7 , 0 table 13-1. signals for uart (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i pa0 (1) 26 u0rx uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o pa1 (1) 27 u0tx uart module 1 clear to send modem status input signal. ttl i pe6 (9) pd0 (9) pa6 (9) 2 10 34 u1cts uart module 1 data carrier detect modem status input signal. ttl i pe7 (9) pd1 (9) pa7 (9) 1 11 35 u1dcd uart module 1 data set ready modem output control line. ttl i pf0 (9) 47 u1dsr uart module 1 data terminal ready modem status input signal. ttl o pg5 (10) pd7 (9) 40 100 u1dtr uart module 1 ring indicator modem status input signal. ttl i pg6 (10) pg4 (10) pd4 (9) 37 41 97 u1ri uart module 1 request to send modem output control line. ttl o pf6 (10) pf1 (9) 43 61 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (5) pd2 (1) pc6 (5) pa0 (9) pb0 (5) pb4 (7) 10 12 23 26 66 92 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o pd1 (5) pd3 (1) pc7 (5) pa1 (9) pb1 (5) pb5 (7) 11 13 22 27 67 91 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (4) pg0 (1) pb4 (4) pd5 (9) 10 19 92 98 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o pe4 (5) pd1 (4) pg1 (1) pd6 (9) 6 11 18 99 u2tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 13-2. signals for uart (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i pa0 (1) l3 u0rx uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o pa1 (1) m3 u0tx uart module 1 clear to send modem status input signal. ttl i pe6 (9) pd0 (9) pa6 (9) a1 g1 l6 u1cts march 20, 2011 612 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) table 13-2. signals for uart (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 1 data carrier detect modem status input signal. ttl i pe7 (9) pd1 (9) pa7 (9) b1 g2 m6 u1dcd uart module 1 data set ready modem output control line. ttl i pf0 (9) m9 u1dsr uart module 1 data terminal ready modem status input signal. ttl o pg5 (10) pd7 (9) m7 a2 u1dtr uart module 1 ring indicator modem status input signal. ttl i pg6 (10) pg4 (10) pd4 (9) l7 k3 b5 u1ri uart module 1 request to send modem output control line. ttl o pf6 (10) pf1 (9) m8 h12 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (5) pd2 (1) pc6 (5) pa0 (9) pb0 (5) pb4 (7) g1 h2 m2 l3 e12 a6 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o pd1 (5) pd3 (1) pc7 (5) pa1 (9) pb1 (5) pb5 (7) g2 h1 l2 m3 d12 b7 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (4) pg0 (1) pb4 (4) pd5 (9) g1 k1 a6 c6 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o pe4 (5) pd1 (4) pg1 (1) pd6 (9) b2 g2 k2 a3 u2tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. 13.3 functional description each stellaris uart performs the functions of parallel-to-serial and serial-to-parallel conversions. it is similar in functionality to a 16c550 uart, but is not register compatible. the uart is configured for transmit and/or receive via the txe and rxe bits of the uart control (uartctl) register (see page 637). transmit and receive are both enabled out of reset. before any control registers are programmed, the uart must be disabled by clearing the uarten bit in uartctl . if the uart is disabled during a tx or rx operation, the current transaction is completed prior to the uart stopping. the uart module also includes a serial ir (sir) encoder/decoder block that can be connected to an infrared transceiver to implement an irda sir physical layer. the sir function is programmed using the uartctl register. 13.3.1 transmit/receive logic the transmit logic performs parallel-to-serial conversion on the data read from the transmit fifo. the control logic outputs the serial bit stream beginning with a start bit and followed by the data bits 613 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller (lsb first), parity bit, and the stop bits according to the programmed configuration in the control registers. see figure 13-2 on page 614 for details. the receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive fifo. figure 13-2. uart character frame 13.3.2 baud-rate generation the baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. the number formed by these two values is used by the baud-rate generator to determine the bit period. having a fractional baud-rate divider allows the uart to generate all the standard baud rates. the 16-bit integer is loaded through the uart integer baud-rate divisor (uartibrd) register (see page 633) and the 6-bit fractional part is loaded with the uart fractional baud-rate divisor (uartfbrd) register (see page 634). the baud-rate divisor (brd) has the following relationship to the system clock (where brdi is the integer part of the brd and brdf is the fractional part, separated by a decimal place.) brd = brdi + brdf = uartsysclk / (clkdiv * baud rate) where uartsysclk is the system clock connected to the uart, and clkdiv is either 16 (if hse in uartctl is clear) or 8 (if hse is set). the 6-bit fractional number (that is to be loaded into the divfrac bit field in the uartfbrd register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: uartfbrd[divfrac] = integer(brdf * 64 + 0.5) the uart generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to as baud8 and baud16 , depending on the setting of the hse bit (bit 5) in uartctl ). this reference clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations. along with the uart line control, high byte (uartlcrh) register (see page 635), the uartibrd and uartfbrd registers form an internal 30-bit register. this internal register is only updated when a write operation to uartlcrh is performed, so any changes to the baud-rate divisor must be followed by a write to the uartlcrh register for the changes to take effect. to update the baud-rate registers, there are four possible sequences: uartibrd write, uartfbrd write, and uartlcrh write uartfbrd write, uartibrd write, and uartlcrh write uartibrd write and uartlcrh write uartfbrd write and uartlcrh write march 20, 2011 614 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) g d w d e l w v / 6 % 0 6 % 3 d u l w \ e l w l i h q d e o h g v w r s e l w v 8 q 7 ; q 6 w d u w 13.3.3 data transmission data received or transmitted is stored in two 16-byte fifos, though the receive fifo has an extra four bits per character for status information. for transmission, data is written into the transmit fifo. if the uart is enabled, it causes a data frame to start transmitting with the parameters indicated in the uartlcrh register. data continues to be transmitted until there is no data left in the transmit fifo. the busy bit in the uart flag (uartfr) register (see page 629) is asserted as soon as data is written to the transmit fifo (that is, if the fifo is non-empty) and remains asserted while data is being transmitted. the busy bit is negated only when the transmit fifo is empty, and the last character has been transmitted from the shift register, including the stop bits. the uart can indicate that it is busy even though the uart may no longer be enabled. when the receiver is idle (the unrx signal is continuously 1), and the data input goes low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of baud16 or fourth cycle of baud8 depending on the setting of the hse bit (bit 5) in uartctl (described in transmit/receive logic on page 613). the start bit is valid and recognized if the unrx signal is still low on the eighth cycle of baud16 (hse clear) or the fourth cycle of baud 8 ( hse set), otherwise it is ignored. after a valid start bit is detected, successive data bits are sampled on every 16th cycle of baud16 or 8th cycle of baud8 (that is, one bit period later) according to the programmed length of the data characters and value of the hse bit in uartctl . the parity bit is then checked if parity mode is enabled. data length and parity are defined in the uartlcrh register. lastly, a valid stop bit is confirmed if the unrx signal is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo along with any error bits associated with that word. 13.3.4 serial ir (sir) the uart peripheral includes an irda serial-ir (sir) encoder/decoder block. the irda sir block provides functionality that converts between an asynchronous uart data stream and a half-duplex serial sir interface. no analog processing is performed on-chip. the role of the sir block is to provide a digital encoded output and decoded input to the uart. when enabled, the sir block uses the untx and unrx pins for the sir protocol. these signals should be connected to an infrared transceiver to implement an irda sir physical layer link. the sir block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. transmission must be stopped before data can be received. the irda sir physical layer specifies a minimum 10-ms delay between transmission and reception.the sir block has two modes of operation: in normal irda mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static low signal. these levels control the driver of an infrared transmitter, sending a pulse of light for each zero. on the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output low and driving the uart input pin low. in low-power irda mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated irlpbaud16 signal (1.63 s, assuming a nominal 1.8432 mhz frequency) by changing the appropriate bit in the uartcr register. see page 632 for more information on irda low-power pulse-duration configuration. figure 13-3 on page 616 shows the uart transmit and receive signals, with and without irda modulation. 615 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 13-3. irda data modulation in both normal and low-power irda modes: during transmission, the uart data bit is used as the base for encoding during reception, the decoded bits are transferred to the uart receive logic the irda sir physical layer specifies a half-duplex communication link, with a minimum 10-ms delay between transmission and reception. this delay must be generated by software because it is not automatically supported by the uart. the delay is required because the infrared receiver electronics might become biased or even saturated from the optical power coupled from the adjacent transmitter led. this delay is known as latency or receiver setup time. 13.3.5 iso 7816 support the uart offers basic support to allow communication with an iso 7816 smartcard. when bit 3 (smart ) of the uartctl register is set, the untx signal is used as a bit clock, and the unrx signal is used as the half-duplex communication line connected to the smartcard. a gpio signal can be used to generate the reset signal to the smartcard. the remaining smartcard signals should be provided by the system design. when using iso 7816 mode, the uartlcrh register must be set to transmit 8-bit words ( wlen bits 6:5 configured to 0x3) with even parity ( pen set and eps set). in this mode, the uart automatically uses 2 stop bits, and the stp2 bit of the uartlcrh register is ignored. if a parity error is detected during transmission, unrx is pulled low during the second stop bit. in this case, the uart aborts the transmission, flushes the transmit fifo and discards any data it contains, and raises a parity error interrupt, allowing software to detect the problem and initiate retransmission of the affected data. note that the uart does not support automatic retransmission in this case. 13.3.6 modem handshake support this section describes how to configure and use the modem status signals for uart1 when connected as a dte (data terminal equipment) or as a dce (data communications equipment). in general, a modem is a dce and a computing device that connects to a modem is the dte. 13.3.6.1 signaling the status signals provided by uart1differ based on whether the uart is used as a dte or dce. when used as a dte, the modem status signals are defined as: march 20, 2011 616 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) ' d w d e l w v ' d w d e l w v 6 w d u w e l w 6 w d u w 6 w r s % l w s h u l r g % l w s h u l r g 8 q 7 [ 8 q 7 [ z l w k , u ' $ 8 q 5 [ z l w k , u ' $ 8 q 5 [ 6 w r s e l w u1cts is clear to send u1dsr is data set ready u1dcd is data carrier detect u1ri is ring indicator u1rts is request to send u1dtr is data terminal ready when used as a dce, the the modem status signals are defined as: u1cts is request to send u1dsr is data terminal ready u1rts is clear to send u1dtr is data set ready note that the support for dce functions data carrier detect and ring indicator are not provided. if these signals are required, their function can be emulated by using a general-purpose i/o signal and providing software support. 13.3.6.2 flow control methods flow control can be accomplished by either hardware or software. the following sections describe the different methods. hardware flow control (rts/cts) hardware flow control between two devices is accomplished by connecting the u1rts output to the clear-to-send input on the receiving device, and connecting the request-to-send output on the receiving device to the u1cts input. the u1cts input controls the transmitter. the transmitter may only transmit data when the u1cts input is asserted. the u1rts output signal indicates the state of the receive fifo. u1cts remains asserted until the preprogrammed watermark level is reached, indicating that the receive fifo has no space to store additional characters. the uartctl register bits 15 ( ctsen ) and 14 (rtsen ) specify the flow control mode as shown in table 13-3 on page 617. table 13-3. flow control mode description rtsen ctsen rts and cts flow control enabled 1 1 only cts flow control enabled 0 1 only rts flow control enabled 1 0 both rts and cts flow control disabled 0 0 note that when rtsen is 1, software cannot modify the u1rts output value through the uartctl register request to send ( rts ) bit, and the status of the rts bit should be ignored. 617 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller software flow control (modem status interrupts) software flow control between two devices is accomplished by using interrupts to indicate the status of the uart. interrupts may be generated for u1dsr , u1dcd , u1cts , and u1ri using the uartim bits 3 through 0 respectively. the raw and masked interrupt status may be checked using the uartris and uartmis register. these interrupts may be cleared using the uarticr register. 13.3.7 lin support the uart module offers hardware support for the lin protocol as either a master or a slave. the lin mode is enabled by setting the lin bit in the uartctl register. a lin message is identified by the use of a sync break at the beginning of the message. the sync break is a transmission of a series of 0s. the sync break is followed by the sync data field (0x55). figure 13-4 on page 618 illustrates the structure of a lin message. figure 13-4. lin message the uart should be configured as followed to operate in lin mode: 1. configure the uart for 1 start bit, 8 data bits, no parity, and 1 stop bit. enable the transmit fifo. 2. set the lin bit in the uartctl register. when preparing to send a lin message, the txfifo should contain the sync data (0x55) at fifo location 0 and the identifier data at location 1, followed by the data to be transmitted, and with the checksum in the final fifo entry. 13.3.7.1 lin master the uart is enabled to be the lin master by setting the master bit in the uartlctl register. the length of the sync break is programmable using the blen field in the uartlctl register and can be 13-16 bits (baud clock cycles). 13.3.7.2 lin slave the lin uart slave is required to adjust its baud rate to that of the lin master. in slave mode, the lin uart recognizes the sync break, which must be at least 13 bits in duration. a timer is provided to capture timing data on the 1st and 5th falling edges of the sync field so that the baud rate can be adjusted to match the master. march 20, 2011 618 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) + h d g h u 5 h v s r q v h 0 h v v d j h ) u d p h 6 \ q f k % u h d n 6 \ q f k ) l h o g , g h q w ) l h o g ' d w d ) l h o g v ' d w d ) l h o g & k h f n v x p ) l h o g , q w h u e \ w h 6 s d f h , q ) u d p h 5 h v s r q v h after detecting a sync break, the uart waits for the synchronization field. the first falling edge generates an interrupt using the lme1ris bit in the uartris register, and the timer value is captured and stored in the uartlss register (t1). on the fifth falling edge, a second interrupt is generated using the lme5ris bit in the uartris register, and the timer value is captured again (t2). the actual baud rate can be calculated using (t2-t1)/8, and the local baud rate should be adjusted as needed. figure 13-5 on page 619 illustrates the synchronization field. figure 13-5. lin synchronization field 13.3.8 fifo operation the uart has two 16-entry fifos; one for transmit and one for receive. both fifos are accessed via the uart data (uartdr) register (see page 624). read operations of the uartdr register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit fifo. out of reset, both fifos are disabled and act as 1-byte-deep holding registers. the fifos are enabled by setting the fen bit in uartlcrh (page 635). fifo status can be monitored via the uart flag (uartfr) register (see page 629) and the uart receive status (uartrsr) register. hardware monitors empty, full and overrun conditions. the uartfr register contains empty and full flags ( txfe, txff, rxfe , and rxff bits), and the uartrsr register shows overrun status via the oe bit. the trigger points at which the fifos generate interrupts is controlled via the uart interrupt fifo level select (uartifls) register (see page 641). both fifos can be individually configured to trigger interrupts at different levels. available configurations include ?, ?, ?, ?, and ?. for example, if the ? option is selected for the receive fifo, the uart generates a receive interrupt after 4 data bytes are received. out of reset, both fifos are configured to trigger an interrupt at the ? mark. 13.3.9 interrupts the uart can generate interrupts when the following conditions are observed: overrun error break error parity error framing error receive timeout transmit (when condition defined in the txiflsel bit in the uartifls register is met, or if the eot bit in uartctl is set, when the last bit of all transmitted data leaves the serializer) 619 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller ( g j h ( g j h 6 \ q f k ) l h o g 7 e l w 6 \ q f % u h d n ' h w h f w 6 \ q f % u h d n receive (when condition defined in the rxiflsel bit in the uartifls register is met) all of the interrupt events are ored together before being sent to the interrupt controller, so the uart can only generate a single interrupt request to the controller at any given time. software can service multiple interrupt events in a single interrupt service routine by reading the uart masked interrupt status (uartmis) register (see page 650). the interrupt events that can trigger a controller-level interrupt are defined in the uart interrupt mask (uartim) register (see page 643) by setting the corresponding im bits. if interrupts are not used, the raw interrupt status is always visible via the uart raw interrupt status (uartris) register (see page 647). interrupts are always cleared (for both the uartmis and uartris registers) by writing a 1 to the corresponding bit in the uart interrupt clear (uarticr) register (see page 653). the receive timeout interrupt is asserted when the receive fifo is not empty, and no further data is received over a 32-bit period. the receive timeout interrupt is cleared either when the fifo becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the uarticr register. 13.3.10 loopback operation the uart can be placed into an internal loopback mode for diagnostic or debug work by setting the lbe bit in the uartctl register (see page 637). in loopback mode, data transmitted on the untx output is received on the unrx input. 13.3.11 dma operation the uart provides an interface to the dma controller with separate channels for transmit and receive. the dma operation of the uart is enabled through the uart dma control (uartdmactl) register. when dma operation is enabled, the uart asserts a dma request on the receive or transmit channel when the associated fifo can transfer data. for the receive channel, a single transfer request is asserted whenever any data is in the receive fifo. a burst transfer request is asserted whenever the amount of data in the receive fifo is at or above the fifo trigger level configured in the uartifls register. for the transmit channel, a single transfer request is asserted whenever there is at least one empty location in the transmit fifo. the burst request is asserted whenever the transmit fifo contains fewer characters than the fifo trigger level. the single and burst dma transfer requests are handled automatically by the dma controller depending on how the dma channel is configured. to enable dma operation for the receive channel, set the rxdmae bit of the dma control (uartdmactl) register. to enable dma operation for the transmit channel, set the txdmae bit of the uartdmactl register. the uart can also be configured to stop using dma for the receive channel if a receive error occurs. if the dmaerr bit of the uartdmacr register is set and a receive error occurs, the dma receive requests are automatically disabled. this error condition can be cleared by clearing the appropriate uart error interrupt. if dma is enabled, then the dma controller triggers an interrupt when a transfer is complete. the interrupt occurs on the uart interrupt vector. therefore, if interrupts are used for uart operation and dma is enabled, the uart interrupt handler must be designed to handle the dma completion interrupt. see micro direct memory access (dma) on page 346 for more details about programming the dma controller. march 20, 2011 620 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) 13.4 initialization and configuration to enable and initialize the uart, the following steps are necessary: 1. the peripheral clock must be enabled by setting the uart0, uart1 , or uart2 bits in the rcgc1 register (see page 260). 2. the clock to the appropriate gpio module must be enabled via the rcgc2 register in the system control module (see page 269). 3. set the gpio afsel bits for the appropriate pins (see page 428). to determine which gpios to configure, see table 21-4 on page 917. 4. configure the gpio current level and/or slew rate as specified for the mode selected (see page 430 and page 438). 5. configure the pmcn fields in the gpiopctl register to assign the uart signals to the appropriate pins (see page 446 and table 21-5 on page 925). to use the uart, the peripheral clock must be enabled by setting the appropriate bit in the rcgc1 register (page 260). in addition, the clock to the appropriate gpio module must be enabled via the rcgc2 register (page 269) in the system control module. to find out which gpio port to enable, refer to table 21-5 on page 925. this section discusses the steps that are required to use a uart module. for this example, the uart clock is assumed to be 20 mhz, and the desired uart configuration is: 115200 baud rate data length of 8 bits one stop bit no parity fifos disabled no interrupts the first thing to consider when programming the uart is the baud-rate divisor (brd), because the uartibrd and uartfbrd registers must be written before the uartlcrh register. using the equation described in baud-rate generation on page 614, the brd can be calculated: brd = 20,000,000 / (16 * 115,200) = 10.8507 which means that the divint field of the uartibrd register (see page 633) should be set to 10 decimal or 0xa. the value to be loaded into the uartfbrd register (see page 634) is calculated by the equation: uartfbrd[divfrac] = integer(0.8507 * 64 + 0.5) = 54 with the brd values in hand, the uart configuration is written to the module in the following order: 1. disable the uart by clearing the uarten bit in the uartctl register. 2. write the integer portion of the brd to the uartibrd register. 621 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 3. write the fractional portion of the brd to the uartfbrd register. 4. write the desired serial parameters to the uartlcrh register (in this case, a value of 0x0000.0060). 5. optionally, configure the dma channel (see micro direct memory access (dma) on page 346) and enable the dma option(s) in the uartdmactl register. 6. enable the uart by setting the uarten bit in the uartctl register. 13.5 register map table 13-4 on page 622 lists the uart registers. the offset listed is a hexadecimal increment to the registers address, relative to that uarts base address: uart0: 0x4000.c000 uart1: 0x4000.d000 uart2: 0x4000.e000 note that the uart module clock must be enabled before the registers can be programmed (see page 260). there must be a delay of 3 system clocks after the uart module clock is enabled before any uart module registers are accessed. note: the uart must be disabled (see the uarten bit in the uartctl register on page 637) before any of the control registers are reprogrammed. when the uart is disabled during a tx or rx operation, the current transaction is completed prior to the uart stopping. table 13-4. uart register map see page description reset type name offset 624 uart data 0x0000.0000 r/w uartdr 0x000 626 uart receive status/error clear 0x0000.0000 r/w uartrsr/uartecr 0x004 629 uart flag 0x0000.0090 ro uartfr 0x018 632 uart irda low-power register 0x0000.0000 r/w uartilpr 0x020 633 uart integer baud-rate divisor 0x0000.0000 r/w uartibrd 0x024 634 uart fractional baud-rate divisor 0x0000.0000 r/w uartfbrd 0x028 635 uart line control 0x0000.0000 r/w uartlcrh 0x02c 637 uart control 0x0000.0300 r/w uartctl 0x030 641 uart interrupt fifo level select 0x0000.0012 r/w uartifls 0x034 643 uart interrupt mask 0x0000.0000 r/w uartim 0x038 647 uart raw interrupt status 0x0000.000f ro uartris 0x03c 650 uart masked interrupt status 0x0000.0000 ro uartmis 0x040 653 uart interrupt clear 0x0000.0000 w1c uarticr 0x044 655 uart dma control 0x0000.0000 r/w uartdmactl 0x048 656 uart lin control 0x0000.0000 r/w uartlctl 0x090 march 20, 2011 622 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) table 13-4. uart register map (continued) see page description reset type name offset 657 uart lin snap shot 0x0000.0000 ro uartlss 0x094 658 uart lin timer 0x0000.0000 ro uartltim 0x098 659 uart peripheral identification 4 0x0000.0000 ro uartperiphid4 0xfd0 660 uart peripheral identification 5 0x0000.0000 ro uartperiphid5 0xfd4 661 uart peripheral identification 6 0x0000.0000 ro uartperiphid6 0xfd8 662 uart peripheral identification 7 0x0000.0000 ro uartperiphid7 0xfdc 663 uart peripheral identification 0 0x0000.0060 ro uartperiphid0 0xfe0 664 uart peripheral identification 1 0x0000.0000 ro uartperiphid1 0xfe4 665 uart peripheral identification 2 0x0000.0018 ro uartperiphid2 0xfe8 666 uart peripheral identification 3 0x0000.0001 ro uartperiphid3 0xfec 667 uart primecell identification 0 0x0000.000d ro uartpcellid0 0xff0 668 uart primecell identification 1 0x0000.00f0 ro uartpcellid1 0xff4 669 uart primecell identification 2 0x0000.0005 ro uartpcellid2 0xff8 670 uart primecell identification 3 0x0000.00b1 ro uartpcellid3 0xffc 13.6 register descriptions the remainder of this section lists and describes the uart registers, in numerical order by address offset. 623 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: uart data (uartdr), offset 0x000 important: this register is read-sensitive. see the register description for details. this register is the data register (the interface to the fifos). for transmitted data, if the fifo is enabled, data written to this location is pushed onto the transmit fifo. if the fifo is disabled, data is stored in the transmitter holding register (the bottom word of the transmit fifo). a write to this register initiates a transmission from the uart. for received data, if the fifo is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive fifo. if the fifo is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive fifo). the received data can be retrieved by reading this register. uart data (uartdr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data fe pe be oe reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 uart overrun error description value new data was received when the fifo was full, resulting in data loss. 1 no data has been lost due to a fifo overrun. 0 0 ro oe 11 uart break error description value a break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 1 no break condition has occurred 0 in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the received data input goes to a 1 (marking state), and the next valid start bit is received. 0 ro be 10 march 20, 2011 624 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart parity error description value the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register. 1 no parity error has occurred 0 in fifo mode, this error is associated with the character at the top of the fifo. 0 ro pe 9 uart framing error description value the received character does not have a valid stop bit (a valid stop bit is 1). 1 no framing error has occurred 0 0 ro fe 8 data transmitted or received data that is to be transmitted via the uart is written to this field. when read, this field contains the data that was received by the uart. 0x00 r/w data 7:0 625 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: uart receive status/error clear (uartrsr/uartecr), offset 0x004 the uartrsr/uartecr register is the receive status register/error clear register. in addition to the uartdr register, receive status can also be read from the uartrsr register. if the status is read from this register, then the status information corresponds to the entry read from uartdr prior to reading uartrsr . the status information for overrun is set immediately when an overrun condition occurs. the uartrsr register cannot be written. a write of any value to the uartecr register clears the framing, parity, break, and overrun errors. all the bits are cleared on reset. read-only status register uart receive status/error clear (uartrsr/uartecr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fe pe be oe reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 uart overrun error description value new data was received when the fifo was full, resulting in data loss. 1 no data has been lost due to a fifo overrun. 0 this bit is cleared by a write to uartecr . the fifo contents remain valid because no further data is written when the fifo is full, only the contents of the shift register are overwritten. the cpu must read the data in order to empty the fifo. 0 ro oe 3 march 20, 2011 626 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart break error description value a break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 1 no break condition has occurred 0 this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0 ro be 2 uart parity error description value the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register. 1 no parity error has occurred 0 this bit is cleared to 0 by a write to uartecr . 0 ro pe 1 uart framing error description value the received character does not have a valid stop bit (a valid stop bit is 1). 1 no framing error has occurred 0 this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. 0 ro fe 0 write-only error clear register uart receive status/error clear (uartrsr/uartecr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x004 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 627 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 wo reserved 31:8 error clear a write to this register of any data clears the framing, parity, break, and overrun flags. 0x00 wo data 7:0 march 20, 2011 628 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 3: uart flag (uartfr), offset 0x018 the uartfr register is the flag register. after reset, the txff, rxff , and busy bits are 0, and txfe and rxfe bits are 1. the ri, dcd, dsr and cts bits indicate the modem status. note that bits [8,2:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart flag (uartfr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x018 type ro, reset 0x0000.0090 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cts dsr dcd busy rxfe txff rxff txfe ri reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 ring indicator description value the u1ri signal is asserted. 1 the u1ri signal is not asserted. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro ri 8 uart transmit fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register. description value if the fifo is disabled ( fen is 0), the transmit holding register is empty. if the fifo is enabled ( fen is 1), the transmit fifo is empty. 1 the transmitter has data to transmit. 0 1 ro txfe 7 629 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field uart receive fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register. description value if the fifo is disabled ( fen is 0), the receive holding register is full. if the fifo is enabled ( fen is 1), the receive fifo is full. 1 the receiver can receive data. 0 0 ro rxff 6 uart transmit fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register. description value if the fifo is disabled ( fen is 0), the transmit holding register is full. if the fifo is enabled ( fen is 1), the transmit fifo is full. 1 the transmitter is not full. 0 0 ro txff 5 uart receive fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register. description value if the fifo is disabled ( fen is 0), the receive holding register is empty. if the fifo is enabled ( fen is 1), the receive fifo is empty. 1 the receiver is not empty. 0 1 ro rxfe 4 uart busy description value the uart is busy transmitting data. this bit remains set until the complete byte, including all stop bits, has been sent from the shift register. 1 the uart is not busy. 0 this bit is set as soon as the transmit fifo becomes non-empty (regardless of whether uart is enabled). 0 ro busy 3 data carrier detect description value the u1dcd signal is asserted. 1 the u1dcd signal is not asserted. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dcd 2 march 20, 2011 630 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) description reset type name bit/field data set ready description value the u1dsr signal is asserted. 1 the u1dsr signal is not asserted. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dsr 1 clear to send description value the u1cts signal is asserted. 1 the u1cts signal is not asserted. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro cts 0 631 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: uart irda low-power register (uartilpr), offset 0x020 the uartilpr register stores the 8-bit low-power counter divisor value used to derive the low-power sir pulse width clock by dividing down the system clock (sysclk). all the bits are cleared when reset. the internal irlpbaud16 clock is generated by dividing down sysclk according to the low-power divisor value written to uartilpr . the duration of sir pulses generated when low-power mode is enabled is three times the period of the irlpbaud16 clock. the low-power divisor value is calculated as follows: ilpdvsr = sysclk / f irlpbaud16 where f irlpbaud16 is nominally 1.8432 mhz. the divisor must be programmed such that 1.42 mhz < f irlpbaud16 < 2.12 mhz, resulting in a low-power pulse duration of 1.41C2.11 s (three times the period of irlpbaud16 ). the minimum frequency of irlpbaud16 ensures that pulses less than one period of irlpbaud16 are rejected, but pulses greater than 1.4 s are accepted as valid pulses. note: zero is an illegal value. programming a zero value results in no irlpbaud16 pulses being generated. uart irda low-power register (uartilpr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ilpdvsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 irda low-power divisor this field contains the 8-bit low-power divisor value. 0x00 r/w ilpdvsr 7:0 march 20, 2011 632 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 5: uart integer baud-rate divisor (uartibrd), offset 0x024 the uartibrd register is the integer part of the baud-rate divisor value. all the bits are cleared on reset. the minimum possible divide ratio is 1 (when uartibrd =0), in which case the uartfbrd register is ignored. when changing the uartibrd register, the new value does not take effect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register. see baud-rate generation on page 614 for configuration details. uart integer baud-rate divisor (uartibrd) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 divint r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 integer baud-rate divisor 0x0000 r/w divint 15:0 633 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 6: uart fractional baud-rate divisor (uartfbrd), offset 0x028 the uartfbrd register is the fractional part of the baud-rate divisor value. all the bits are cleared on reset. when changing the uartfbrd register, the new value does not take effect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register. see baud-rate generation on page 614 for configuration details. uart fractional baud-rate divisor (uartfbrd) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x028 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 divfrac reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:6 fractional baud-rate divisor 0x0 r/w divfrac 5:0 march 20, 2011 634 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 7: uart line control (uartlcrh), offset 0x02c the uartlcrh register is the line control register. serial parameters such as data length, parity, and stop bit selection are implemented in this register. when updating the baud-rate divisor ( uartibrd and/or uartifrd ), the uartlcrh register must also be written. the write strobe for the baud-rate divisor registers is tied to the uartlcrh register. uart line control (uartlcrh) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x02c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 brk pen eps stp2 fen wlen sps reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart stick parity select when bits 1, 2, and 7 of uartlcrh are set, the parity bit is transmitted and checked as a 0. when bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. when this bit is cleared, stick parity is disabled. 0 r/w sps 7 uart word length the bits indicate the number of data bits transmitted or received in a frame as follows: description value 5 bits (default) 0x0 6 bits 0x1 7 bits 0x2 8 bits 0x3 0x0 r/w wlen 6:5 uart enable fifos description value the transmit and receive fifo buffers are enabled (fifo mode). 1 the fifos are disabled (character mode). the fifos become 1-byte-deep holding registers. 0 0 r/w fen 4 635 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field uart two stop bits select description value two stop bits are transmitted at the end of a frame. the receive logic does not check for two stop bits being received. when in 7816 smartcard mode (the smart bit is set in the uartctl register), the number of stop bits is forced to 2. 1 one stop bit is transmitted at the end of a frame. 0 0 r/w stp2 3 uart even parity select description value even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 1 odd parity is performed, which checks for an odd number of 1s. 0 this bit has no effect when parity is disabled by the pen bit. 0 r/w eps 2 uart parity enable description value parity checking and generation is enabled. 1 parity is disabled and no parity bit is added to the data frame. 0 0 r/w pen 1 uart send break description value a low level is continually output on the untx signal, after completing transmission of the current character. for the proper execution of the break command, software must set this bit for at least two frames (character periods). 1 normal use. 0 0 r/w brk 0 march 20, 2011 636 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 8: uart control (uartctl), offset 0x030 the uartctl register is the control register. all the bits are cleared on reset except for the transmit enable ( txe ) and receive enable (rxe ) bits, which are set. to enable the uart module, the uarten bit must be set. if software requires a configuration change in the module, the uarten bit must be cleared before the configuration changes are written. if the uart is disabled during a transmit or receive operation, the current transaction is completed prior to the uart stopping. note that bits [15:14,11:10] are only implemented on uart1. these bits are reserved on uart0 and uart2. note: the uartctl register should not be changed while the uart is enabled or else the results are unpredictable. the following sequence is recommended for making changes to the uartctl register. 1. disable the uart. 2. wait for the end of transmission or reception of the current character. 3. flush the transmit fifo by clearing bit 4 ( fen ) in the line control register (uartlcrh ). 4. reprogram the control register. 5. enable the uart. uart control (uartctl) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x030 type r/w, reset 0x0000.0300 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uarten siren sirlp smart eot hse lin lbe txe rxe dtr rts reserved rtsen ctsen r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro r/w r/w type 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 637 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field enable clear to send description value cts hardware flow control is enabled. data is only transmitted when the u1cts signal is asserted. 1 cts hardware flow control is disabled. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w ctsen 15 enable request to send description value rts hardware flow control is enabled. data is only requested (by asserting u1rts ) when the receive fifo has available entries. 1 rts hardware flow control is disabled. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w rtsen 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13:12 request to send when rtsen is clear, the status of this bit is reflected on the u1rts signal. if rtsen is set, this bit is ignored on a write and should be ignored on read. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w rts 11 data terminal ready this bit sets the state of the u1dtr output. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w dtr 10 uart receive enable description value the receive section of the uart is enabled. 1 the receive section of the uart is disabled. 0 if the uart is disabled in the middle of a receive, it completes the current character before stopping. note: to enable reception, the uarten bit must also be set. 1 r/w rxe 9 march 20, 2011 638 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart transmit enable description value the transmit section of the uart is enabled. 1 the transmit section of the uart is disabled. 0 if the uart is disabled in the middle of a transmission, it completes the current character before stopping. note: to enable transmission, the uarten bit must also be set. 1 r/w txe 8 uart loop back enable description value the untx path is fed through the unrx path. 1 normal operation. 0 0 r/w lbe 7 lin mode enable description value the uart operates in lin mode. 1 normal operation. 0 0 r/w lin 6 high-speed enable description value the uart is clocked using the system clock divided by 16. 0 the uart is clocked using the system clock divided by 8. 1 note: system clock used is also dependent on the baud-rate divisor configuration (see page 633) and page 634). 0 r/w hse 5 end of transmission this bit determines the behavior of the txris bit in the uartris register. description value the txris bit is set only after all transmitted data, including stop bits, have cleared the serializer. 1 the txris bit is set when the transmit fifo condition specified in uartifls is met. 0 0 r/w eot 4 639 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field iso 7816 smart card support description value the uart operates in smart card mode. 1 normal operation. 0 the application must ensure that it sets 8-bit word length ( wlen set to 0x3) and even parity ( pen set to 1, eps set to 1, sps set to 0) in uartlcrh when using iso 7816 mode. in this mode, the value of the stp2 bit in uartlcrh is ignored and the number of stop bits is forced to 2. note that the uart does not support automatic retransmission on parity errors. if a parity error is detected on transmission, all further transmit operations are aborted and software must handle retransmission of the affected byte or message. 0 r/w smart 3 uart sir low-power mode this bit selects the irda encoding mode. description value the uart operates in sir low-power mode. low-level bits are transmitted with a pulse width which is 3 times the period of the irlpbaud16 input signal, regardless of the selected bit rate. 1 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. 0 setting this bit uses less power, but might reduce transmission distances. see page 632 for more information. 0 r/w sirlp 2 uart sir enable description value the irda sir block is enabled, and the uart will transmit and receive data using sir protocol. 1 normal operation. 0 0 r/w siren 1 uart enable description value the uart is enabled. 1 the uart is disabled. 0 if the uart is disabled in the middle of transmission or reception, it completes the current character before stopping. 0 r/w uarten 0 march 20, 2011 640 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 9: uart interrupt fifo level select (uartifls), offset 0x034 the uartifls register is the interrupt fifo level select register. you can use this register to define the fifo level at which the txris and rxris bits in the uartris register are triggered. the interrupts are generated based on a transition through a level rather than being based on the level. that is, the interrupts are generated when the fill level progresses through the trigger level. for example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. out of reset, the txiflsel and rxiflsel bits are configured so that the fifos trigger an interrupt at the half-way mark. uart interrupt fifo level select (uartifls) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x034 type r/w, reset 0x0000.0012 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txiflsel rxiflsel reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 uart receive interrupt fifo level select the trigger points for the receive interrupt are as follows: description value rx fifo ? full 0x0 rx fifo ? full 0x1 rx fifo ? full (default) 0x2 rx fifo ? full 0x3 rx fifo ? full 0x4 reserved 0x5-0x7 0x2 r/w rxiflsel 5:3 641 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field uart transmit interrupt fifo level select the trigger points for the transmit interrupt are as follows: description value tx fifo ? empty 0x0 tx fifo ? empty 0x1 tx fifo ? empty (default) 0x2 tx fifo ? empty 0x3 tx fifo ? empty 0x4 reserved 0x5-0x7 note: if the eot bit in uartctl is set (see page 637), the transmit interrupt is generated once the fifo is completely empty and all data including stop bits have left the transmit serializer. in this case, the setting of txiflsel is ignored. 0x2 r/w txiflsel 2:0 march 20, 2011 642 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 10: uart interrupt mask (uartim), offset 0x038 the uartim register is the interrupt mask set/clear register. on a read, this register gives the current value of the mask on the relevant interrupt. setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller. note that bits [3:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart interrupt mask (uartim) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 riim ctsim dcdim dsrim rxim txim rtim feim peim beim oeim reserved lmsbim lme1im lme5im r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 lin mode edge 5 interrupt mask description value an interrupt is sent to the interrupt controller when the lme5ris bit in the uartris register is set. 1 the lme5ris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w lme5im 15 lin mode edge 1 interrupt mask description value an interrupt is sent to the interrupt controller when the lme1ris bit in the uartris register is set. 1 the lme1ris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w lme1im 14 lin mode sync break interrupt mask description value an interrupt is sent to the interrupt controller when the lmsbris bit in the uartris register is set. 1 the lmsbris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w lmsbim 13 643 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:11 uart overrun error interrupt mask description value an interrupt is sent to the interrupt controller when the oeris bit in the uartris register is set. 1 the oeris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w oeim 10 uart break error interrupt mask description value an interrupt is sent to the interrupt controller when the beris bit in the uartris register is set. 1 the beris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w beim 9 uart parity error interrupt mask description value an interrupt is sent to the interrupt controller when the peris bit in the uartris register is set. 1 the peris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w peim 8 uart framing error interrupt mask description value an interrupt is sent to the interrupt controller when the feris bit in the uartris register is set. 1 the feris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w feim 7 uart receive time-out interrupt mask description value an interrupt is sent to the interrupt controller when the rtris bit in the uartris register is set. 1 the rtris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w rtim 6 march 20, 2011 644 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart transmit interrupt mask description value an interrupt is sent to the interrupt controller when the txris bit in the uartris register is set. 1 the txris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w txim 5 uart receive interrupt mask description value an interrupt is sent to the interrupt controller when the rxris bit in the uartris register is set. 1 the rxris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w rxim 4 uart data set ready modem interrupt mask description value an interrupt is sent to the interrupt controller when the dsrris bit in the uartris register is set. 1 the dsrris interrupt is suppressed and not sent to the interrupt controller. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w dsrim 3 uart data carrier detect modem interrupt mask description value an interrupt is sent to the interrupt controller when the dcdris bit in the uartris register is set. 1 the dcdris interrupt is suppressed and not sent to the interrupt controller. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w dcdim 2 uart clear to send modem interrupt mask description value an interrupt is sent to the interrupt controller when the ctsris bit in the uartris register is set. 1 the ctsris interrupt is suppressed and not sent to the interrupt controller. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w ctsim 1 645 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field uart ring indicator modem interrupt mask description value an interrupt is sent to the interrupt controller when the riris bit in the uartris register is set. 1 the riris interrupt is suppressed and not sent to the interrupt controller. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w riim 0 march 20, 2011 646 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 11: uart raw interrupt status (uartris), offset 0x03c the uartris register is the raw interrupt status register. on a read, this register gives the current raw status value of the corresponding interrupt. a write has no effect. note that bits [3:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart raw interrupt status (uartris) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x03c type ro, reset 0x0000.000f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 riris ctsris dcdris dsrris rxris txris rtris feris peris beris oeris reserved lmsbris lme1ris lme5ris ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 lin mode edge 5 raw interrupt status description value the timer value at the 5th falling edge of the lin sync field has been captured. 1 no interrupt 0 this bit is cleared by writing a 1 to the lme5ic bit in the uarticr register. 0 ro lme5ris 15 lin mode edge 1 raw interrupt status description value the timer value at the 1st falling edge of the lin sync field has been captured. 1 no interrupt 0 this bit is cleared by writing a 1 to the lme1ic bit in the uarticr register. 0 ro lme1ris 14 lin mode sync break raw interrupt status description value a lin sync break has been detected. 1 no interrupt 0 this bit is cleared by writing a 1 to the lmsbic bit in the uarticr register. 0 ro lmsbris 13 647 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:11 uart overrun error raw interrupt status description value an overrun error has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the oeic bit in the uarticr register. 0 ro oeris 10 uart break error raw interrupt status description value a break error has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the beic bit in the uarticr register. 0 ro beris 9 uart parity error raw interrupt status description value a parity error has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the peic bit in the uarticr register. 0 ro peris 8 uart framing error raw interrupt status description value a framing error has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the feic bit in the uarticr register. 0 ro feris 7 uart receive time-out raw interrupt status description value a receive time out has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the rtic bit in the uarticr register. 0 ro rtris 6 uart transmit raw interrupt status description value if the eot bit in the uartctl register is clear, the transmit fifo level has passed through the condition defined in the uartifls register. if the eot bit is set, the last bit of all transmitted data and flags has left the serializer. 1 no interrupt 0 this bit is cleared by writing a 1 to the txic bit in the uarticr register. 0 ro txris 5 march 20, 2011 648 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart receive raw interrupt status description value the receive fifo level has passed through the condition defined in the uartifls register. 1 no interrupt 0 this bit is cleared by writing a 1 to the rxic bit in the uarticr register. 0 ro rxris 4 uart data set ready modem raw interrupt status description value data set ready used for software flow control. 1 no interrupt 0 this bit is cleared by writing a 1 to the dsric bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dsrris 3 uart data carrier detect modem raw interrupt status description value data carrier detect used for software flow control. 1 no interrupt 0 this bit is cleared by writing a 1 to the dcdic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dcdris 2 uart clear to send modem raw interrupt status description value clear to send used for software flow control. 1 no interrupt 0 this bit is cleared by writing a 1 to the ctsic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro ctsris 1 uart ring indicator modem raw interrupt status description value ring indicator used for software flow control. 1 no interrupt 0 this bit is cleared by writing a 1 to the riic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro riris 0 649 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: uart masked interrupt status (uartmis), offset 0x040 the uartmis register is the masked interrupt status register. on a read, this register gives the current masked status value of the corresponding interrupt. a write has no effect. note that bits [3:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart masked interrupt status (uartmis) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x040 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rimis ctsmis dcdmis dsrmis rxmis txmis rtmis femis pemis bemis oemis reserved lmsbmis lme1mis lme5mis ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 lin mode edge 5 masked interrupt status description value an unmasked interrupt was signaled due to the 5th falling edge of the lin sync field. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the lme5ic bit in the uarticr register. 0 ro lme5mis 15 lin mode edge 1 masked interrupt status description value an unmasked interrupt was signaled due to the 1st falling edge of the lin sync field. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the lme1ic bit in the uarticr register. 0 ro lme1mis 14 lin mode sync break masked interrupt status description value an unmasked interrupt was signaled due to the receipt of a lin sync break. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the lmsbic bit in the uarticr register. 0 ro lmsbmis 13 march 20, 2011 650 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:11 uart overrun error masked interrupt status description value an unmasked interrupt was signaled due to an overrun error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the oeic bit in the uarticr register. 0 ro oemis 10 uart break error masked interrupt status description value an unmasked interrupt was signaled due to a break error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the beic bit in the uarticr register. 0 ro bemis 9 uart parity error masked interrupt status description value an unmasked interrupt was signaled due to a parity error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the peic bit in the uarticr register. 0 ro pemis 8 uart framing error masked interrupt status description value an unmasked interrupt was signaled due to a framing error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the feic bit in the uarticr register. 0 ro femis 7 uart receive time-out masked interrupt status description value an unmasked interrupt was signaled due to a receive time out. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the rtic bit in the uarticr register. 0 ro rtmis 6 uart transmit masked interrupt status description value an unmasked interrupt was signaled due to passing through the specified transmit fifo level (if the eot bit is clear) or due to the transmission of the last data bit (if the eot bit is set). 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the txic bit in the uarticr register. 0 ro txmis 5 651 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field uart receive masked interrupt status description value an unmasked interrupt was signaled due to passing through the specified receive fifo level. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the rxic bit in the uarticr register. 0 ro rxmis 4 uart data set ready modem masked interrupt status description value an unmasked interrupt was signaled due to data set ready. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the dsric bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dsrmis 3 uart data carrier detect modem masked interrupt status description value an unmasked interrupt was signaled due to data carrier detect. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the dcdic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dcdmis 2 uart clear to send modem masked interrupt status description value an unmasked interrupt was signaled due to clear to send. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the ctsic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro ctsmis 1 uart ring indicator modem masked interrupt status description value an unmasked interrupt was signaled due to ring indicator. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the riic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro rimis 0 march 20, 2011 652 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 13: uart interrupt clear (uarticr), offset 0x044 the uarticr register is the interrupt clear register. on a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. a write of 0 has no effect. note that bits [3:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart interrupt clear (uarticr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x044 type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rimic ctsmic dcdmic dsrmic rxic txic rtic feic peic beic oeic reserved lmsbmic lme1mic lme5mic w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c ro ro w1c w1c w1c type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 lin mode edge 5 interrupt clear writing a 1 to this bit clears the lme5ris bit in the uartris register and the lme5mis bit in the uartmis register. 0 w1c lme5mic 15 lin mode edge 1 interrupt clear writing a 1 to this bit clears the lme1ris bit in the uartris register and the lme1mis bit in the uartmis register. 0 w1c lme1mic 14 lin mode sync break interrupt clear writing a 1 to this bit clears the lmsbris bit in the uartris register and the lmsbmis bit in the uartmis register. 0 w1c lmsbmic 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:11 overrun error interrupt clear writing a 1 to this bit clears the oeris bit in the uartris register and the oemis bit in the uartmis register. 0 w1c oeic 10 break error interrupt clear writing a 1 to this bit clears the beris bit in the uartris register and the bemis bit in the uartmis register. 0 w1c beic 9 parity error interrupt clear writing a 1 to this bit clears the peris bit in the uartris register and the pemis bit in the uartmis register. 0 w1c peic 8 framing error interrupt clear writing a 1 to this bit clears the feris bit in the uartris register and the femis bit in the uartmis register. 0 w1c feic 7 653 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field receive time-out interrupt clear writing a 1 to this bit clears the rtris bit in the uartris register and the rtmis bit in the uartmis register. 0 w1c rtic 6 transmit interrupt clear writing a 1 to this bit clears the txris bit in the uartris register and the txmis bit in the uartmis register. 0 w1c txic 5 receive interrupt clear writing a 1 to this bit clears the rxris bit in the uartris register and the rxmis bit in the uartmis register. 0 w1c rxic 4 uart data set ready modem interrupt clear writing a 1 to this bit clears the dsrris bit in the uartris register and the dsrmis bit in the uartmis register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 w1c dsrmic 3 uart data carrier detect modem interrupt clear writing a 1 to this bit clears the dcdris bit in the uartris register and the dcdmis bit in the uartmis register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 w1c dcdmic 2 uart clear to send modem interrupt clear writing a 1 to this bit clears the ctsris bit in the uartris register and the ctsmis bit in the uartmis register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 w1c ctsmic 1 uart ring indicator modem interrupt clear writing a 1 to this bit clears the riris bit in the uartris register and the rimis bit in the uartmis register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 w1c rimic 0 march 20, 2011 654 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 14: uart dma control (uartdmactl), offset 0x048 the uartdmactl register is the dma control register. uart dma control (uartdmactl) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x048 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxdmae txdmae dmaerr reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00000.000 ro reserved 31:3 dma on error description value dma receive requests are automatically disabled when a receive error occurs. 1 dma receive requests are unaffected when a receive error occurs. 0 0 r/w dmaerr 2 transmit dma enable description value dma for the transmit fifo is enabled. 1 dma for the transmit fifo is disabled. 0 0 r/w txdmae 1 receive dma enable description value dma for the receive fifo is enabled. 1 dma for the receive fifo is disabled. 0 0 r/w rxdmae 0 655 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 15: uart lin control (uartlctl), offset 0x090 the uartlctl register is the configures the operation of the uart when in lin mode. uart lin control (uartlctl) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x090 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 master reserved blen reserved r/w ro ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 sync break length description value sync break length is 16t bits 0x3 sync break length is 15t bits 0x2 sync break length is 14t bits 0x1 sync break length is 13t bits (default) 0x0 0x0 r/w blen 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 lin master enable description value the uart operates as a lin master. 1 the uart operates as a lin slave. 0 0 r/w master 0 march 20, 2011 656 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 16: uart lin snap shot (uartlss), offset 0x094 the uartlss register captures the free-running timer value when either the sync edge 1 or the sync edge 5 is detected in lin mode. uart lin snap shot (uartlss) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x094 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tss ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 timer snap shot this field contains the value of the free-running timer when either the sync edge 5 or the sync edge 1 was detected. 0x0000 ro tss 15:0 657 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 17: uart lin timer (uartltim), offset 0x098 the uartltim register contains the current timer value for the free-running timer that is used to calculate the baud rate when in lin slave mode. the value in this register is used along with the value in the uart lin snap shot (uartlss) register to adjust the baud rate to match that of the master. uart lin timer (uartltim) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x098 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 timer value this field contains the value of the free-running timer. 0x0000 ro timer 15:0 march 20, 2011 658 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 18: uart peripheral identification 4 (uartperiphid4), offset 0xfd0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 4 (uartperiphid4) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfd0 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x00 ro pid4 7:0 659 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 19: uart peripheral identification 5 (uartperiphid5), offset 0xfd4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 5 (uartperiphid5) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfd4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid5 7:0 march 20, 2011 660 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 20: uart peripheral identification 6 (uartperiphid6), offset 0xfd8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 6 (uartperiphid6) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfd8 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x00 ro pid6 7:0 661 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 21: uart peripheral identification 7 (uartperiphid7), offset 0xfdc the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 7 (uartperiphid7) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfdc type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x00 ro pid7 7:0 march 20, 2011 662 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 22: uart peripheral identification 0 (uartperiphid0), offset 0xfe0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 0 (uartperiphid0) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfe0 type ro, reset 0x0000.0060 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x60 ro pid0 7:0 663 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 23: uart peripheral identification 1 (uartperiphid1), offset 0xfe4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 1 (uartperiphid1) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfe4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 march 20, 2011 664 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 24: uart peripheral identification 2 (uartperiphid2), offset 0xfe8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 2 (uartperiphid2) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfe8 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 665 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 25: uart peripheral identification 3 (uartperiphid3), offset 0xfec the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 3 (uartperiphid3) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfec type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 march 20, 2011 666 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 26: uart primecell identification 0 (uartpcellid0), offset 0xff0 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uart primecell identification 0 (uartpcellid0) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 667 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 27: uart primecell identification 1 (uartpcellid1), offset 0xff4 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uart primecell identification 1 (uartpcellid1) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 march 20, 2011 668 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) register 28: uart primecell identification 2 (uartpcellid2), offset 0xff8 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uart primecell identification 2 (uartpcellid2) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xff8 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 669 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 29: uart primecell identification 3 (uartpcellid3), offset 0xffc the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uart primecell identification 3 (uartpcellid3) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 march 20, 2011 670 texas instruments-advance information universal asynchronous receivers/transmitters (uarts) 14 synchronous serial interface (ssi) the stellaris ? microcontroller includes two synchronous serial interface (ssi) modules. each ssi is a master or slave interface for synchronous serial communication with peripheral devices that have either freescale spi, microwire, or texas instruments synchronous serial interfaces. the stellaris lm3s1p51 controller includes two ssi modules with the following features: programmable interface operation for freescale spi, microwire, or texas instruments synchronous serial interfaces master or slave operation programmable clock bit rate and prescaler separate transmit and receive fifos, each 16 bits wide and 8 locations deep programmable data frame size from 4 to 16 bits internal loopback test mode for diagnostic/debug testing standard fifo-based interrupts and end-of-transmission interrupt efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive single request asserted when data is in the fifo; burst request asserted when fifo contains 4 entries C transmit single request asserted when there is space in the fifo; burst request asserted when fifo contains 4 entries 671 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 14.1 block diagram figure 14-1. ssi module block diagram 14.2 signal description table 14-1 on page 673 and table 14-2 on page 673 list the external signals of the ssi module and describe the function of each. the ssi signals are alternate functions for some gpio signals and default to be gpio signals at reset., with the exception of the ssi0clk, ssi0fss, ssi0rx , and ssi0tx pins which default to the ssi function. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the ssi signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the ssi march 20, 2011 672 texas instruments-advance information synchronous serial interface (ssi) , g h q w l i l f d w l r q 5 h j l v w h u v 6 6 , 3 & h o o , ' 6 6 , 3 & h o o , ' 6 6 , 3 & h o o , ' 6 6 , 3 & h o o , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' & o r f n 3 u h v f d o h u 6 6 , & 3 6 5 & r q w u r o 6 w d w x v , q w h u u x s w & r q w u r o 6 6 , ' 5 7 [ ) , ) 2 [ 5 [ ) , ) 2 [ 7 u d q v p l w 5 h f h l y h / r j l f 6 6 , 7 [ 6 6 , 5 [ 6 6 , & o n 6 6 , ) v v ' 0 $ & r q w u r o 6 6 , ' 0 $ & 7 / ' 0 $ 5 h t x h v w , q w h u u x s w 6 \ v w h p & o r f n 6 6 , 6 5 6 6 , & 5 6 6 , & 5 6 6 , 5 , 6 6 6 , 0 , 6 6 6 , , 0 6 6 , , & 5 function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the ssi signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. table 14-1. signals for ssi (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name ssi module 0 clock. ttl i/o pa2 (1) 28 ssi0clk ssi module 0 frame. ttl i/o pa3 (1) 29 ssi0fss ssi module 0 receive. ttl i pa4 (1) 30 ssi0rx ssi module 0 transmit. ttl o pa5 (1) 31 ssi0tx ssi module 1 clock. ttl i/o pf2 (9) pe0 (2) ph4 (11) 60 74 76 ssi1clk ssi module 1 frame. ttl i/o pf3 (9) ph5 (11) pe1 (2) 59 63 75 ssi1fss ssi module 1 receive. ttl i pf4 (9) ph6 (11) pe2 (2) 58 62 95 ssi1rx ssi module 1 transmit. ttl o ph7 (11) pf5 (9) pe3 (2) 15 46 96 ssi1tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 14-2. signals for ssi (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name ssi module 0 clock. ttl i/o pa2 (1) m4 ssi0clk ssi module 0 frame. ttl i/o pa3 (1) l4 ssi0fss ssi module 0 receive. ttl i pa4 (1) l5 ssi0rx ssi module 0 transmit. ttl o pa5 (1) m5 ssi0tx ssi module 1 clock. ttl i/o pf2 (9) pe0 (2) ph4 (11) j11 b11 b10 ssi1clk ssi module 1 frame. ttl i/o pf3 (9) ph5 (11) pe1 (2) j12 f10 a12 ssi1fss ssi module 1 receive. ttl i pf4 (9) ph6 (11) pe2 (2) l9 g3 a4 ssi1rx ssi module 1 transmit. ttl o ph7 (11) pf5 (9) pe3 (2) h3 l8 b4 ssi1tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. 14.3 functional description the ssi performs serial-to-parallel conversion on data received from a peripheral device. the cpu accesses data, control, and status information. the transmit and receive paths are buffered with 673 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller internal fifo memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. the ssi also supports the dma interface. the transmit and receive fifos can be programmed as destination/source addresses in the dma module. dma operation is enabled by setting the appropriate bit(s) in the ssidmactl register (see page 701). 14.3.1 bit rate generation the ssi includes a programmable bit rate clock divider and prescaler to generate the serial output clock. bit rates are supported to 2 mhz and higher, although maximum bit rate is determined by peripheral devices. the serial bit rate is derived by dividing down the input clock (sysclk). the clock is first divided by an even prescale value cpsdvsr from 2 to 254, which is programmed in the ssi clock prescale (ssicpsr) register (see page 694). the clock is further divided by a value from 1 to 256, which is 1 + scr , where scr is the value programmed in the ssi control 0 (ssicr0) register (see page 687). the frequency of the output clock ssiclk is defined by: ssiclk = sysclk / (cpsdvsr * (1 + scr)) note: for master mode, the system clock must be at least two times faster than the ssiclk , with the restriction that ssiclk cannot be faster than 25 mhz. for slave mode, the system clock must be at least 12 times faster than the ssiclk. see synchronous serial interface (ssi) on page 981 to view ssi timing parameters. 14.3.2 fifo operation 14.3.2.1 transmit fifo the common transmit fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. the cpu writes data to the fifo by writing the ssi data (ssidr) register (see page 691), and data is stored in the fifo until it is read out by the transmission logic. when configured as a master or a slave, parallel data is written into the transmit fifo prior to serial conversion and transmission to the attached slave or master, respectively, through the ssitx pin. in slave mode, the ssi transmits data each time the master initiates a transaction. if the transmit fifo is empty and the master initiates, the slave transmits the 8th most recent value in the transmit fifo. if less than 8 values have been written to the transmit fifo since the ssi module clock was enabled using the ssi bit in the rgcg1 register, then 0 is transmitted. care should be taken to ensure that valid data is in the fifo as needed. the ssi can be configured to generate an interrupt or a dma request when the fifo is empty. 14.3.2.2 receive fifo the common receive fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. received data from the serial interface is stored in the buffer until read out by the cpu, which accesses the read fifo by reading the ssidr register. when configured as a master or slave, serial data received through the ssirx pin is registered prior to parallel loading into the attached slave or master receive fifo, respectively. 14.3.3 interrupts the ssi can generate interrupts when the following conditions are observed: transmit fifo service (when the transmit fifo is half full or less) march 20, 2011 674 texas instruments-advance information synchronous serial interface (ssi) receive fifo service (when the receive fifo is half full or more) receive fifo time-out receive fifo overrun end of transmission all of the interrupt events are ored together before being sent to the interrupt controller, so the ssi generates a single interrupt request to the controller regardless of the number of active interrupts. each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the ssi interrupt mask (ssiim) register (see page 695). setting the appropriate mask bit enables the interrupt. the individual outputs, along with a combined interrupt output, allow use of either a global interrupt service routine or modular device drivers to handle interrupts. the transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the fifo trigger levels. the status of the individual interrupt sources can be read from the ssi raw interrupt status (ssiris) and ssi masked interrupt status (ssimis) registers (see page 696 and page 698, respectively). the receive fifo has a time-out period that is 32 periods at the rate of ssiclk (whether or not ssiclk is currently active) and is started when the rx fifo goes from empty to not-empty. if the rx fifo is emptied before 32 clocks have passed, the time-out period is reset. as a result, the isr should clear the receive fifo time-out interrupt just after reading out the rx fifo by writing a 1 to the rtic bit in the ssi interrupt clear (ssiicr) register. the interrupt should not be cleared so late that the isr returns before the interrupt is actually cleared, or the isr may be re-activated unnecessarily. the end-of-transmission (eot) interrupt indicates that the data has been transmitted completely. this interrupt can be used to indicate when it is safe to turn off the ssi module clock or enter sleep mode. in addition, because transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read data is ready immediately, without waiting for the receive fifo time-out period to complete. 14.3.4 frame formats each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the msb. there are three basic frame types that can be selected: texas instruments synchronous serial freescale spi microwire for all three formats, the serial clock ( ssiclk ) is held inactive while the ssi is idle, and ssiclk transitions at the programmed frequency only during active transmission or reception of data. the idle state of ssiclk is utilized to provide a receive timeout indication that occurs when the receive fifo still contains data after a timeout period. for freescale spi and microwire frame formats, the serial frame ( ssifss ) pin is active low, and is asserted (pulled down) during the entire transmission of the frame. for texas instruments synchronous serial frame format, the ssifss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. for this frame format, 675 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller both the ssi and the off-chip slave device drive their output data on the rising edge of ssiclk and latch data from the other device on the falling edge. unlike the full-duplex transmission of the other two frame formats, the microwire format uses a special master-slave messaging technique which operates at half-duplex. in this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. during this transmit, no incoming data is received by the ssi. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. the returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 14.3.4.1 texas instruments synchronous serial frame format figure 14-2 on page 676 shows the texas instruments synchronous serial frame format for a single transmitted frame. figure 14-2. ti synchronous serial frame format (single transfer) in this mode, ssiclk and ssifss are forced low, and the transmit data line ssitx is tristated whenever the ssi is idle. once the bottom entry of the transmit fifo contains data, ssifss is pulsed high for one ssiclk period. the value to be transmitted is also transferred from the transmit fifo to the serial shift register of the transmit logic. on the next rising edge of ssiclk , the msb of the 4 to 16-bit data frame is shifted out on the ssitx pin. likewise, the msb of the received data is shifted onto the ssirx pin by the off-chip serial slave device. both the ssi and the off-chip serial slave device then clock each data bit into their serial shifter on each falling edge of ssiclk . the received data is transferred from the serial shifter to the receive fifo on the first rising edge of ssiclk after the lsb has been latched. figure 14-3 on page 677 shows the texas instruments synchronous serial frame format when back-to-back frames are transmitted. march 20, 2011 676 texas instruments-advance information synchronous serial interface (ssi) 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ 0 6 % / 6 % w r e l w v figure 14-3. ti synchronous serial frame format (continuous transfer) 14.3.4.2 freescale spi frame format the freescale spi interface is a four-wire interface where the ssifss signal behaves as a slave select. the main feature of the freescale spi format is that the inactive state and phase of the ssiclk signal are programmable through the spo and sph bits in the ssiscr0 control register. spo clock polarity bit when the spo clock polarity control bit is clear, it produces a steady state low value on the ssiclk pin. if the spo bit is set, a steady state high value is placed on the ssiclk pin when data is not being transferred. sph phase control bit the sph phase control bit selects the clock edge that captures data and allows it to change state. the state of this bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph phase control bit is clear, data is captured on the first clock edge transition. if the sph bit is set, data is captured on the second clock edge transition. 14.3.4.3 freescale spi frame format with spo=0 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo =0 and sph =0 are shown in figure 14-4 on page 677 and figure 14-5 on page 678. figure 14-4. freescale spi format (single transfer) with spo=0 and sph=0 note: q is undefined. 677 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 4 6 6 , 7 [ 0 6 % 0 6 % / 6 % / 6 % w r e l w v 0 6 % / 6 % 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ w r e l w v figure 14-5. freescale spi format (continuous transfer) with spo=0 and sph=0 in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master, it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and valid data is in the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low, causing slave data to be enabled onto the ssirx input line of the master. the master ssitx output pad is enabled. one half ssiclk period later, valid master data is transferred to the ssitx pin. once both the master and slave data have been set, the ssiclk master clock pin goes high after one additional half ssiclk period. the data is now captured on the rising and propagated on the falling edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however, in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is clear. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. 14.3.4.4 freescale spi frame format with spo=0 and sph=1 the transfer signal sequence for freescale spi format with spo =0 and sph =1 is shown in figure 14-6 on page 679, which covers both single and continuous transfers. march 20, 2011 678 texas instruments-advance information synchronous serial interface (ssi) 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ / 6 % 6 6 , 7 [ 0 6 % / 6 % / 6 % 0 6 % 0 6 % 0 6 % / 6 % w r e l w v figure 14-6. freescale spi frame format with spo=0 and sph=1 note: q is undefined. in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master, it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and valid data is in the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. the master ssitx output is enabled. after an additional one-half ssiclk period, both master and slave valid data are enabled onto their respective transmission lines. at the same time, the ssiclk is enabled with a rising edge transition. data is then captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transfer, after all bits have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transfers, the ssifss pin is held low between successive data words, and termination is the same as that of the single word transfer. 14.3.4.5 freescale spi frame format with spo=1 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo =1 and sph =0 are shown in figure 14-7 on page 679 and figure 14-8 on page 680. figure 14-7. freescale spi frame format (single transfer) with spo=1 and sph=0 note: q is undefined. 679 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 6 6 , 7 [ 4 0 6 % 0 6 % / 6 % / 6 % w r e l w v 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 6 6 , 7 [ 4 0 6 % 4 0 6 % / 6 % / 6 % w r e l w v 4 figure 14-8. freescale spi frame format (continuous transfer) with spo=1 and sph=0 in this configuration, during idle periods: ssiclk is forced high ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master, it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and valid data is in the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low, causing slave data to be immediately transferred onto the ssirx line of the master. the master ssitx output pad is enabled. one-half period later, valid master data is transferred to the ssitx line. once both the master and slave data have been set, the ssiclk master clock pin becomes low after one additional half ssiclk period, meaning that data is captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word are transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however, in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is clear. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. 14.3.4.6 freescale spi frame format with spo=1 and sph=1 the transfer signal sequence for freescale spi format with spo =1 and sph =1 is shown in figure 14-9 on page 681, which covers both single and continuous transfers. march 20, 2011 680 texas instruments-advance information synchronous serial interface (ssi) 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ 0 6 % / 6 % / 6 % 0 6 % w r e l w v figure 14-9. freescale spi frame format with spo=1 and sph=1 note: q is undefined. in this configuration, during idle periods: ssiclk is forced high ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master, it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and valid data is in the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. the master ssitx output pad is enabled. after an additional one-half ssiclk period, both master and slave data are enabled onto their respective transmission lines. at the same time, ssiclk is enabled with a falling edge transition. data is then captured on the rising edges and propagated on the falling edges of the ssiclk signal. after all bits have been transferred, in the case of a single word transmission, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transmissions, the ssifss pin remains in its active low state until the final bit of the last word has been captured and then returns to its idle state as described above. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer. 14.3.4.7 microwire frame format figure 14-10 on page 681 shows the microwire frame format for a single frame. figure 14-11 on page 682 shows the same format when back-to-back frames are transmitted. figure 14-10. microwire frame format (single frame) 681 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 6 6 , 7 [ e l w f r q w u r o w r e l w v r x w s x w g d w d / 6 % 0 6 % 0 6 % / 6 % 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 6 6 , 7 [ 4 0 6 % 0 6 % / 6 % / 6 % w r e l w v 4 microwire format is very similar to spi format, except that transmission is half-duplex instead of full-duplex and uses a master-slave message passing technique. each serial transmission begins with an 8-bit control word that is transmitted from the ssi to the off-chip slave device. during this transmission, no incoming data is received by the ssi. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low a transmission is triggered by writing a control byte to the transmit fifo. the falling edge of ssifss causes the value contained in the bottom entry of the transmit fifo to be transferred to the serial shift register of the transmit logic and the msb of the 8-bit control frame to be shifted out onto the ssitx pin. ssifss remains low for the duration of the frame transmission. the ssirx pin remains tristated during this transmission. the off-chip serial slave device latches each control bit into its serial shifter on each rising edge of ssiclk . after the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the ssi. each bit is driven onto the ssirx line on the falling edge of ssiclk . the ssi in turn latches each bit on the rising edge of ssiclk . at the end of the frame, for single transfers, the ssifss signal is pulled high one clock period after the last bit has been latched in the receive serial shifter, causing the data to be transferred to the receive fifo. note: the off-chip slave device can tristate the receive line either on the falling edge of ssiclk after the lsb has been latched by the receive shifter or when the ssifss pin goes high. for continuous transfers, data transmission begins and ends in the same manner as a single transfer. however, the ssifss line is continuously asserted (held low) and transmission of data occurs back-to-back. the control byte of the next frame follows directly after the lsb of the received data from the current frame. each of the received values is transferred from the receive shifter on the falling edge of ssiclk , after the lsb of the frame has been latched into the ssi. figure 14-11. microwire frame format (continuous transfer) in the microwire mode, the ssi slave samples the first bit of receive data on the rising edge of ssiclk after ssifss has gone low. masters that drive a free-running ssiclk must ensure that the ssifss signal has sufficient setup and hold margins with respect to the rising edge of ssiclk. march 20, 2011 682 texas instruments-advance information synchronous serial interface (ssi) 6 6 , & o n 6 6 , ) v v / 6 % 0 6 % 6 6 , 5 [ 6 6 , 7 [ / 6 % / 6 % 0 6 % w r e l w v r x w s x w g d w d e l w f r q w u r o 0 6 % figure 14-12 on page 683 illustrates these setup and hold time requirements. with respect to the ssiclk rising edge on which the first bit of receive data is to be sampled by the ssi slave, ssifss must have a setup of at least two times the period of ssiclk on which the ssi operates. with respect to the ssiclk rising edge previous to this edge, ssifss must have a hold of at least one ssiclk period. figure 14-12. microwire frame format, ssifss input setup and hold requirements 14.3.5 dma operation the ssi peripheral provides an interface to the dma controller with separate channels for transmit and receive. the dma operation of the ssi is enabled through the ssi dma control (ssidmactl) register. when dma operation is enabled, the ssi asserts a dma request on the receive or transmit channel when the associated fifo can transfer data. for the receive channel, a single transfer request is asserted whenever any data is in the receive fifo. a burst transfer request is asserted whenever the amount of data in the receive fifo is 4 or more items. for the transmit channel, a single transfer request is asserted whenever at least one empty location is in the transmit fifo. the burst request is asserted whenever the transmit fifo has 4 or more empty slots. the single and burst dma transfer requests are handled automatically by the dma controller depending how the dma channel is configured. to enable dma operation for the receive channel, the rxdmae bit of the dma control (ssidmactl) register should be set. to enable dma operation for the transmit channel, the txdmae bit of ssidmactl should be set. if dma is enabled, then the dma controller triggers an interrupt when a transfer is complete. the interrupt occurs on the ssi interrupt vector. therefore, if interrupts are used for ssi operation and dma is enabled, the ssi interrupt handler must be designed to handle the dma completion interrupt. see micro direct memory access (dma) on page 346 for more details about programming the dma controller. 14.4 initialization and configuration to enable and initialize the ssi, the following steps are necessary: 1. enable the ssi module by setting the ssi bit in the rcgc1 register (see page 260). 2. enable the clock to the appropriate gpio module via the rcgc2 register (see page 269). to find out which gpio port to enable, refer to table 21-5 on page 925. 3. set the gpio afsel bits for the appropriate pins (see page 428). to determine which gpios to configure, see table 21-4 on page 917. 4. configure the pmcn fields in the gpiopctl register to assign the ssi signals to the appropriate pins. see page 446 and table 21-5 on page 925. 683 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ ) l u v w 5 ; g d w d w r e h v d p s o h g e \ 6 6 , v o d y h w 6 h w x s w 6 6 , & o n w + r o g w 6 6 , & o n for each of the frame formats, the ssi is configured using the following steps: 1. ensure that the sse bit in the ssicr1 register is clear before making any configuration changes. 2. select whether the ssi is a master or slave: a. for master operations, set the ssicr1 register to 0x0000.0000. b. for slave mode (output enabled), set the ssicr1 register to 0x0000.0004. c. for slave mode (output disabled), set the ssicr1 register to 0x0000.000c. 3. configure the clock prescale divisor by writing the ssicpsr register. 4. write the ssicr0 register with the following configuration: serial clock rate ( scr) desired clock phase/polarity, if using freescale spi mode ( sph and spo) the protocol mode: freescale spi, ti ssf, microwire ( frf) the data size ( dss) 5. optionally, configure the dma channel (see micro direct memory access (dma) on page 346) and enable the dma option(s) in the ssidmactl register. 6. enable the ssi by setting the sse bit in the ssicr1 register. as an example, assume the ssi must be configured to operate with the following parameters: master operation freescale spi mode (spo=1, sph=1) 1 mbps bit rate 8 data bits assuming the system clock is 20 mhz, the bit rate calculation would be: ssiclk = sysclk / (cpsdvsr * (1 + scr)) 1x106 = 20x106 / (cpsdvsr * (1 + scr)) in this case, if cpsdvsr=0x2, scr must be 0x9. the configuration sequence would be as follows: 1. ensure that the sse bit in the ssicr1 register is clear. 2. write the ssicr1 register with a value of 0x0000.0000. 3. write the ssicpsr register with a value of 0x0000.0002. 4. write the ssicr0 register with a value of 0x0000.09c7. 5. the ssi is then enabled by setting the sse bit in the ssicr1 register. march 20, 2011 684 texas instruments-advance information synchronous serial interface (ssi) 14.5 register map table 14-3 on page 685 lists the ssi registers. the offset listed is a hexadecimal increment to the registers address, relative to that ssi modules base address: ssi0: 0x4000.8000 ssi1: 0x4000.9000 note that the ssi module clock must be enabled before the registers can be programmed (see page 260). there must be a delay of 3 system clocks after the ssi module clock is enabled before any ssi module registers are accessed. note: the ssi must be disabled (see the sse bit in the ssicr1 register) before any of the control registers are reprogrammed. table 14-3. ssi register map see page description reset type name offset 687 ssi control 0 0x0000.0000 r/w ssicr0 0x000 689 ssi control 1 0x0000.0000 r/w ssicr1 0x004 691 ssi data 0x0000.0000 r/w ssidr 0x008 692 ssi status 0x0000.0003 ro ssisr 0x00c 694 ssi clock prescale 0x0000.0000 r/w ssicpsr 0x010 695 ssi interrupt mask 0x0000.0000 r/w ssiim 0x014 696 ssi raw interrupt status 0x0000.0008 ro ssiris 0x018 698 ssi masked interrupt status 0x0000.0000 ro ssimis 0x01c 700 ssi interrupt clear 0x0000.0000 w1c ssiicr 0x020 701 ssi dma control 0x0000.0000 r/w ssidmactl 0x024 702 ssi peripheral identification 4 0x0000.0000 ro ssiperiphid4 0xfd0 703 ssi peripheral identification 5 0x0000.0000 ro ssiperiphid5 0xfd4 704 ssi peripheral identification 6 0x0000.0000 ro ssiperiphid6 0xfd8 705 ssi peripheral identification 7 0x0000.0000 ro ssiperiphid7 0xfdc 706 ssi peripheral identification 0 0x0000.0022 ro ssiperiphid0 0xfe0 707 ssi peripheral identification 1 0x0000.0000 ro ssiperiphid1 0xfe4 708 ssi peripheral identification 2 0x0000.0018 ro ssiperiphid2 0xfe8 709 ssi peripheral identification 3 0x0000.0001 ro ssiperiphid3 0xfec 710 ssi primecell identification 0 0x0000.000d ro ssipcellid0 0xff0 711 ssi primecell identification 1 0x0000.00f0 ro ssipcellid1 0xff4 712 ssi primecell identification 2 0x0000.0005 ro ssipcellid2 0xff8 713 ssi primecell identification 3 0x0000.00b1 ro ssipcellid3 0xffc 685 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 14.6 register descriptions the remainder of this section lists and describes the ssi registers, in numerical order by address offset. march 20, 2011 686 texas instruments-advance information synchronous serial interface (ssi) register 1: ssi control 0 (ssicr0), offset 0x000 the ssicr0 register contains bit fields that control various functions within the ssi module. functionality such as protocol mode, clock rate, and data size are configured in this register. ssi control 0 (ssicr0) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dss frf spo sph scr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 ssi serial clock rate this bit field is used to generate the transmit and receive bit rate of the ssi. the bit rate is: br=ssiclk/(cpsdvsr * (1 + scr)) where cpsdvsr is an even value from 2-254 programmed in the ssicpsr register, and scr is a value from 0-255. 0x00 r/w scr 15:8 ssi serial clock phase this bit is only applicable to the freescale spi format. the sph control bit selects the clock edge that captures data and allows it to change state. this bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. description value data is captured on the first clock edge transition. 0 data is captured on the second clock edge transition. 1 0 r/w sph 7 ssi serial clock polarity description value a steady state low value is placed on the ssiclk pin. 0 a steady state high value is placed on the ssiclk pin when data is not being transferred. 1 0 r/w spo 6 687 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ssi frame format select frame format value freescale spi frame format 0x0 texas instruments synchronous serial frame format 0x1 microwire frame format 0x2 reserved 0x3 0x0 r/w frf 5:4 ssi data size select data size value reserved 0x0-0x2 4-bit data 0x3 5-bit data 0x4 6-bit data 0x5 7-bit data 0x6 8-bit data 0x7 9-bit data 0x8 10-bit data 0x9 11-bit data 0xa 12-bit data 0xb 13-bit data 0xc 14-bit data 0xd 15-bit data 0xe 16-bit data 0xf 0x0 r/w dss 3:0 march 20, 2011 688 texas instruments-advance information synchronous serial interface (ssi) register 2: ssi control 1 (ssicr1), offset 0x004 the ssicr1 register contains bit fields that control various functions within the ssi module. master and slave mode functionality is controlled by this register. ssi control 1 (ssicr1) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lbm sse ms sod eot reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:5 end of transmission description value the txris interrupt indicates that the transmit fifo is half full or less. 0 the end of transmit interrupt mode for the txris interrupt is enabled. 1 0 r/w eot 4 ssi slave mode output disable this bit is relevant only in the slave mode ( ms =1). in multiple-slave systems, it is possible for the ssi master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. in such systems, the txd lines from multiple slaves could be tied together. to operate in such a system, the sod bit can be configured so that the ssi slave does not drive the ssitx pin. description value ssi can drive the ssitx output in slave mode. 0 ssi must not drive the ssitx output in slave mode. 1 0 r/w sod 3 ssi master/slave select this bit selects master or slave mode and can be modified only when the ssi is disabled ( sse=0). description value the ssi is configured as a master. 0 the ssi is configured as a slave. 1 0 r/w ms 2 689 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field ssi synchronous serial port enable description value ssi operation is disabled. 0 ssi operation is enabled. 1 note: this bit must be cleared before any control registers are reprogrammed. 0 r/w sse 1 ssi loopback mode description value normal serial port operation enabled. 0 output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 1 0 r/w lbm 0 march 20, 2011 690 texas instruments-advance information synchronous serial interface (ssi) register 3: ssi data (ssidr), offset 0x008 important: this register is read-sensitive. see the register description for details. the ssidr register is 16-bits wide. when the ssidr register is read, the entry in the receive fifo that is pointed to by the current fifo read pointer is accessed. when a data value is removed by the ssi receive logic from the incoming data frame, it is placed into the entry in the receive fifo pointed to by the current fifo write pointer. when the ssidr register is written to, the entry in the transmit fifo that is pointed to by the write pointer is written to. data values are removed from the transmit fifo one value at a time by the transmit logic. each data value is loaded into the transmit serial shifter, then serially shifted out onto the ssitx pin at the programmed bit rate. when a data size of less than 16 bits is selected, the user must right-justify data written to the transmit fifo. the transmit logic ignores the unused bits. received data less than 16 bits is automatically right-justified in the receive buffer. when the ssi is programmed for microwire frame format, the default size for transmit data is eight bits (the most significant byte is ignored). the receive data size is controlled by the programmer. the transmit fifo and the receive fifo are not cleared even when the sse bit in the ssicr1 register is cleared, allowing the software to fill the transmit fifo before enabling the ssi. ssi data (ssidr) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 ssi receive/transmit data a read operation reads the receive fifo. a write operation writes the transmit fifo. software must right-justify data when the ssi is programmed for a data size that is less than 16 bits. unused bits at the top are ignored by the transmit logic. the receive logic automatically right-justifies the data. 0x0000 r/w data 15:0 691 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: ssi status (ssisr), offset 0x00c the ssisr register contains bits that indicate the fifo fill status and the ssi busy status. ssi status (ssisr) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x00c type ro, reset 0x0000.0003 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tfe tnf rne rff bsy reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 ssi busy bit description value the ssi is idle. 0 the ssi is currently transmitting and/or receiving a frame, or the transmit fifo is not empty. 1 0 ro bsy 4 ssi receive fifo full description value the receive fifo is not full. 0 the receive fifo is full. 1 0 ro rff 3 ssi receive fifo not empty description value the receive fifo is empty. 0 the receive fifo is not empty. 1 0 ro rne 2 ssi transmit fifo not full description value the transmit fifo is full. 0 the transmit fifo is not full. 1 1 ro tnf 1 march 20, 2011 692 texas instruments-advance information synchronous serial interface (ssi) description reset type name bit/field ssi transmit fifo empty description value the transmit fifo is not empty. 0 the transmit fifo is empty. 1 1 ro tfe 0 693 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 5: ssi clock prescale (ssicpsr), offset 0x010 the ssicpsr register specifies the division factor which is used to derive the ssiclk from the system clock. the clock is further divided by a value from 1 to 256, which is 1 + scr. scr is programmed in the ssicr0 register. the frequency of the ssiclk is defined by: ssiclk = sysclk / (cpsdvsr * (1 + scr)) the value programmed into this register must be an even number between 2 and 254. the least-significant bit of the programmed number is hard-coded to zero. if an odd number is written to this register, data read back from this register has the least-significant bit as zero. ssi clock prescale (ssicpsr) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cpsdvsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi clock prescale divisor this value must be an even number from 2 to 254, depending on the frequency of ssiclk . the lsb always returns 0 on reads. 0x00 r/w cpsdvsr 7:0 march 20, 2011 694 texas instruments-advance information synchronous serial interface (ssi) register 6: ssi interrupt mask (ssiim), offset 0x014 the ssiim register is the interrupt mask set or clear register. it is a read/write register and all bits are cleared on reset. on a read, this register gives the current value of the mask on the corresponding interrupt. setting a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. clearing a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller. ssi interrupt mask (ssiim) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rorim rtim rxim txim reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 ssi transmit fifo interrupt mask description value the transmit fifo interrupt is masked. 0 the transmit fifo interrupt is not masked. 1 0 r/w txim 3 ssi receive fifo interrupt mask description value the receive fifo interrupt is masked. 0 the receive fifo interrupt is not masked. 1 0 r/w rxim 2 ssi receive time-out interrupt mask description value the receive fifo time-out interrupt is masked. 0 the receive fifo time-out interrupt is not masked. 1 0 r/w rtim 1 ssi receive overrun interrupt mask description value the receive fifo overrun interrupt is masked. 0 the receive fifo overrun interrupt is not masked. 1 0 r/w rorim 0 695 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 7: ssi raw interrupt status (ssiris), offset 0x018 the ssiris register is the raw interrupt status register. on a read, this register gives the current raw status value of the corresponding interrupt prior to masking. a write has no effect. ssi raw interrupt status (ssiris) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x018 type ro, reset 0x0000.0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rorris rtris rxris txris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 ssi transmit fifo raw interrupt status description value no interrupt. 0 if the eot bit in the ssicr1 register is clear, the transmit fifo is half full or less. if the eot bit is set, the transmit fifo is empty, and the last bit has been transmitted out of the serializer. 1 this bit is cleared when the transmit fifo is more than half full (if the eot bit is clear) or when it has any data in it (if the eot bit is set). 1 ro txris 3 ssi receive fifo raw interrupt status description value no interrupt. 0 the receive fifo is half full or more. 1 this bit is cleared when the receive fifo is less than half full. 0 ro rxris 2 ssi receive time-out raw interrupt status description value no interrupt. 0 the receive time-out has occurred. 1 this bit is cleared when a 1 is written to the rtic bit in the ssi interrupt clear (ssiicr) register. 0 ro rtris 1 march 20, 2011 696 texas instruments-advance information synchronous serial interface (ssi) description reset type name bit/field ssi receive overrun raw interrupt status description value no interrupt. 0 the receive fifo has overflowed 1 this bit is cleared when a 1 is written to the roric bit in the ssi interrupt clear (ssiicr) register. 0 ro rorris 0 697 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 8: ssi masked interrupt status (ssimis), offset 0x01c the ssimis register is the masked interrupt status register. on a read, this register gives the current masked status value of the corresponding interrupt. a write has no effect. ssi masked interrupt status (ssimis) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x01c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rormis rtmis rxmis txmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 ssi transmit fifo masked interrupt status description value an interrupt has not occurred or is masked. 0 an unmasked interrupt was signaled due to the transmit fifo being half full or less (if the eot bit is clear) or due to the transmission of the last data bit (if the eot bit is set). 1 this bit is cleared when the transmit fifo is more than half full (if the eot bit is clear) or when it has any data in it (if the eot bit is set). 0 ro txmis 3 ssi receive fifo masked interrupt status description value an interrupt has not occurred or is masked. 0 an unmasked interrupt was signaled due to the receive fifo being half full or less. 1 this bit is cleared when the receive fifo is less than half full. 0 ro rxmis 2 ssi receive time-out masked interrupt status description value an interrupt has not occurred or is masked. 0 an unmasked interrupt was signaled due to the receive time out. 1 this bit is cleared when a 1 is written to the rtic bit in the ssi interrupt clear (ssiicr) register. 0 ro rtmis 1 march 20, 2011 698 texas instruments-advance information synchronous serial interface (ssi) description reset type name bit/field ssi receive overrun masked interrupt status description value an interrupt has not occurred or is masked. 0 an unmasked interrupt was signaled due to the receive fifo overflowing. 1 this bit is cleared when a 1 is written to the roric bit in the ssi interrupt clear (ssiicr) register. 0 ro rormis 0 699 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 9: ssi interrupt clear (ssiicr), offset 0x020 the ssiicr register is the interrupt clear register. on a write of 1, the corresponding interrupt is cleared. a write of 0 has no effect. ssi interrupt clear (ssiicr) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x020 type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 roric rtic reserved w1c w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 ssi receive time-out interrupt clear writing a 1 to this bit clears the rtris bit in the ssiris register and the rtmis bit in the ssimis register. 0 w1c rtic 1 ssi receive overrun interrupt clear writing a 1 to this bit clears the rorris bit in the ssiris register and the rormis bit in the ssimis register. 0 w1c roric 0 march 20, 2011 700 texas instruments-advance information synchronous serial interface (ssi) register 10: ssi dma control (ssidmactl), offset 0x024 the ssidmactl register is the dma control register. ssi dma control (ssidmactl) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxdmae txdmae reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 transmit dma enable description value dma for the transmit fifo is disabled. 0 dma for the transmit fifo is enabled. 1 0 r/w txdmae 1 receive dma enable description value dma for the receive fifo is disabled. 0 dma for the receive fifo is enabled. 1 0 r/w rxdmae 0 701 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 11: ssi peripheral identification 4 (ssiperiphid4), offset 0xfd0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 4 (ssiperiphid4) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfd0 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x00 ro pid4 7:0 march 20, 2011 702 texas instruments-advance information synchronous serial interface (ssi) register 12: ssi peripheral identification 5 (ssiperiphid5), offset 0xfd4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 5 (ssiperiphid5) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfd4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid5 7:0 703 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 13: ssi peripheral identification 6 (ssiperiphid6), offset 0xfd8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 6 (ssiperiphid6) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfd8 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x00 ro pid6 7:0 march 20, 2011 704 texas instruments-advance information synchronous serial interface (ssi) register 14: ssi peripheral identification 7 (ssiperiphid7), offset 0xfdc the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 7 (ssiperiphid7) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfdc type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x00 ro pid7 7:0 705 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 15: ssi peripheral identification 0 (ssiperiphid0), offset 0xfe0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 0 (ssiperiphid0) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfe0 type ro, reset 0x0000.0022 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x22 ro pid0 7:0 march 20, 2011 706 texas instruments-advance information synchronous serial interface (ssi) register 16: ssi peripheral identification 1 (ssiperiphid1), offset 0xfe4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 1 (ssiperiphid1) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfe4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 707 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 17: ssi peripheral identification 2 (ssiperiphid2), offset 0xfe8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 2 (ssiperiphid2) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfe8 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 march 20, 2011 708 texas instruments-advance information synchronous serial interface (ssi) register 18: ssi peripheral identification 3 (ssiperiphid3), offset 0xfec the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 3 (ssiperiphid3) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfec type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 709 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 19: ssi primecell identification 0 (ssipcellid0), offset 0xff0 the ssipcellidn registers are hard-coded, and the fields within the register determine the reset value. ssi primecell identification 0 (ssipcellid0) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 march 20, 2011 710 texas instruments-advance information synchronous serial interface (ssi) register 20: ssi primecell identification 1 (ssipcellid1), offset 0xff4 the ssipcellidn registers are hard-coded, and the fields within the register determine the reset value. ssi primecell identification 1 (ssipcellid1) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 711 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 21: ssi primecell identification 2 (ssipcellid2), offset 0xff8 the ssipcellidn registers are hard-coded, and the fields within the register determine the reset value. ssi primecell identification 2 (ssipcellid2) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xff8 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 march 20, 2011 712 texas instruments-advance information synchronous serial interface (ssi) register 22: ssi primecell identification 3 (ssipcellid3), offset 0xffc the ssipcellidn registers are hard-coded, and the fields within the register determine the reset value. ssi primecell identification 3 (ssipcellid3) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 713 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 15 inter-integrated circuit (i 2 c) interface the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sda and a serial clock line scl), and interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture. the lm3s1p51 microcontroller includes two i 2 c modules, providing the ability to interact (both transmit and receive) with other i 2 c devices on the bus. the stellaris ? lm3s1p51 controller includes two i 2 c modules with the following features: devices on the i 2 c bus can be designated as either a master or a slave C supports both transmitting and receiving data as either a master or a slave C supports simultaneous master and slave operation four i 2 c modes C master transmit C master receive C slave transmit C slave receive two transmission speeds: standard (100 kbps) and fast (400 kbps) master and slave interrupt generation C master generates interrupts when a transmit or receive operation completes (or aborts due to an error) C slave generates interrupts when data has been transferred or requested by a master or when a start or stop condition is detected master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode march 20, 2011 714 texas instruments-advance information inter-integrated circuit (i 2 c) interface 15.1 block diagram figure 15-1. i 2 c block diagram 15.2 signal description table 15-1 on page 715 and table 15-2 on page 715 list the external signals of the i 2 c interface and describe the function of each. the i 2 c interface signals are alternate functions for some gpio signals and default to be gpio signals at reset., with the exception of the i2c0scl and i2csda pins which default to the i 2 c function. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the i 2 c signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the i 2 c function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the i 2 c signal to the specified gpio port pin. note that the i 2 c pins should be set to open drain using the gpio open drain select (gpioodr) register. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. table 15-1. signals for i2c (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 c module 0 clock. od i/o pb2 (1) 72 i2c0scl i 2 c module 0 data. od i/o pb3 (1) 65 i2c0sda i 2 c module 1 clock. od i/o pj0 (11) pg0 (3) pa0 (8) pa6 (1) 14 19 26 34 i2c1scl i 2 c module 1 data. od i/o pg1 (3) pa1 (8) pa7 (1) pj1 (11) 18 27 35 87 i2c1sda a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 15-2. signals for i2c (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 c module 0 clock. od i/o pb2 (1) a11 i2c0scl 715 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller , & , 2 6 h o h f w , & 0 d v w h u & r u h , q w h u u x s w , & 6 o d y h & r u h , & 6 & / , & 6 ' $ , & 6 ' $ , & 6 & / , & 6 ' $ , & 6 & / , & 0 6 $ , & 0 & 6 , & 0 ' 5 , & 0 7 3 5 , & 0 , 0 5 , & 0 5 , 6 , & 0 , & 5 , & 0 & 5 , & 6 2 $ 5 , & 6 & 6 5 , & 6 ' 5 , & 6 , 0 5 , & 6 5 , 6 , & 6 0 , 6 , & 6 , & 5 , & 0 0 , 6 , & & r q w u r o table 15-2. signals for i2c (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 c module 0 data. od i/o pb3 (1) e11 i2c0sda i 2 c module 1 clock. od i/o pj0 (11) pg0 (3) pa0 (8) pa6 (1) f3 k1 l3 l6 i2c1scl i 2 c module 1 data. od i/o pg1 (3) pa1 (8) pa7 (1) pj1 (11) k2 m3 m6 b6 i2c1sda a. the ttl designation indicates the pin has ttl-compatible voltage levels. 15.3 functional description each i 2 c module is comprised of both master and slave functions. for proper operation, the sda and scl pins must be configured as open-drain signals. a typical i 2 c bus configuration is shown in figure 15-2. see inter-integrated circuit (i 2 c) interface on page 983 for i 2 c timing diagrams. figure 15-2. i 2 c bus configuration 15.3.1 i 2 c bus functional overview the i 2 c bus uses only two signals: sda and scl, named i2csda and i2cscl on stellaris microcontrollers. sda is the bi-directional serial data line and scl is the bi-directional serial clock line. the bus is considered idle when both lines are high. every transaction on the i 2 c bus is nine bits long, consisting of eight data bits and a single acknowledge bit. the number of bytes per transfer (defined as the time between a valid start and stop condition, described in start and stop conditions on page 716) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred msb first. when a receiver cannot receive another complete byte, it can hold the clock line scl low and force the transmitter into a wait state. the data transfer continues when the receiver releases the clock scl. 15.3.1.1 start and stop conditions the protocol of the i 2 c bus defines two states to begin and end a transaction: start and stop. a high-to-low transition on the sda line while the scl is high is defined as a start condition, and a low-to-high transition on the sda line while scl is high is defined as a stop condition. the bus is considered busy after a start condition and free after a stop condition. see figure 15-3. march 20, 2011 716 texas instruments-advance information inter-integrated circuit (i 2 c) interface 5 3 8 3 6 w h o o d u l v ? , & 6 & / , & 6 ' $ 5 3 8 3 u g 3 d u w \ ' h y l f h z l w k , & , q w h u i d f h 6 & / 6 ' $ , & % x v 6 & / 6 ' $ u g 3 d u w \ ' h y l f h z l w k , & , q w h u i d f h 6 & / 6 ' $ figure 15-3. start and stop conditions the stop bit determines if the cycle stops at the end of the data cycle or continues on to a repeated start condition. to generate a single transmit cycle, the i 2 c master slave address (i2cmsa) register is written with the desired address, the r/s bit is cleared, and the control register is written with ack =x (0 or 1), stop=1, start =1, and run =1 to perform the operation and stop. when the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the i 2 c master data (i2cmdr) register. when the i 2 c module operates in master receiver mode, the ack bit is normally set causing the i 2 c bus controller to transmit an acknowledge automatically after each byte. this bit must be cleared when the i 2 c bus controller requires no further data to be transmitted from the slave transmitter. when operating in slave mode, two bits in the i 2 c slave raw interrupt status (i2csris) register indicate detection of start and stop conditions on the bus; while two bits in the i 2 c slave masked interrupt status (i2csmis) register allow start and stop conditions to be promoted to controller interrupts (when interrupts are enabled). 15.3.1.2 data format with 7-bit address data transfers follow the format shown in figure 15-4. after the start condition, a slave address is transmitted. this address is 7-bits long followed by an eighth bit, which is a data direction bit ( r/s bit in the i2cmsa register). if the r/s bit is clear, it indicates a transmit operation (send), and if it is set, it indicates a request for data (receive). a data transfer is always terminated by a stop condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated start condition and addressing another slave without first generating a stop condition. various combinations of receive/transmit formats are then possible within a single transfer. figure 15-4. complete data transfer with a 7-bit address the first seven bits of the first byte make up the slave address (see figure 15-5). the eighth bit determines the direction of the message. a zero in the r/s position of the first byte means that the master transmits (sends) data to the selected slave, and a one in this position means that the master receives data from the slave. 717 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller ' d w d 6 o d y h d g g u h v v $ & . / 6 % 0 6 % $ & . 5 6 / 6 % 0 6 % 6 ' $ 6 & / 6 w r s 6 w d u w 6 7 $ 5 7 f r q g l w l r q 6 ' $ 6 & / 6 7 2 3 f r q g l w l r q 6 ' $ 6 & / figure 15-5. r/s bit in first byte 15.3.1.3 data validity the data on the sda line must be stable during the high period of the clock, and the data line can only change when scl is low (see figure 15-6). figure 15-6. data validity during bit transfer on the i 2 c bus 15.3.1.4 acknowledge all bus transactions have a required acknowledge clock cycle that is generated by the master. during the acknowledge cycle, the transmitter (which can be the master or slave) releases the sda line. to acknowledge the transaction, the receiver must pull down sda during the acknowledge clock cycle. the data transmitted out by the receiver during the acknowledge cycle must comply with the data validity requirements described in data validity on page 718. when a slave receiver does not acknowledge the slave address, sda must be left high by the slave so that the master can generate a stop condition and abort the current transfer. if the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. because the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. the slave transmitter must then release sda to allow the master to generate the stop or a repeated start condition. 15.3.1.5 arbitration a master may start a transfer only if the bus is idle. it's possible for two or more masters to generate a start condition within minimum hold time of the start condition. in these situations, an arbitration scheme takes place on the sda line, while scl is high. during arbitration, the first of the competing master devices to place a '1' (high) on sda while another master transmits a '0' (low) switches off its data output stage and retires until the bus is idle again. arbitration can take place over several bits. its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 15.3.2 available speed modes the i 2 c bus can run in either standard mode (100 kbps) or fast mode (400 kbps). the selected mode should match the speed of the other i 2 c devices on the bus. march 20, 2011 718 texas instruments-advance information inter-integrated circuit (i 2 c) interface & k d q j h r i g d w d d o o r z h g ' d w d o l q h v w d e o h 6 ' $ 6 & / 5 6 / 6 % 6 o d y h d g g u h v v 0 6 % 15.3.2.1 standard and fast modes standard and fast modes are selected using a value in the i 2 c master timer period (i2cmtpr) register that results in an scl frequency of 100 kbps for standard mode or 400 kbps for fast mode. the i 2 c clock rate is determined by the parameters clk_prd, timer_prd, scl_lp , and scl_hp where: clk_prd is the system clock period scl_lp is the low phase of scl (fixed at 6) scl_hp is the high phase of scl (fixed at 4) timer_prd is the programmed value in the i2cmtpr register (see page 737). the i 2 c clock period is calculated as follows: scl_period = 2 (1 + timer_prd ) (scl_lp + scl_hp ) clk_prd for example: clk_prd = 50 ns timer_prd = 2 scl_lp=6 scl_hp=4 yields a scl frequency of: 1/scl_period = 333 khz table 15-3 gives examples of the timer periods that should be used to generate both standard and fast mode scl frequencies based on various system clock frequencies. table 15-3. examples of i 2 c master timer period versus speed mode fast mode timer period standard mode timer period system clock - - 100 kbps 0x01 4 mhz - - 100 kbps 0x02 6 mhz 312 kbps 0x01 89 kbps 0x06 12.5 mhz 278 kbps 0x02 93 kbps 0x08 16.7 mhz 333 kbps 0x02 100 kbps 0x09 20 mhz 312 kbps 0x03 96.2 kbps 0x0c 25 mhz 330 kbps 0x04 97.1 kbps 0x10 33 mhz 400 kbps 0x04 100 kbps 0x13 40 mhz 357 kbps 0x06 100 kbps 0x18 50 mhz 400 kbps 0x09 100 kbps 0x27 80 mhz 15.3.3 interrupts the i 2 c can generate interrupts when the following conditions are observed: master transaction completed master arbitration lost 719 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller master transaction error slave transaction received slave transaction requested stop condition on bus detected start condition on bus detected the i 2 c master and i 2 c slave modules have separate interrupt signals. while both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 15.3.3.1 i 2 c master interrupts the i 2 c master module generates an interrupt when a transaction completes (either transmit or receive), when arbitration is lost, or when an error occurs during a transaction. to enable the i 2 c master interrupt, software must set the im bit in the i 2 c master interrupt mask (i2cmimr) register. when an interrupt condition is met, software must check the error and arblst bits in the i 2 c master control/status (i2cmcs) register to verify that an error didn't occur during the last transaction and to ensure that arbitration has not been lost. an error condition is asserted if the last transaction wasn't acknowledged by the slave. if an error is not detected and the master has not lost arbitration, the application can proceed with the transfer. the interrupt is cleared by writing a 1 to the ic bit in the i 2 c master interrupt clear (i2cmicr) register. if the application doesn't require the use of interrupts, the raw interrupt status is always visible via the i 2 c master raw interrupt status (i2cmris) register. 15.3.3.2 i 2 c slave interrupts the slave module can generate an interrupt when data has been received or requested. this interrupt is enabled by setting the dataim bit in the i 2 c slave interrupt mask (i2csimr) register. software determines whether the module should write (transmit) or read (receive) data from the i 2 c slave data (i2csdr) register, by checking the rreq and treq bits of the i 2 c slave control/status (i2cscsr) register. if the slave module is in receive mode and the first byte of a transfer is received, the fbr bit is set along with the rreq bit. the interrupt is cleared by setting the dataic bit in the i 2 c slave interrupt clear (i2csicr) register. in addition, the slave module can generate an interrupt when a start and stop condition is detected. these interrupts are enabled by setting the startim and stopim bits of the i 2 c slave interrupt mask (i2csimr) register and cleared by writing a 1 to the stopic and startic bits of the i 2 c slave interrupt clear (i2csicr) register. if the application doesn't require the use of interrupts, the raw interrupt status is always visible via the i 2 c slave raw interrupt status (i2csris) register. 15.3.4 loopback operation the i 2 c modules can be placed into an internal loopback mode for diagnostic or debug work by setting the lpbk bit in the i 2 c master configuration (i2cmcr) register. in loopback mode, the sda and scl signals from the master and slave modules are tied together. march 20, 2011 720 texas instruments-advance information inter-integrated circuit (i 2 c) interface 15.3.5 command sequence flow charts this section details the steps required to perform the various i 2 c transfer types in both master and slave mode. 15.3.5.1 i 2 c master command sequences the figures that follow show the command sequences available for the i 2 c master. 721 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 15-7. master single transmit march 20, 2011 722 texas instruments-advance information inter-integrated circuit (i 2 c) interface , g o h : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ : u l w h g d w d w r , & 0 ' 5 5 h d g , & 0 & 6 6 h t x h q f h p d \ e h r p l w w h g l q d 6 l q j o h 0 d v w h u v \ v w h p % 8 6 % 6 < e l w " 1 2 : u l w h --- 0 - 111 0 0 figure 15-8. master single receive 723 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller , g o h : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ 5 h d g , & 0 & 6 6 h t x h q f h p d \ e h r p l w w h g l q d 6 l q j o h 0 d v w h u v \ v w h p % 8 6 % 6 < e l w " 1 2 : u l w h --- 00111 0 0 figure 15-9. master transmit with repeated start march 20, 2011 724 texas instruments-advance information inter-integrated circuit (i 2 c) interface , g o h : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ : u l w h g d w d w r , & 0 ' 5 5 h d g , & 0 & 6 % 8 6 % 6 < e l w " < ( 6 : u l w h --- 0 - 011 0 0 1 --- 0 - 100 --- 0 - 001 --- 0 - 101 0 0 figure 15-10. master receive with repeated start 725 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller , g o h : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ 5 h d g , & 0 & 6 % 8 6 % 6 < e l w " 1 2 : u l w h --- 01011 0 0 1 --- 0 - 100 -1 --- 00101 0 --- 01001 0 figure 15-11. master receive with repeated start after transmit with repeated start march 20, 2011 726 texas instruments-advance information inter-integrated circuit (i 2 c) interface , g o h 0 d v w h u r s h u d w h v l q 0 d v w h u 7 u d q v p l w p r g h 6 7 2 3 f r q g l w l r q l v q r w j h q h u d w h g : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ : u l w h --- 01011 figure 15-12. master transmit with repeated start after receive with repeated start 15.3.5.2 i 2 c slave command sequences figure 15-13 on page 728 presents the command sequence available for the i 2 c slave. 727 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller , g o h 0 d v w h u r s h u d w h v l q 0 d v w h u 5 h f h l y h p r g h 6 7 2 3 f r q g l w l r q l v q r w j h q h u d w h g : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ : u l w h --- 0 - 011 figure 15-13. slave command sequence 15.4 initialization and configuration the following example shows how to configure the i 2 c module to transmit a single byte as a master. this assumes the system clock is 20 mhz. 1. enable the i 2 c clock by writing a value of 0x0000.1000 to the rcgc1 register in the system control module (see page 260). 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module (see page 269). to find out which gpio port to enable, refer to table 21-5 on page 925. 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register (see page 428). to determine which gpios to configure, see table 21-4 on page 917. 4. enable the i 2 c pins for open drain operation. see page 433. 5. configure the pmcn fields in the gpiopctl register to assign the i 2 c signals to the appropriate pins. see page 446 and table 21-5 on page 925. 6. initialize the i 2 c master by writing the i2cmcr register with a value of 0x0000.0010. march 20, 2011 728 texas instruments-advance information inter-integrated circuit (i 2 c) interface , g o h : u l w h 2 : 1 6 o d y h $ g g u h v v w r , & 6 2 $ 5 : u l w h ------- 1 1 1 7. set the desired scl clock speed of 100 kbps by writing the i2cmtpr register with the correct value. the value written to the i2cmtpr register represents the number of system clock periods in one scl clock period. the tpr value is determined by the following equation: tpr = (system clock/(2*(scl_lp + scl_hp)*scl_clk))-1; tpr = (20mhz/(2*(6+4)*100000))-1; tpr = 9 write the i2cmtpr register with the value of 0x0000.0009. 8. specify the slave address of the master and that the next operation is a transmit by writing the i2cmsa register with a value of 0x0000.0076. this sets the slave address to 0x3b. 9. place data (byte) to be transmitted in the data register by writing the i2cmdr register with the desired data. 10. initiate a single byte transmit of the data from master to slave by writing the i2cmcs register with a value of 0x0000.0007 (stop, start, run). 11. wait until the transmission completes by polling the i2cmcs registers busbsy bit until it has been cleared. 12. check the error bit in the i2cmcs register to confirm the transmit was acknowledged. 15.5 register map table 15-4 on page 729 lists the i 2 c registers. all addresses given are relative to the i 2 c base address: i 2 c 0: 0x4002.0000 i 2 c 1: 0x4002.1000 note that the i 2 c module clock must be enabled before the registers can be programmed (see page 260). there must be a delay of 3 system clocks after the i 2 c module clock is enabled before any i 2 c module registers are accessed. the hw_i2c.h file in the stellarisware ? driver library uses a base address of 0x800 for the i 2 c slave registers. be aware when using registers with offsets between 0x800 and 0x818 that stellarisware uses an offset between 0x000 and 0x018 with the slave base address. table 15-4. inter-integrated circuit (i 2 c) interface register map see page description reset type name offset i 2 c master 731 i2c master slave address 0x0000.0000 r/w i2cmsa 0x000 732 i2c master control/status 0x0000.0000 r/w i2cmcs 0x004 736 i2c master data 0x0000.0000 r/w i2cmdr 0x008 737 i2c master timer period 0x0000.0001 r/w i2cmtpr 0x00c 738 i2c master interrupt mask 0x0000.0000 r/w i2cmimr 0x010 739 i2c master raw interrupt status 0x0000.0000 ro i2cmris 0x014 729 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 15-4. inter-integrated circuit (i 2 c) interface register map (continued) see page description reset type name offset 740 i2c master masked interrupt status 0x0000.0000 ro i2cmmis 0x018 741 i2c master interrupt clear 0x0000.0000 wo i2cmicr 0x01c 742 i2c master configuration 0x0000.0000 r/w i2cmcr 0x020 i 2 c slave 743 i2c slave own address 0x0000.0000 r/w i2csoar 0x800 744 i2c slave control/status 0x0000.0000 ro i2cscsr 0x804 746 i2c slave data 0x0000.0000 r/w i2csdr 0x808 747 i2c slave interrupt mask 0x0000.0000 r/w i2csimr 0x80c 748 i2c slave raw interrupt status 0x0000.0000 ro i2csris 0x810 749 i2c slave masked interrupt status 0x0000.0000 ro i2csmis 0x814 750 i2c slave interrupt clear 0x0000.0000 wo i2csicr 0x818 15.6 register descriptions (i 2 c master) the remainder of this section lists and describes the i 2 c master registers, in numerical order by address offset. march 20, 2011 730 texas instruments-advance information inter-integrated circuit (i 2 c) interface register 1: i 2 c master slave address (i2cmsa), offset 0x000 this register consists of eight bits: seven address bits (a6-a0), and a receive/send bit, which determines if the next operation is a receive (high), or transmit (low). i2c master slave address (i2cmsa) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r/s sa reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 i 2 c slave address this field specifies bits a6 through a0 of the slave address. 0x00 r/w sa 7:1 receive/send the r/s bit specifies if the next operation is a receive (high) or transmit (low). description value transmit 0 receive 1 0 r/w r/s 0 731 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: i 2 c master control/status (i2cmcs), offset 0x004 this register accesses status bits when read and control bits when written. when read, the status register indicates the state of the i 2 c bus controller. when written, the control register configures the i 2 c controller operation. the start bit generates the start or repeated start condition. the stop bit determines if the cycle stops at the end of the data cycle or continues on to a repeated start condition. to generate a single transmit cycle, the i 2 c master slave address (i2cmsa) register is written with the desired address, the r/s bit is cleared, and this register is written with ack =x (0 or 1), stop=1, start =1, and run =1 to perform the operation and stop. when the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the i2cmdr register. when the i 2 c module operates in master receiver mode, the ack bit is normally set, causing the i 2 c bus controller to transmit an acknowledge automatically after each byte. this bit must be cleared when the i 2 c bus controller requires no further data to be transmitted from the slave transmitter. read-only status register i2c master control/status (i2cmcs) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 busy error adrack datack arblst idle busbsy reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:7 bus busy description value the i 2 c bus is idle. 0 the i 2 c bus is busy. 1 the bit changes based on the start and stop conditions. 0 ro busbsy 6 i 2 c idle description value the i 2 c controller is not idle. 0 the i 2 c controller is idle. 1 0 ro idle 5 march 20, 2011 732 texas instruments-advance information inter-integrated circuit (i 2 c) interface description reset type name bit/field arbitration lost description value the i 2 c controller won arbitration. 0 the i 2 c controller lost arbitration. 1 0 ro arblst 4 acknowledge data description value the transmitted data was acknowledged 0 the transmitted data was not acknowledged. 1 0 ro datack 3 acknowledge address description value the transmitted address was acknowledged 0 the transmitted address was not acknowledged. 1 0 ro adrack 2 error description value no error was detected on the last operation. 0 an error occurred on the last operation. 1 the error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0 ro error 1 i 2 c busy description value the controller is idle. 0 the controller is busy. 1 when the busy bit is set, the other status bits are not valid. 0 ro busy 0 write-only control register i2c master control/status (i2cmcs) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x004 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 run start stop ack reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 733 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 wo reserved 31:4 data acknowledge enable description value the received data byte is not acknowledged automatically by the master. 0 the received data byte is acknowledged automatically by the master. see field decoding in table 15-5 on page 734. 1 0 wo ack 3 generate stop description value the controller does not generate the stop condition. 0 the controller generates the stop condition. see field decoding in table 15-5 on page 734. 1 0 wo stop 2 generate start description value the controller does not generate the start condition. 0 the controller generates the start or repeated start condition. see field decoding in table 15-5 on page 734. 1 0 wo start 1 i 2 c master enable description value the master is disabled. 0 the master is enabled to transmit or receive data. see field decoding in table 15-5 on page 734. 1 0 wo run 0 table 15-5. write field decoding for i2cmcs[3:0] field description i2cmcs[3:0] i2cmsa[0] current state run start stop ack r/s start condition followed by transmit (master goes to the master transmit state). 1 1 0 x a 0 idle start condition followed by a transmit and stop condition (master remains in idle state). 1 1 1 x 0 start condition followed by receive operation with negative ack (master goes to the master receive state). 1 1 0 0 1 start condition followed by receive and stop condition (master remains in idle state). 1 1 1 0 1 start condition followed by receive (master goes to the master receive state). 1 1 0 1 1 illegal 1 1 1 1 1 nop all other combinations not listed are non-operations. march 20, 2011 734 texas instruments-advance information inter-integrated circuit (i 2 c) interface table 15-5. write field decoding for i2cmcs[3:0] field (continued) description i2cmcs[3:0] i2cmsa[0] current state run start stop ack r/s transmit operation (master remains in master transmit state). 1 0 0 x x master transmit stop condition (master goes to idle state). 0 0 1 x x transmit followed by stop condition (master goes to idle state). 1 0 1 x x repeated start condition followed by a transmit (master remains in master transmit state). 1 1 0 x 0 repeated start condition followed by transmit and stop condition (master goes to idle state). 1 1 1 x 0 repeated start condition followed by a receive operation with a negative ack (master goes to master receive state). 1 1 0 0 1 repeated start condition followed by a transmit and stop condition (master goes to idle state). 1 1 1 0 1 repeated start condition followed by receive (master goes to master receive state). 1 1 0 1 1 illegal. 1 1 1 1 1 nop. all other combinations not listed are non-operations. receive operation with negative ack (master remains in master receive state). 1 0 0 0 x master receive stop condition (master goes to idle state). b 0 0 1 x x receive followed by stop condition (master goes to idle state). 1 0 1 0 x receive operation (master remains in master receive state). 1 0 0 1 x illegal. 1 0 1 1 x repeated start condition followed by receive operation with a negative ack (master remains in master receive state). 1 1 0 0 1 repeated start condition followed by receive and stop condition (master goes to idle state). 1 1 1 0 1 repeated start condition followed by receive (master remains in master receive state). 1 1 0 1 1 repeated start condition followed by transmit (master goes to master transmit state). 1 1 0 x 0 repeated start condition followed by transmit and stop condition (master goes to idle state). 1 1 1 x 0 nop. all other combinations not listed are non-operations. a. an x in a table cell indicates the bit can be 0 or 1. b. in master receive mode, a stop condition should be generated only after a data negative acknowledge executed by the master or an address negative acknowledge executed by the slave. 735 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 3: i 2 c master data (i2cmdr), offset 0x008 important: this register is read-sensitive. see the register description for details. this register contains the data to be transmitted when in the master transmit state and the data received when in the master receive state. i2c master data (i2cmdr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 data transferred data transferred during transaction. 0x00 r/w data 7:0 march 20, 2011 736 texas instruments-advance information inter-integrated circuit (i 2 c) interface register 4: i 2 c master timer period (i2cmtpr), offset 0x00c this register specifies the period of the scl clock. caution C take care not to set bit 7 when accessing this register as unpredictable behavior can occur. i2c master timer period (i2cmtpr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x00c type r/w, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tpr reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:7 scl clock period this field specifies the period of the scl clock. scl_prd = 2(1 + tpr)( scl_lp + scl_hp)clk_prd where: scl_prd is the scl line period (i 2 c clock). tpr is the timer period register value (range of 1 to 127). scl_lp is the scl low period (fixed at 6). scl_hp is the scl high period (fixed at 4). clk_prd is the system clock period in ns. 0x1 r/w tpr 6:0 737 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 5: i 2 c master interrupt mask (i2cmimr), offset 0x010 this register controls whether a raw interrupt is promoted to a controller interrupt. i2c master interrupt mask (i2cmimr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 im reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 interrupt mask description value the master interrupt is sent to the interrupt controller when the ris bit in the i2cmris register is set. 1 the ris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w im 0 march 20, 2011 738 texas instruments-advance information inter-integrated circuit (i 2 c) interface register 6: i 2 c master raw interrupt status (i2cmris), offset 0x014 this register specifies whether an interrupt is pending. i2c master raw interrupt status (i2cmris) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x014 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 raw interrupt status description value a master interrupt is pending. 1 no interrupt. 0 this bit is cleared by writing a 1 to the ic bit in the i2cmicr register. 0 ro ris 0 739 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 7: i 2 c master masked interrupt status (i2cmmis), offset 0x018 this register specifies whether an interrupt was signaled. i2c master masked interrupt status (i2cmmis) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 masked interrupt status description value an unmasked master interrupt was signaled and is pending. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the ic bit in the i2cmicr register. 0 ro mis 0 march 20, 2011 740 texas instruments-advance information inter-integrated circuit (i 2 c) interface register 8: i 2 c master interrupt clear (i2cmicr), offset 0x01c this register clears the raw and masked interrupts. i2c master interrupt clear (i2cmicr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x01c type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ic reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 interrupt clear writing a 1 to this bit clears the ris bit in the i2cmris register and the mis bit in the i2cmmis register. a read of this register returns no meaningful data. 0 wo ic 0 741 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 9: i 2 c master configuration (i2cmcr), offset 0x020 this register configures the mode (master or slave) and sets the interface for test mode loopback. i2c master configuration (i2cmcr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lpbk reserved mfe sfe reserved r/w ro ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 i 2 c slave function enable description value slave mode is enabled. 1 slave mode is disabled. 0 0 r/w sfe 5 i 2 c master function enable description value master mode is enabled. 1 master mode is disabled. 0 0 r/w mfe 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 i 2 c loopback description value the controller in a test mode loopback configuration. 1 normal operation. 0 0 r/w lpbk 0 15.7 register descriptions (i 2 c slave) the remainder of this section lists and describes the i 2 c slave registers, in numerical order by address offset. march 20, 2011 742 texas instruments-advance information inter-integrated circuit (i 2 c) interface register 10: i 2 c slave own address (i2csoar), offset 0x800 this register consists of seven address bits that identify the stellaris i 2 c device on the i 2 c bus. i2c slave own address (i2csoar) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x800 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 oar reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:7 i 2 c slave own address this field specifies bits a6 through a0 of the slave address. 0x00 r/w oar 6:0 743 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 11: i 2 c slave control/status (i2cscsr), offset 0x804 this register functions as a control register when written, and a status register when read. read-only status register i2c slave control/status (i2cscsr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x804 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rreq treq fbr reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 first byte received description value the first byte following the slaves own address has been received. 1 the first byte has not been received. 0 this bit is only valid when the rreq bit is set and is automatically cleared when data has been read from the i2csdr register. note: this bit is not used for slave transmit operations. 0 ro fbr 2 transmit request description value the i 2 c controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the i2csdr register. 1 no outstanding transmit request. 0 0 ro treq 1 receive request description value the i 2 c controller has outstanding receive data from the i 2 c master and is using clock stretching to delay the master until the data has been read from the i2csdr register. 1 no outstanding receive data. 0 0 ro rreq 0 march 20, 2011 744 texas instruments-advance information inter-integrated circuit (i 2 c) interface write-only control register i2c slave control/status (i2cscsr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x804 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 device active description value disables the i 2 c slave operation. 0 enables the i 2 c slave operation. 1 0 wo da 0 745 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: i 2 c slave data (i2csdr), offset 0x808 important: this register is read-sensitive. see the register description for details. this register contains the data to be transmitted when in the slave transmit state, and the data received when in the slave receive state. i2c slave data (i2csdr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x808 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 data for transfer this field contains the data for transfer during a slave receive or transmit operation. 0x00 r/w data 7:0 march 20, 2011 746 texas instruments-advance information inter-integrated circuit (i 2 c) interface register 13: i 2 c slave interrupt mask (i2csimr), offset 0x80c this register controls whether a raw interrupt is promoted to a controller interrupt. i2c slave interrupt mask (i2csimr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x80c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dataim startim stopim reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 stop condition interrupt mask description value the stop condition interrupt is sent to the interrupt controller when the stopris bit in the i2csris register is set. 1 the stopris interrupt is suppressed and not sent to the interrupt controller. 0 0 ro stopim 2 start condition interrupt mask description value the start condition interrupt is sent to the interrupt controller when the startris bit in the i2csris register is set. 1 the startris interrupt is suppressed and not sent to the interrupt controller. 0 0 ro startim 1 data interrupt mask description value the data received or data requested interrupt is sent to the interrupt controller when the dataris bit in the i2csris register is set. 1 the dataris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w dataim 0 747 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 14: i 2 c slave raw interrupt status (i2csris), offset 0x810 this register specifies whether an interrupt is pending. i2c slave raw interrupt status (i2csris) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x810 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dataris startris stopris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 stop condition raw interrupt status description value a stop condition interrupt is pending. 1 no interrupt. 0 this bit is cleared by writing a 1 to the stopic bit in the i2csicr register. 0 ro stopris 2 start condition raw interrupt status description value a start condition interrupt is pending. 1 no interrupt. 0 this bit is cleared by writing a 1 to the startic bit in the i2csicr register. 0 ro startris 1 data raw interrupt status description value a data received or data requested interrupt is pending. 1 no interrupt. 0 this bit is cleared by writing a 1 to the dataic bit in the i2csicr register. 0 ro dataris 0 march 20, 2011 748 texas instruments-advance information inter-integrated circuit (i 2 c) interface register 15: i 2 c slave masked interrupt status (i2csmis), offset 0x814 this register specifies whether an interrupt was signaled. i2c slave masked interrupt status (i2csmis) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x814 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 datamis startmis stopmis reserved ro r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 stop condition masked interrupt status description value an unmasked stop condition interrupt was signaled is pending. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the stopic bit in the i2csicr register. 0 r/w stopmis 2 start condition masked interrupt status description value an unmasked start condition interrupt was signaled is pending. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the startic bit in the i2csicr register. 0 r/w startmis 1 data masked interrupt status description value an unmasked data received or data requested interrupt was signaled is pending. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the dataic bit in the i2csicr register. 0 ro datamis 0 749 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 16: i 2 c slave interrupt clear (i2csicr), offset 0x818 this register clears the raw interrupt. a read of this register returns no meaningful data. i2c slave interrupt clear (i2csicr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x818 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dataic startic stopic reserved wo wo wo ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 stop condition interrupt clear writing a 1 to this bit clears the stopris bit in the i2csris register and the stopmis bit in the i2csmis register. a read of this register returns no meaningful data. 0 wo stopic 2 start condition interrupt clear writing a 1 to this bit clears the stopris bit in the i2csris register and the stopmis bit in the i2csmis register. a read of this register returns no meaningful data. 0 wo startic 1 data interrupt clear writing a 1 to this bit clears the stopris bit in the i2csris register and the stopmis bit in the i2csmis register. a read of this register returns no meaningful data. 0 wo dataic 0 march 20, 2011 750 texas instruments-advance information inter-integrated circuit (i 2 c) interface 16 inter-integrated circuit sound (i 2 s) interface the i 2 s module is a configurable serial audio core that contains a transmit module and a receive module. the module is configurable for the i 2 s as well as left-justified and right-justified serial audio formats. data can be in one of four modes: stereo, mono, compact 16-bit stereo and compact 8-bit stereo. the transmit and receive modules each have an 8-entry audio-sample fifo. an audio sample can consist of a left and right stereo sample, a mono sample, or a left and right compact stereo sample. in compact 16-bit stereo, each fifo entry contains both the 16-bit left and 16-bit right samples, allowing efficient data transfers and requiring less memory space. in compact 8-bit stereo, each fifo entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements further. both the transmitter and receiver are capable of being a master or a slave. the stellaris ? i 2 s module has the following features: configurable audio format supporting i 2 s, left-justification, and right-justification configurable sample size from 8 to 32 bits mono and stereo support 8-, 16-, and 32-bit fifo interface for packing memory independent transmit and receive 8-entry fifos configurable fifo-level interrupt and dma requests independent transmit and receive mclk direction control transmit and receive internal mclk sources independent transmit and receive control for serial clock and word select mclk and sclk can be independently set to master or slave configurable transmit zero or last sample when fifo empty efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C burst requests C channel requests asserted when fifo contains required amount of data 751 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16.1 block diagram figure 16-1. i 2 s block diagram 16.2 signal description table 16-1 on page 753 and table 16-2 on page 753 list the external signals of the i 2 s module and describe the function of each. the i 2 s module signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the i 2 s signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the i 2 s function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the i 2 s signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. march 20, 2011 752 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface , 6 7 ; 0 & / . 6 \ v w h p $ + % % x v 6 \ v & o n , 6 5 ; & ) * 5 h f h l y h ) , ) 2 5 h f h l y h ) , ) 2 h q w u \ , 6 5 ; 6 & . , 6 5 ; 6 ' , 6 5 ; : 6 , 6 5 ; 0 & / . , 6 5 ; ) , ) 2 , 6 5 ; ) , ) 2 & ) * , 6 5 ; / , 0 , 7 , 6 5 ; / ( 9 6 h u l d o ' h f r g h u % l w & o n : g 6 h o * h q h u d w l r q , 6 5 ; , 6 0 , q w h u u x s w v ' 0 $ 5 h j l v w h u v , 6 , & , 6 , 0 , 6 5 , 6 , 6 0 , 6 , 6 & ) * , 6 7 ; , 6 0 7 u d q v p l w ) , ) 2 7 u d q v p l w ) , ) 2 h q w u \ 6 h u l d o ( q f r g h u , 6 7 ; 6 ' , 6 7 ; 6 & . % l w & o n : g 6 h o * h q h u d w l r q , 6 7 ; : 6 , 6 7 ; ) , ) 2 , 6 7 ; ) , ) 2 & ) * , 6 7 ; / , 0 , 7 , 6 7 ; / ( 9 , 6 7 ; & ) * table 16-1. signals for i2s (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 s module 0 receive master clock. ttl i/o pg3 (9) pa3 (9) pd5 (8) 16 29 98 i2s0rxmclk i 2 s module 0 receive clock. ttl i/o pd0 (8) pg5 (9) 10 40 i2s0rxsck i 2 s module 0 receive data. ttl i/o pg2 (9) pa2 (9) pd4 (8) 17 28 97 i2s0rxsd i 2 s module 0 receive word select. ttl i/o pd1 (8) pg6 (9) 11 37 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o pf6 (9) pf1 (8) 43 61 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o pa4 (9) pb6 (9) pd6 (8) 30 90 99 i2s0txsck i 2 s module 0 transmit data. ttl i/o pe5 (9) pf0 (8) 5 47 i2s0txsd i 2 s module 0 transmit word select. ttl i/o pe4 (9) pa5 (9) pd7 (8) 6 31 100 i2s0txws a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 16-2. signals for i2s (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 s module 0 receive master clock. ttl i/o pg3 (9) pa3 (9) pd5 (8) j2 l4 c6 i2s0rxmclk i 2 s module 0 receive clock. ttl i/o pd0 (8) pg5 (9) g1 m7 i2s0rxsck i 2 s module 0 receive data. ttl i/o pg2 (9) pa2 (9) pd4 (8) j1 m4 b5 i2s0rxsd i 2 s module 0 receive word select. ttl i/o pd1 (8) pg6 (9) g2 l7 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o pf6 (9) pf1 (8) m8 h12 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o pa4 (9) pb6 (9) pd6 (8) l5 a7 a3 i2s0txsck i 2 s module 0 transmit data. ttl i/o pe5 (9) pf0 (8) b3 m9 i2s0txsd i 2 s module 0 transmit word select. ttl i/o pe4 (9) pa5 (9) pd7 (8) b2 m5 a2 i2s0txws a. the ttl designation indicates the pin has ttl-compatible voltage levels. 753 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16.3 functional description the inter-integrated circuit sound (i 2 s) module contains separate transmit and receive engines. each engine consists of the following: serial encoder for the transmitter; serial decoder for the receiver 8-entry fifo to store sample data independent configuration of all programmable settings the basic programming model of the i 2 s block is as follows: configuration C overall i 2 s module configuration in the i 2 s module configuration (i2scfg) register. this register is used to select the mclk source and enable the receiver and transmitter. C transmit and receive configuration in the i 2 s transmit module configuration (i2stxcfg) and i 2 s receive module configuration (i2srxcfg) registers. these registers set the basic parameters for the receiver and transmitter such as data configuration (justification, delay, read mode, sample size, and system data size); sclk (polarity and source); and word select polarity. C transmit and receive fifo configuration in the i 2 s transmit fifo configuration (i2stxfifocfg) and i 2 s receive fifo configuration (i2srxfifocfg) registers. these registers select the compact stereo mode size (16-bit or 8-bit), provide indication of whether the next sample is left or right, and select mono mode for the receiver. fifo C transmit and receive fifo data in the i 2 s transmit fifo data (i2stxfifo) and i 2 s receive fifo data (i2srxfifo) registers C information on fifo data levels in the i 2 s transmit fifo level (i2stxlev) and i 2 s receive fifo level (i2srxlev) registers C configuration for fifo service requests based on fifo levels in the i 2 s transmit fifo limit (i2stxlimit) and i 2 s receive fifo limit (i2srxlim) registers interrupt control C interrupt masking configuration in the i 2 s interrupt mask (i2sim) register C raw and masked interrupt status in the i 2 s raw interrupt status (i2sris) and i 2 s masked interrupt status (i2smis ) registers C interrupt clearing through the i 2 s interrupt clear (i2sic) register C configuration for fifo service requests interrupts and transmit/receive error interrupts in the i 2 s transmit interrupt status and mask (i2stxism) and i 2 s receive interrupt status and mask (i2srxism) registers march 20, 2011 754 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface figure 16-2 on page 755 provides an example of an i 2 s data transfer. figure 16-3 on page 755 provides an example of an left-justified data transfer. figure 16-4 on page 755 provides an example of an right-justified data transfer. figure 16-2. i 2 s data transfer figure 16-3. left-justified data transfer figure 16-4. right-justified data transfer 16.3.1 transmit the transmitter consists of a serial encoder, an 8-entry fifo, and control logic. the transmitter has independent mclk ( i2s0txmclk ), sclk (i2s0txsck ), and word-select (i2s0txws ) signals. 16.3.1.1 serial encoder the serial encoder reads audio samples from the receive fifo and converts them into an audio stream. by configuring the serial encoder, common audio formats i 2 s, left-justified, and right-justified are supported. the msb is transmitted first. the sample size and system data size 755 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 0 6 % / 6 % 6 \ v w h p ' d w d 6 l ] h / h i w & k d q q h o 6 d p s o h 6 l ] h : r u g 6 h o h f w 6 h u l d o ' d w d 6 & / . 0 6 % / 6 % 5 l j k w & k d q q h o 6 \ v w h p ' d w d 6 l ] h / h i w & k d q q h o 5 l j k w & k d q q h o 0 6 % / 6 % 0 6 % / 6 % 6 d p s o h 6 l ] h 6 h u l d o ' d w d : r u g 6 h o h f w 6 & / . 6 & . : r u g 6 h o h f w 6 h u l d o ' d w d 0 6 % / 6 % : 2 5 ' q 5 , * + 7 & + $ 1 1 ( / : 2 5 ' q / ( ) 7 & + $ 1 1 ( / : 2 5 ' q 5 , * + 7 & + $ 1 1 ( / 0 6 % are configurable with the ssz and sdsz bits in the i 2 s transmit module configuration (i2stxcfg) register. the sample size is the number of bits of data being transmitted, and the system data size is the number of i2s0txsck transitions between the word select transitions. the system data size must be large enough to accommodate the maximum sample size. in mono mode, the sample data is repeated in both the left and right channels. when the fifo is empty, the user may select either transmission of zeros or of the last sample. the serial encoder is enabled using the txen bit in the i 2 s module configuration (i2scfg) register. 16.3.1.2 fifo operation the transmit fifo stores eight mono samples or eight stereo sample-pairs of data and is accessed through the i 2 s transmit fifo data (i2stxfifo) register. the fifo interface for the audio data is different based on the write mode, defined by the i 2 s transmit fifo configuration (i2stxfifocfg) compact stereo sample size bit ( css ) and the i2stxcfg write mode field ( wm). all data samples are msb-aligned. table 16-3 on page 756 defines the interface for each write mode. stereo samples are written first left then right. the next sample (right or left) to be written is indicated by the lrs bit in the i2stxfifocfg register. table 16-3. i 2 s transmit fifo interface data alignment samples per fifo write sample width write mode css bit in i2stxfifocfg wm field in i2stxcfg msb 1 8-32 bits stereo don't care 0x0 msb right [31:16], left [15:0] 2 8-16 bits compact stereo - 16 bit 0 0x1 right [15:8], left[7:0] 2 8 bits compact stereo - 8 bit 1 0x1 msb 1 8-32 bits mono don't care 0x2 the number of samples in the transmit fifo can be read using the i 2 s transmit fifo level (i2stxlev) register. the value ranges from 0 to 16. stereo and compact stereo sample pairs are counted as two. the mono samples also increment the count by two, therefore, four mono samples will have a count of eight. 16.3.1.3 clock control the transmitter mclk and sclk can be independently programmed to be the master or slave. the transmitter is programmed to be the master or slave of the sclk using the msl bit in the i2stxcfg register. when the transmitter is the master, the i2s0txsck frequency is the specified i2s0txmclk divided by four. the i2s0txsck may be inverted using the scp bit in the i2stxcfg register. the transmitter can also be the master or slave of the mclk. when the transmitter is the master, the pll must be active and a fractional clock divider must be programmed. see page 227 for the setup for the master i2s0txmclk source. an external transmit i2s0txmclk does not require the use of the pll and is selected using the txslv bit in the i2scfg register. the following tables show combinations of the txint and txfrac bits in the i 2 s mclk configuration (i2smclkcfg) register that provide mclk frequencies within acceptable error limits. in the table, fs is the sampling frequency in khz and possible crystal frequencies are shown in mhz across the top row of the table. the words "not supported" in the table mean that it is not possible to obtain the specified sampling frequencies with the specified crystal frequency within the error tolerance of 0.3%. the values in the table are based on the following values: mclk = fs 256 pll = 400 mhz march 20, 2011 756 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface the integer value is taken from the result of the following calculation: round(pll/mclk) the remaining fractional component is converted to binary, and the first four bits are the fractional value. table 16-4. crystal frequency (values from 3.5795 mhz to 5 mhz) crystal frequency (mhz) sampling frequency fs (khz) 5 4.9152 4.096 4 3.6864 3.5795 fractional integer fractional integer fractional integer fractional integer fractional integer fractional integer 5 195 6 194 0 196 5 195 6 194 12 195 8 12 141 1 141 4 142 12 141 1 141 1 142 11.025 3 130 10 129 11 130 3 130 10 129 8 130 12 10 97 3 97 0 98 10 97 3 97 14 97 16 14 70 8 70 2 71 14 70 8 70 0 71 22.05 2 65 13 64 5 65 2 65 13 64 4 65 24 13 48 10 48 0 49 13 48 10 48 15 48 32 7 35 4 35 9 35 7 35 4 35 8 35 44.1 9 32 6 32 11 32 9 32 6 32 10 32 48 7 24 5 24 8 24 7 24 5 24 8 24 64 11 17 10 17 12 17 11 17 10 17 12 17 88.2 4 16 3 16 5 16 4 16 3 16 5 16 96 3 12 2 12 4 12 3 12 2 12 4 12 128 14 8 13 8 14 8 14 8 13 8 14 8 176.4 2 8 not supported 3 8 2 8 not supported not supported 192 table 16-5. crystal frequency (values from 5.12 mhz to 8.192 mhz) crystal frequency (mhz) sampling frequency fs (khz) 8.192 8 7.3728 6.144 6 5.12 fractional integer fractional integer fractional integer fractional integer fractional integer fractional integer 11 194 5 195 6 194 0 195 5 195 0 195 8 4 141 12 141 1 141 8 141 12 141 8 141 11.025 12 129 3 130 10 129 0 130 3 130 0 130 12 5 97 10 97 3 97 8 97 10 97 8 97 16 10 70 14 70 8 70 12 70 14 70 12 70 22.05 14 64 2 65 13 64 0 65 2 65 0 65 24 11 48 13 48 10 48 12 48 13 48 12 48 32 5 35 7 35 4 35 6 35 7 35 6 35 44.1 7 32 9 32 6 32 8 32 9 32 8 32 48 5 24 7 24 5 24 6 24 7 24 6 24 64 11 17 11 17 10 17 11 17 11 17 11 17 88.2 4 16 4 16 3 16 4 16 4 16 4 16 96 3 12 3 12 2 12 3 12 3 12 3 12 128 13 8 14 8 13 8 not supported 14 8 not supported 176.4 2 8 2 8 not supported 2 8 2 8 2 8 192 757 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 16-6. crystal frequency (values from 10 mhz to 14.3181 mhz) crystal frequency (mhz) sampling frequency fs (khz) 14.3181 13.56 12.288 12 10 fractional integer fractional integer fractional integer fractional integer fractional integer 12 195 3 194 0 196 5 195 5 195 8 1 142 15 140 4 142 12 141 12 141 11.025 8 130 8 129 11 130 3 130 3 130 12 14 97 2 97 0 98 10 97 10 97 16 0 71 7 70f 2 71 14 70 14 70 22.05 4 65 12 64 5 65 2 65 2 65 24 15 48 9 48 0 49 13 48 13 48 32 8 35 4 35 9 35 7 35 7 35 44.1 10 32 6 32 11 32 9 32 9 32 48 8 24 4 24 8 24 7 24 7 24 64 12 17 10 17 12 17 11 17 11 17 88.2 5 16 3 16 5 16 4 16 4 16 96 4 12 2 12 4 12 3 12 3 12 128 14 8 13 8 14 8 14 8 14 8 176.4 not supported not supported 3 8 2 8 2 8 192 table 16-7. crystal frequency (values from 16 mhz to 16.384 mhz) crystal frequency (mhz) sampling frequency fs (khz) 16.384 16 fractional integer fractional integer 0 192 5 195 8 5 139 12 141 11.025 0 128 3 130 12 0 96 10 97 16 11 69 14 70 22.05 0 64 2 65 24 0 48 13 48 32 13 34 7 35 44.1 0 32 9 32 48 0 24 7 24 64 7 17 11 17 88.2 0 16 4 16 96 0 12 3 12 128 11 8 14 8 176.4 0 8 2 8 192 16.3.1.4 interrupt control a single interrupt is asserted to the cpu whenever any of the transmit or receive sources is asserted. the transmit module has two interrupt sources: the fifo service request and write error. the interrupts may be masked using the txsrim and txweim bits in the i 2 s interrupt mask (i2sim) march 20, 2011 758 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface register. the status of the interrupt source is indicated by the i 2 s raw interrupt status (i2sris) register. the status of enabled interrupts is indicated by the i 2 s masked interrupt status (i2smis) register. the fifo level interrupt has a second level of masking using the ffm bit in the i 2 s transmit interrupt status and mask (i2stxism) register. the fifo service request interrupt is asserted when the fifo level (indicated by the level field in the i 2 s transmit fifo level (i2stxlev) register) is below the fifo limit (programmed using the i 2 s transmit fifo limit (i2stxlimit) register) and both the txsrim and ffm bits are set. if software attempts to write to a full fifo, a transmit fifo write error occurs (indicated by the txweris bit in the i 2 s raw interrupt status (i2sris) register). the txweris bit in the i2sris register and the txwemis bit in the i2smis register are cleared by setting the txweic bit in the i 2 s interrupt clear (i2sic) register. 16.3.1.5 dma support the dma can be used to more efficiently stream data to and from the i 2 s bus. the i 2 s tranmit and receive modules have separate dma channels. the fifo interrupt mask bit ( ffm ) in the i2stxism register must be set for the request signaling to propagate to the dma module. see micro direct memory access (dma) on page 346 for channel configuration. the i 2 s module uses the dma burst request signal, not the single request. thus each time a dma request is made, the dma controller transfers the number of items specified as the burst size for the dma channel. therefore, the dma channel burst size and the i 2 s fifo service request limit must be set to the same value (using the limit field in the i2stxlimit register). 16.3.2 receive the receiver consists of a serial decoder, an 8-entry fifo, and control logic. the receiver has independent mclk ( i2s0rxmclk ), sclk (i2s0rxsck ), and word-select (i2s0rxws ) signals. 16.3.2.1 serial decoder the serial decoder accepts incoming audio stream data and places the sample data in the receive fifo. by configuring the serial decoder, common audio formats i 2 s, left-justified, and right-justified are supported. the msb is transmitted first. the sample size and system data size are configurable with the ssz and sdsz bits in the i 2 s receive module configuration (i2srxcfg) register. the sample size is the number of bits of data being received, and the system data size is the number of i2s0rxsck transitions between the word select transitions. the system data size must be large enough to accommodate the maximum sample size. any bits received after the lsb are 0s. if the fifo is full, the incoming sample (in mono) or sample-pairs (stereo) are dropped until the fifo has space. the serial decoder is enabled using the rxen bit in the i2scfg register. 16.3.2.2 fifo operation the receive fifo stores eight mono samples or eight stereo sample-pairs of data and is accessed through the i 2 s receive fifo data (i2srxfifo) register. table 16-8 on page 760 defines the interface for each read mode. all data is stored msb-aligned. the stereo data is read left sample then right. in mono mode, the fifo interface can be configured to read the right or left channel by setting the fifo mono mode bit ( fmm ) in the i 2 s receive fifo configuration (i2srxfifocfg) register. this enables reads from a single channel, where the channel selected can be either the right or left as determined by the lrp bit in the i2srxcfg register. 759 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 16-8. i 2 s receive fifo interface data alignment samples per fifo read sample width read mode css bit in i2srxfifocfg rm bit in i2rxcfg msb 1 8-32 bits stereo don't care 0 msb right [31:15], left [15:0] 2 8-16 bits compact stereo - 16 bit 0 1 right [15:8] left[7:0] 2 8 bits compact stereo - 8 bit 1 1 msb 1 8-32 bits mono ( fmm bit in the i2srxfifocfg register must be set.) don't care 0 the number of samples in the receive fifo can be read using the i 2 s receive fifo level (i2srxlev) register. the value ranges from 0 to 16. stereo and compact stereo sample pairs are counted as two. the mono samples also increment the count by two, therefore four mono samples will have a count of eight. 16.3.2.3 clock control the receiver mclk and sclk can be independently programmed to be the master or slave. the receiver is programmed to be the master or slave of the sclk using the msl bit in the i2srxcfg register. when the receiver is the master, the i2s0rxsck frequency is the specified i2s0rxmclk divided by four. the i2s0rxsck may be inverted using the scp bit in the i2srxcfg register. the receiver can also be the master or slave of the mclk. when the receiver is the master, the pll must be active and a fractional clock divider must be programmed. see page 227 for the setup for the master i2s0rxmclk source. an external transmit i2s0rxmclk does not require the use of the pll and is selected using the rxslv bit in the i2scfg register. refer to clock control on page 756 for combinations of the rxint and rxfrac bits in the i 2 s mclk configuration (i2smclkcfg) register that provide mclk frequencies within acceptable error limits. in the table, fs is the sampling frequency in khz and possible crystal frequencies are shown in mhz across the top row of the table. the words "not supported" in the table mean that it is not possible to obtain the specified sampling frequencies with the specified crystal frequency within the error tolerance of 0.3%. 16.3.2.4 interrupt control a single interrupt is asserted to the cpu whenever any of the transmit or receive sources is asserted. the receive module has two interrupt sources: the fifo service request and read error. the interrupts may be masked using the rxsrim and rxreim bits in the i2sim register. the status of the interrupt source is indicated by the i2sris register. the status of enabled interrupts is indicated by the i2smis register. the fifo service request interrupt has a second level of masking using the ffm bit in the i 2 s receive interrupt status and mask (i2srxism) register. the sources may be masked using the i2sim register. the fifo service request interrupt is asserted when the fifo level (indicated by the level field in the i 2 s receive fifo level (i2srxlev) register) is above the fifo limit (programmed using the i 2 s receive fifo limit (i2srxlimit) register) and both the rxsrim and ffm bits are set. an error occurs when reading an empty fifo or if a stereo sample pair is not read left then right. to clear an interrupt, write a 1 to the appropriate bit in the i2sic register. if software attempts to read an empty fifo or if a stereo sample pair is not read left then right, a receive fifo read error occurs (indicated by the rxreris bit in the i2sris register). the rxreris bit in the i2sris register and the rxremis bit in the i2smis register are cleared by setting the rxreic bit in the i2sic register. march 20, 2011 760 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface 16.3.2.5 dma support the dma can be used to more efficiently stream data to and from the i 2 s bus. the i 2 s transmit and receive modules have separate dma channels. the fifo interrupt mask bit ( ffm ) in the i2srxism register must be set for the request signaling to propagate to the dma module. see micro direct memory access (dma) on page 346 for channel configuration. the i 2 s module uses the dma burst request signal, not the single request. thus each time a dma request is made, the dma controller transfers the number of items specified as the burst size for the dma channel. therefore, the dma channel burst size and the i 2 s fifo service request limit must be set to the same value (using the limit field in the i2srxlimit register). 16.4 initialization and configuration the default setup for the i 2 s transmit and receive is to use external mclk, external sclk, stereo, i 2 s audio format, and 32-bit data samples. the following example shows how to configure a system using the internal mclk, internal sclk, compact stereo, and left-justified audio format with 16-bit data samples. 1. enable the i 2 s peripheral clock by writing a value of 0x1000.0000 to the rcgc1 register in the system control module (see page 260). 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module (see page 269). to find out which gpio port to enable, refer to table 21-5 on page 925. 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register (see page 428). to determine which gpios to configure, see table 21-4 on page 917. 4. configure the pmcn fields in the gpiopctl register to assign the i 2 s signals to the appropriate pins (see page 446 and table 21-5 on page 925). 5. set up the mclk sources for a 48-khz sample rate. the input crystal is assumed to be 6 mhz for this example (internal source). enable the pll by clearing the pwrdwn bit in the rcc register in the system control module (see page 211). set the mclk dividers and enable them by writing 0x0208.0208 to the i2smclkcfg register in the system control module (see page 227). enable the mclk internal sources by writing 0x8208.8208 to the i2smclkcfg register in the system control module. to allow an external mclk to be used, set bits 4 and 5 of the i2scfg register. starting up the pll and enabling the mclk sources is not required. 6. set up the serial bit clock sclk source. by default, the sclk is externally sourced. receiver: masters the i2s0rxsck by oring 0x0040.0000 into the i2srxcfg register. transmitter: masters the i2s0txsck by oring 0x0040.0000 into the i2stxcfg register. 7. configure the serial encoder/decoder (left-justified, compact stereo, 16-bit samples, 32-bit system data size). 761 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller set the audio format using the justification ( jst ), data delay (dly ), sclk polarity (scp), and left-right polarity ( lrp ) bits written to the i2stxcfg and i2srxcfg registers. the settings are shown in the table below. table 16-9. audio formats configuration i2stxcfg/i2srxcfg register bit audio format lrp scp dly jst 1 0 1 0 i 2 s 0 0 0 0 left-justified 0 0 0 1 right-justified write 0x0140.3df0 to both the i2stxcfg and i2srxcfg registers to program the following configurations: C set the sample size to 16 bits using the ssz field of the i2stxcfg and i2srxcfg registers. C set the system data size to 32 bits using the sdsz field of the i2stxcfg and i2srxcfg registers. C set the write and read modes using the wm and rm fields in the i2stxcfg and i2srxcfg registers, respectively. 8. set up the fifo limits for triggering interrupts (also used for dma) set up the transmit fifo to trigger when it has less than four sample pairs by writing a 0x0000.0008 to the i2stxlimit register. set up the receive fifo to trigger when there are more than four sample pairs by writing a 0x0000.00008 to the i2srxlimit register. 9. enable interrupts. enable the transmit fifo interrupt by setting the ffm bit in the i2stxism register (write 0x0000.0001). set up the receive fifo interrupts by setting the ffm bit in the i2srxism register (write 0x0000.0001). enable the tx fifo service request, the tx error, the rx fifo service request, and the rx error interrupts to be sent to the cpu by writing a 0x0000.0033 to the i2ssim register. 10. enable the serial encoder and serial decoders by writing a 0x0000.0003 to the i2scfg register. 16.5 register map table 16-10 on page 763 lists the i 2 s registers. the offset listed is a hexadecimal increment to the registers address, relative to the i 2 s interface base address of 0x4005.4000. note that the i 2 s module clock must be enabled before the registers can be programmed (see page 260). there must be a delay of 3 system clocks after the i 2 s module clock is enabled before any i 2 s module registers are accessed. march 20, 2011 762 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface table 16-10. inter-integrated circuit sound (i 2 s) interface register map see page description reset type name offset 764 i2s transmit fifo data 0x0000.0000 wo i2stxfifo 0x000 765 i2s transmit fifo configuration 0x0000.0000 r/w i2stxfifocfg 0x004 766 i2s transmit module configuration 0x1400.7df0 r/w i2stxcfg 0x008 768 i2s transmit fifo limit 0x0000.0000 r/w i2stxlimit 0x00c 769 i2s transmit interrupt status and mask 0x0000.0000 r/w i2stxism 0x010 770 i2s transmit fifo level 0x0000.0000 ro i2stxlev 0x018 771 i2s receive fifo data 0x0000.0000 ro i2srxfifo 0x800 772 i2s receive fifo configuration 0x0000.0000 r/w i2srxfifocfg 0x804 773 i2s receive module configuration 0x1400.7df0 r/w i2srxcfg 0x808 775 i2s receive fifo limit 0x0000.7fff r/w i2srxlimit 0x80c 776 i2s receive interrupt status and mask 0x0000.0000 r/w i2srxism 0x810 777 i2s receive fifo level 0x0000.0000 ro i2srxlev 0x818 778 i2s module configuration 0x0000.0000 r/w i2scfg 0xc00 780 i2s interrupt mask 0x0000.0000 r/w i2sim 0xc10 782 i2s raw interrupt status 0x0000.0000 ro i2sris 0xc14 784 i2s masked interrupt status 0x0000.0000 ro i2smis 0xc18 786 i2s interrupt clear 0x0000.0000 wo i2sic 0xc1c 16.6 register descriptions the remainder of this section lists and describes the i 2 s registers, in numerical order by address offset. 763 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: i 2 s transmit fifo data (i2stxfifo), offset 0x000 this register is the 32-bit serial audio transmit data register. in stereo mode, the data is written left, right, left, right, and so on. the lrs bit in the i 2 s transmit fifo configuration (i2stxfifocfg) register can be read to verify the next position expected. in compact 16-bit mode, bits [31:16] contain the right sample, and bits [15:0] contain the left sample. in compact 8-bit mode, bits [15:8] contain the right sample, and bits [7:0] contain the left sample. in mono mode, each 32-bit entry is a single sample. note that if the fifo is full and a write is attempted, a transmit fifo write error is generated. i2s transmit fifo data (i2stxfifo) base 0x4005.4000 offset 0x000 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 txfifo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txfifo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field tx data serial audio sample data to be transmitted. 0x0000.0000 wo txfifo 31:0 march 20, 2011 764 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface register 2: i 2 s transmit fifo configuration (i2stxfifocfg), offset 0x004 this register configures the sample for dual-channel operation. in stereo mode, the lrs bit toggles between left and right samples as the transmit fifo is written. the left sample is written first, followed by the right. i2s transmit fifo configuration (i2stxfifocfg) base 0x4005.4000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lrs css reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 compact stereo sample size description value the transmitter is in compact 16-bit stereo mode with a 16-bit sample size. 0 the transmitter is in compact 8-bit stereo mode with an 8-bit sample size. 1 0 r/w css 1 left-right sample indicator description value the left sample is the next position. 0 the right sample is the next position. 1 in mono mode and compact stereo mode, this bit toggles as if it were in stereo mode, but it has no meaning and should be ignored. 0 r/w lrs 0 765 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 3: i 2 s transmit module configuration (i2stxcfg), offset 0x008 this register controls the configuration of the transmit module. i2s transmit module configuration (i2stxcfg) base 0x4005.4000 offset 0x008 type r/w, reset 0x1400.7df0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved msl fmt wm lrp scp dly jst reserved ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved sdsz ssz ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:30 justification of output data description value the data is left-justified. 0 the data is right-justified. 1 0 r/w jst 29 data delay description value data is latched on the next latching edge of i2s0txsck as defined by the scp bit. this bit should be clear in left-justified or right-justified mode. 0 a one- i2s0txsck delay from the edge of i2s0txws is inserted before data is latched. this bit should be set in i 2 s mode. 1 1 r/w dly 28 sclk polarity description value data and the i2s0txws signal (when the msl bit is set) are launched on the falling edge of i2s0txsck. 0 data and the i2s0txws signal (when the msl bit is set) are launched on the rising edge of i2s0txsck. 1 0 r/w scp 27 left/right clock polarity description value i2s0txws is high during the transmission of the left channel data. 0 i2s0txws is high during the transmission of the right channel data. 1 1 r/w lrp 26 march 20, 2011 766 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface description reset type name bit/field write mode this bit field selects the mode in which the transmit data is stored in the fifo and transmitted. description value stereo mode 0x0 compact stereo mode left/right sample packed. refer to i2stxfifocfg for 8/16-bit sample size selection. 0x1 mono mode 0x2 reserved 0x3 0x0 r/w wm 25:24 fifo empty description value all zeroes are transmitted if the fifo is empty. 0 the last sample is transmitted if the fifo is empty. 1 0 r/w fmt 23 sclk master/slave source of serial bit clock ( i2s0txsck ) and word select (i2s0txws). description value the transmitter is a slave using the externally driven i2s0txsck and i2s0txws signals. 0 the transmitter is a master using the internally generated i2s0txsck and i2s0txws signals. 1 0 r/w msl 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 21:16 sample size this field contains the number of bits minus one in the sample. note: this field is only used in right-justified mode. unused bits are not masked. 0x1f r/w ssz 15:10 system data size this field contains the number of bits minus one during the high or low phase of the i2s0txws signal. 0x1f r/w sdsz 9:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 767 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: i 2 s transmit fifo limit (i2stxlimit), offset 0x00c this register sets the lower fifo limit at which a fifo service request is issued. i2s transmit fifo limit (i2stxlimit) base 0x4005.4000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 limit reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 fifo limit this field sets the fifo level at which a fifo service request is issued, generating an interrupt or a dma transfer request. the transmit fifo generates a service request when the number of items in the fifo is less than the level specified by the limit field. for example, if the limit field is set to 8, then a service request is generated when there are less than 8 samples remaining in the transmit fifo. 0x00 r/w limit 4:0 march 20, 2011 768 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface register 5: i 2 s transmit interrupt status and mask (i2stxism), offset 0x010 this register indicates the transmit interrupt status and interrupt masking control. i2s transmit interrupt status and mask (i2stxism) base 0x4005.4000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ffi reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ffm reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 transmit fifo service request interrupt description value the fifo level is equal to or above the fifo limit. 0 the fifo level is below the fifo limit. 1 0 ro ffi 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:1 fifo interrupt mask description value the fifo interrupt is masked and not sent to the cpu. 0 the fifo interrupt is enabled to be sent to the interrupt controller. 1 0 r/w ffm 0 769 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 6: i 2 s transmit fifo level (i2stxlev), offset 0x018 the number of samples in the transmit fifo can be read using the i2stxlev register. the value ranges from 0 to 16. stereo and compact stereo sample-pairs are counted as two. mono samples also increment the count by two. for example, the level field is set to eight if there are four mono samples. i2s transmit fifo level (i2stxlev) base 0x4005.4000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 level reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 number of audio samples this field contains the number of samples in the fifo. 0x00 ro level 4:0 march 20, 2011 770 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface register 7: i 2 s receive fifo data (i2srxfifo), offset 0x800 important: this register is read-sensitive. see the register description for details. this register is the 32-bit serial audio receive data register. in stereo mode, the data is read left, right, left, right, and so on. the lrs bit in the i 2 s receive fifo configuration (i2srxfifocfg) register can be read to verify the next position expected. in compact 16-bit mode, bits [31:16] contain the right sample, and bits [15:0] contain the left sample. in compact 8-bit mode, bits [15:8] contain the right sample, and bits [7:0] contain the left sample. in mono mode, each 32-bit entry is a single sample. if the fifo is empty, a read of this register returns a value of 0x0000.0000 and generates a receive fifo read error. i2s receive fifo data (i2srxfifo) base 0x4005.4000 offset 0x800 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rxfifo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxfifo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field rx data serial audio sample data received. the read of an empty fifo returns a value of 0x0. 0x0000.0000 ro rxfifo 31:0 771 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 8: i 2 s receive fifo configuration (i2srxfifocfg), offset 0x804 this register configures the sample for dual-channel operation. in stereo mode, the lrs bit toggles between left and right as the samples are read from the receive fifo. in mono mode, both the left and right samples are stored in the fifo. the fmm bit can be used to read only the left or right sample as determined by the lrp bit. in compact stereo 8- or 16-bit mode, both the left and right samples are read in one access from the fifo. i2s receive fifo configuration (i2srxfifocfg) base 0x4005.4000 offset 0x804 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lrs css fmm reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 fifo mono mode description value the receiver is in stereo mode. 0 the receiver is in mono mode. if the lrp bit in the i2srxcfg register is clear, data is read while the i2s0rxws signal is low (right channel); if the lrp bit is set, data is read while the i2s0rxws signal is high (left channel). 1 0 r/w fmm 2 compact stereo sample size description value the receiver is in compact 16-bit stereo mode with a 16-bit sample size. 0 the receiver is in compact 8-bit stereo mode with a 8-bit sample size. 1 0 r/w css 1 left-right sample indicator description value the left sample is the next position to be read. 0 the right sample is the next position to be read. 1 this bit is only meaningful in compact stereo mode. 0 r/w lrs 0 march 20, 2011 772 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface register 9: i 2 s receive module configuration (i2srxcfg), offset 0x808 this register controls the configuration of the receive module. i2s receive module configuration (i2srxcfg) base 0x4005.4000 offset 0x808 type r/w, reset 0x1400.7df0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved msl reserved rm reserved lrp scp dly jst reserved ro ro ro ro ro ro r/w ro r/w ro r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved sdsz ssz ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:30 justification of input data description value the data is left-justified. 0 the data is right-justified. 1 0 r/w jst 29 data delay description value data is latched on the next latching edge of i2s0rxsck as defined by the scp bit. this bit should be clear in left-justified or right-justified mode. 0 a one- i2s0rxsck delay from the edge of i2s0rxws is inserted before data is latched. this bit should be set in i 2 s mode. 1 1 r/w dly 28 sclk polarity description value data is latched on the rising edge and the i2s0rxws signal (when the msl bit is set) is launched on the falling edge of i2s0rxsck. 0 data is latched on the falling edge and the i2s0rxws signal (when the msl bit is set) is launched on the rising edge of i2s0rxsck. 1 0 r/w scp 27 773 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field left/right clock polarity description value in stereo mode, i2s0rxws is high during the transmission of the left channel data. in mono mode, data is read while the i2s0rxws signal is low (right channel). 0 in stereo mode, i2s0rxws is high during the transmission of the right channel data. in mono mode, data is read while the i2s0rxws signal is high (left channel). 1 1 r/w lrp 26 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 25 read mode this bit selects the mode in which the receive data is received and stored in the fifo. description value stereo/mono mode i2srxfifocfg fmm bit specifies stereo or mono fifo read behavior. 0 compact stereo mode left/right sample packed. refer to i2srxfifocfg for 8/16-bit sample size selection. 1 0 r/w rm 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23 sclk master/slave description value the receiver is a slave and uses the externally driven i2s0rxsck and i2s0rxws signals. 0 the receiver is a master and uses the internally generated i2s0rxsck and i2s0rxws signals. 1 0 r/w msl 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 21:16 sample size this field contains the number of bits minus one in the sample. 0x1f r/w ssz 15:10 system data size this field contains the number of bits minus one during the high or low phase of the i2s0rxws signal. 0x1f r/w sdsz 9:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 march 20, 2011 774 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface register 10: i 2 s receive fifo limit (i2srxlimit), offset 0x80c this register sets the upper fifo limit at which a fifo service request is issued. i2s receive fifo limit (i2srxlimit) base 0x4005.4000 offset 0x80c type r/w, reset 0x0000.7fff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 limit reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x7ff ro reserved 15:5 fifo limit this field sets the fifo level at which a fifo service request is issued, generating an interrupt or a dma transfer request. the receive fifo generates a service request when the number of items in the fifo is greater than the level specified by the limit field. for example, if the limit field is set to 4, then a service request is generated when there are more than 4 samples remaining in the transmit fifo. 0x1f r/w limit 4:0 775 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 11: i 2 s receive interrupt status and mask (i2srxism), offset 0x810 this register indicates the receive interrupt status and interrupt masking control. i2s receive interrupt status and mask (i2srxism) base 0x4005.4000 offset 0x810 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ffi reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ffm reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 receive fifo service request interrupt description value the fifo level is equal to or below the fifo limit. 0 the fifo level is above the fifo limit. 1 0 ro ffi 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:1 fifo interrupt mask description value the fifo interrupt is masked and not sent to the cpu. 0 the fifo interrupt is enabled to be sent to the interrupt controller. 1 0 r/w ffm 0 march 20, 2011 776 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface register 12: i 2 s receive fifo level (i2srxlev), offset 0x818 the number of samples in the receive fifo can be read using the i2srxlev register. the value ranges from 0 to 16. stereo and compact stereo sample pairs are counted as two. mono samples also increment the count by two. for example, the level field is set to eight if there are four mono samples. i2s receive fifo level (i2srxlev) base 0x4005.4000 offset 0x818 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 level reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 number of audio samples this field contains the number of samples in the fifo. 0x00 ro level 4:0 777 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 13: i 2 s module configuration (i2scfg), offset 0xc00 this register enables the transmit and receive serial engines and sets the source of the i2s0txmclk and i2s0rxmclk signals. i2s module configuration (i2scfg) base 0x4005.4000 offset 0xc00 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txen rxen reserved txslv rxslv reserved r/w r/w ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 use external i2s0rxmclk description value the receiver uses the internally generated mclk as the i2s0rxmclk signal. see clock control on page 756 for information on how to program the i2s0rxmclk. 0 the receiver uses the externally driven i2s0rxmclk signal. 1 0 r/w rxslv 5 use external i2s0txmclk description value the transmitter uses the internally generated mclk as the i2s0txmclk signal. see clock control on page 756 for information on how to program the i2s0txmclk. 0 the transmitter uses the externally driven i2s0txmclk signal. 1 0 r/w txslv 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 serial receive engine enable description value disables the serial receive engine. 0 enables the serial receive engine. 1 0 r/w rxen 1 march 20, 2011 778 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface description reset type name bit/field serial transmit engine enable description value disables the serial transmit engine. 0 enables the serial transmit engine. 1 0 r/w txen 0 779 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 14: i 2 s interrupt mask (i2sim), offset 0xc10 this register masks the interrupts to the cpu. i2s interrupt mask (i2sim) base 0x4005.4000 offset 0xc10 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txsrim txweim reserved rxsrim rxreim reserved r/w r/w ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 receive fifo read error description value the receive fifo read error interrupt is masked and not sent to the cpu. 0 the receive fifo read error is enabled to be sent to the interrupt controller. 1 0 r/w rxreim 5 receive fifo service request description value the receive fifo service request interrupt is masked and not sent to the cpu. 0 the receive fifo service request is enabled to be sent to the interrupt controller. 1 0 r/w rxsrim 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 transmit fifo write error description value the transmit fifo write error interrupt is masked and not sent to the cpu. 0 the transmit fifo write error is enabled to be sent to the interrupt controller. 1 0 r/w txweim 1 march 20, 2011 780 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface description reset type name bit/field transmit fifo service request description value the transmit fifo service request interrupt is masked and not sent to the cpu. 0 the transmit fifo service request is enabled to be sent to the interrupt controller. 1 0 r/w txsrim 0 781 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 15: i 2 s raw interrupt status (i2sris), offset 0xc14 this register reads the unmasked interrupt status. i2s raw interrupt status (i2sris) base 0x4005.4000 offset 0xc14 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txsrris txweris reserved rxsrris rxreris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 receive fifo read error description value a receive fifo read error interrupt has occurred. 1 no interrupt 0 this bit is cleared by setting the rxreic bit in the i2sic register. 0 ro rxreris 5 receive fifo service request description value a receive fifo service request interrupt has occurred. 1 no interrupt 0 this bit is cleared when the level in the receive fifo has risen to a value greater than the value programmed in the limit field in the i2srxlimit register. 0 ro rxsrris 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 transmit fifo write error description value a transmit fifo write error interrupt has occurred. 1 no interrupt 0 this bit is cleared by setting the txweic bit in the i2sic register. 0 ro txweris 1 march 20, 2011 782 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface description reset type name bit/field transmit fifo service request description value a transmit fifo service request interrupt has occurred. 1 no interrupt 0 this bit is cleared when the level in the transmit fifo has fallen to a value less than the value programmed in the limit field in the i2stxlimit register. 0 ro txsrris 0 783 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 16: i 2 s masked interrupt status (i2smis), offset 0xc18 this register reads the masked interrupt status. the mask is defined in the i2sim register. i2s masked interrupt status (i2smis) base 0x4005.4000 offset 0xc18 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txsrmis txwemis reserved rxsrmis rxremis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 receive fifo read error description value an unmasked interrupt was signaled due to a receive fifo read error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by setting the rxreic bit in the i2sic register. 0 ro rxremis 5 receive fifo service request description value an unmasked interrupt was signaled due to a receive fifo service request. 1 an interrupt has not occurred or is masked. 0 this bit is cleared when the level in the receive fifo has risen to a value greater than the value programmed in the limit field in the i2srxlimit register. 0 ro rxsrmis 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0s0 ro reserved 3:2 transmit fifo write error description value an unmasked interrupt was signaled due to a transmit fifo write error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by setting the txweic bit in the i2sic register. 0 ro txwemis 1 march 20, 2011 784 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface description reset type name bit/field transmit fifo service request description value an unmasked interrupt was signaled due to a transmit fifo service request. 1 an interrupt has not occurred or is masked. 0 this bit is cleared when the level in the transmit fifo has fallen to a value less than the value programmed in the limit field in the i2stxlimit register. 0 ro txsrmis 0 785 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 17: i 2 s interrupt clear (i2sic), offset 0xc1c writing a 1 to a bit in this register clears the corresponding interrupt. i2s interrupt clear (i2sic) base 0x4005.4000 offset 0xc1c type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved txweic reserved rxreic reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 wo reserved 31:6 receive fifo read error writing a 1 to this bit clears the rxreris bit in the i2cris register and the rxremis bit in the i2cmis register. 0 wo rxreic 5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 wo reserved 4:2 transmit fifo write error writing a 1 to this bit clears the txweris bit in the i2cris register and the txwemis bit in the i2cmis register. 0 wo txweic 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 wo reserved 0 march 20, 2011 786 texas instruments-advance information inter-integrated circuit sound (i 2 s) interface 17 analog comparators an analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. note: not all comparators have the option to drive an output pin. see signal description on page 788 for more information. the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board. in addition, the comparator can signal the application via interrupts or trigger the start of a sample sequence in the adc. the interrupt generation and adc triggering logic is separate and independent. this flexibility means, for example, that an interrupt can be generated on a rising edge and the adc triggered on a falling edge. the stellaris ? lm3s1p51 microcontroller provides two independent integrated analog comparators with the following functions: compare external pin input to external pin input or to internal programmable voltage reference compare a test voltage against any one of the following voltages: C an individual external reference voltage C a shared single external reference voltage C a shared internal reference voltage 17.1 block diagram figure 17-1. analog comparator module block diagram 787 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 9 r o w d j h 5 h i $ & 5 ( ) & 7 / r x w s x w y h l q s x w d o w h u q d w h y h l q s x w l q w h u u x s w w u l j j h u y h l q s x w u h i h u h q f h l q s x w & r p s d u d w r u $ & 6 7 $ 7 $ & & 7 / & l q w h u q d o e x v w u l j j h u & & r w u l j j h u & & r x w s x w y h l q s x w d o w h u q d w h y h l q s x w l q w h u u x s w w u l j j h u y h l q s x w u h i h u h q f h l q s x w & r p s d u d w r u $ & 6 7 $ 7 $ & & 7 / & r , q w h u u x s w & r q w u r o $ & 5 , 6 $ & 0 , 6 $ & , 1 7 ( 1 l q w h u u x s w 17.2 signal description table 17-1 on page 788 and table 17-2 on page 788 list the external signals of the analog comparators and describe the function of each. the analog comparator output signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the analog comparator signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the analog comparator function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the analog comparator signal to the specified gpio port pin. the positive and negative input signals are configured by clearing the den bit in the gpio digital enable (gpioden) register. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. table 17-1. signals for analog comparators (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name analog comparator 0 positive input. analog i pb6 90 c0+ analog comparator 0 negative input. analog i pb4 92 c0- analog comparator 0 output. ttl o pc5 (3) pf4 (2) pb6 (3) pb5 (1) pd7 (2) 24 58 90 91 100 c0o analog comparator 1 positive input. analog i pc5 24 c1+ analog comparator 1 negative input. analog i pb5 91 c1- analog comparator 1 output. ttl o pe6 (2) pc7 (7) pc5 (2) pf5 (2) ph2 (2) 2 22 24 46 84 c1o a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 17-2. signals for analog comparators (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name analog comparator 0 positive input. analog i pb6 a7 c0+ analog comparator 0 negative input. analog i pb4 a6 c0- analog comparator 0 output. ttl o pc5 (3) pf4 (2) pb6 (3) pb5 (1) pd7 (2) m1 l9 a7 b7 a2 c0o analog comparator 1 positive input. analog i pc5 m1 c1+ analog comparator 1 negative input. analog i pb5 b7 c1- analog comparator 1 output. ttl o pe6 (2) pc7 (7) pc5 (2) pf5 (2) ph2 (2) a1 l2 m1 l8 d11 c1o a. the ttl designation indicates the pin has ttl-compatible voltage levels. march 20, 2011 788 texas instruments-advance information analog comparators 17.3 functional description the comparator compares the vin- and vin+ inputs to produce an output, vout. vin- < vin+, vout = 1 vin- > vin+, vout = 0 as shown in figure 17-2 on page 789, the input source for vin- is an external input, cn- . in addition to an external input, cn+ , input sources for vin+ can be the c0+ or an internal reference, v iref . figure 17-2. structure of comparator unit a comparator is configured through two status/control registers, analog comparator control (acctl) and analog comparator status (acstat) . the internal reference is configured through one control register, analog comparator reference voltage control (acrefctl) . interrupt status and control are configured through three registers, analog comparator masked interrupt status (acmis) , analog comparator raw interrupt status (acris) , and analog comparator interrupt enable (acinten) . typically, the comparator output is used internally to generate an interrupt as controlled by the isen bit in the acctl register. the output may also be used to drive an external pin, co or generate an analog-to-digital converter (adc) trigger. important: the asrcp bits in the acctl register must be set before using the analog comparators. 17.3.1 internal reference programming the structure of the internal reference is shown in figure 17-3 on page 790. the internal reference is controlled by a single configuration register ( acrefctl ). table 17-3 on page 790 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally (v iref ). 789 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller $ & & 7 / & , 1 9 l q w h u q d o e x v l q w h u u x s w w u l j j h u 7 u l j * h q r x w s x w $ & 6 7 $ 7 , q w * h q y h l q s x w d o w h u q d w h y h l q s x w y h l q s x w u h i h u h q f h l q s x w figure 17-3. comparator internal reference structure table 17-3. internal reference voltage and acrefctl field values output reference voltage based on vref field value acrefctl register rng bit value en bit value 0 v (gnd) for any value of vref ; however, it is recommended that rng =1 and vref =0 for the least noisy ground reference. rng=x en=0 total resistance in ladder is 31 r. the range of internal reference in this mode is 0.85-2.448 v. rng=0 en=1 total resistance in ladder is 23 r. the range of internal reference for this mode is 0-2.152 v. rng=1 march 20, 2011 790 texas instruments-advance information analog comparators t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 5 5 5 5 5 ? ? ? ? ? ? ' h f r g h u 9 ' ' $ ( 1 l q w h u q d o u h i h u h q f h 9 , 5 ( ) 9 5 ( ) 5 1 * t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 17.4 initialization and configuration the following example shows how to configure an analog comparator to read back its output value from an internal register. 1. enable the analog comparator clock by writing a value of 0x0010.0000 to the rcgc1 register in the system control module (see page 260). 2. enable the clock to the appropriate gpio modules via the rcgc2 register (see page 269). to find out which gpio ports to enable, refer to table 21-5 on page 925. 3. in the gpio module, enable the gpio port/pin associated with the input signals as gpio inputs. to determine which gpio to configure, see table 21-4 on page 917. 4. configure the pmcn fields in the gpiopctl register to assign the analog comparator output signals to the appropriate pins (see page 446 and table 21-5 on page 925). 5. configure the internal voltage reference to 1.65 v by writing the acrefctl register with the value 0x0000.030c. 6. configure the comparator to use the internal voltage reference and to not invert the output by writing the acctln register with the value of 0x0000.040c. 7. delay for 10 s. 8. read the comparator output value by reading the acstatn registers oval value. change the level of the comparator negative input signal c- to see the oval value change. 17.5 register map table 17-4 on page 791 lists the comparator registers. the offset listed is a hexadecimal increment to the registers address, relative to the analog comparator base address of 0x4003.c000. note that the analog comparator clock must be enabled before the registers can be programmed (see page 260). there must be a delay of 3 system clocks after the analog comparator module clock is enabled before any analog comparator module registers are accessed. table 17-4. analog comparators register map see page description reset type name offset 793 analog comparator masked interrupt status 0x0000.0000 r/w1c acmis 0x000 794 analog comparator raw interrupt status 0x0000.0000 ro acris 0x004 795 analog comparator interrupt enable 0x0000.0000 r/w acinten 0x008 796 analog comparator reference voltage control 0x0000.0000 r/w acrefctl 0x010 797 analog comparator status 0 0x0000.0000 ro acstat0 0x020 798 analog comparator control 0 0x0000.0000 r/w acctl0 0x024 797 analog comparator status 1 0x0000.0000 ro acstat1 0x040 798 analog comparator control 1 0x0000.0000 r/w acctl1 0x044 791 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 17.6 register descriptions the remainder of this section lists and describes the analog comparator registers, in numerical order by address offset. march 20, 2011 792 texas instruments-advance information analog comparators register 1: analog comparator masked interrupt status (acmis), offset 0x000 this register provides a summary of the interrupt status (masked) of the comparators. analog comparator masked interrupt status (acmis) base 0x4003.c000 offset 0x000 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in0 in1 reserved r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 comparator 1 masked interrupt status description value the in1 bits in the acris register and the acinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the in1 bit in the acris register. 0 r/w1c in1 1 comparator 0 masked interrupt status description value the in0 bits in the acris register and the acinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the in0 bit in the acris register. 0 r/w1c in0 0 793 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: analog comparator raw interrupt status (acris), offset 0x004 this register provides a summary of the interrupt status (raw) of the comparators. the bits in this register must be enabled to generate interrupts using the acinten register. analog comparator raw interrupt status (acris) base 0x4003.c000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in0 in1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 comparator 1 interrupt status description value comparator 1 has generated an interruptfor an event as configured by the isen bit in the acctl1 register. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in1 bit in the acmis register. 0 ro in1 1 comparator 0 interrupt status description value comparator 0 has generated an interrupt for an event as configured by the isen bit in the acctl0 register. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in0 bit in the acmis register. 0 ro in0 0 march 20, 2011 794 texas instruments-advance information analog comparators register 3: analog comparator interrupt enable (acinten), offset 0x008 this register provides the interrupt enable for the comparators. analog comparator interrupt enable (acinten) base 0x4003.c000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in0 in1 reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 comparator 1 interrupt enable description value the raw interrupt signal comparator 1 is sent to the interrupt controller. 1 a comparator 1 interrupt does not affect the interrupt status. 0 0 r/w in1 1 comparator 0 interrupt enable description value the raw interrupt signal comparator 0 is sent to the interrupt controller. 1 a comparator 0 interrupt does not affect the interrupt status. 0 0 r/w in0 0 795 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 4: analog comparator reference voltage control (acrefctl), offset 0x010 this register specifies whether the resistor ladder is powered on as well as the range and tap. analog comparator reference voltage control (acrefctl) base 0x4003.c000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vref reserved rng en reserved r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:10 resistor ladder enable description value the resistor ladder is unpowered. 0 powers on the resistor ladder. the resistor ladder is connected to v dda . 1 this bit is cleared at reset so that the internal reference consumes the least amount of power if it is not used. 0 r/w en 9 resistor ladder range description value the resistor ladder has a total resistance of 31 r. 0 the resistor ladder has a total resistance of 23 r. 1 0 r/w rng 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 resistor ladder voltage ref the vref bit field specifies the resistor ladder tap that is passed through an analog multiplexer. the voltage corresponding to the tap position is the internal reference voltage available for comparison. see table 17-3 on page 790 for some output reference voltage examples. 0x0 r/w vref 3:0 march 20, 2011 796 texas instruments-advance information analog comparators register 5: analog comparator status 0 (acstat0), offset 0x020 register 6: analog comparator status 1 (acstat1), offset 0x040 these registers specify the current output value of the comparator. analog comparator status 0 (acstat0) base 0x4003.c000 offset 0x020 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved oval reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 comparator output value description value vin- > vin+ 0 vin- < vin+ 1 vin - is the voltage on the cn- pin. vin+ is the voltage on the cn+ pin, the c0+ pin, or the internal voltage reference (v iref ) as defined by the asrcp bit in the acctl register. 0 ro oval 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 797 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 7: analog comparator control 0 (acctl0), offset 0x024 register 8: analog comparator control 1 (acctl1), offset 0x044 these registers configure the comparators input and output. analog comparator control 0 (acctl0) base 0x4003.c000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved cinv isen islval tsen tslval reserved asrcp toen reserved ro r/w r/w r/w r/w r/w r/w r/w ro r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 trigger output enable description value adc events are suppressed and not sent to the adc. 0 adc events are sent to the adc. 1 0 r/w toen 11 analog source positive the asrcp field specifies the source of input voltage to the vin+ terminal of the comparator. the encodings for this field are as follows: description value pin value of cn+ 0x0 pin value of c0+ 0x1 internal voltage reference (v iref ) 0x2 reserved 0x3 0x0 r/w asrcp 10:9 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 8 trigger sense level value description value an adc event is generated if the comparator output is low. 0 an adc event is generated if the comparator output is high. 1 0 r/w tslval 7 march 20, 2011 798 texas instruments-advance information analog comparators description reset type name bit/field trigger sense the tsen field specifies the sense of the comparator output that generates an adc event. the sense conditioning is as follows: description value level sense, see tslval 0x0 falling edge 0x1 rising edge 0x2 either edge 0x3 0x0 r/w tsen 6:5 interrupt sense level value description value an interrupt is generated if the comparator output is low. 0 an interrupt is generated if the comparator output is high. 1 0 r/w islval 4 interrupt sense the isen field specifies the sense of the comparator output that generates an interrupt. the sense conditioning is as follows: description value level sense, see islval 0x0 falling edge 0x1 rising edge 0x2 either edge 0x3 0x0 r/w isen 3:2 comparator output invert description value the output of the comparator is unchanged. 0 the output of the comparator is inverted prior to being processed by hardware. 1 0 r/w cinv 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 799 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 18 pulse width modulator (pwm) pulse width modulation (pwm) is a powerful technique for digitally encoding analog signal levels. high-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. typical applications include switching power supplies and motor control. the stellaris ? microcontroller contains one pwm module, with three pwm generator blocks and a control block, for a total of 6 pwm outputs. the control block determines the polarity of the pwm signals, and which signals are passed through to the pins. each pwm generator block produces two pwm signals that share the same timer and frequency and can either be programmed with independent actions or as a single pair of complementary signals with dead-band delays inserted. the output signals, pwma' and pwmb', of the pwm generation blocks are managed by the output control block before being passed to the device pins as pwm0 and pwm1 or pwm2 and pwm3 , and so on. the stellaris pwm module provides a great deal of flexibility and can generate simple pwm signals, such as those required by a simple charge pump as well as paired pwm signals with dead-band delays, such as those required by a half-h bridge driver. each pwm generator block has the following features: four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled one 16-bit counter C runs in down or up/down mode C output frequency controlled by a 16-bit load value C load value updates can be synchronized C produces output signals at zero and load value two pwm comparators C comparator value updates can be synchronized C produces output signals on match pwm signal generator C output pwm signal is constructed based on actions taken as a result of the counter and pwm comparator output signals C produces two independent pwm signals dead-band generator C produces two pwm signals with programmable dead-band delays suitable for driving a half-h bridge C can be bypassed, leaving input pwm signals unmodified march 20, 2011 800 texas instruments-advance information pulse width modulator (pwm) can initiate an adc sample sequence the control block determines the polarity of the pwm signals and which signals are passed through to the pins. the output of the pwm generation blocks are managed by the output control block before being passed to the device pins. the pwm control block has the following options: pwm output enable of each pwm signal optional output inversion of each pwm signal (polarity control) optional fault handling for each pwm signal synchronization of timers in the pwm generator blocks synchronization of timer/comparator updates across the pwm generator blocks synchronization of pwm output enables across the pwm generator blocks interrupt status summary of the pwm generator blocks extended fault capabilities with multiple fault signals, programmable polarities, and filtering pwm generators can be operated independently or synchronized with other generators 18.1 block diagram figure 18-1 on page 802 provides the stellaris pwm module diagram and figure 18-2 on page 802 provides a more detailed diagram of a stellaris pwm generator. the lm3s1p51 controller contains three generator blocks that generate six independent pwm signals or three paired pwm signals with dead-band delays inserted. 801 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 18-1. pwm module diagram figure 18-2. pwm generator block diagram 18.2 signal description table 18-1 on page 803 and table 18-2 on page 804 list the external signals of the pwm module and describe the function of each. the pwm controller signals are alternate functions for some gpio march 20, 2011 802 texas instruments-advance information pulse width modulator (pwm) 3 : 0 q & 0 3 $ & r p s d u d w r u v 3 : 0 q & 0 3 % 3 : 0 q / 2 $ ' 7 l p h u 3 : 0 q & 2 8 1 7 3 : 0 q ' % & 7 / ' h d g % d q g * h q h u d w r u 3 : 0 q ' % 5 , 6 ( 3 : 0 q ' % ) $ / / 3 : 0 q & 7 / & r q w u r o 3 : 0 q ) / 7 6 5 & ) d x o w & r q g l w l r q 3 : 0 q ) / 7 6 5 & 3 : 0 q 0 , 1 ) / 7 3 ( 5 3 : 0 q ) / 7 6 ( 1 3 : 0 q ) / 7 6 7 $ 7 3 : 0 q ) / 7 6 7 $ 7 3 : 0 & o r f n 3 : 0 * h q h u d w r u % o r f n 6 l j q d o * h q h u d w r u 3 : 0 q * ( 1 $ 3 : 0 q * ( 1 % 3 : 0 q , 1 7 ( 1 , q w h u u x s w d q g 7 u l j j h u * h q h u d w r u 3 : 0 q 5 , 6 3 : 0 q , 6 & ' l j l w d o 7 u l j j h u v ) d x o w v s z p $ ? s z p % ? , q w h u u x s w v 7 u l j j h u v s z p i d x o w f p s $ f p s % ] h u r o r d g g l u s z p $ s z p % 3 : 0 , 1 7 ( 1 , q w h u u x s w 3 : 0 5 , 6 3 : 0 , 6 & 3 : 0 & 7 / & r q w u r o d q g 6 w d w x v 3 : 0 6 < 1 & 3 : 0 6 7 $ 7 8 6 3 : 0 * h q h u d w r u 3 : 0 * h q h u d w r u 3 : 0 * h q h u d w r u 3 : 0 3 : 0 3 : 0 3 : 0 3 : 0 3 : 0 3 : 0 2 x w s x w & r q w u r o / r j l f 3 : 0 & o r f n 6 \ v w h p & o r f n , q w h u u x s w v 7 u l j j h u v s z p $ ? s z p % ? s z p $ ? s z p % ? s z p $ ? s z p % ? s z p i d x o w s z p i d x o w s z p i d x o w 7 u l j j h u v ) d x o w v 3 : 0 ( 1 $ % / ( 2 x w s x w 3 : 0 , 1 9 ( 5 7 3 : 0 ) $ 8 / 7 3 : 0 ) $ 8 / 7 9 $ / 3 : 0 ( 1 8 3 ' signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these pwm signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the pwm function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the pwm signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. table 18-1. signals for pwm (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name pwm fault 0. ttl i pe4 (4) pg3 (8) pg2 (4) pj2 (10) pf4 (4) pb3 (2) pe1 (3) ph3 (2) pd6 (1) 6 16 17 39 58 65 75 83 99 fault0 pwm fault 1. ttl i pg6 (8) pg5 (5) pg4 (4) pf7 (9) pb6 (4) 37 40 41 42 90 fault1 pwm fault 2. ttl i pg3 (4) pc5 (4) ph5 (10) 16 24 63 fault2 pwm fault 3. ttl i pb3 (4) ph2 (4) 65 84 fault3 pwm 0. this signal is controlled by pwm generator 0. ttl o pd0 (1) pj0 (10) pg2 (1) pg0 (2) pa6 (4) pf0 (3) 10 14 17 19 34 47 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o pd1 (1) pg3 (1) pg1 (2) pa7 (4) pf1 (3) pj1 (10) 11 16 18 35 61 87 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o pd2 (3) pf2 (4) pb0 (2) ph0 (2) 12 60 66 86 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o pd3 (3) pf3 (4) pb1 (2) ph1 (2) 13 59 67 85 pwm3 803 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 18-1. signals for pwm (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name pwm 4. this signal is controlled by pwm generator 2. ttl o pe6 (1) pg0 (4) pa2 (4) pa6 (5) pf2 (2) ph6 (10) pe0 (1) ph0 (9) 2 19 28 34 60 62 74 86 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o pe7 (1) ph7 (10) pg1 (4) pa3 (4) pa7 (5) pf3 (2) pe1 (1) ph1 (9) 1 15 18 29 35 59 75 85 pwm5 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 18-2. signals for pwm (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name pwm fault 0. ttl i pe4 (4) pg3 (8) pg2 (4) pj2 (10) pf4 (4) pb3 (2) pe1 (3) ph3 (2) pd6 (1) b2 j2 j1 k6 l9 e11 a12 d10 a3 fault0 pwm fault 1. ttl i pg6 (8) pg5 (5) pg4 (4) pf7 (9) pb6 (4) l7 m7 k3 k4 a7 fault1 pwm fault 2. ttl i pg3 (4) pc5 (4) ph5 (10) j2 m1 f10 fault2 pwm fault 3. ttl i pb3 (4) ph2 (4) e11 d11 fault3 pwm 0. this signal is controlled by pwm generator 0. ttl o pd0 (1) pj0 (10) pg2 (1) pg0 (2) pa6 (4) pf0 (3) g1 f3 j1 k1 l6 m9 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o pd1 (1) pg3 (1) pg1 (2) pa7 (4) pf1 (3) pj1 (10) g2 j2 k2 m6 h12 b6 pwm1 march 20, 2011 804 texas instruments-advance information pulse width modulator (pwm) table 18-2. signals for pwm (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name pwm 2. this signal is controlled by pwm generator 1. ttl o pd2 (3) pf2 (4) pb0 (2) ph0 (2) h2 j11 e12 c9 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o pd3 (3) pf3 (4) pb1 (2) ph1 (2) h1 j12 d12 c8 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o pe6 (1) pg0 (4) pa2 (4) pa6 (5) pf2 (2) ph6 (10) pe0 (1) ph0 (9) a1 k1 m4 l6 j11 g3 b11 c9 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o pe7 (1) ph7 (10) pg1 (4) pa3 (4) pa7 (5) pf3 (2) pe1 (1) ph1 (9) b1 h3 k2 l4 m6 j12 a12 c8 pwm5 a. the ttl designation indicates the pin has ttl-compatible voltage levels. 18.3 functional description 18.3.1 pwm timer the timer in each pwm generator runs in one of two modes: count-down mode or count-up/down mode. in count-down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. in count-up/down mode, the timer counts from zero up to the load value, back down to zero, back up to the load value, and so on. generally, count-down mode is used for generating left- or right-aligned pwm signals, while the count-up/down mode is used for generating center-aligned pwm signals. the timers output three signals that are used in the pwm generation process: the direction signal (this is always low in count-down mode, but alternates between low and high in count-up/down mode), a single-clock-cycle-width high pulse when the counter is zero, and a single-clock-cycle-width high pulse when the counter is equal to the load value. note that in count-down mode, the zero pulse is immediately followed by the load pulse. in the figures in this chapter, these signals are labelled "dir," "zero," and "load." 18.3.2 pwm comparators each pwm generator has two comparators that monitor the value of the counter; when either comparator matches the counter, they output a single-clock-cycle-width high pulse, labelled "cmpa" and "cmpb" in the figures in this chapter. when in count-up/down mode, these comparators match both when counting up and when counting down, and thus are qualified by the counter direction signal. these qualified pulses are used in the pwm generation process. if either comparator match value is greater than the counter load value, then that comparator never outputs a high pulse. 805 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 18-3 on page 806 shows the behavior of the counter and the relationship of these pulses when the counter is in count-down mode. figure 18-4 on page 807 shows the behavior of the counter and the relationship of these pulses when the counter is in count-up/down mode. in these figures, the following definitions apply: load is the value in the pwmnload register compa is the value in the pwmncmpa register compb is the value in the pwmncmpb register 0 is the value zero load is the internal signal that has a single-clock-cycle-width high pulse when the counter is equal to the load value zero is the internal signal that has a single-clock-cycle-width high pulse when the counter is zero cmpa is the internal signal that has a single-clock-cycle-width high pulse when the counter is equal to compa cmpb is the internal signal that has a single-clock-cycle-width high pulse when the counter is equal to compb dir is the internal signal that indicates the count direction figure 18-3. pwm count-down mode march 20, 2011 806 texas instruments-advance information pulse width modulator (pwm) / 2 $ ' & 2 0 3 % & 2 0 3 $ o r d g ] h u r f p s % f p s $ g l u $ ' r z q % ' r z q figure 18-4. pwm count-up/down mode 18.3.3 pwm signal generator each pwm generator takes the load, zero, cmpa, and cmpb pulses (qualified by the dir signal) and generates two internal pwm signals, pwma and pwmb. in count-down mode, there are four events that can affect these signals: zero, load, match a down, and match b down. in count-up/down mode, there are six events that can affect these signals: zero, load, match a down, match a up, match b down, and match b up. the match a or match b events are ignored when they coincide with the zero or load events. if the match a and match b events coincide, the first signal, pwma, is generated based only on the match a event, and the second signal, pwmb, is generated based only on the match b event. for each event, the effect on each output pwm signal is programmable: it can be left alone (ignoring the event), it can be toggled, it can be driven low, or it can be driven high. these actions can be used to generate a pair of pwm signals of various positions and duty cycles, which do or do not overlap. figure 18-5 on page 807 shows the use of count-up/down mode to generate a pair of center-aligned, overlapped pwm signals that have different duty cycles. this figure shows the pwma and pwmb signals before they have passed through the dead-band generator. figure 18-5. pwm generation example in count-up/down mode in this example, the first generator is set to drive high on match a up, drive low on match a down, and ignore the other four events. the second generator is set to drive high on match b up, drive low on match b down, and ignore the other four events. changing the value of comparator a changes the duty cycle of the pwma signal, and changing the value of comparator b changes the duty cycle of the pwmb signal. 807 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller / 2 $ ' & 2 0 3 % & 2 0 3 $ s z p % s z p $ / 2 $ ' & 2 0 3 $ o r d g ] h u r f p s % f p s $ g l u % 8 s $ 8 s $ ' r z q % ' r z q & 2 0 3 % 18.3.4 dead-band generator the pwma and pwmb signals produced by each pwm generator are passed to the dead-band generator. if the dead-band generator is disabled, the pwm signals simply pass through to the pwma' and pwmb' signals unmodified. if the dead-band generator is enabled, the pwmb signal is lost and two pwm signals are generated based on the pwma signal. the first output pwm signal, pwma' is the pwma signal with the rising edge delayed by a programmable amount. the second output pwm signal, pwmb', is the inversion of the pwma signal with a programmable delay added between the falling edge of the pwma signal and the rising edge of the pwmb' signal. the resulting signals are a pair of active high signals where one is always high, except for a programmable amount of time at transitions where both are low. these signals are therefore suitable for driving a half-h bridge, with the dead-band delays preventing shoot-through current from damaging the power electronics. figure 18-6 on page 808 shows the effect of the dead-band generator on the pwma signal and the resulting pwma' and pwmb' signals that are transmitted to the output control block. figure 18-6. pwm dead-band generator 18.3.5 interrupt/adc-trigger selector each pwm generator also takes the same four (or six) counter events and uses them to generate an interrupt or an adc trigger. any of these events or a set of these events can be selected as a source for an interrupt; when any of the selected events occur, an interrupt is generated. additionally, the same event, a different event, the same set of events, or a different set of events can be selected as a source for an adc trigger; when any of these selected events occur, an adc trigger pulse is generated. the selection of events allows the interrupt or adc trigger to occur at a specific position within the pwma or pwmb signal. note that interrupts and adc triggers are based on the raw events; delays in the pwm signal edges caused by the dead-band generator are not taken into account. 18.3.6 synchronization methods the pwm module provides three pwm generators, each providing two pwm outputs that may be used in a wide variety of applications. generally speaking, the pwm is used in one of two categories of operation: unsynchronized. the pwm generator and its two output signals are used alone, independent of other pwm generators. synchronized. the pwm generator and its two outputs signals are used in conjunction with other pwm generators using a common, unified time base. if multiple pwm generators are configured with the same counter load value, synchronization can be used to guarantee that they also have the same count value (the pwm generators must be configured before they are synchronized). with this feature, more than two pwmn signals can be produced with a known relationship between the edges of those signals because the counters always have the same values. other states in the module provide mechanisms to maintain the common time base and mutual synchronization. march 20, 2011 808 texas instruments-advance information pulse width modulator (pwm) s z p $ s z p $ ? s z p % ? 5 l v l q j ( g j h ' h o d \ ) d o o l q j ( g j h ' h o d \ the counter in a pwm generator can be reset to zero by writing the pwm time base sync (pwmsync) register and setting the syncn bit associated with the generator. multiple pwm generators can be synchronized together by setting all necessary syncn bits in one access. for example, setting the sync0 and sync1 bits in the pwmsync register causes the counters in pwm generators 0 and 1 to reset together. additional synchronization can occur between multiple pwm generators by updating register contents in one of the following three ways: immediately. the write value has immediate effect, and the hardware reacts immediately. locally synchronized. the write value does not affect the logic until the counter reaches the value zero at the end of the pwm cycle. in this case, the effect of the write is deferred, providing a guaranteed defined behavior and preventing overly short or overly long output pwm pulses. globally synchronized. the write value does not affect the logic until two sequential events have occurred: (1) the update mode for the generator function is programmed for global synchronization in the pwmnctl register, and (2) the counter reaches zero at the end of the pwm cycle. in this case, the effect of the write is deferred until the end of the pwm cycle following the end of all updates. this mode allows multiple items in multiple pwm generators to be updated simultaneously without odd effects during the update; everything runs from the old values until a point at which they all run from the new values. the update mode of the load and comparator match values can be individually configured in each pwm generator block. it typically makes sense to use the synchronous update mechanism across pwm generator blocks when the timers in those blocks are synchronized, although this is not required in order for this mechanism to function properly. the following registers provide either local or global synchronization based on the state of various update mode bits and fields in the pwmnctl register ( loadupd; cmpaupd; cmpbupd): generator registers: pwmnload , pwmncmpa , and pwmncmpb the following registers default to immediate update, but are provided with the optional functionality of synchronously updating rather than having all updates take immediate effect: module-level register: pwmenable (based on the state of the enupdn bits in the pwmenupd register). generator register: pwmngena , pwmngenb , pwmndbctl , pwmndbrise , and pwmndbfall (based on the state of various update mode bits and fields in the pwmnctl register ( genaupd; genbupd; dbctlupd; dbriseupd; dbfallupd)). all other registers are considered statically provisioned for the execution of an application or are used dynamically for purposes unrelated to maintaining synchronization and therefore do not need synchronous update functionality. 18.3.7 fault conditions a fault condition is one in which the controller must be signaled to stop normal pwm function and then set the pwmn signals to a safe state. two basic situations cause fault conditions: the microcontroller is stalled and cannot perform the necessary computation in the time required for motion control an external error or event is detected 809 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller the pwm generator can use the following inputs to generate a fault condition, including: faultn pin assertion a stall of the controller generated by the debugger the trigger of an adc digital comparator fault conditions are calculated on a per-pwm generator basis. each pwm generator configures the necessary conditions to indicate a fault condition exists. this method allows the development of applications with dependent and independent control. four fault input pins ( fault0-fault3 ). these inputs may be used with circuits that generate an active high or active low signal to indicate an error condition. a faultn pins may be individually programmed for the appropriate logic sense using the pwmnfltsen register. the pwm generator's mode control, including fault condition handling, is provided in the pwmnctl register. this register determines whether the input or a combination of faultn input signals and/or digital comparator triggers (as configured by the pwmnfltsrc0 and pwmnfltsrc1 registers) is used to generate a fault condition. the pwmnctl register also selects whether the fault condition is maintained as long as the external condition lasts or if it is latched until the fault condition until cleared by software. finally, this register also enables a counter that may be used to extend the period of a fault condition for external events to assure that the duration is a minimum length. the minimum fault period count is specified in the pwmnminfltper register. status regarding the specific fault cause is provided in the pwmnfltstat0 and pwmnfltstat1 registers. pwm generator fault conditions may be promoted to a controller interrupt using the pwminten register. 18.3.8 output control block the output control block takes care of the final conditioning of the pwma' and pwmb' signals before they go to the pins as the pwmn signals. via a single register, the pwm output enable (pwnenable) register, the set of pwm signals that are actually enabled to the pins can be modified. this function can be used, for example, to perform commutation of a brushless dc motor with a single register write (and without modifying the individual pwm generators, which are modified by the feedback control loop). in addition, the updating of the bits in the pwmenable register can be configured to be immediate or locally or globally synchronized to the next synchronous update using the pwm enable update (pwmenupd) register. during fault conditions, the pwm output signals, pwmn , usually must be driven to safe values so that external equipment may be safely controlled. the pwmfault register specifies whether during a fault condition, the generated signal continues to be passed driven or to an encoding specified in the pwmfaultval register. a final inversion can be applied to any of the pwmn signals, making them active low instead of the default active high using the pwm output inversion (pwminvert) . the inversion is applied even if a value has been enabled in the pwmfault register and specified in the pwmfaultval register. in other words, if a bit is set in the pwmfault , pwmfaultval , and pwminvert registers, the output on the pwmn signal is 0, not 1 as specified in the pwmfaultval register. march 20, 2011 810 texas instruments-advance information pulse width modulator (pwm) 18.4 initialization and configuration the following example shows how to initialize pwm generator 0 with a 25-khz frequency, a 25% duty cycle on the pwm0 pin, and a 75% duty cycle on the pwm1 pin. this example assumes the system clock is 20 mhz. 1. enable the pwm clock by writing a value of 0x0010.0000 to the rcgc0 register in the system control module (see page 252). 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module (see page 269). 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register. to determine which gpios to configure, see table 21-4 on page 917. 4. configure the pmcn fields in the gpiopctl register to assign the pwm signals to the appropriate pins (see page 446 and table 21-5 on page 925). 5. configure the run-mode clock configuration (rcc) register in the system control module to use the pwm divide ( usepwmdiv ) and set the divider (pwmdiv ) to divide by 2 (000). 6. configure the pwm generator for countdown mode with immediate updates to the parameters. write the pwm0ctl register with a value of 0x0000.0000. write the pwm0gena register with a value of 0x0000.008c. write the pwm0genb register with a value of 0x0000.080c. 7. set the period. for a 25-khz frequency, the period = 1/25,000, or 40 microseconds. the pwm clock source is 10 mhz; the system clock divided by 2. thus there are 400 clock ticks per period. use this value to set the pwm0load register. in count-down mode, set the load field in the pwm0load register to the requested period minus one. write the pwm0load register with a value of 0x0000.018f. 8. set the pulse width of the pwm0 pin for a 25% duty cycle. write the pwm0cmpa register with a value of 0x0000.012b. 9. set the pulse width of the pwm1 pin for a 75% duty cycle. write the pwm0cmpb register with a value of 0x0000.0063. 10. start the timers in pwm generator 0. write the pwm0ctl register with a value of 0x0000.0001. 11. enable pwm outputs. write the pwmenable register with a value of 0x0000.0003. 18.5 register map table 18-3 on page 812 lists the pwm registers. the offset listed is a hexadecimal increment to the register's address, relative to the pwm module's base address: 811 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller pwm0: 0x4002.8000 note that the pwm module clock must be enabled before the registers can be programmed (see page 252). there must be a delay of 3 system clocks after the pwm module clock is enabled before any pwm module registers are accessed. table 18-3. pwm register map see page description reset type name offset 815 pwm master control 0x0000.0000 r/w pwmctl 0x000 816 pwm time base sync 0x0000.0000 r/w pwmsync 0x004 817 pwm output enable 0x0000.0000 r/w pwmenable 0x008 819 pwm output inversion 0x0000.0000 r/w pwminvert 0x00c 821 pwm output fault 0x0000.0000 r/w pwmfault 0x010 823 pwm interrupt enable 0x0000.0000 r/w pwminten 0x014 825 pwm raw interrupt status 0x0000.0000 ro pwmris 0x018 827 pwm interrupt status and clear 0x0000.0000 r/w1c pwmisc 0x01c 829 pwm status 0x0000.0000 ro pwmstatus 0x020 831 pwm fault condition value 0x0000.0000 r/w pwmfaultval 0x024 833 pwm enable update 0x0000.0000 r/w pwmenupd 0x028 836 pwm0 control 0x0000.0000 r/w pwm0ctl 0x040 841 pwm0 interrupt and trigger enable 0x0000.0000 r/w pwm0inten 0x044 844 pwm0 raw interrupt status 0x0000.0000 ro pwm0ris 0x048 846 pwm0 interrupt status and clear 0x0000.0000 r/w1c pwm0isc 0x04c 848 pwm0 load 0x0000.0000 r/w pwm0load 0x050 849 pwm0 counter 0x0000.0000 ro pwm0count 0x054 850 pwm0 compare a 0x0000.0000 r/w pwm0cmpa 0x058 851 pwm0 compare b 0x0000.0000 r/w pwm0cmpb 0x05c 852 pwm0 generator a control 0x0000.0000 r/w pwm0gena 0x060 855 pwm0 generator b control 0x0000.0000 r/w pwm0genb 0x064 858 pwm0 dead-band control 0x0000.0000 r/w pwm0dbctl 0x068 859 pwm0 dead-band rising-edge delay 0x0000.0000 r/w pwm0dbrise 0x06c 860 pwm0 dead-band falling-edge-delay 0x0000.0000 r/w pwm0dbfall 0x070 861 pwm0 fault source 0 0x0000.0000 r/w pwm0fltsrc0 0x074 863 pwm0 fault source 1 0x0000.0000 r/w pwm0fltsrc1 0x078 866 pwm0 minimum fault period 0x0000.0000 r/w pwm0minfltper 0x07c 836 pwm1 control 0x0000.0000 r/w pwm1ctl 0x080 march 20, 2011 812 texas instruments-advance information pulse width modulator (pwm) table 18-3. pwm register map (continued) see page description reset type name offset 841 pwm1 interrupt and trigger enable 0x0000.0000 r/w pwm1inten 0x084 844 pwm1 raw interrupt status 0x0000.0000 ro pwm1ris 0x088 846 pwm1 interrupt status and clear 0x0000.0000 r/w1c pwm1isc 0x08c 848 pwm1 load 0x0000.0000 r/w pwm1load 0x090 849 pwm1 counter 0x0000.0000 ro pwm1count 0x094 850 pwm1 compare a 0x0000.0000 r/w pwm1cmpa 0x098 851 pwm1 compare b 0x0000.0000 r/w pwm1cmpb 0x09c 852 pwm1 generator a control 0x0000.0000 r/w pwm1gena 0x0a0 855 pwm1 generator b control 0x0000.0000 r/w pwm1genb 0x0a4 858 pwm1 dead-band control 0x0000.0000 r/w pwm1dbctl 0x0a8 859 pwm1 dead-band rising-edge delay 0x0000.0000 r/w pwm1dbrise 0x0ac 860 pwm1 dead-band falling-edge-delay 0x0000.0000 r/w pwm1dbfall 0x0b0 861 pwm1 fault source 0 0x0000.0000 r/w pwm1fltsrc0 0x0b4 863 pwm1 fault source 1 0x0000.0000 r/w pwm1fltsrc1 0x0b8 866 pwm1 minimum fault period 0x0000.0000 r/w pwm1minfltper 0x0bc 836 pwm2 control 0x0000.0000 r/w pwm2ctl 0x0c0 841 pwm2 interrupt and trigger enable 0x0000.0000 r/w pwm2inten 0x0c4 844 pwm2 raw interrupt status 0x0000.0000 ro pwm2ris 0x0c8 846 pwm2 interrupt status and clear 0x0000.0000 r/w1c pwm2isc 0x0cc 848 pwm2 load 0x0000.0000 r/w pwm2load 0x0d0 849 pwm2 counter 0x0000.0000 ro pwm2count 0x0d4 850 pwm2 compare a 0x0000.0000 r/w pwm2cmpa 0x0d8 851 pwm2 compare b 0x0000.0000 r/w pwm2cmpb 0x0dc 852 pwm2 generator a control 0x0000.0000 r/w pwm2gena 0x0e0 855 pwm2 generator b control 0x0000.0000 r/w pwm2genb 0x0e4 858 pwm2 dead-band control 0x0000.0000 r/w pwm2dbctl 0x0e8 859 pwm2 dead-band rising-edge delay 0x0000.0000 r/w pwm2dbrise 0x0ec 860 pwm2 dead-band falling-edge-delay 0x0000.0000 r/w pwm2dbfall 0x0f0 861 pwm2 fault source 0 0x0000.0000 r/w pwm2fltsrc0 0x0f4 863 pwm2 fault source 1 0x0000.0000 r/w pwm2fltsrc1 0x0f8 866 pwm2 minimum fault period 0x0000.0000 r/w pwm2minfltper 0x0fc 867 pwm0 fault pin logic sense 0x0000.0000 r/w pwm0fltsen 0x800 813 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 18-3. pwm register map (continued) see page description reset type name offset 868 pwm0 fault status 0 0x0000.0000 - pwm0fltstat0 0x804 870 pwm0 fault status 1 0x0000.0000 - pwm0fltstat1 0x808 867 pwm1 fault pin logic sense 0x0000.0000 r/w pwm1fltsen 0x880 868 pwm1 fault status 0 0x0000.0000 - pwm1fltstat0 0x884 870 pwm1 fault status 1 0x0000.0000 - pwm1fltstat1 0x888 867 pwm2 fault pin logic sense 0x0000.0000 r/w pwm2fltsen 0x900 868 pwm2 fault status 0 0x0000.0000 - pwm2fltstat0 0x904 870 pwm2 fault status 1 0x0000.0000 - pwm2fltstat1 0x908 867 pwm3 fault pin logic sense 0x0000.0000 r/w pwm3fltsen 0x980 18.6 register descriptions the remainder of this section lists and describes the pwm registers, in numerical order by address offset. march 20, 2011 814 texas instruments-advance information pulse width modulator (pwm) register 1: pwm master control (pwmctl), offset 0x000 this register provides master control over the pwm generation blocks. pwm master control (pwmctl) pwm0 base: 0x4002.8000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 globalsync0 globalsync1 globalsync2 reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:3 update pwm generator 2 description value any queued update to a load or comparator register in pwm generator 2 is applied the next time the corresponding counter becomes zero. 1 no effect. 0 this bit automatically clears when the updates have completed; it cannot be cleared by software. 0 r/w globalsync2 2 update pwm generator 1 description value any queued update to a load or comparator register in pwm generator 1 is applied the next time the corresponding counter becomes zero. 1 no effect. 0 this bit automatically clears when the updates have completed; it cannot be cleared by software. 0 r/w globalsync1 1 update pwm generator 0 description value any queued update to a load or comparator register in pwm generator 0 is applied the next time the corresponding counter becomes zero. 1 no effect. 0 this bit automatically clears when the updates have completed; it cannot be cleared by software. 0 r/w globalsync0 0 815 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 2: pwm time base sync (pwmsync), offset 0x004 this register provides a method to perform synchronization of the counters in the pwm generation blocks. setting a bit in this register causes the specified counter to reset back to 0; setting multiple bits resets multiple counters simultaneously. the bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed. pwm time base sync (pwmsync) pwm0 base: 0x4002.8000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sync0 sync1 sync2 reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 reset generator 2 counter description value resets the pwm generator 2 counter. 1 no effect. 0 0 r/w sync2 2 reset generator 1 counter description value resets the pwm generator 1 counter. 1 no effect. 0 0 r/w sync1 1 reset generator 0 counter description value resets the pwm generator 0 counter. 1 no effect. 0 0 r/w sync0 0 march 20, 2011 816 texas instruments-advance information pulse width modulator (pwm) register 3: pwm output enable (pwmenable), offset 0x008 this register provides a master control of which generated pwma' and pwmb' signals are output to the pwmn pins. by disabling a pwm output, the generation process can continue (for example, when the time bases are synchronized) without driving pwm signals to the pins. when bits in this register are set, the corresponding pwma' or pwmb' signal is passed through to the output stage. when bits are clear, the pwma' or pwmb' signal is replaced by a zero value which is also passed to the output stage. the pwminvert register controls the output stage, so if the corresponding bit is set in that register, the value seen on the pwmn signal is inverted from what is configured by the bits in this register. updates to the bits in this register can be immediate or locally or globally synchronized to the next synchronous update as controlled by the enupdn fields in the pwmenupd register. pwm output enable (pwmenable) pwm0 base: 0x4002.8000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0en pwm1en pwm2en pwm3en pwm4en pwm5en reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 pwm5 output enable description value the generated pwm2b' signal is passed to the pwm5 pin. 1 the pwm5 signal has a zero value. 0 0 r/w pwm5en 5 pwm4 output enable description value the generated pwm2a' signal is passed to the pwm4 pin. 1 the pwm4 signal has a zero value. 0 0 r/w pwm4en 4 pwm3 output enable description value the generated pwm1b' signal is passed to the pwm3 pin. 1 the pwm3 signal has a zero value. 0 0 r/w pwm3en 3 817 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field pwm2 output enable description value the generated pwm1a' signal is passed to the pwm2 pin. 1 the pwm2 signal has a zero value. 0 0 r/w pwm2en 2 pwm1 output enable description value the generated pwm0b' signal is passed to the pwm1 pin. 1 the pwm1 signal has a zero value. 0 0 r/w pwm1en 1 pwm0 output enable description value the generated pwm0a' signal is passed to the pwm0 pin. 1 the pwm0 signal has a zero value. 0 0 r/w pwm0en 0 march 20, 2011 818 texas instruments-advance information pulse width modulator (pwm) register 4: pwm output inversion (pwminvert), offset 0x00c this register provides a master control of the polarity of the pwmn signals on the device pins. the pwma' and pwmb' signals generated by the pwm generator are active high; but can be made active low via this register. disabled pwm channels are also passed through the output inverter (if so configured) so that inactive signals can be high. in addition, if the pwmfault register enables a specific value to be placed on the pwmn signals during a fault condition, that value is inverted if the corresponding bit in this register is set. pwm output inversion (pwminvert) pwm0 base: 0x4002.8000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0inv pwm1inv pwm2inv pwm3inv pwm4inv pwm5inv reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 invert pwm5 signal description value the pwm5 signal is inverted. 1 the pwm5 signal is not inverted. 0 0 r/w pwm5inv 5 invert pwm4 signal description value the pwm4 signal is inverted. 1 the pwm4 signal is not inverted. 0 0 r/w pwm4inv 4 invert pwm3 signal description value the pwm3 signal is inverted. 1 the pwm3 signal is not inverted. 0 0 r/w pwm3inv 3 invert pwm2 signal description value the pwm2 signal is inverted. 1 the pwm2 signal is not inverted. 0 0 r/w pwm2inv 2 819 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field invert pwm1 signal description value the pwm1 signal is inverted. 1 the pwm1 signal is not inverted. 0 0 r/w pwm1inv 1 invert pwm0 signal description value the pwm0 signal is inverted. 1 the pwm0 signal is not inverted. 0 0 r/w pwm0inv 0 march 20, 2011 820 texas instruments-advance information pulse width modulator (pwm) register 5: pwm output fault (pwmfault), offset 0x010 this register controls the behavior of the pwmn outputs in the presence of fault conditions. both the fault inputs ( faultn pins and digital comparator outputs) and debug events are considered fault conditions. on a fault condition, each pwma' or pwmb' signal can be passed through unmodified or driven to the value specified by the corresponding bit in the pwmfaultval register. for outputs that are configured for pass-through, the debug event handling on the corresponding pwm generator also determines if the pwma' or pwmb' signal continues to be generated. fault condition control occurs before the output inverter, so pwm signals driven to a specified value on fault are inverted if the channel is configured for inversion (therefore, the pin is driven to the logical complement of the specified value on a fault condition). pwm output fault (pwmfault) pwm0 base: 0x4002.8000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 fault4 fault5 reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 pwm5 fault description value the pwm5 output signal is driven to the value specified by the pwm5 bit in the pwmfaultval register. 1 the generated pwm2b' signal is passed to the pwm5 pin. 0 0 r/w fault5 5 pwm4 fault description value the pwm4 output signal is driven to the value specified by the pwm4 bit in the pwmfaultval register. 1 the generated pwm2a' signal is passed to the pwm4 pin. 0 0 r/w fault4 4 pwm3 fault description value the pwm3 output signal is driven to the value specified by the pwm3 bit in the pwmfaultval register. 1 the generated pwm1b' signal is passed to the pwm3 pin. 0 0 r/w fault3 3 821 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field pwm2 fault description value the pwm2 output signal is driven to the value specified by the pwm2 bit in the pwmfaultval register. 1 the generated pwm1a' signal is passed to the pwm2 pin. 0 0 r/w fault2 2 pwm1 fault description value the pwm1 output signal is driven to the value specified by the pwm1 bit in the pwmfaultval register. 1 the generated pwm0b' signal is passed to the pwm1 pin. 0 0 r/w fault1 1 pwm0 fault description value the pwm0 output signal is driven to the value specified by the pwm0 bit in the pwmfaultval register. 1 the generated pwm0a' signal is passed to the pwm0 pin. 0 0 r/w fault0 0 march 20, 2011 822 texas instruments-advance information pulse width modulator (pwm) register 6: pwm interrupt enable (pwminten), offset 0x014 this register controls the global interrupt generation capabilities of the pwm module. the events that can cause an interrupt are the fault input and the individual interrupts from the pwm generators. pwm interrupt enable (pwminten) pwm0 base: 0x4002.8000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault0 intfault1 intfault2 intfault3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intpwm0 intpwm1 intpwm2 reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 interrupt fault 3 description value an interrupt is sent to the interrupt controller when the fault condition for pwm generator 3 is asserted. 1 the fault condition for pwm generator 3 is suppressed and not sent to the interrupt controller. 0 0 r/w intfault3 19 interrupt fault 2 description value an interrupt is sent to the interrupt controller when the fault condition for pwm generator 2 is asserted. 1 the fault condition for pwm generator 2 is suppressed and not sent to the interrupt controller. 0 0 r/w intfault2 18 interrupt fault 1 description value an interrupt is sent to the interrupt controller when the fault condition for pwm generator 1 is asserted. 1 the fault condition for pwm generator 1 is suppressed and not sent to the interrupt controller. 0 0 r/w intfault1 17 823 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field interrupt fault 0 description value an interrupt is sent to the interrupt controller when the fault condition for pwm generator 0 is asserted. 1 the fault condition for pwm generator 0 is suppressed and not sent to the interrupt controller. 0 0 r/w intfault0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:3 pwm2 interrupt enable description value an interrupt is sent to the interrupt controller when the pwm generator 2 block asserts an interrupt. 1 the pwm generator 2 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intpwm2 2 pwm1 interrupt enable description value an interrupt is sent to the interrupt controller when the pwm generator 1 block asserts an interrupt. 1 the pwm generator 1 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intpwm1 1 pwm0 interrupt enable description value an interrupt is sent to the interrupt controller when the pwm generator 0 block asserts an interrupt. 1 the pwm generator 0 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intpwm0 0 march 20, 2011 824 texas instruments-advance information pulse width modulator (pwm) register 7: pwm raw interrupt status (pwmris), offset 0x018 this register provides the current set of interrupt sources that are asserted, regardless of whether they are enabled to cause an interrupt to be asserted to the interrupt controller. the fault interrupt is asserted based on the fault condition source that is specified by the pwmnctl , pwmnfltsrc0 and pwmnfltsrc1 registers. the fault interrupt is latched on detection and must be cleared through the pwm interrupt status and clear (pwmisc) register. the actual value of the faultn signals can be observed using the pwmstatus register. the pwm generator interrupts simply reflect the status of the pwm generators and are cleared via the interrupt status register in the pwm generator blocks. if a bit is set, the event is active; if a bit is clear the event is not active. pwm raw interrupt status (pwmris) pwm0 base: 0x4002.8000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault0 intfault1 intfault2 intfault3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intpwm0 intpwm1 intpwm2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 interrupt fault pwm 3 description value the fault condition for pwm generator 3 is asserted. 1 the fault condition for pwm generator 3 has not been asserted. 0 this bit is cleared by writing a 1 to the intfault3 bit in the pwmisc register. 0 ro intfault3 19 interrupt fault pwm 2 description value the fault condition for pwm generator 2 is asserted. 1 the fault condition for pwm generator 2 has not been asserted. 0 this bit is cleared by writing a 1 to the intfault2 bit in the pwmisc register. 0 ro intfault2 18 825 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field interrupt fault pwm 1 description value the fault condition for pwm generator 1 is asserted. 1 the fault condition for pwm generator 1 has not been asserted. 0 this bit is cleared by writing a 1 to the intfault1 bit in the pwmisc register. 0 ro intfault1 17 interrupt fault pwm 0 description value the fault condition for pwm generator 0 is asserted. 1 the fault condition for pwm generator 0 has not been asserted. 0 this bit is cleared by writing a 1 to the intfault0 bit in the pwmisc register. 0 ro intfault0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:3 pwm2 interrupt asserted description value the pwm generator 2 block interrupt is asserted. 1 the pwm generator 2 block interrupt has not been asserted. 0 the pwm2ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm2isc register. 0 ro intpwm2 2 pwm1 interrupt asserted description value the pwm generator 1 block interrupt is asserted. 1 the pwm generator 1 block interrupt has not been asserted. 0 the pwm1ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm1isc register. 0 ro intpwm1 1 pwm0 interrupt asserted description value the pwm generator 0 block interrupt is asserted. 1 the pwm generator 0 block interrupt has not been asserted. 0 the pwm0ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm0isc register. 0 ro intpwm0 0 march 20, 2011 826 texas instruments-advance information pulse width modulator (pwm) register 8: pwm interrupt status and clear (pwmisc), offset 0x01c this register provides a summary of the interrupt status of the individual pwm generator blocks. if a fault interrupt is set, the corresponding faultn input has caused an interrupt. for the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. if an block interrupt bit is set, the corresponding generator block is asserting an interrupt. the individual interrupt status registers, pwmnisc , in each block must be consulted to determine the reason for the interrupt and used to clear the interrupt. pwm interrupt status and clear (pwmisc) pwm0 base: 0x4002.8000 offset 0x01c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault0 intfault1 intfault2 intfault3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intpwm0 intpwm1 intpwm2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 fault3 interrupt asserted description value an enabled interrupt for the fault condition for pwm generator 3 is asserted or is latched. 1 the fault condition for pwm generator 3 has not been asserted or is not enabled. 0 writing a 1 to this bit clears it and the intfault3 bit in the pwmris register. 0 r/w1c intfault3 19 fault2 interrupt asserted description value an enabled interrupt for the fault condition for pwm generator 2 is asserted or is latched. 1 the fault condition for pwm generator 2 has not been asserted or is not enabled. 0 writing a 1 to this bit clears it and the intfault2 bit in the pwmris register. 0 r/w1c intfault2 18 827 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field fault1 interrupt asserted description value an enabled interrupt for the fault condition for pwm generator 1 is asserted or is latched. 1 the fault condition for pwm generator 1 has not been asserted or is not enabled. 0 writing a 1 to this bit clears it and the intfault1 bit in the pwmris register. 0 r/w1c intfault1 17 fault0 interrupt asserted description value an enabled interrupt for the fault condition for pwm generator 0 is asserted or is latched. 1 the fault condition for pwm generator 0 has not been asserted or is not enabled. 0 writing a 1 to this bit clears it and the intfault0 bit in the pwmris register. 0 r/w1c intfault0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:3 pwm2 interrupt status description value an enabled interrupt for the pwm generator 2 block is asserted. 1 the pwm generator 2 block interrupt is not asserted or is not enabled. 0 the pwm2ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm2isc register. 0 ro intpwm2 2 pwm1 interrupt status description value an enabled interrupt for the pwm generator 1 block is asserted. 1 the pwm generator 1 block interrupt is not asserted or is not enabled. 0 the pwm1ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm1isc register. 0 ro intpwm1 1 pwm0 interrupt status description value an enabled interrupt for the pwm generator 0 block is asserted. 1 the pwm generator 0 block interrupt is not asserted or is not enabled. 0 the pwm0ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm0isc register. 0 ro intpwm0 0 march 20, 2011 828 texas instruments-advance information pulse width modulator (pwm) register 9: pwm status (pwmstatus), offset 0x020 this register provides the unlatched status of the pwm generator fault condition. pwm status (pwmstatus) pwm0 base: 0x4002.8000 offset 0x020 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 generator 3 fault status description value the fault condition for pwm generator 3 is asserted. if the fltsrc bit in the pwm3ctl register is clear, the input is the source of the fault condition, and is therefore asserted. 1 the fault condition for pwm generator 3 is not asserted. 0 0 ro fault3 3 generator 2 fault status description value the fault condition for pwm generator 2 is asserted. if the fltsrc bit in the pwm2ctl register is clear, the input is the source of the fault condition, and is therefore asserted. 1 the fault condition for pwm generator 2 is not asserted. 0 0 ro fault2 2 generator 1 fault status description value the fault condition for pwm generator 1 is asserted. if the fltsrc bit in the pwm1ctl register is clear, the input is the source of the fault condition, and is therefore asserted. 1 the fault condition for pwm generator 1 is not asserted. 0 0 ro fault1 1 829 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field generator 0 fault status description value the fault condition for pwm generator 0 is asserted. if the fltsrc bit in the pwm0ctl register is clear, the input is the source of the fault condition, and is therefore asserted. 1 the fault condition for pwm generator 0 is not asserted. 0 0 ro fault0 0 march 20, 2011 830 texas instruments-advance information pulse width modulator (pwm) register 10: pwm fault condition value (pwmfaultval), offset 0x024 this register specifies the output value driven on the pwmn signals during a fault condition if enabled by the corresponding bit in the pwmfault register. note that if the corresponding bit in the pwminvert register is set, the output value is driven to the logical not of the bit value in this register. pwm fault condition value (pwmfaultval) pwm0 base: 0x4002.8000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 pwm5 fault value description value the pwm5 output signal is driven high during fault conditions if the fault5 bit in the pwmfault register is set. 1 the pwm5 output signal is driven low during fault conditions if the fault5 bit in the pwmfault register is set. 0 0 r/w pwm5 5 pwm4 fault value description value the pwm4 output signal is driven high during fault conditions if the fault4 bit in the pwmfault register is set. 1 the pwm4 output signal is driven low during fault conditions if the fault4 bit in the pwmfault register is set. 0 0 r/w pwm4 4 pwm3 fault value description value the pwm3 output signal is driven high during fault conditions if the fault3 bit in the pwmfault register is set. 1 the pwm3 output signal is driven low during fault conditions if the fault3 bit in the pwmfault register is set. 0 0 r/w pwm3 3 831 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field pwm2 fault value description value the pwm2 output signal is driven high during fault conditions if the fault2 bit in the pwmfault register is set. 1 the pwm2 output signal is driven low during fault conditions if the fault2 bit in the pwmfault register is set. 0 0 r/w pwm2 2 pwm1 fault value description value the pwm1 output signal is driven high during fault conditions if the fault1 bit in the pwmfault register is set. 1 the pwm1 output signal is driven low during fault conditions if the fault1 bit in the pwmfault register is set. 0 0 r/w pwm1 1 pwm0 fault value description value the pwm0 output signal is driven high during fault conditions if the fault0 bit in the pwmfault register is set. 1 the pwm0 output signal is driven low during fault conditions if the fault0 bit in the pwmfault register is set. 0 0 r/w pwm0 0 march 20, 2011 832 texas instruments-advance information pulse width modulator (pwm) register 11: pwm enable update (pwmenupd), offset 0x028 this register specifies when updates to the pwmnen bit in the pwmenable register are performed. the pwmnen bit enables the pwma' or pwmb' output to be passed to the microcontroller's pin. updates can be immediate or locally or globally synchronized to the next synchronous update. pwm enable update (pwmenupd) pwm0 base: 0x4002.8000 offset 0x028 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enupd0 enupd1 enupd2 enupd3 enupd4 enupd5 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:12 pwm5 enable update mode description value immediate writes to the pwm5en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm5en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm5en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd5 11:10 833 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field pwm4 enable update mode description value immediate writes to the pwm4en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm4en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm4en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd4 9:8 enable update mode description value immediate writes to the pwm3en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm3en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm3en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd3 7:6 pwm2 enable update mode description value immediate writes to the pwm2en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm2en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm2en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd2 5:4 march 20, 2011 834 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field pwm1 enable update mode description value immediate writes to the pwm1en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm1en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm1en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd1 3:2 pwm0 enable update mode description value immediate writes to the pwm0en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm0en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm0en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd0 1:0 835 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 12: pwm0 control (pwm0ctl), offset 0x040 register 13: pwm1 control (pwm1ctl), offset 0x080 register 14: pwm2 control (pwm2ctl), offset 0x0c0 these registers configure the pwm signal generation blocks (pwm0ctl controls the pwm generator 0 block, and so on). the register update mode, debug mode, counting mode, and block enable mode are all controlled via these registers. the blocks produce the pwm signals, which can be either two independent pwm signals (from the same counter), or a paired set of pwm signals with dead-band delays added. the pwm0 block produces the pwm0 and pwm1 outputs, the pwm1 block produces the pwm2 and pwm3 outputs, and the pwm2 block produces the pwm4 and pwm5 outputs. pwm0 control (pwm0ctl) pwm0 base: 0x4002.8000 offset 0x040 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fltsrc minfltper latch reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:19 latch fault input description value fault condition not latched a fault condition is in effect for as long as the generating source is asserting. 0 fault condition latched a fault condition is set as the result of the assertion of the faulting source and is held (latched) while the pwmisc intfaultn bit is set. clearing the intfaultn bit clears the fault condition. 1 0 r/w latch 18 march 20, 2011 836 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field minimum fault period this bit specifies that the pwm generator enables a one-shot counter to provide a minimum fault condition period. the timer begins counting on the rising edge of the fault condition to extend the condition for a minimum duration of the count value. the timer ignores the state of the fault condition while counting. the minimum fault delay is in effect only when the minfltper bit is set. if a detected fault is in the process of being extended when the minfltper bit is cleared, the fault condition extension is aborted. the delay time is specified by the pwmnminfltper register mfp field value. the effect of this is to pulse stretch the fault condition input. the delay value is defined by the pwm clock period. because the fault input is not synchronized to the pwm clock, the period of the time is pwmclock * (mfp value + 1) or pwmclock * (mfp value + 2). the delay function makes sense only if the fault source is unlatched. a latched fault source makes the fault condition appear asserted until cleared by software and negates the utility of the extend feature. it applies to all fault condition sources as specified in the fltsrc field. description value the fault input deassertion is unaffected. 0 the pwmnminfltper one-shot counter is active and extends the period of the fault condition to a minimum period. 1 0 r/w minfltper 17 fault condition source description value the fault condition is determined by the fault0 input. 0 the fault condition is determined by the configuration of the pwmnfltsrc0 and pwmnfltsrc1 registers. 1 0 r/w fltsrc 16 pwmndbfall update mode description value immediate the pwmndbfall register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w dbfallupd 15:14 837 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field pwmndbrise update mode description value immediate the pwmndbrise register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w dbriseupd 13:12 pwmndbctl update mode description value immediate the pwmndbctl register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w dbctlupd 11:10 pwmngenb update mode description value immediate the pwmngenb register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w genbupd 9:8 march 20, 2011 838 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field pwmngena update mode description value immediate the pwmngena register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w genaupd 7:6 comparator b update mode description value locally synchronized updates to the pwmncmpb register are reflected to the generator the next time the counter is 0. 0 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 1 0 r/w cmpbupd 5 comparator a update mode description value locally synchronized updates to the pwmncmpa register are reflected to the generator the next time the counter is 0. 0 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 1 0 r/w cmpaupd 4 load register update mode description value locally synchronized updates to the pwmnload register are reflected to the generator the next time the counter is 0. 0 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 1 0 r/w loadupd 3 839 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field debug mode description value the counter stops running when it next reaches 0 and continues running again when no longer in debug mode. 0 the counter always runs when in debug mode. 1 0 r/w debug 2 counter mode description value the counter counts down from the load value to 0 and then wraps back to the load value (count-down mode). 0 the counter counts up from 0 to the load value, back down to 0, and then repeats (count-up/down mode). 1 0 r/w mode 1 pwm block enable description value the entire pwm generation block is disabled and not clocked. 0 the pwm generation block is enabled and produces pwm signals. 1 0 r/w enable 0 march 20, 2011 840 texas instruments-advance information pulse width modulator (pwm) register 15: pwm0 interrupt and trigger enable (pwm0inten), offset 0x044 register 16: pwm1 interrupt and trigger enable (pwm1inten), offset 0x084 register 17: pwm2 interrupt and trigger enable (pwm2inten), offset 0x0c4 these registers control the interrupt and adc trigger generation capabilities of the pwm generators (pwm0inten controls the pwm generator 0 block, and so on). the events that can cause an interrupt or an adc trigger are: the counter being equal to the load register the counter being equal to zero the counter being equal to the pwmncmpa register while counting up the counter being equal to the pwmncmpa register while counting down the counter being equal to the pwmncmpb register while counting up the counter being equal to the pwmncmpb register while counting down any combination of these events can generate either an interrupt or an adc trigger, though no determination can be made as to the actual event that caused an adc trigger if more than one is specified. the pwmnris register provides information about which events have caused raw interrupts. pwm0 interrupt and trigger enable (pwm0inten) pwm0 base: 0x4002.8000 offset 0x044 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd reserved r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:14 trigger for counter= pwmncmpb down description value an adc trigger pulse is output when the counter matches the value in the pwmncmpb register value while counting down. 1 no adc trigger is output. 0 0 r/w trcmpbd 13 841 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field trigger for counter= pwmncmpb up description value an adc trigger pulse is output when the counter matches the value in the pwmncmpb register value while counting up. 1 no adc trigger is output. 0 0 r/w trcmpbu 12 trigger for counter= pwmncmpa down description value an adc trigger pulse is output when the counter matches the value in the pwmncmpa register value while counting down. 1 no adc trigger is output. 0 0 r/w trcmpad 11 trigger for counter= pwmncmpa up description value an adc trigger pulse is output when the counter matches the value in the pwmncmpa register value while counting up. 1 no adc trigger is output. 0 0 r/w trcmpau 10 trigger for counter= pwmnload description value an adc trigger pulse is output when the counter matches the pwmnload register. 1 no adc trigger is output. 0 0 r/w trcntload 9 trigger for counter=0 description value an adc trigger pulse is output when the counter is 0. 1 no adc trigger is output. 0 0 r/w trcntzero 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 interrupt for counter= pwmncmpb down description value a raw interrupt occurs when the counter matches the value in the pwmncmpb register value while counting down. 1 no interrupt. 0 0 r/w intcmpbd 5 march 20, 2011 842 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field interrupt for counter= pwmncmpb up description value a raw interrupt occurs when the counter matches the value in the pwmncmpb register value while counting up. 1 no interrupt. 0 0 r/w intcmpbu 4 interrupt for counter= pwmncmpa down description value a raw interrupt occurs when the counter matches the value in the pwmncmpa register value while counting down. 1 no interrupt. 0 0 r/w intcmpad 3 interrupt for counter= pwmncmpa up description value a raw interrupt occurs when the counter matches the value in the pwmncmpa register value while counting up. 1 no interrupt. 0 0 r/w intcmpau 2 interrupt for counter= pwmnload description value a raw interrupt occurs when the counter matches the value in the pwmnload register value. 1 no interrupt. 0 0 r/w intcntload 1 interrupt for counter=0 description value a raw interrupt occurs when the counter is zero. 1 no interrupt. 0 0 r/w intcntzero 0 843 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 18: pwm0 raw interrupt status (pwm0ris), offset 0x048 register 19: pwm1 raw interrupt status (pwm1ris), offset 0x088 register 20: pwm2 raw interrupt status (pwm2ris), offset 0x0c8 these registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller ( pwm0ris controls the pwm generator 0 block, and so on). if a bit is set, the event has occurred; if a bit is clear, the event has not occurred. bits in this register are cleared by writing a 1 to the corresponding bit in the pwmnisc register. pwm0 raw interrupt status (pwm0ris) pwm0 base: 0x4002.8000 offset 0x048 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:6 comparator b down interrupt status description value the counter has matched the value in the pwmncmpb register while counting down. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcmpbd bit in the pwmnisc register. 0 ro intcmpbd 5 comparator b up interrupt status description value the counter has matched the value in the pwmncmpb register while counting up. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcmpbu bit in the pwmnisc register. 0 ro intcmpbu 4 march 20, 2011 844 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field comparator a down interrupt status description value the counter has matched the value in the pwmncmpa register while counting down. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcmpad bit in the pwmnisc register. 0 ro intcmpad 3 comparator a up interrupt status description value the counter has matched the value in the pwmncmpa register while counting up. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcmpau bit in the pwmnisc register. 0 ro intcmpau 2 counter=load interrupt status description value the counter has matched the value in the pwmnload register. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcntload bit in the pwmnisc register. 0 ro intcntload 1 counter=0 interrupt status description value the counter has matched zero. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcntzero bit in the pwmnisc register. 0 ro intcntzero 0 845 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 21: pwm0 interrupt status and clear (pwm0isc), offset 0x04c register 22: pwm1 interrupt status and clear (pwm1isc), offset 0x08c register 23: pwm2 interrupt status and clear (pwm2isc), offset 0x0cc these registers provide the current set of interrupt sources that are asserted to the interrupt controller (pwm0isc controls the pwm generator 0 block, and so on). a bit is set if the event has occurred and is enabled in the pwmninten register; if a bit is clear, the event has not occurred or is not enabled. these are r/w1c registers; writing a 1 to a bit position clears the corresponding interrupt reason. pwm0 interrupt status and clear (pwm0isc) pwm0 base: 0x4002.8000 offset 0x04c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 comparator b down interrupt description value the intcmpbd bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcmpbd bit in the pwmnris register. 0 r/w1c intcmpbd 5 comparator b up interrupt description value the intcmpbu bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcmpbu bit in the pwmnris register. 0 r/w1c intcmpbu 4 march 20, 2011 846 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field comparator a down interrupt description value the intcmpad bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcmpad bit in the pwmnris register. 0 r/w1c intcmpad 3 comparator a up interrupt description value the intcmpau bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcmpau bit in the pwmnris register. 0 r/w1c intcmpau 2 counter=load interrupt description value the intcntload bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcntload bit in the pwmnris register. 0 r/w1c intcntload 1 counter=0 interrupt description value the intcntzero bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcntzero bit in the pwmnris register. 0 r/w1c intcntzero 0 847 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 24: pwm0 load (pwm0load), offset 0x050 register 25: pwm1 load (pwm1load), offset 0x090 register 26: pwm2 load (pwm2load), offset 0x0d0 these registers contain the load value for the pwm counter ( pwm0load controls the pwm generator 0 block, and so on). based on the counter mode configured by the mode bit in the pwmnctl register, this value is either loaded into the counter after it reaches zero or is the limit of up-counting after which the counter decrements back to zero. when this value matches the counter, a pulse is output which can be configured to drive the generation of the pwma and/or pwmb signal (via the pwmngena / pwmngenb register) or drive an interruptor adc trigger (via the pwmninten register). if the load value update mode is locally synchronized (based on the loadupd field encoding in the pwmnctl register), the 16-bit load value is used the next time the counter reaches zero. if the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 815). if this register is re-written before the actual update occurs, the previous value is never used and is lost. pwm0 load (pwm0load) pwm0 base: 0x4002.8000 offset 0x050 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 counter load value the counter load value. 0x0000 r/w load 15:0 march 20, 2011 848 texas instruments-advance information pulse width modulator (pwm) register 27: pwm0 counter (pwm0count), offset 0x054 register 28: pwm1 counter (pwm1count), offset 0x094 register 29: pwm2 counter (pwm2count), offset 0x0d4 these registers contain the current value of the pwm counter ( pwm0count is the value of the pwm generator 0 block, and so on). when this value matches zero or the value in the pwmnload , pwmncmpa , or pwmncmpb registers, a pulse is output which can be configured to drive the generation of a pwm signal or drive an interrupt or adc trigger. pwm0 counter (pwm0count) pwm0 base: 0x4002.8000 offset 0x054 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 counter value the current value of the counter. 0x0000 ro count 15:0 849 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 30: pwm0 compare a (pwm0cmpa), offset 0x058 register 31: pwm1 compare a (pwm1cmpa), offset 0x098 register 32: pwm2 compare a (pwm2cmpa), offset 0x0d8 these registers contain a value to be compared against the counter ( pwm0cmpa controls the pwm generator 0 block, and so on). when this value matches the counter, a pulse is output which can be configured to drive the generation of the pwma and pwmb signals (via the pwmngena and pwmngenb registers) or drive an interrupt or adc trigger (via the pwmninten register). if the value of this register is greater than the pwmnload register (see page 848), then no pulse is ever output. if the comparator a update mode is locally synchronized (based on the cmpaupd bit in the pwmnctl register), the 16-bit compa value is used the next time the counter reaches zero. if the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 815). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 compare a (pwm0cmpa) pwm0 base: 0x4002.8000 offset 0x058 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 compa r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 comparator a value the value to be compared against the counter. 0x00 r/w compa 15:0 march 20, 2011 850 texas instruments-advance information pulse width modulator (pwm) register 33: pwm0 compare b (pwm0cmpb), offset 0x05c register 34: pwm1 compare b (pwm1cmpb), offset 0x09c register 35: pwm2 compare b (pwm2cmpb), offset 0x0dc these registers contain a value to be compared against the counter ( pwm0cmpb controls the pwm generator 0 block, and so on). when this value matches the counter, a pulse is output which can be configured to drive the generation of the pwma and pwmb signals (via the pwmngena and pwmngenb registers) or drive an interrupt or adc trigger (via the pwmninten register). if the value of this register is greater than the pwmnload register, no pulse is ever output. if the comparator b update mode is locally synchronized (based on the cmpbupd bit in the pwmnctl register), the 16-bit compb value is used the next time the counter reaches zero. if the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 815). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 compare b (pwm0cmpb) pwm0 base: 0x4002.8000 offset 0x05c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 compb r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 comparator b value the value to be compared against the counter. 0x0000 r/w compb 15:0 851 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 36: pwm0 generator a control (pwm0gena), offset 0x060 register 37: pwm1 generator a control (pwm1gena), offset 0x0a0 register 38: pwm2 generator a control (pwm2gena), offset 0x0e0 these registers control the generation of the pwma signal based on the load and zero output pulses from the counter, as well as the compare a and compare b pulses from the comparators (pwm0gena controls the pwm generator 0 block, and so on). when the counter is running in count-down mode, only four of these events occur; when running in count-up/down mode, all six occur. these events provide great flexibility in the positioning and duty cycle of the resulting pwm signal. the pwm0gena register controls generation of the pwm0a signal; pwm1gena , the pwm1a signal; and pwm2gena , the pwm2a signal. if a zero or load event coincides with a compare a or compare b event, the zero or load action is taken and the compare a or compare b action is ignored. if a compare a event coincides with a compare b event, the compare a action is taken and the compare b action is ignored. if the generator a update mode is immediate (based on the genaupd field encoding in the pwmnctl register), the actcmpbd, actcmpbu, actcmpad, actcmpau, actload , and actzero values are used immediately. if the update mode is locally synchronized, these values are used the next time the counter reaches zero. if the update mode is globally synchronized, these values are used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 815). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 generator a control (pwm0gena) pwm0 base: 0x4002.8000 offset 0x060 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 actzero actload actcmpau actcmpad actcmpbu actcmpbd reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 action for comparator b down this field specifies the action to be taken when the counter matches comparator b while counting down. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actcmpbd 11:10 march 20, 2011 852 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field action for comparator b up this field specifies the action to be taken when the counter matches comparator b while counting up. this action can only occur when the mode bit in the pwmnctl register is set. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actcmpbu 9:8 action for comparator a down this field specifies the action to be taken when the counter matches comparator a while counting down. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actcmpad 7:6 action for comparator a up this field specifies the action to be taken when the counter matches comparator a while counting up. this action can only occur when the mode bit in the pwmnctl register is set. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actcmpau 5:4 action for counter= load this field specifies the action to be taken when the counter matches the value in the pwmnload register. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actload 3:2 853 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field action for counter=0 this field specifies the action to be taken when the counter is zero. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actzero 1:0 march 20, 2011 854 texas instruments-advance information pulse width modulator (pwm) register 39: pwm0 generator b control (pwm0genb), offset 0x064 register 40: pwm1 generator b control (pwm1genb), offset 0x0a4 register 41: pwm2 generator b control (pwm2genb), offset 0x0e4 these registers control the generation of the pwmb signal based on the load and zero output pulses from the counter, as well as the compare a and compare b pulses from the comparators (pwm0genb controls the pwm generator 0 block, and so on). when the counter is running in count-down mode, only four of these events occur; when running in count-up/down mode, all six occur. these events provide great flexibility in the positioning and duty cycle of the resulting pwm signal. the pwm0genb register controls generation of the pwm0b signal; pwm1genb , the pwm1b signal; and pwm2genb , the pwm2b signal. if a zero or load event coincides with a compare a or compare b event, the zero or load action is taken and the compare a or compare b action is ignored. if a compare a event coincides with a compare b event, the compare b action is taken and the compare a action is ignored. if the generator b update mode is immediate (based on the genbupd field encoding in the pwmnctl register), the actcmpbd, actcmpbu, actcmpad, actcmpau, actload , and actzero values are used immediately. if the update mode is locally synchronized, these values are used the next time the counter reaches zero. if the update mode is globally synchronized, these values are used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 815). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 generator b control (pwm0genb) pwm0 base: 0x4002.8000 offset 0x064 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 actzero actload actcmpau actcmpad actcmpbu actcmpbd reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 action for comparator b down this field specifies the action to be taken when the counter matches comparator b while counting down. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actcmpbd 11:10 855 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field action for comparator b up this field specifies the action to be taken when the counter matches comparator b while counting up. this action can only occur when the mode bit in the pwmnctl register is set. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actcmpbu 9:8 action for comparator a down this field specifies the action to be taken when the counter matches comparator a while counting down. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actcmpad 7:6 action for comparator a up this field specifies the action to be taken when the counter matches comparator a while counting up. this action can only occur when the mode bit in the pwmnctl register is set. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actcmpau 5:4 action for counter= load this field specifies the action to be taken when the counter matches the load value. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actload 3:2 march 20, 2011 856 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field action for counter=0 this field specifies the action to be taken when the counter is 0. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actzero 1:0 857 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 42: pwm0 dead-band control (pwm0dbctl), offset 0x068 register 43: pwm1 dead-band control (pwm1dbctl), offset 0x0a8 register 44: pwm2 dead-band control (pwm2dbctl), offset 0x0e8 the pwmndbctl register controls the dead-band generator, which produces the pwmn signals based on the pwma and pwmb signals. when disabled, the pwma signal passes through to the pwma' signal and the pwmb signal passes through to the pwmb' signal. when dead-band control is enabled, the pwmb signal is ignored, the pwma' signal is generated by delaying the rising edge(s) of the pwma signal by the value in the pwmndbrise register (see page 859), and the pwmb' signal is generated by inverting the pwma signal and delaying the falling edge(s) of the pwma signal by the value in the pwmndbfall register (see page 860). the output control block outputs the pwm0a' signal on the pwm0 signal and the pwm0b' signal on the pwm1 signal. in a similar manner, pwm2 and pwm3 are produced from the pwm1a' and pwm1b' signals, and pwm4 and pwm5 are produced from the pwm2a' and pwm2b' signals. if the dead-band control mode is immediate (based on the dbctlupd field encoding in the pwmnctl register), the enable bit value is used immediately. if the update mode is locally synchronized, this value is used the next time the counter reaches zero. if the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 815). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 dead-band control (pwm0dbctl) pwm0 base: 0x4002.8000 offset 0x068 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 dead-band generator enable description value the dead-band generator modifies the pwma signal by inserting dead bands into the pwma' and pwmb' signals. 1 the pwma and pwmb signals pass through to the pwma' and pwmb' signals unmodified. 0 0 r/w enable 0 march 20, 2011 858 texas instruments-advance information pulse width modulator (pwm) register 45: pwm0 dead-band rising-edge delay (pwm0dbrise), offset 0x06c register 46: pwm1 dead-band rising-edge delay (pwm1dbrise), offset 0x0ac register 47: pwm2 dead-band rising-edge delay (pwm2dbrise), offset 0x0ec the pwmndbrise register contains the number of clock cycles to delay the rising edge of the pwma signal when generating the pwma' signal. if the dead-band generator is disabled through the pwmndbctl register, this register is ignored. if the value of this register is larger than the width of a high pulse on the pwma signal, the rising-edge delay consumes the entire high time of the signal, resulting in no high time on the output. care must be taken to ensure that the pwma high time always exceeds the rising-edge delay. if the dead-band rising-edge delay mode is immediate (based on the dbriseupd field encoding in the pwmnctl register), the 12-bit risedelay value is used immediately. if the update mode is locally synchronized, this value is used the next time the counter reaches zero. if the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 815). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 dead-band rising-edge delay (pwm0dbrise) pwm0 base: 0x4002.8000 offset 0x06c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 risedelay reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 dead-band rise delay the number of clock cycles to delay the rising edge of pwma' after the rising edge of pwma. 0x000 r/w risedelay 11:0 859 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 48: pwm0 dead-band falling-edge-delay (pwm0dbfall), offset 0x070 register 49: pwm1 dead-band falling-edge-delay (pwm1dbfall), offset 0x0b0 register 50: pwm2 dead-band falling-edge-delay (pwm2dbfall), offset 0x0f0 the pwmndbfall register contains the number of clock cycles to delay the rising edge of the pwmb' signal from the falling edge of the pwma signal. if the dead-band generator is disabled through the pwmndbctl register, this register is ignored. if the value of this register is larger than the width of a low pulse on the pwma signal, the falling-edge delay consumes the entire low time of the signal, resulting in no low time on the output. care must be taken to ensure that the pwma low time always exceeds the falling-edge delay. if the dead-band falling-edge-delay mode is immediate (based on the dbfallup field encoding in the pwmnctl register), the 12-bit falldelay value is used immediately. if the update mode is locally synchronized, this value is used the next time the counter reaches zero. if the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 815). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 dead-band falling-edge-delay (pwm0dbfall) pwm0 base: 0x4002.8000 offset 0x070 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 falldelay reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 dead-band fall delay the number of clock cycles to delay the falling edge of pwmb' from the rising edge of pwma. 0x000 r/w falldelay 11:0 march 20, 2011 860 texas instruments-advance information pulse width modulator (pwm) register 51: pwm0 fault source 0 (pwm0fltsrc0), offset 0x074 register 52: pwm1 fault source 0 (pwm1fltsrc0), offset 0x0b4 register 53: pwm2 fault source 0 (pwm2fltsrc0), offset 0x0f4 this register specifies which fault pin inputs are used to generate a fault condition. each bit in the following register indicates whether the corresponding fault pin is included in the fault condition. all enabled fault pins are ored together to form the pwmnfltsrc0 portion of the fault condition. the pwmnfltsrc0 fault condition is then ored with the pwmnfltsrc1 fault condition to generate the final fault condition for the pwm generator. if the fltsrc bit in the pwmnctl register (see page 836) is clear, only the fault0 signal affects the fault condition generated. otherwise, sources defined in pwmnfltsrc0 and pwmnfltsrc1 affect the fault condition generated. pwm0 fault source 0 (pwm0fltsrc0) pwm0 base: 0x4002.8000 offset 0x074 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:4 fault3 input description value the fault3 signal is suppressed and cannot generate a fault condition. 0 the fault3 signal value is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w fault3 3 fault2 input description value the fault2 signal is suppressed and cannot generate a fault condition. 0 the fault2 signal value is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w fault2 2 861 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field fault1 input description value the fault1 signal is suppressed and cannot generate a fault condition. 0 the fault1 signal value is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w fault1 1 fault0 input description value the fault0 signal is suppressed and cannot generate a fault condition. 0 the fault0 signal value is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w fault0 0 march 20, 2011 862 texas instruments-advance information pulse width modulator (pwm) register 54: pwm0 fault source 1 (pwm0fltsrc1), offset 0x078 register 55: pwm1 fault source 1 (pwm1fltsrc1), offset 0x0b8 register 56: pwm2 fault source 1 (pwm2fltsrc1), offset 0x0f8 this register specifies which digital comparator triggers from the adc are used to generate a fault condition. each bit in the following register indicates whether the corresponding digital comparator trigger is included in the fault condition. all enabled digital comparator triggers are ored together to form the pwmnfltsrc1 portion of the fault condition. the pwmnfltsrc1 fault condition is then ored with the pwmnfltsrc0 fault condition to generate the final fault condition for the pwm generator. if the fltsrc bit in the pwmnctl register (see page 836) is clear, only the pwm fault0 pin affects the fault condition generated. otherwise, sources defined in pwmnfltsrc0 and pwmnfltsrc1 affect the fault condition generated. pwm0 fault source 1 (pwm0fltsrc1) pwm0 base: 0x4002.8000 offset 0x078 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 digital comparator 7 description value the trigger from digital comparator 7 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 7 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp7 7 863 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field digital comparator 6 description value the trigger from digital comparator 6 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 6 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp6 6 digital comparator 5 description value the trigger from digital comparator 5 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 5 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp5 5 digital comparator 4 description value the trigger from digital comparator 4 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 4 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp4 4 digital comparator 3 description value the trigger from digital comparator 3 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 3 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp3 3 march 20, 2011 864 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field digital comparator 2 description value the trigger from digital comparator 2 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 2 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp2 2 digital comparator 1 description value the trigger from digital comparator 1 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 1 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp1 1 digital comparator 0 description value the trigger from digital comparator 0 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 0 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp0 0 865 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 57: pwm0 minimum fault period (pwm0minfltper), offset 0x07c register 58: pwm1 minimum fault period (pwm1minfltper), offset 0x0bc register 59: pwm2 minimum fault period (pwm2minfltper), offset 0x0fc if the minfltper bit in the pwmnctl register is set, this register specifies the 16-bit time-extension value to be used in extending the fault condition. the value is loaded into a 16-bit down counter, and the counter value is used to extend the fault condition. the fault condition is released in the clock immediately after the counter value reaches 0. the fault condition is asynchronous to the pwm clock; and the delay value is the product of the pwm clock period and the (mfp field value + 1) or (mfp field value + 2) depending on when the fault condition asserts with respect to the pwm clock. the counter decrements at the pwm clock rate, without pause or condition. pwm0 minimum fault period (pwm0minfltper) pwm0 base: 0x4002.8000 offset 0x07c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mfp ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 r/w reserved 31:16 minimum fault period the number of pwm clocks by which a fault condition is extended when the delay is enabled by pwmnctl minfltper. 0x0000 ro mfp 15:0 march 20, 2011 866 texas instruments-advance information pulse width modulator (pwm) register 60: pwm0 fault pin logic sense (pwm0fltsen), offset 0x800 register 61: pwm1 fault pin logic sense (pwm1fltsen), offset 0x880 register 62: pwm2 fault pin logic sense (pwm2fltsen), offset 0x900 register 63: pwm3 fault pin logic sense (pwm3fltsen), offset 0x980 this register defines the pwm fault pin logic sense. pwm0 fault pin logic sense (pwm0fltsen) pwm0 base: 0x4002.8000 offset 0x800 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 fault3 sense description value an error is indicated if the fault3 signal is high. 0 an error is indicated if the fault3 signal is low. 1 0 r/w fault3 3 fault2 sense description value an error is indicated if the fault2 signal is high. 0 an error is indicated if the fault2 signal is low. 1 0 r/w fault2 2 fault1 sense description value an error is indicated if the fault1 signal is high. 0 an error is indicated if the fault1 signal is low. 1 0 r/w fault1 1 fault0 sense description value an error is indicated if the fault0 signal is high. 0 an error is indicated if the fault0 signal is low. 1 0 r/w fault0 0 867 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 64: pwm0 fault status 0 (pwm0fltstat0), offset 0x804 register 65: pwm1 fault status 0 (pwm1fltstat0), offset 0x884 register 66: pwm2 fault status 0 (pwm2fltstat0), offset 0x904 along with the pwmnfltstat1 register, this register provides status regarding the fault condition inputs. if the latch bit in the pwmnctl register is clear, the contents of the pwmnfltstat0 register are read-only (ro) and provide the current state of the faultn inputs. if the latch bit in the pwmnctl register is set, the contents of the pwmnfltstat0 register are read / write 1 to clear (r/w1c) and provide a latched version of the faultn inputs. in this mode, the register bits are cleared by writing a 1 to a set bit. the faultn inputs are recorded after their sense is adjusted in the generator. the contents of this register can only be written if the fault source extensions are enabled (the fltsrc bit in the pwmnctl register is set). pwm0 fault status 0 (pwm0fltstat0) pwm0 base: 0x4002.8000 offset 0x804 type -, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 reserved - - - - ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:4 fault input 3 if the pwmnctl register latch bit is clear, this bit is ro and represents the current state of the fault3 input signal after the logic sense adjustment. if the pwmnctl register latch bit is set, this bit is r/w1c and represents a sticky version of the fault3 input signal after the logic sense adjustment. if fault3 is set, the input transitioned to the active state previously. if fault3 is clear, the input has not transitioned to the active state since the last time it was cleared. the fault3 bit is cleared by writing it with the value 1. 0 - fault3 3 march 20, 2011 868 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field fault input 2 if the pwmnctl register latch bit is clear, this bit is ro and represents the current state of the fault2 input signal after the logic sense adjustment. if the pwmnctl register latch bit is set, this bit is r/w1c and represents a sticky version of the fault2 input signal after the logic sense adjustment. if fault2 is set, the input transitioned to the active state previously. if fault2 is clear, the input has not transitioned to the active state since the last time it was cleared. the fault2 bit is cleared by writing it with the value 1. 0 - fault2 2 fault input 1 if the pwmnctl register latch bit is clear, this bit is ro and represents the current state of the fault1 input signal after the logic sense adjustment. if the pwmnctl register latch bit is set, this bit is r/w1c and represents a sticky version of the fault1 input signal after the logic sense adjustment. if fault1 is set, the input transitioned to the active state previously. if fault1 is clear, the input has not transitioned to the active state since the last time it was cleared. the fault1 bit is cleared by writing it with the value 1. 0 - fault1 1 fault input 0 if the pwmnctl register latch bit is clear, this bit is ro and represents the current state of the input signal after the logic sense adjustment. if the pwmnctl register latch bit is set, this bit is r/w1c and represents a sticky version of the input signal after the logic sense adjustment. if fault0 is set, the input transitioned to the active state previously. if fault0 is clear, the input has not transitioned to the active state since the last time it was cleared. the fault0 bit is cleared by writing it with the value 1. 0 - fault0 0 869 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 67: pwm0 fault status 1 (pwm0fltstat1), offset 0x808 register 68: pwm1 fault status 1 (pwm1fltstat1), offset 0x888 register 69: pwm2 fault status 1 (pwm2fltstat1), offset 0x908 along with the pwmnfltstat0 register, this register provides status regarding the fault condition inputs. if the latch bit in the pwmnctl register is clear, the contents of the pwmnfltstat1 register are read-only (ro) and provide the current state of the digital comparator triggers. if the latch bit in the pwmnctl register is set, the contents of the pwmnfltstat1 register are read / write 1 to clear (r/w1c) and provide a latched version of the digital comparator triggers. in this mode, the register bits are cleared by writing a 1 to a set bit. the contents of this register can only be written if the fault source extensions are enabled (the fltsrc bit in the pwmnctl register is set). pwm0 fault status 1 (pwm0fltstat1) pwm0 base: 0x4002.8000 offset 0x808 type -, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 reserved - - - - - - - - ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 digital comparator 7 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 7 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp7 is set, the trigger transitioned to the active state previously. if dcmp7 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp7 bit is cleared by writing it with the value 1. 0 - dcmp7 7 march 20, 2011 870 texas instruments-advance information pulse width modulator (pwm) description reset type name bit/field digital comparator 6 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 6 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp6 is set, the trigger transitioned to the active state previously. if dcmp6 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp6 bit is cleared by writing it with the value 1. 0 - dcmp6 6 digital comparator 5 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 5 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp5 is set, the trigger transitioned to the active state previously. if dcmp5 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp5 bit is cleared by writing it with the value 1. 0 - dcmp5 5 digital comparator 4 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 4 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp4 is set, the trigger transitioned to the active state previously. if dcmp4 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp4 bit is cleared by writing it with the value 1. 0 - dcmp4 4 digital comparator 3 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 3 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp3 is set, the trigger transitioned to the active state previously. if dcmp3 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp3 bit is cleared by writing it with the value 1. 0 - dcmp3 3 871 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field digital comparator 2 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 2 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp2 is set, the trigger transitioned to the active state previously. if dcmp2 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp2 bit is cleared by writing it with the value 1. 0 - dcmp2 2 digital comparator 1 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 1 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp1 is set, the trigger transitioned to the active state previously. if dcmp1 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp1 bit is cleared by writing it with the value 1. 0 - dcmp1 1 digital comparator 0 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 0 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp0 is set, the trigger transitioned to the active state previously. if dcmp0 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp0 bit is cleared by writing it with the value 1. 0 - dcmp0 0 march 20, 2011 872 texas instruments-advance information pulse width modulator (pwm) 19 quadrature encoder interface (qei) a quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. by monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. in addition, a third channel, or index signal, can be used to reset the position counter. the lm3s1p51 microcontroller includes two quadrature encoder interface (qei) modules. each qei module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. the stellaris ? lm3s1p51 microcontroller includes two qei modules providing control of two motors at the same time with the following features: position integrator that tracks the encoder position programmable noise filter on the inputs velocity capture using built-in timer the input frequency of the qei inputs may be as high as 1/4 of the processor frequency (for example, 12.5 mhz for a 50-mhz system) interrupt generation on: C index pulse C velocity-timer expiration C direction change C quadrature error detection 19.1 block diagram figure 19-1 on page 874 provides a block diagram of a stellaris qei module. 873 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure 19-1. qei block diagram 19.2 signal description table 19-1 on page 874 and table 19-2 on page 875 list the external signals of the qei module and describe the function of each. the qei signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these qei signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 428) should be set to choose the qei function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 446) to assign the qei signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 404. table 19-1. signals for qei (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name qei module 0 index. ttl i pd0 (3) pg5 (4) pb2 (2) pb6 (5) pb4 (6) pd7 (1) 10 40 72 90 92 100 idx0 qei module 1 index. ttl i pg2 (8) pf1 (2) ph2 (1) 17 61 84 idx1 qei module 0 phase a. ttl i pd1 (3) pc4 (2) pf6 (4) pe2 (4) 11 25 43 95 pha0 march 20, 2011 874 texas instruments-advance information quadrature encoder interface (qei) 4 x d g u d w x u h ( q f r g h u 9 h o r f l w \ 3 u h g l y l g h u , q w h u u x s w & r q w u r o 4 ( , , 1 7 ( 1 4 ( , 5 , 6 4 ( , , 6 & 3 r v l w l r q , q w h j u d w r u 4 ( , 0 $ ; 3 2 6 4 ( , 3 2 6 9 h o r f l w \ $ f f x p x o d w r u 4 ( , & 2 8 1 7 4 ( , 6 3 ( ( ' 9 h o r f l w \ 7 l p h u 4 ( , / 2 $ ' 4 ( , 7 , 0 ( 3 k $ 3 k % , ' ; f o n g l u , q w h u u x s w & r q w u r o 6 w d w x v 4 ( , & 7 / 4 ( , 6 7 $ 7 table 19-1. signals for qei (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name qei module 1 phase a. ttl i pg6 (1) pe3 (3) 37 96 pha1 qei module 0 phase b. ttl i pc7 (2) pc6 (2) pf7 (4) pf0 (2) ph3 (1) pe3 (4) 22 23 42 47 83 96 phb0 qei module 1 phase b. ttl i pd1 (11) pg7 (1) pe2 (3) 11 36 95 phb1 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 19-2. signals for qei (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name qei module 0 index. ttl i pd0 (3) pg5 (4) pb2 (2) pb6 (5) pb4 (6) pd7 (1) g1 m7 a11 a7 a6 a2 idx0 qei module 1 index. ttl i pg2 (8) pf1 (2) ph2 (1) j1 h12 d11 idx1 qei module 0 phase a. ttl i pd1 (3) pc4 (2) pf6 (4) pe2 (4) g2 l1 m8 a4 pha0 qei module 1 phase a. ttl i pg6 (1) pe3 (3) l7 b4 pha1 qei module 0 phase b. ttl i pc7 (2) pc6 (2) pf7 (4) pf0 (2) ph3 (1) pe3 (4) l2 m2 k4 m9 d10 b4 phb0 qei module 1 phase b. ttl i pd1 (11) pg7 (1) pe2 (3) g2 c10 a4 phb1 a. the ttl designation indicates the pin has ttl-compatible voltage levels. 19.3 functional description the qei module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. the position integrator and velocity capture can be independently enabled, though the position integrator must be enabled before the velocity capture can be enabled. the two phase signals, pha and phb , can be swapped before being interpreted by the qei module to change the meaning of 875 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller forward and backward and to correct for miswiring of the system. alternatively, the phase signals can be interpreted as a clock and direction signal as output by some encoders. the qei module input signals have a digital noise filter on them that can be enabled to prevent spurious operation. the noise filter requires that the inputs be stable for a specified number of consecutive clock cycles before updating the edge detector. the filter is enabled by the filten bit in the qei control (qeictl) register. the frequency of the input update is programmable using the filtcnt bit field in the qeictl register. the qei module supports two modes of signal operation: quadrature phase mode and clock/direction mode. in quadrature phase mode, the encoder produces two clocks that are 90 degrees out of phase; the edge relationship is used to determine the direction of rotation. in clock/direction mode, the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction of rotation. this mode is determined by the sigmode bit of the qeictl register (see page 880). when the qei module is set to use the quadrature phase mode ( sigmode bit is clear), the capture mode for the position integrator can be set to update the position counter on every edge of the pha signal or to update on every edge of both pha and phb . updating the position counter on every pha and phb edge provides more positional resolution at the cost of less range in the positional counter. when edges on pha lead edges on phb , the position counter is incremented. when edges on phb lead edges on pha , the position counter is decremented. when a rising and falling edge pair is seen on one of the phases without any edges on the other, the direction of rotation has changed. the positional counter is automatically reset on one of two conditions: sensing the index pulse or reaching the maximum position value. the reset mode is determined by the resmode bit of the qeictl register. when resmode is set, the positional counter is reset when the index pulse is sensed. this mode limits the positional counter to the values [0:n-1], where n is the number of phase edges in a full revolution of the encoder wheel. the qei maximum position (qeimaxpos) register must be programmed with n-1 so that the reverse direction from position 0 can move the position counter to n-1. in this mode, the position register contains the absolute position of the encoder relative to the index (or home) position once an index pulse has been seen. when resmode is clear, the positional counter is constrained to the range [0:m], where m is the programmable maximum value. the index pulse is ignored by the positional counter in this mode. velocity capture uses a configurable timer and a count register. the timer counts the number of phase edges (using the same configuration as for the position integrator) in a given time period. the edge count from the previous time period is available to the controller via the qei velocity (qeispeed) register, while the edge count for the current time period is being accumulated in the qei velocity counter (qeicount) register. as soon as the current time period is complete, the total number of edges counted in that time period is made available in the qeispeed register (overwriting the previous value), the qeicount register is cleared, and counting commences on a new time period. the number of edges counted in a given time period is directly proportional to the velocity of the encoder. figure 19-2 on page 877 shows how the stellaris quadrature encoder converts the phase input signals into clock pulses, the direction signal, and how the velocity predivider operates (in divide by 4 mode). march 20, 2011 876 texas instruments-advance information quadrature encoder interface (qei) figure 19-2. quadrature encoder and velocity predivider operation the period of the timer is configurable by specifying the load value for the timer in the qei timer load (qeiload) register. when the timer reaches zero, an interrupt can be triggered, and the hardware reloads the timer with the qeiload value and continues to count down. at lower encoder speeds, a longer timer period is required to be able to capture enough edges to have a meaningful result. at higher encoder speeds, both a shorter timer period and/or the velocity predivider can be used. the following equation converts the velocity counter value into an rpm value: rpm = (clock * (2 ^ veldiv) * speed * 60) (load * ppr * edges) where: clock is the controller clock rate ppr is the number of pulses per revolution of the physical encoder edges is 2 or 4, based on the capture mode set in the qeictl register (2 for capmode clear and 4 for capmode set) for example, consider a motor running at 600 rpm. a 2048 pulse per revolution quadrature encoder is attached to the motor, producing 8192 phase edges per revolution. with a velocity predivider of 1 ( veldiv is clear) and clocking on both pha and phb edges, this results in 81,920 pulses per second (the motor turns 10 times per second). if the timer were clocked at 10,000 hz, and the load value was 2,500 (? of a second), it would count 20,480 pulses per update. using the above equation: rpm = (10000 * 1 * 20480 * 60) (2500 * 2048 * 4) = 600 rpm now, consider that the motor is sped up to 3000 rpm. this results in 409,600 pulses per second, or 102,400 every ? of a second. again, the above equation gives: rpm = (10000 * 1 * 102400 * 60) (2500 * 2048 * 4) = 3000 rpm care must be taken when evaluating this equation because intermediate values may exceed the capacity of a 32-bit integer. in the above examples, the clock is 10,000 and the divider is 2,500; both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. in fact, if they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled by the 4 for the edge-count factor. important: reducing constant factors at compile time is the best way to control the intermediate values of this equation and reduce the processing requirement of computing this equation. the division can be avoided by selecting a timer load value such that the divisor is a power of 2; a simple shift can therefore be done in place of the division. for encoders with a power of 2 pulses per revolution, the load value can be a power of 2. for other encoders, a load value must be selected such that the product is very close to a power of 2. for example, a 100 pulse-per-revolution encoder 877 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 3 k $ 3 k % f o n f o n g l y g l u s r v u h o could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 2 14 . in this case a shift by 15 would be an adequate approximation of the divide in most cases. if absolute accuracy were required, the microcontrollers divide instruction could be used. the qei module can produce a controller interrupt on several events: phase error, direction change, reception of the index pulse, and expiration of the velocity timer. standard masking, raw interrupt status, interrupt status, and interrupt clear capabilities are provided. 19.4 initialization and configuration the following example shows how to configure the quadrature encoder module to read back an absolute position: 1. enable the qei clock by writing a value of 0x0000.0100 to the rcgc1 register in the system control module (see page 260). 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module (see page 269). 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register. to determine which gpios to configure, see table 21-4 on page 917. 4. configure the pmcn fields in the gpiopctl register to assign the qei signals to the appropriate pins (see page 446 and table 21-5 on page 925). 5. configure the quadrature encoder to capture edges on both signals and maintain an absolute position by resetting on index pulses. a 1000-line encoder with four edges per line, results in 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xf9f) as the count is zero-based. write the qeictl register with the value of 0x0000.0018. write the qeimaxpos register with the value of 0x0000.0f9f. 6. enable the quadrature encoder by setting bit 0 of the qeictl register. 7. delay until the encoder position is required. 8. read the encoder position by reading the qei position (qeipos) register value. 19.5 register map table 19-3 on page 879 lists the qei registers. the offset listed is a hexadecimal increment to the registers address, relative to the modules base address: qei0: 0x4002.c000 qei1: 0x4002.d000 note that the qei module clock must be enabled before the registers can be programmed (see page 260). there must be a delay of 3 system clocks after the qei module clock is enabled before any qei module registers are accessed. march 20, 2011 878 texas instruments-advance information quadrature encoder interface (qei) table 19-3. qei register map see page description reset type name offset 880 qei control 0x0000.0000 r/w qeictl 0x000 883 qei status 0x0000.0000 ro qeistat 0x004 884 qei position 0x0000.0000 r/w qeipos 0x008 885 qei maximum position 0x0000.0000 r/w qeimaxpos 0x00c 886 qei timer load 0x0000.0000 r/w qeiload 0x010 887 qei timer 0x0000.0000 ro qeitime 0x014 888 qei velocity counter 0x0000.0000 ro qeicount 0x018 889 qei velocity 0x0000.0000 ro qeispeed 0x01c 890 qei interrupt enable 0x0000.0000 r/w qeiinten 0x020 892 qei raw interrupt status 0x0000.0000 ro qeiris 0x024 894 qei interrupt status and clear 0x0000.0000 r/w1c qeiisc 0x028 19.6 register descriptions the remainder of this section lists and describes the qei registers, in numerical order by address offset. 879 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 1: qei control (qeictl), offset 0x000 this register contains the configuration of the qei module. separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity, but the velocity does not need to be captured in applications that do not need it. the phase signal interpretation, phase swap, position update mode, position reset mode, and velocity predivider are all set via this register. qei control (qeictl) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 filtcnt reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable swap sigmode capmode resmode velen veldiv inva invb invi stallen filten reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 input filter prescale count this field controls the frequency of the input update. when this field is clear, the input is sampled after 2 system clocks. when this field ix 0x1, the input is sampled after 3 system clocks. similarly, when this field is 0xf, the input is sampled after 17 clocks. 0x0 r/w filtcnt 19:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:14 enable input filter description value the qei inputs are not filtered. 0 enables the digital noise filter on the qei input signals. inputs must be stable for 3 consecutive clock edges before the edge detector is updated. 1 0 r/w filten 13 stall qei description value the qei module does not stall when the microcontroller is stopped by a debugger. 0 the qei module stalls when the microcontroller is stopped by a debugger. 1 0 r/w stallen 12 march 20, 2011 880 texas instruments-advance information quadrature encoder interface (qei) description reset type name bit/field invert index pulse description value no effect. 0 inverts the idx input. 1 0 r/w invi 11 invert phb description value no effect. 0 inverts the phb input. 1 0 r/w invb 10 invert pha description value no effect. 0 inverts the pha input. 1 0 r/w inva 9 predivide velocity this field defines the predivider of the input quadrature pulses before being applied to the qeicount accumulator. predivider value 10x0 20x1 40x2 80x3 160x4 320x5 640x6 128 0x7 0x0 r/w veldiv 8:6 capture velocity description value no effect. 0 enables capture of the velocity of the quadrature encoder. 1 0 r/w velen 5 reset mode description value the position counter is reset when it reaches the maximum as defined by the maxpos field in the qeimaxpos register. 0 the position counter is reset when the index pulse is captured. 1 0 r/w resmode 4 881 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller description reset type name bit/field capture mode description value only the pha edges are counted. 0 the pha and phb edges are counted, providing twice the positional resolution but half the range. 1 0 r/w capmode 3 signal mode description value the pha and phb signals operate as quadrature phase signals. 0 the pha and phb signals operate as clock and direction. 1 0 r/w sigmode 2 swap signals description value no effect. 0 swaps the pha and phb signals. 1 0 r/w swap 1 enable qei description value no effect. 0 enables the quadrature encoder module. 1 0 r/w enable 0 march 20, 2011 882 texas instruments-advance information quadrature encoder interface (qei) register 2: qei status (qeistat), offset 0x004 this register provides status about the operation of the qei module. qei status (qeistat) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 error direction reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 direction of rotation indicates the direction the encoder is rotating. description value the encoder is rotating forward. 0 the encoder is rotating in reverse. 1 0 ro direction 1 error detected description value no error. 0 an error was detected in the gray code sequence (that is, both signals changing at the same time). 1 0 ro error 0 883 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 3: qei position (qeipos), offset 0x008 this register contains the current value of the position integrator. the value is updated by the status of the qei phase inputs and can be set to a specific value by writing to it. qei position (qeipos) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 position r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 position r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field current position integrator value the current value of the position integrator. 0x0000.0000 r/w position 31:0 march 20, 2011 884 texas instruments-advance information quadrature encoder interface (qei) register 4: qei maximum position (qeimaxpos), offset 0x00c this register contains the maximum value of the position integrator. when moving forward, the position register resets to zero when it increments past this value. when moving in reverse, the position register resets to this value when it decrements from zero. qei maximum position (qeimaxpos) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 maxpos r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 maxpos r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field maximum position integrator value the maximum value of the position integrator. 0x0000.0000 r/w maxpos 31:0 885 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 5: qei timer load (qeiload), offset 0x010 this register contains the load value for the velocity timer. because this value is loaded into the timer on the clock cycle after the timer is zero, this value should be one less than the number of clocks in the desired period. so, for example, to have 2000 decimal clocks per timer period, this register should contain 1999 decimal. qei timer load (qeiload) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field velocity timer load value the load value for the velocity timer. 0x0000.0000 r/w load 31:0 march 20, 2011 886 texas instruments-advance information quadrature encoder interface (qei) register 6: qei timer (qeitime), offset 0x014 this register contains the current value of the velocity timer. this counter does not increment when the velen bit in the qeictl register is clear. qei timer (qeitime) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x014 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 time ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 time ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field velocity timer current value the current value of the velocity timer. 0x0000.0000 ro time 31:0 887 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 7: qei velocity counter (qeicount), offset 0x018 this register contains the running count of velocity pulses for the current time period. because this count is a running total, the time period to which it applies cannot be known with precision (that is, a read of this register does not necessarily correspond to the time returned by the qeitime register because there is a small window of time between the two reads, during which either value may have changed). the qeispeed register should be used to determine the actual encoder velocity; this register is provided for information purposes only. this counter does not increment when the velen bit in the qeictl register is clear. qei velocity counter (qeicount) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field velocity pulse count the running total of encoder pulses during this velocity timer period. 0x0000.0000 ro count 31:0 march 20, 2011 888 texas instruments-advance information quadrature encoder interface (qei) register 8: qei velocity (qeispeed), offset 0x01c this register contains the most recently measured velocity of the quadrature encoder. this value corresponds to the number of velocity pulses counted in the previous velocity timer period. this register does not update when the velen bit in the qeictl register is clear. qei velocity (qeispeed) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x01c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 speed ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 speed ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field velocity the measured speed of the quadrature encoder in pulses per period. 0x0000.0000 ro speed 31:0 889 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 9: qei interrupt enable (qeiinten), offset 0x020 this register contains enables for each of the qei module interrupts. an interrupt is asserted to the interrupt controller if the corresponding bit in this register is set. qei interrupt enable (qeiinten) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intindex inttimer intdir interror reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 phase error interrupt enable description value an interrupt is sent to the interrupt controller when the interror bit in the qeiris register is set. 1 the interror interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w interror 3 direction change interrupt enable description value an interrupt is sent to the interrupt controller when the intdir bit in the qeiris register is set. 1 the intdir interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intdir 2 timer expires interrupt enable description value an interrupt is sent to the interrupt controller when the inttimer bit in the qeiris register is set. 1 the inttimer interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w inttimer 1 march 20, 2011 890 texas instruments-advance information quadrature encoder interface (qei) description reset type name bit/field index pulse detected interrupt enable description value an interrupt is sent to the interrupt controller when the intindex bit in the qeiris register is set. 1 the intindex interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intindex 0 891 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 10: qei raw interrupt status (qeiris), offset 0x024 this register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (configured through the qeiinten register). if a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred. qei raw interrupt status (qeiris) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x024 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intindex inttimer intdir interror reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 phase error detected description value a phase error has been detected. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the interror bit in the qeiisc register. 0 ro interror 3 direction change detected description value the rotation direction has changed 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intdir bit in the qeiisc register. 0 ro intdir 2 velocity timer expired description value the velocity timer has expired. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the inttimer bit in the qeiisc register. 0 ro inttimer 1 march 20, 2011 892 texas instruments-advance information quadrature encoder interface (qei) description reset type name bit/field index pulse asserted description value the index pulse has occurred. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intindex bit in the qeiisc register. 0 ro intindex 0 893 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller register 11: qei interrupt status and clear (qeiisc), offset 0x028 this register provides the current set of interrupt sources that are asserted to the controller. if a bit is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the event in question has not occurred or is not enabled to generate an interrupt. this register is r/w1c; writing a 1 to a bit position clears the bit and the corresponding interrupt reason. qei interrupt status and clear (qeiisc) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x028 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intindex inttimer intdir interror reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 phase error interrupt description value the interror bits in the qeiris register and the qeiinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the interror bit in the qeiris register. 0 r/w1c interror 3 direction change interrupt description value the intdir bits in the qeiris register and the qeiinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intdir bit in the qeiris register. 0 r/w1c intdir 2 velocity timer expired interrupt description value the inttimer bits in the qeiris register and the qeiinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inttimer bit in the qeiris register. 0 r/w1c inttimer 1 march 20, 2011 894 texas instruments-advance information quadrature encoder interface (qei) description reset type name bit/field index pulse interrupt description value the intindex bits in the qeiris register and the qeiinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intindex bit in the qeiris register. 0 r/w1c intindex 0 895 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 20 pin diagram the lm3s1p51 microcontroller pin diagram is shown below. each gpio signal is identified by its gpio port unless it defaults to an alternate function on reset. in this case, the gpio port name is followed by the default alternate function. to see a complete list of possible functions for each pin, see table 21-5 on page 925. figure 20-1. 100-pin lqfp package pin diagram march 20, 2011 896 texas instruments-advance information pin diagram figure 20-2. 108-ball bga package pin diagram (top view) 897 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 21 signal tables the following tables list the signals available for each pin. signals are configured as gpios on reset, except for those noted below. use the gpioamsel register (see page 444) to select analog mode. for a gpio pin to be used for an alternate digital function, the corresponding bit in the gpioafsel register (see page 428) must be set. further pin muxing options are provided through the pmcx bit field in the gpiopctl register (see page 446), which selects one of several available peripheral functions for that gpio. important: all gpio pins are configured as gpios by default with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 21-1. gpio pins with default alternate functions gpiopctl pmcx bit field gpioafsel bit default state gpio pin 0x1 0 uart0 pa[1:0] 0x1 0 ssi0 pa[5:2] 0x1 0 i 2 c0 pb[3:2] 0x3 1 jtag/swd pc[3:0] table 21-2 on page 899 shows the pin-to-signal-name mapping, including functional characteristics of the signals. each possible alternate analog and digital function is listed for each pin. table 21-3 on page 909 lists the signals in alphabetical order by signal name. if it is possible for a signal to be on multiple pins, each possible pin assignment is listed. the "pin mux" column indicates the gpio and the encoding needed in the pmcx bit field in the gpiopctl register. table 21-4 on page 917 groups the signals by functionality, except for gpios. if it is possible for a signal to be on multiple pins, each possible pin assignment is listed. table 21-5 on page 925 lists the gpio pins and their analog and digital alternate functions. the ainx and vrefa analog signals are not 5-v tolerant and go through an isolation circuit before reaching their circuitry. these signals are configured by clearing the corresponding den bit in the gpio digital enable (gpioden) register and setting the corresponding amsel bit in the gpio analog mode select (gpioamsel) register. other analog signals are 5-v tolerant and are connected directly to their circuitry ( c0-, c0+, c1-, c1+ ). these signals are configured by clearing the den bit in the gpio digital enable (gpioden) register. the digital signals are enabled by setting the appropriate bit in the gpio alternate function select (gpioafsel) and gpioden registers and configuring the pmcx bit field in the gpio port control (gpiopctl) register to the numeric enoding shown in the table below. table entries that are shaded gray are the default values for the corresponding gpio pin. table 21-6 on page 928 lists the signals based on number of possible pin assignments. this table can be used to plan how to configure the pins for a particular functionality. application note an01274 configuring stellaris? microcontrollers with pin multiplexing provides an overview of the pin muxing implementation, an explanation of how a system designer defines a pin configuration, and examples of the pin configuration process. note: all digital inputs are schmitt triggered. march 20, 2011 898 texas instruments-advance information signal tables 21.1 100-pin lqfp package pin tables table 21-2. signals by pin number description buffer type a pin type pin name pin number gpio port e bit 7. ttl i/o pe7 1 analog-to-digital converter input 0. analog i ain0 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 1 data carrier detect modem status input signal. ttl i u1dcd gpio port e bit 6. ttl i/o pe6 2 analog-to-digital converter input 1. analog i ain1 analog comparator 1 output. ttl o c1o pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 1 clear to send modem status input signal. ttl i u1cts the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be connected to 3.3 v, regardless of system implementation. power - vdda 3 the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - gnda 4 gpio port e bit 5. ttl i/o pe5 5 analog-to-digital converter input 2. analog i ain2 capture/compare/pwm 5. ttl i/o ccp5 i 2 s module 0 transmit data. ttl i/o i2s0txsd gpio port e bit 4. ttl i/o pe4 6 analog-to-digital converter input 3. analog i ain3 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 3. ttl i/o ccp3 pwm fault 0. ttl i fault0 i 2 s module 0 transmit word select. ttl i/o i2s0txws uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - ldo 7 positive supply for i/o and some logic. power - vdd 8 ground reference for logic and i/o pins. power - gnd 9 899 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port d bit 0. ttl i/o pd0 10 analog-to-digital converter input 15. analog i ain15 capture/compare/pwm 6. ttl i/o ccp6 i 2 s module 0 receive clock. ttl i/o i2s0rxsck qei module 0 index. ttl i idx0 pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 uart module 1 clear to send modem status input signal. ttl i u1cts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx gpio port d bit 1. ttl i/o pd1 11 analog-to-digital converter input 14. analog i ain14 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 7. ttl i/o ccp7 i 2 s module 0 receive word select. ttl i/o i2s0rxws pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 qei module 0 phase a. ttl i pha0 qei module 1 phase b. ttl i phb1 uart module 1 data carrier detect modem status input signal. ttl i u1dcd uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port d bit 2. ttl i/o pd2 12 analog-to-digital converter input 13. analog i ain13 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 6. ttl i/o ccp6 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port d bit 3. ttl i/o pd3 13 analog-to-digital converter input 12. analog i ain12 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 7. ttl i/o ccp7 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port j bit 0. ttl i/o pj0 14 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 march 20, 2011 900 texas instruments-advance information signal tables table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port h bit 7. ttl i/o ph7 15 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 transmit. ttl o ssi1tx gpio port g bit 3. ttl i/o pg3 16 pwm fault 0. ttl i fault0 pwm fault 2. ttl i fault2 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 gpio port g bit 2. ttl i/o pg2 17 pwm fault 0. ttl i fault0 i 2 s module 0 receive data. ttl i/o i2s0rxsd qei module 1 index. ttl i idx1 pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 gpio port g bit 1. ttl i/o pg1 18 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port g bit 0. ttl i/o pg0 19 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx positive supply for i/o and some logic. power - vdd 20 ground reference for logic and i/o pins. power - gnd 21 gpio port c bit 7. ttl i/o pc7 22 analog comparator 1 output. ttl o c1o capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 4. ttl i/o ccp4 qei module 0 phase b. ttl i phb0 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port c bit 6. ttl i/o pc6 23 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 qei module 0 phase b. ttl i phb0 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx 901 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port c bit 5. ttl i/o pc5 24 analog comparator 0 output. ttl o c0o analog comparator 1 positive input. analog i c1+ analog comparator 1 output. ttl o c1o capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 3. ttl i/o ccp3 pwm fault 2. ttl i fault2 gpio port c bit 4. ttl i/o pc4 25 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 capture/compare/pwm 5. ttl i/o ccp5 qei module 0 phase a. ttl i pha0 gpio port a bit 0. ttl i/o pa0 26 i 2 c module 1 clock. od i/o i2c1scl uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i u0rx uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port a bit 1. ttl i/o pa1 27 i 2 c module 1 data. od i/o i2c1sda uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o u0tx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port a bit 2. ttl i/o pa2 28 i 2 s module 0 receive data. ttl i/o i2s0rxsd pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 0 clock. ttl i/o ssi0clk gpio port a bit 3. ttl i/o pa3 29 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 0 frame. ttl i/o ssi0fss gpio port a bit 4. ttl i/o pa4 30 i 2 s module 0 transmit clock. ttl i/o i2s0txsck ssi module 0 receive. ttl i ssi0rx gpio port a bit 5. ttl i/o pa5 31 i 2 s module 0 transmit word select. ttl i/o i2s0txws ssi module 0 transmit. ttl o ssi0tx positive supply for i/o and some logic. power - vdd 32 ground reference for logic and i/o pins. power - gnd 33 march 20, 2011 902 texas instruments-advance information signal tables table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port a bit 6. ttl i/o pa6 34 capture/compare/pwm 1. ttl i/o ccp1 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 1 clear to send modem status input signal. ttl i u1cts gpio port a bit 7. ttl i/o pa7 35 capture/compare/pwm 3. ttl i/o ccp3 capture/compare/pwm 4. ttl i/o ccp4 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 1 data carrier detect modem status input signal. ttl i u1dcd gpio port g bit 7. ttl i/o pg7 36 capture/compare/pwm 5. ttl i/o ccp5 qei module 1 phase b. ttl i phb1 gpio port g bit 6. ttl i/o pg6 37 pwm fault 1. ttl i fault1 i 2 s module 0 receive word select. ttl i/o i2s0rxws qei module 1 phase a. ttl i pha1 uart module 1 ring indicator modem status input signal. ttl i u1ri positive supply for most of the logic function, including the processor core and most peripherals. power - vddc 38 gpio port j bit 2. ttl i/o pj2 39 capture/compare/pwm 0. ttl i/o ccp0 pwm fault 0. ttl i fault0 gpio port g bit 5. ttl i/o pg5 40 capture/compare/pwm 5. ttl i/o ccp5 pwm fault 1. ttl i fault1 i 2 s module 0 receive clock. ttl i/o i2s0rxsck qei module 0 index. ttl i idx0 uart module 1 data terminal ready modem status input signal. ttl o u1dtr gpio port g bit 4. ttl i/o pg4 41 capture/compare/pwm 3. ttl i/o ccp3 pwm fault 1. ttl i fault1 uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port f bit 7. ttl i/o pf7 42 capture/compare/pwm 4. ttl i/o ccp4 pwm fault 1. ttl i fault1 qei module 0 phase b. ttl i phb0 903 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port f bit 6. ttl i/o pf6 43 capture/compare/pwm 1. ttl i/o ccp1 i 2 s module 0 transmit master clock. ttl i/o i2s0txmclk qei module 0 phase a. ttl i pha0 uart module 1 request to send modem output control line. ttl o u1rts positive supply for i/o and some logic. power - vdd 44 ground reference for logic and i/o pins. power - gnd 45 gpio port f bit 5. ttl i/o pf5 46 analog comparator 1 output. ttl o c1o capture/compare/pwm 2. ttl i/o ccp2 ssi module 1 transmit. ttl o ssi1tx gpio port f bit 0. ttl i/o pf0 47 i 2 s module 0 transmit data. ttl i/o i2s0txsd pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 qei module 0 phase b. ttl i phb0 uart module 1 data set ready modem output control line. ttl i u1dsr main oscillator crystal input or an external clock reference input. analog i osc0 48 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o osc1 49 an external input that brings the processor out of hibernate mode when asserted. ttl i wake 50 an output that indicates the processor is in hibernate mode. od o hib 51 hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.194304-mhz crystal or a 32.768-khz oscillator for the hibernation module rtc. see the clksel bit in the hibctl register. analog i xosc0 52 hibernation module oscillator crystal output. leave unconnected when using a single-ended clock source. analog o xosc1 53 ground reference for logic and i/o pins. power - gnd 54 power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply. power - vbat 55 positive supply for i/o and some logic. power - vdd 56 ground reference for logic and i/o pins. power - gnd 57 gpio port f bit 4. ttl i/o pf4 58 analog comparator 0 output. ttl o c0o capture/compare/pwm 0. ttl i/o ccp0 pwm fault 0. ttl i fault0 ssi module 1 receive. ttl i ssi1rx gpio port f bit 3. ttl i/o pf3 59 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 frame. ttl i/o ssi1fss march 20, 2011 904 texas instruments-advance information signal tables table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port f bit 2. ttl i/o pf2 60 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 clock. ttl i/o ssi1clk gpio port f bit 1. ttl i/o pf1 61 capture/compare/pwm 3. ttl i/o ccp3 i 2 s module 0 transmit master clock. ttl i/o i2s0txmclk qei module 1 index. ttl i idx1 pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 uart module 1 request to send modem output control line. ttl o u1rts gpio port h bit 6. ttl i/o ph6 62 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 receive. ttl i ssi1rx gpio port h bit 5. ttl i/o ph5 63 pwm fault 2. ttl i fault2 ssi module 1 frame. ttl i/o ssi1fss system reset input. ttl i rst 64 gpio port b bit 3. ttl i/o pb3 65 pwm fault 0. ttl i fault0 pwm fault 3. ttl i fault3 i 2 c module 0 data. od i/o i2c0sda gpio port b bit 0. ttl i/o pb0 66 capture/compare/pwm 0. ttl i/o ccp0 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port b bit 1. ttl i/o pb1 67 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 2. ttl i/o ccp2 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx positive supply for i/o and some logic. power - vdd 68 ground reference for logic and i/o pins. power - gnd 69 no connect. leave the pin electrically unconnected/isolated. - - nc 70 no connect. leave the pin electrically unconnected/isolated. - - nc 71 gpio port b bit 2. ttl i/o pb2 72 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 i 2 c module 0 clock. od i/o i2c0scl qei module 0 index. ttl i idx0 no connect. leave the pin electrically unconnected/isolated. - - nc 73 905 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port e bit 0. ttl i/o pe0 74 capture/compare/pwm 3. ttl i/o ccp3 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 clock. ttl i/o ssi1clk gpio port e bit 1. ttl i/o pe1 75 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 6. ttl i/o ccp6 pwm fault 0. ttl i fault0 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 frame. ttl i/o ssi1fss gpio port h bit 4. ttl i/o ph4 76 ssi module 1 clock. ttl i/o ssi1clk gpio port c bit 3. ttl i/o pc3 77 jtag tdo and swo. ttl o swo jtag tdo and swo. ttl o tdo gpio port c bit 2. ttl i/o pc2 78 jtag tdi. ttl i tdi gpio port c bit 1. ttl i/o pc1 79 jtag tms and swdio. ttl i/o swdio jtag tms and swdio. ttl i tms gpio port c bit 0. ttl i/o pc0 80 jtag/swd clk. ttl i swclk jtag/swd clk. ttl i tck positive supply for i/o and some logic. power - vdd 81 ground reference for logic and i/o pins. power - gnd 82 gpio port h bit 3. ttl i/o ph3 83 pwm fault 0. ttl i fault0 qei module 0 phase b. ttl i phb0 gpio port h bit 2. ttl i/o ph2 84 analog comparator 1 output. ttl o c1o pwm fault 3. ttl i fault3 qei module 1 index. ttl i idx1 gpio port h bit 1. ttl i/o ph1 85 capture/compare/pwm 7. ttl i/o ccp7 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 gpio port h bit 0. ttl i/o ph0 86 capture/compare/pwm 6. ttl i/o ccp6 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 march 20, 2011 906 texas instruments-advance information signal tables table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port j bit 1. ttl i/o pj1 87 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 positive supply for most of the logic function, including the processor core and most peripherals. power - vddc 88 gpio port b bit 7. ttl i/o pb7 89 non-maskable interrupt. ttl i nmi gpio port b bit 6. ttl i/o pb6 90 analog comparator 0 positive input. analog i c0+ analog comparator 0 output. ttl o c0o capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 7. ttl i/o ccp7 pwm fault 1. ttl i fault1 i 2 s module 0 transmit clock. ttl i/o i2s0txsck qei module 0 index. ttl i idx0 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 1023. the vrefa input is limited to the range specified in table 23-29 on page 981. analog i vrefa gpio port b bit 5. ttl i/o pb5 91 analog-to-digital converter input 11. analog i ain11 analog comparator 0 output. ttl o c0o analog comparator 1 negative input. analog i c1- capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 6. ttl i/o ccp6 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port b bit 4. ttl i/o pb4 92 analog-to-digital converter input 10. analog i ain10 analog comparator 0 negative input. analog i c0- qei module 0 index. ttl i idx0 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx positive supply for i/o and some logic. power - vdd 93 ground reference for logic and i/o pins. power - gnd 94 907 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port e bit 2. ttl i/o pe2 95 analog-to-digital converter input 9. analog i ain9 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 qei module 0 phase a. ttl i pha0 qei module 1 phase b. ttl i phb1 ssi module 1 receive. ttl i ssi1rx gpio port e bit 3. ttl i/o pe3 96 analog-to-digital converter input 8. analog i ain8 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 7. ttl i/o ccp7 qei module 1 phase a. ttl i pha1 qei module 0 phase b. ttl i phb0 ssi module 1 transmit. ttl o ssi1tx gpio port d bit 4. ttl i/o pd4 97 analog-to-digital converter input 7. analog i ain7 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 i 2 s module 0 receive data. ttl i/o i2s0rxsd uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port d bit 5. ttl i/o pd5 98 analog-to-digital converter input 6. analog i ain6 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx gpio port d bit 6. ttl i/o pd6 99 analog-to-digital converter input 5. analog i ain5 pwm fault 0. ttl i fault0 i 2 s module 0 transmit clock. ttl i/o i2s0txsck uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port d bit 7. ttl i/o pd7 100 analog-to-digital converter input 4. analog i ain4 analog comparator 0 output. ttl o c0o capture/compare/pwm 1. ttl i/o ccp1 i 2 s module 0 transmit word select. ttl i/o i2s0txws qei module 0 index. ttl i idx0 uart module 1 data terminal ready modem status input signal. ttl o u1dtr a. the ttl designation indicates the pin has ttl-compatible voltage levels. march 20, 2011 908 texas instruments-advance information signal tables table 21-3. signals by signal name description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 0. analog i pe7 1 ain0 analog-to-digital converter input 1. analog i pe6 2 ain1 analog-to-digital converter input 2. analog i pe5 5 ain2 analog-to-digital converter input 3. analog i pe4 6 ain3 analog-to-digital converter input 4. analog i pd7 100 ain4 analog-to-digital converter input 5. analog i pd6 99 ain5 analog-to-digital converter input 6. analog i pd5 98 ain6 analog-to-digital converter input 7. analog i pd4 97 ain7 analog-to-digital converter input 8. analog i pe3 96 ain8 analog-to-digital converter input 9. analog i pe2 95 ain9 analog-to-digital converter input 10. analog i pb4 92 ain10 analog-to-digital converter input 11. analog i pb5 91 ain11 analog-to-digital converter input 12. analog i pd3 13 ain12 analog-to-digital converter input 13. analog i pd2 12 ain13 analog-to-digital converter input 14. analog i pd1 11 ain14 analog-to-digital converter input 15. analog i pd0 10 ain15 analog comparator 0 positive input. analog i pb6 90 c0+ analog comparator 0 negative input. analog i pb4 92 c0- analog comparator 0 output. ttl o pc5 (3) pf4 (2) pb6 (3) pb5 (1) pd7 (2) 24 58 90 91 100 c0o analog comparator 1 positive input. analog i pc5 24 c1+ analog comparator 1 negative input. analog i pb5 91 c1- analog comparator 1 output. ttl o pe6 (2) pc7 (7) pc5 (2) pf5 (2) ph2 (2) 2 22 24 46 84 c1o capture/compare/pwm 0. ttl i/o pd3 (4) pc7 (4) pc6 (6) pj2 (9) pf4 (1) pb0 (1) pb2 (5) pb5 (4) pd4 (1) 13 22 23 39 58 66 72 91 97 ccp0 capture/compare/pwm 1. ttl i/o pc5 (1) pc4 (9) pa6 (2) pf6 (1) pb1 (4) pb6 (1) pe3 (1) pd7 (3) 24 25 34 43 67 90 96 100 ccp1 909 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 2. ttl i/o pe4 (6) pd1 (10) pc4 (5) pf5 (1) pb1 (1) pe1 (4) pb5 (6) pe2 (5) pd5 (1) 6 11 25 46 67 75 91 95 98 ccp2 capture/compare/pwm 3. ttl i/o pe4 (1) pc6 (1) pc5 (5) pa7 (7) pg4 (1) pf1 (10) pb2 (4) pe0 (3) pd4 (2) 6 23 24 35 41 61 72 74 97 ccp3 capture/compare/pwm 4. ttl i/o pc7 (1) pc4 (6) pa7 (2) pf7 (1) pe2 (1) pd5 (2) 22 25 35 42 95 98 ccp4 capture/compare/pwm 5. ttl i/o pe5 (1) pd2 (4) pc4 (1) pg7 (8) pg5 (1) pb6 (6) pb5 (2) 5 12 25 36 40 90 91 ccp5 capture/compare/pwm 6. ttl i/o pd0 (6) pd2 (2) pe1 (5) ph0 (1) pb5 (3) 10 12 75 86 91 ccp6 capture/compare/pwm 7. ttl i/o pd1 (6) pd3 (2) ph1 (1) pb6 (2) pe3 (5) 11 13 85 90 96 ccp7 pwm fault 0. ttl i pe4 (4) pg3 (8) pg2 (4) pj2 (10) pf4 (4) pb3 (2) pe1 (3) ph3 (2) pd6 (1) 6 16 17 39 58 65 75 83 99 fault0 pwm fault 1. ttl i pg6 (8) pg5 (5) pg4 (4) pf7 (9) pb6 (4) 37 40 41 42 90 fault1 march 20, 2011 910 texas instruments-advance information signal tables table 21-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name pwm fault 2. ttl i pg3 (4) pc5 (4) ph5 (10) 16 24 63 fault2 pwm fault 3. ttl i pb3 (4) ph2 (4) 65 84 fault3 ground reference for logic and i/o pins. power - fixed 9 21 33 45 54 57 69 82 94 gnd the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - fixed 4 gnda an output that indicates the processor is in hibernate mode. od o fixed 51 hib i 2 c module 0 clock. od i/o pb2 (1) 72 i2c0scl i 2 c module 0 data. od i/o pb3 (1) 65 i2c0sda i 2 c module 1 clock. od i/o pj0 (11) pg0 (3) pa0 (8) pa6 (1) 14 19 26 34 i2c1scl i 2 c module 1 data. od i/o pg1 (3) pa1 (8) pa7 (1) pj1 (11) 18 27 35 87 i2c1sda i 2 s module 0 receive master clock. ttl i/o pg3 (9) pa3 (9) pd5 (8) 16 29 98 i2s0rxmclk i 2 s module 0 receive clock. ttl i/o pd0 (8) pg5 (9) 10 40 i2s0rxsck i 2 s module 0 receive data. ttl i/o pg2 (9) pa2 (9) pd4 (8) 17 28 97 i2s0rxsd i 2 s module 0 receive word select. ttl i/o pd1 (8) pg6 (9) 11 37 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o pf6 (9) pf1 (8) 43 61 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o pa4 (9) pb6 (9) pd6 (8) 30 90 99 i2s0txsck i 2 s module 0 transmit data. ttl i/o pe5 (9) pf0 (8) 5 47 i2s0txsd i 2 s module 0 transmit word select. ttl i/o pe4 (9) pa5 (9) pd7 (8) 6 31 100 i2s0txws 911 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name qei module 0 index. ttl i pd0 (3) pg5 (4) pb2 (2) pb6 (5) pb4 (6) pd7 (1) 10 40 72 90 92 100 idx0 qei module 1 index. ttl i pg2 (8) pf1 (2) ph2 (1) 17 61 84 idx1 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - fixed 7 ldo no connect. leave the pin electrically unconnected/isolated. - - fixed 70 71 73 nc non-maskable interrupt. ttl i pb7 (4) 89 nmi main oscillator crystal input or an external clock reference input. analog i fixed 48 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed 49 osc1 gpio port a bit 0. ttl i/o - 26 pa0 gpio port a bit 1. ttl i/o - 27 pa1 gpio port a bit 2. ttl i/o - 28 pa2 gpio port a bit 3. ttl i/o - 29 pa3 gpio port a bit 4. ttl i/o - 30 pa4 gpio port a bit 5. ttl i/o - 31 pa5 gpio port a bit 6. ttl i/o - 34 pa6 gpio port a bit 7. ttl i/o - 35 pa7 gpio port b bit 0. ttl i/o - 66 pb0 gpio port b bit 1. ttl i/o - 67 pb1 gpio port b bit 2. ttl i/o - 72 pb2 gpio port b bit 3. ttl i/o - 65 pb3 gpio port b bit 4. ttl i/o - 92 pb4 gpio port b bit 5. ttl i/o - 91 pb5 gpio port b bit 6. ttl i/o - 90 pb6 gpio port b bit 7. ttl i/o - 89 pb7 gpio port c bit 0. ttl i/o - 80 pc0 gpio port c bit 1. ttl i/o - 79 pc1 gpio port c bit 2. ttl i/o - 78 pc2 gpio port c bit 3. ttl i/o - 77 pc3 gpio port c bit 4. ttl i/o - 25 pc4 gpio port c bit 5. ttl i/o - 24 pc5 march 20, 2011 912 texas instruments-advance information signal tables table 21-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name gpio port c bit 6. ttl i/o - 23 pc6 gpio port c bit 7. ttl i/o - 22 pc7 gpio port d bit 0. ttl i/o - 10 pd0 gpio port d bit 1. ttl i/o - 11 pd1 gpio port d bit 2. ttl i/o - 12 pd2 gpio port d bit 3. ttl i/o - 13 pd3 gpio port d bit 4. ttl i/o - 97 pd4 gpio port d bit 5. ttl i/o - 98 pd5 gpio port d bit 6. ttl i/o - 99 pd6 gpio port d bit 7. ttl i/o - 100 pd7 gpio port e bit 0. ttl i/o - 74 pe0 gpio port e bit 1. ttl i/o - 75 pe1 gpio port e bit 2. ttl i/o - 95 pe2 gpio port e bit 3. ttl i/o - 96 pe3 gpio port e bit 4. ttl i/o - 6 pe4 gpio port e bit 5. ttl i/o - 5 pe5 gpio port e bit 6. ttl i/o - 2 pe6 gpio port e bit 7. ttl i/o - 1 pe7 gpio port f bit 0. ttl i/o - 47 pf0 gpio port f bit 1. ttl i/o - 61 pf1 gpio port f bit 2. ttl i/o - 60 pf2 gpio port f bit 3. ttl i/o - 59 pf3 gpio port f bit 4. ttl i/o - 58 pf4 gpio port f bit 5. ttl i/o - 46 pf5 gpio port f bit 6. ttl i/o - 43 pf6 gpio port f bit 7. ttl i/o - 42 pf7 gpio port g bit 0. ttl i/o - 19 pg0 gpio port g bit 1. ttl i/o - 18 pg1 gpio port g bit 2. ttl i/o - 17 pg2 gpio port g bit 3. ttl i/o - 16 pg3 gpio port g bit 4. ttl i/o - 41 pg4 gpio port g bit 5. ttl i/o - 40 pg5 gpio port g bit 6. ttl i/o - 37 pg6 gpio port g bit 7. ttl i/o - 36 pg7 gpio port h bit 0. ttl i/o - 86 ph0 gpio port h bit 1. ttl i/o - 85 ph1 gpio port h bit 2. ttl i/o - 84 ph2 gpio port h bit 3. ttl i/o - 83 ph3 gpio port h bit 4. ttl i/o - 76 ph4 gpio port h bit 5. ttl i/o - 63 ph5 gpio port h bit 6. ttl i/o - 62 ph6 913 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name gpio port h bit 7. ttl i/o - 15 ph7 qei module 0 phase a. ttl i pd1 (3) pc4 (2) pf6 (4) pe2 (4) 11 25 43 95 pha0 qei module 1 phase a. ttl i pg6 (1) pe3 (3) 37 96 pha1 qei module 0 phase b. ttl i pc7 (2) pc6 (2) pf7 (4) pf0 (2) ph3 (1) pe3 (4) 22 23 42 47 83 96 phb0 qei module 1 phase b. ttl i pd1 (11) pg7 (1) pe2 (3) 11 36 95 phb1 gpio port j bit 0. ttl i/o - 14 pj0 gpio port j bit 1. ttl i/o - 87 pj1 gpio port j bit 2. ttl i/o - 39 pj2 pwm 0. this signal is controlled by pwm generator 0. ttl o pd0 (1) pj0 (10) pg2 (1) pg0 (2) pa6 (4) pf0 (3) 10 14 17 19 34 47 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o pd1 (1) pg3 (1) pg1 (2) pa7 (4) pf1 (3) pj1 (10) 11 16 18 35 61 87 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o pd2 (3) pf2 (4) pb0 (2) ph0 (2) 12 60 66 86 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o pd3 (3) pf3 (4) pb1 (2) ph1 (2) 13 59 67 85 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o pe6 (1) pg0 (4) pa2 (4) pa6 (5) pf2 (2) ph6 (10) pe0 (1) ph0 (9) 2 19 28 34 60 62 74 86 pwm4 march 20, 2011 914 texas instruments-advance information signal tables table 21-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name pwm 5. this signal is controlled by pwm generator 2. ttl o pe7 (1) ph7 (10) pg1 (4) pa3 (4) pa7 (5) pf3 (2) pe1 (1) ph1 (9) 1 15 18 29 35 59 75 85 pwm5 system reset input. ttl i fixed 64 rst ssi module 0 clock. ttl i/o pa2 (1) 28 ssi0clk ssi module 0 frame. ttl i/o pa3 (1) 29 ssi0fss ssi module 0 receive. ttl i pa4 (1) 30 ssi0rx ssi module 0 transmit. ttl o pa5 (1) 31 ssi0tx ssi module 1 clock. ttl i/o pf2 (9) pe0 (2) ph4 (11) 60 74 76 ssi1clk ssi module 1 frame. ttl i/o pf3 (9) ph5 (11) pe1 (2) 59 63 75 ssi1fss ssi module 1 receive. ttl i pf4 (9) ph6 (11) pe2 (2) 58 62 95 ssi1rx ssi module 1 transmit. ttl o ph7 (11) pf5 (9) pe3 (2) 15 46 96 ssi1tx jtag/swd clk. ttl i pc0 (3) 80 swclk jtag tms and swdio. ttl i/o pc1 (3) 79 swdio jtag tdo and swo. ttl o pc3 (3) 77 swo jtag/swd clk. ttl i pc0 (3) 80 tck jtag tdi. ttl i pc2 (3) 78 tdi jtag tdo and swo. ttl o pc3 (3) 77 tdo jtag tms and swdio. ttl i pc1 (3) 79 tms uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i pa0 (1) 26 u0rx uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o pa1 (1) 27 u0tx uart module 1 clear to send modem status input signal. ttl i pe6 (9) pd0 (9) pa6 (9) 2 10 34 u1cts uart module 1 data carrier detect modem status input signal. ttl i pe7 (9) pd1 (9) pa7 (9) 1 11 35 u1dcd uart module 1 data set ready modem output control line. ttl i pf0 (9) 47 u1dsr uart module 1 data terminal ready modem status input signal. ttl o pg5 (10) pd7 (9) 40 100 u1dtr 915 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 1 ring indicator modem status input signal. ttl i pg6 (10) pg4 (10) pd4 (9) 37 41 97 u1ri uart module 1 request to send modem output control line. ttl o pf6 (10) pf1 (9) 43 61 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (5) pd2 (1) pc6 (5) pa0 (9) pb0 (5) pb4 (7) 10 12 23 26 66 92 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o pd1 (5) pd3 (1) pc7 (5) pa1 (9) pb1 (5) pb5 (7) 11 13 22 27 67 91 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (4) pg0 (1) pb4 (4) pd5 (9) 10 19 92 98 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o pe4 (5) pd1 (4) pg1 (1) pd6 (9) 6 11 18 99 u2tx power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply. power - fixed 55 vbat positive supply for i/o and some logic. power - fixed 8 20 32 44 56 68 81 93 vdd the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be connected to 3.3 v, regardless of system implementation. power - fixed 3 vdda positive supply for most of the logic function, including the processor core and most peripherals. power - fixed 38 88 vddc this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 1023. the vrefa input is limited to the range specified in table 23-29 on page 981. analog i pb6 90 vrefa an external input that brings the processor out of hibernate mode when asserted. ttl i fixed 50 wake march 20, 2011 916 texas instruments-advance information signal tables table 21-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.194304-mhz crystal or a 32.768-khz oscillator for the hibernation module rtc. see the clksel bit in the hibctl register. analog i fixed 52 xosc0 hibernation module oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed 53 xosc1 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 21-4. signals by function, except for gpio description buffer type a pin type pin number pin name function analog-to-digital converter input 0. analog i 1 ain0 adc analog-to-digital converter input 1. analog i 2 ain1 analog-to-digital converter input 2. analog i 5 ain2 analog-to-digital converter input 3. analog i 6 ain3 analog-to-digital converter input 4. analog i 100 ain4 analog-to-digital converter input 5. analog i 99 ain5 analog-to-digital converter input 6. analog i 98 ain6 analog-to-digital converter input 7. analog i 97 ain7 analog-to-digital converter input 8. analog i 96 ain8 analog-to-digital converter input 9. analog i 95 ain9 analog-to-digital converter input 10. analog i 92 ain10 analog-to-digital converter input 11. analog i 91 ain11 analog-to-digital converter input 12. analog i 13 ain12 analog-to-digital converter input 13. analog i 12 ain13 analog-to-digital converter input 14. analog i 11 ain14 analog-to-digital converter input 15. analog i 10 ain15 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 1023. the vrefa input is limited to the range specified in table 23-29 on page 981. analog i 90 vrefa 917 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function analog comparator 0 positive input. analog i 90 c0+ analog comparators analog comparator 0 negative input. analog i 92 c0- analog comparator 0 output. ttl o 24 58 90 91 100 c0o analog comparator 1 positive input. analog i 24 c1+ analog comparator 1 negative input. analog i 91 c1- analog comparator 1 output. ttl o 2 22 24 46 84 c1o march 20, 2011 918 texas instruments-advance information signal tables table 21-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function capture/compare/pwm 0. ttl i/o 13 22 23 39 58 66 72 91 97 ccp0 general-purpose timers capture/compare/pwm 1. ttl i/o 24 25 34 43 67 90 96 100 ccp1 capture/compare/pwm 2. ttl i/o 6 11 25 46 67 75 91 95 98 ccp2 capture/compare/pwm 3. ttl i/o 6 23 24 35 41 61 72 74 97 ccp3 capture/compare/pwm 4. ttl i/o 22 25 35 42 95 98 ccp4 capture/compare/pwm 5. ttl i/o 5 12 25 36 40 90 91 ccp5 capture/compare/pwm 6. ttl i/o 10 12 75 86 91 ccp6 capture/compare/pwm 7. ttl i/o ccp7 919 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function 11 13 85 90 96 an output that indicates the processor is in hibernate mode. od o 51 hib hibernate power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply. power - 55 vbat an external input that brings the processor out of hibernate mode when asserted. ttl i 50 wake hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.194304-mhz crystal or a 32.768-khz oscillator for the hibernation module rtc. see the clksel bit in the hibctl register. analog i 52 xosc0 hibernation module oscillator crystal output. leave unconnected when using a single-ended clock source. analog o 53 xosc1 i 2 c module 0 clock. od i/o 72 i2c0scl i2c i 2 c module 0 data. od i/o 65 i2c0sda i 2 c module 1 clock. od i/o 14 19 26 34 i2c1scl i 2 c module 1 data. od i/o 18 27 35 87 i2c1sda i 2 s module 0 receive master clock. ttl i/o 16 29 98 i2s0rxmclk i2s i 2 s module 0 receive clock. ttl i/o 10 40 i2s0rxsck i 2 s module 0 receive data. ttl i/o 17 28 97 i2s0rxsd i 2 s module 0 receive word select. ttl i/o 11 37 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o 43 61 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o 30 90 99 i2s0txsck i 2 s module 0 transmit data. ttl i/o 5 47 i2s0txsd i 2 s module 0 transmit word select. ttl i/o 6 31 100 i2s0txws march 20, 2011 920 texas instruments-advance information signal tables table 21-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function jtag/swd clk. ttl i 80 swclk jtag/swd/swo jtag tms and swdio. ttl i/o 79 swdio jtag tdo and swo. ttl o 77 swo jtag/swd clk. ttl i 80 tck jtag tdi. ttl i 78 tdi jtag tdo and swo. ttl o 77 tdo jtag tms and swdio. ttl i 79 tms 921 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function pwm fault 0. ttl i 6 16 17 39 58 65 75 83 99 fault0 pwm pwm fault 1. ttl i 37 40 41 42 90 fault1 pwm fault 2. ttl i 16 24 63 fault2 pwm fault 3. ttl i 65 84 fault3 pwm 0. this signal is controlled by pwm generator 0. ttl o 10 14 17 19 34 47 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o 11 16 18 35 61 87 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o 12 60 66 86 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o 13 59 67 85 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o 2 19 28 34 60 62 74 86 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o 1 15 18 29 35 59 75 85 pwm5 march 20, 2011 922 texas instruments-advance information signal tables table 21-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function ground reference for logic and i/o pins. power - 9 21 33 45 54 57 69 82 94 gnd power the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - 4 gnda low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - 7 ldo positive supply for i/o and some logic. power - 8 20 32 44 56 68 81 93 vdd the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be connected to 3.3 v, regardless of system implementation. power - 3 vdda positive supply for most of the logic function, including the processor core and most peripherals. power - 38 88 vddc 923 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function qei module 0 index. ttl i 10 40 72 90 92 100 idx0 qei qei module 1 index. ttl i 17 61 84 idx1 qei module 0 phase a. ttl i 11 25 43 95 pha0 qei module 1 phase a. ttl i 37 96 pha1 qei module 0 phase b. ttl i 22 23 42 47 83 96 phb0 qei module 1 phase b. ttl i 11 36 95 phb1 ssi module 0 clock. ttl i/o 28 ssi0clk ssi ssi module 0 frame. ttl i/o 29 ssi0fss ssi module 0 receive. ttl i 30 ssi0rx ssi module 0 transmit. ttl o 31 ssi0tx ssi module 1 clock. ttl i/o 60 74 76 ssi1clk ssi module 1 frame. ttl i/o 59 63 75 ssi1fss ssi module 1 receive. ttl i 58 62 95 ssi1rx ssi module 1 transmit. ttl o 15 46 96 ssi1tx non-maskable interrupt. ttl i 89 nmi system control & clocks main oscillator crystal input or an external clock reference input. analog i 48 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o 49 osc1 system reset input. ttl i 64 rst march 20, 2011 924 texas instruments-advance information signal tables table 21-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i 26 u0rx uart uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o 27 u0tx uart module 1 clear to send modem status input signal. ttl i 2 10 34 u1cts uart module 1 data carrier detect modem status input signal. ttl i 1 11 35 u1dcd uart module 1 data set ready modem output control line. ttl i 47 u1dsr uart module 1 data terminal ready modem status input signal. ttl o 40 100 u1dtr uart module 1 ring indicator modem status input signal. ttl i 37 41 97 u1ri uart module 1 request to send modem output control line. ttl o 43 61 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i 10 12 23 26 66 92 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o 11 13 22 27 67 91 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i 10 19 92 98 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o 6 11 18 99 u2tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 21-5. gpio pins and alternate functions digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1rx i2c1scl ------ u0rx -26 pa0 -- u1tx i2c1sda ------ u0tx -27 pa1 -- i2s0rxsd ---- pwm4 -- ssi0clk -28 pa2 -- i2s0rxmclk ---- pwm5 -- ssi0fss -29 pa3 -- i2s0txsck ------- ssi0rx -30 pa4 -- i2s0txws ------- ssi0tx -31 pa5 925 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-5. gpio pins and alternate functions (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1cts --- pwm4 pwm0 - ccp1 i2c1scl -34 pa6 -- u1dcd - ccp3 - pwm5 pwm1 - ccp4 i2c1sda -35 pa7 ------ u1rx -- pwm2 ccp0 -66 pb0 ------ u1tx ccp1 - pwm3 ccp2 -67 pb1 ------ ccp0 ccp3 - idx0 i2c0scl -72 pb2 ------- fault3 - fault0 i2c0sda -65 pb3 ---- u1rx idx0 - u2rx --- ain10 c0- 92 pb4 ---- u1tx ccp2 - ccp0 ccp6 ccp5 c0o ain11 c1- 91 pb5 -- i2s0txsck -- ccp5 idx0 fault1 c0o ccp7 ccp1 vrefa c0+ 90 pb6 ------- nmi ----89 pb7 -------- tck swclk ---80 pc0 -------- tms swdio ---79 pc1 -------- tdi ---78 pc2 -------- tdo swo ---77 pc3 -- ccp1 -- ccp4 ccp2 -- pha0 ccp5 -25 pc4 ------ ccp3 fault2 c0o c1o ccp1 c1+ 24 pc5 ----- ccp0 u1rx -- phb0 ccp3 -23 pc6 ---- c1o - u1tx ccp0 - phb0 ccp4 -22 pc7 -- u1cts i2s0rxsck - ccp6 u1rx u2rx idx0 - pwm0 ain15 10 pd0 phb1 ccp2 u1dcd i2s0rxws - ccp7 u1tx u2tx pha0 - pwm1 ain14 11 pd1 ------- ccp5 pwm2 ccp6 u1rx ain13 12 pd2 ------- ccp0 pwm3 ccp7 u1tx ain12 13 pd3 -- u1ri i2s0rxsd ----- ccp3 ccp0 ain7 97 pd4 -- u2rx i2s0rxmclk ----- ccp4 ccp2 ain6 98 pd5 -- u2tx i2s0txsck ------ fault0 ain5 99 pd6 -- u1dtr i2s0txws ---- ccp1 c0o idx0 ain4 100 pd7 -------- ccp3 ssi1clk pwm4 -74 pe0 ------ ccp6 ccp2 fault0 ssi1fss pwm5 -75 pe1 ------ ccp2 pha0 phb1 ssi1rx ccp4 ain9 95 pe2 ------ ccp7 phb0 pha1 ssi1tx ccp1 ain8 96 pe3 -- i2s0txws -- ccp2 u2tx fault0 -- ccp3 ain3 6 pe4 -- i2s0txsd ------- ccp5 ain2 5 pe5 -- u1cts ------ c1o pwm4 ain1 2 pe6 -- u1dcd ------- pwm5 ain0 1 pe7 -- u1dsr i2s0txsd ---- pwm0 phb0 --47 pf0 - ccp3 u1rts i2s0txmclk ---- pwm1 idx1 --61 pf1 march 20, 2011 926 texas instruments-advance information signal tables table 21-5. gpio pins and alternate functions (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- ssi1clk ---- pwm2 - pwm4 --60 pf2 -- ssi1fss ---- pwm3 - pwm5 --59 pf3 -- ssi1rx ---- fault0 - c0o ccp0 -58 pf4 -- ssi1tx ------ c1o ccp2 -46 pf5 - u1rts i2s0txmclk ---- pha0 -- ccp1 -43 pf6 -- fault1 ---- phb0 -- ccp4 -42 pf7 ------- pwm4 i2c1scl pwm0 u2rx -19 pg0 ------- pwm5 i2c1sda pwm1 u2tx -18 pg1 -- i2s0rxsd idx1 --- fault0 -- pwm0 -17 pg2 -- i2s0rxmclk fault0 --- fault2 -- pwm1 -16 pg3 - u1ri ----- fault1 -- ccp3 -41 pg4 - u1dtr i2s0rxsck --- fault1 idx0 -- ccp5 -40 pg5 - u1ri i2s0rxws fault1 ------ pha1 -37 pg6 --- ccp5 ------ phb1 -36 pg7 -- pwm4 ------ pwm2 ccp6 -86 ph0 -- pwm5 ------ pwm3 ccp7 -85 ph1 ------- fault3 - c1o idx1 -84 ph2 --------- fault0 phb0 -83 ph3 ssi1clk -----------76 ph4 ssi1fss fault2 ----------63 ph5 ssi1rx pwm4 ----------62 ph6 ssi1tx pwm5 ----------15 ph7 i2c1scl pwm0 ----------14 pj0 i2c1sda pwm1 ----------87 pj1 - fault0 ccp0 ---------39 pj2 a. the digital signals that are shaded gray are the power-on default values for the corresponding gpio pin. 927 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-6. possible pin assignments for alternate functions gpio function alternate function # of possible assignments pe7 ain0 one pe6 ain1 pb4 ain10 pb5 ain11 pd3 ain12 pd2 ain13 pd1 ain14 pd0 ain15 pe5 ain2 pe4 ain3 pd7 ain4 pd6 ain5 pd5 ain6 pd4 ain7 pe3 ain8 pe2 ain9 pb6 c0+ pb4 c0- pc5 c1+ pb5 c1- pb2 i2c0scl pb3 i2c0sda pb7 nmi pa2 ssi0clk pa3 ssi0fss pa4 ssi0rx pa5 ssi0tx pc0 swclk pc1 swdio pc3 swo pc0 tck pc2 tdi pc3 tdo pc1 tms pa0 u0rx pa1 u0tx pf0 u1dsr pb6 vrefa march 20, 2011 928 texas instruments-advance information signal tables table 21-6. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments pb3 ph2 fault3 two pd0 pg5 i2s0rxsck pd1 pg6 i2s0rxws pf1 pf6 i2s0txmclk pe5 pf0 i2s0txsd pe3 pg6 pha1 pd7 pg5 u1dtr pf1 pf6 u1rts pc5 pg3 ph5 fault2 three pa3 pd5 pg3 i2s0rxmclk pa2 pd4 pg2 i2s0rxsd pa4 pb6 pd6 i2s0txsck pa5 pd7 pe4 i2s0txws pf1 pg2 ph2 idx1 pd1 pe2 pg7 phb1 pe0 pf2 ph4 ssi1clk pe1 pf3 ph5 ssi1fss pe2 pf4 ph6 ssi1rx pe3 pf5 ph7 ssi1tx pa6 pd0 pe6 u1cts pa7 pd1 pe7 u1dcd pd4 pg4 pg6 u1ri pa0 pa6 pg0 pj0 i2c1scl four pa1 pa7 pg1 pj1 i2c1sda pb0 pd2 pf2 ph0 pwm2 pb1 pd3 pf3 ph1 pwm3 pc4 pd1 pe2 pf6 pha0 pb4 pd0 pd5 pg0 u2rx pd1 pd6 pe4 pg1 u2tx pb5 pb6 pc5 pd7 pf4 c0o five pc5 pc7 pe6 pf5 ph2 c1o pb5 pd0 pd2 pe1 ph0 ccp6 pb6 pd1 pd3 pe3 ph1 ccp7 pb6 pf7 pg4 pg5 pg6 fault1 pa7 pc4 pc7 pd5 pe2 pf7 ccp4 six pb2 pb4 pb6 pd0 pd7 pg5 idx0 pa6 pd0 pf0 pg0 pg2 pj0 pwm0 pa7 pd1 pf1 pg1 pg3 pj1 pwm1 pc6 pc7 pe3 pf0 pf7 ph3 phb0 pa0 pb0 pb4 pc6 pd0 pd2 u1rx pa1 pb1 pb5 pc7 pd1 pd3 u1tx 929 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-6. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments pb5 pb6 pc4 pd2 pe5 pg5 pg7 ccp5 seven pa6 pb1 pb6 pc4 pc5 pd7 pe3 pf6 ccp1 eight pa2 pa6 pe0 pe6 pf2 pg0 ph0 ph6 pwm4 pa3 pa7 pe1 pe7 pf3 pg1 ph1 ph7 pwm5 pb0 pb2 pb5 pc6 pc7 pd3 pd4 pf4 pj2 ccp0 nine pb1 pb5 pc4 pd1 pd5 pe1 pe2 pe4 pf5 ccp2 pa7 pb2 pc5 pc6 pd4 pe0 pe4 pf1 pg4 ccp3 pb3 pd6 pe1 pe4 pf4 pg2 pg3 ph3 pj2 fault0 21.2 108-pin bga package pin tables table 21-7. signals by pin number description buffer type a pin type pin name pin number gpio port e bit 6. ttl i/o pe6 a1 analog-to-digital converter input 1. analog i ain1 analog comparator 1 output. ttl o c1o pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 1 clear to send modem status input signal. ttl i u1cts gpio port d bit 7. ttl i/o pd7 a2 analog-to-digital converter input 4. analog i ain4 analog comparator 0 output. ttl o c0o capture/compare/pwm 1. ttl i/o ccp1 i 2 s module 0 transmit word select. ttl i/o i2s0txws qei module 0 index. ttl i idx0 uart module 1 data terminal ready modem status input signal. ttl o u1dtr gpio port d bit 6. ttl i/o pd6 a3 analog-to-digital converter input 5. analog i ain5 pwm fault 0. ttl i fault0 i 2 s module 0 transmit clock. ttl i/o i2s0txsck uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port e bit 2. ttl i/o pe2 a4 analog-to-digital converter input 9. analog i ain9 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 qei module 0 phase a. ttl i pha0 qei module 1 phase b. ttl i phb1 ssi module 1 receive. ttl i ssi1rx the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - gnda a5 march 20, 2011 930 texas instruments-advance information signal tables table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port b bit 4. ttl i/o pb4 a6 analog-to-digital converter input 10. analog i ain10 analog comparator 0 negative input. analog i c0- qei module 0 index. ttl i idx0 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx gpio port b bit 6. ttl i/o pb6 a7 analog comparator 0 positive input. analog i c0+ analog comparator 0 output. ttl o c0o capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 7. ttl i/o ccp7 pwm fault 1. ttl i fault1 i 2 s module 0 transmit clock. ttl i/o i2s0txsck qei module 0 index. ttl i idx0 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 1023. the vrefa input is limited to the range specified in table 23-29 on page 981. analog i vrefa gpio port b bit 7. ttl i/o pb7 a8 non-maskable interrupt. ttl i nmi gpio port c bit 0. ttl i/o pc0 a9 jtag/swd clk. ttl i swclk jtag/swd clk. ttl i tck gpio port c bit 3. ttl i/o pc3 a10 jtag tdo and swo. ttl o swo jtag tdo and swo. ttl o tdo gpio port b bit 2. ttl i/o pb2 a11 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 i 2 c module 0 clock. od i/o i2c0scl qei module 0 index. ttl i idx0 gpio port e bit 1. ttl i/o pe1 a12 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 6. ttl i/o ccp6 pwm fault 0. ttl i fault0 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 frame. ttl i/o ssi1fss 931 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port e bit 7. ttl i/o pe7 b1 analog-to-digital converter input 0. analog i ain0 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 1 data carrier detect modem status input signal. ttl i u1dcd gpio port e bit 4. ttl i/o pe4 b2 analog-to-digital converter input 3. analog i ain3 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 3. ttl i/o ccp3 pwm fault 0. ttl i fault0 i 2 s module 0 transmit word select. ttl i/o i2s0txws uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port e bit 5. ttl i/o pe5 b3 analog-to-digital converter input 2. analog i ain2 capture/compare/pwm 5. ttl i/o ccp5 i 2 s module 0 transmit data. ttl i/o i2s0txsd gpio port e bit 3. ttl i/o pe3 b4 analog-to-digital converter input 8. analog i ain8 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 7. ttl i/o ccp7 qei module 1 phase a. ttl i pha1 qei module 0 phase b. ttl i phb0 ssi module 1 transmit. ttl o ssi1tx gpio port d bit 4. ttl i/o pd4 b5 analog-to-digital converter input 7. analog i ain7 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 i 2 s module 0 receive data. ttl i/o i2s0rxsd uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port j bit 1. ttl i/o pj1 b6 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 gpio port b bit 5. ttl i/o pb5 b7 analog-to-digital converter input 11. analog i ain11 analog comparator 0 output. ttl o c0o analog comparator 1 negative input. analog i c1- capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 6. ttl i/o ccp6 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx march 20, 2011 932 texas instruments-advance information signal tables table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port c bit 2. ttl i/o pc2 b8 jtag tdi. ttl i tdi gpio port c bit 1. ttl i/o pc1 b9 jtag tms and swdio. ttl i/o swdio jtag tms and swdio. ttl i tms gpio port h bit 4. ttl i/o ph4 b10 ssi module 1 clock. ttl i/o ssi1clk gpio port e bit 0. ttl i/o pe0 b11 capture/compare/pwm 3. ttl i/o ccp3 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 clock. ttl i/o ssi1clk no connect. leave the pin electrically unconnected/isolated. - - nc b12 no connect. leave the pin electrically unconnected/isolated. - - nc c1 no connect. leave the pin electrically unconnected/isolated. - - nc c2 positive supply for most of the logic function, including the processor core and most peripherals. power - vddc c3 ground reference for logic and i/o pins. power - gnd c4 ground reference for logic and i/o pins. power - gnd c5 gpio port d bit 5. ttl i/o pd5 c6 analog-to-digital converter input 6. analog i ain6 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be connected to 3.3 v, regardless of system implementation. power - vdda c7 gpio port h bit 1. ttl i/o ph1 c8 capture/compare/pwm 7. ttl i/o ccp7 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 gpio port h bit 0. ttl i/o ph0 c9 capture/compare/pwm 6. ttl i/o ccp6 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 gpio port g bit 7. ttl i/o pg7 c10 capture/compare/pwm 5. ttl i/o ccp5 qei module 1 phase b. ttl i phb1 no connect. leave the pin electrically unconnected/isolated. - - nc c11 no connect. leave the pin electrically unconnected/isolated. - - nc c12 933 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number no connect. leave the pin electrically unconnected/isolated. - - nc d1 no connect. leave the pin electrically unconnected/isolated. - - nc d2 positive supply for most of the logic function, including the processor core and most peripherals. power - vddc d3 gpio port h bit 3. ttl i/o ph3 d10 pwm fault 0. ttl i fault0 qei module 0 phase b. ttl i phb0 gpio port h bit 2. ttl i/o ph2 d11 analog comparator 1 output. ttl o c1o pwm fault 3. ttl i fault3 qei module 1 index. ttl i idx1 gpio port b bit 1. ttl i/o pb1 d12 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 2. ttl i/o ccp2 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx no connect. leave the pin electrically unconnected/isolated. - - nc e1 no connect. leave the pin electrically unconnected/isolated. - - nc e2 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - ldo e3 positive supply for i/o and some logic. power - vdd e10 gpio port b bit 3. ttl i/o pb3 e11 pwm fault 0. ttl i fault0 pwm fault 3. ttl i fault3 i 2 c module 0 data. od i/o i2c0sda gpio port b bit 0. ttl i/o pb0 e12 capture/compare/pwm 0. ttl i/o ccp0 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx no connect. leave the pin electrically unconnected/isolated. - - nc f1 no connect. leave the pin electrically unconnected/isolated. - - nc f2 gpio port j bit 0. ttl i/o pj0 f3 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 gpio port h bit 5. ttl i/o ph5 f10 pwm fault 2. ttl i fault2 ssi module 1 frame. ttl i/o ssi1fss ground reference for logic and i/o pins. power - gnd f11 march 20, 2011 934 texas instruments-advance information signal tables table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number ground reference for logic and i/o pins. power - gnd f12 gpio port d bit 0. ttl i/o pd0 g1 analog-to-digital converter input 15. analog i ain15 capture/compare/pwm 6. ttl i/o ccp6 i 2 s module 0 receive clock. ttl i/o i2s0rxsck qei module 0 index. ttl i idx0 pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 uart module 1 clear to send modem status input signal. ttl i u1cts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx gpio port d bit 1. ttl i/o pd1 g2 analog-to-digital converter input 14. analog i ain14 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 7. ttl i/o ccp7 i 2 s module 0 receive word select. ttl i/o i2s0rxws pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 qei module 0 phase a. ttl i pha0 qei module 1 phase b. ttl i phb1 uart module 1 data carrier detect modem status input signal. ttl i u1dcd uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port h bit 6. ttl i/o ph6 g3 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 receive. ttl i ssi1rx positive supply for i/o and some logic. power - vdd g10 positive supply for i/o and some logic. power - vdd g11 positive supply for i/o and some logic. power - vdd g12 gpio port d bit 3. ttl i/o pd3 h1 analog-to-digital converter input 12. analog i ain12 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 7. ttl i/o ccp7 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx 935 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port d bit 2. ttl i/o pd2 h2 analog-to-digital converter input 13. analog i ain13 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 6. ttl i/o ccp6 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port h bit 7. ttl i/o ph7 h3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 transmit. ttl o ssi1tx positive supply for i/o and some logic. power - vdd h10 system reset input. ttl i rst h11 gpio port f bit 1. ttl i/o pf1 h12 capture/compare/pwm 3. ttl i/o ccp3 i 2 s module 0 transmit master clock. ttl i/o i2s0txmclk qei module 1 index. ttl i idx1 pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 uart module 1 request to send modem output control line. ttl o u1rts gpio port g bit 2. ttl i/o pg2 j1 pwm fault 0. ttl i fault0 i 2 s module 0 receive data. ttl i/o i2s0rxsd qei module 1 index. ttl i idx1 pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 gpio port g bit 3. ttl i/o pg3 j2 pwm fault 0. ttl i fault0 pwm fault 2. ttl i fault2 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 ground reference for logic and i/o pins. power - gnd j3 ground reference for logic and i/o pins. power - gnd j10 gpio port f bit 2. ttl i/o pf2 j11 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 clock. ttl i/o ssi1clk gpio port f bit 3. ttl i/o pf3 j12 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 frame. ttl i/o ssi1fss march 20, 2011 936 texas instruments-advance information signal tables table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port g bit 0. ttl i/o pg0 k1 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx gpio port g bit 1. ttl i/o pg1 k2 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port g bit 4. ttl i/o pg4 k3 capture/compare/pwm 3. ttl i/o ccp3 pwm fault 1. ttl i fault1 uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port f bit 7. ttl i/o pf7 k4 capture/compare/pwm 4. ttl i/o ccp4 pwm fault 1. ttl i fault1 qei module 0 phase b. ttl i phb0 ground reference for logic and i/o pins. power - gnd k5 gpio port j bit 2. ttl i/o pj2 k6 capture/compare/pwm 0. ttl i/o ccp0 pwm fault 0. ttl i fault0 positive supply for i/o and some logic. power - vdd k7 positive supply for i/o and some logic. power - vdd k8 positive supply for i/o and some logic. power - vdd k9 ground reference for logic and i/o pins. power - gnd k10 hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.194304-mhz crystal or a 32.768-khz oscillator for the hibernation module rtc. see the clksel bit in the hibctl register. analog i xosc0 k11 hibernation module oscillator crystal output. leave unconnected when using a single-ended clock source. analog o xosc1 k12 gpio port c bit 4. ttl i/o pc4 l1 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 capture/compare/pwm 5. ttl i/o ccp5 qei module 0 phase a. ttl i pha0 937 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port c bit 7. ttl i/o pc7 l2 analog comparator 1 output. ttl o c1o capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 4. ttl i/o ccp4 qei module 0 phase b. ttl i phb0 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port a bit 0. ttl i/o pa0 l3 i 2 c module 1 clock. od i/o i2c1scl uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i u0rx uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port a bit 3. ttl i/o pa3 l4 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 0 frame. ttl i/o ssi0fss gpio port a bit 4. ttl i/o pa4 l5 i 2 s module 0 transmit clock. ttl i/o i2s0txsck ssi module 0 receive. ttl i ssi0rx gpio port a bit 6. ttl i/o pa6 l6 capture/compare/pwm 1. ttl i/o ccp1 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 1 clear to send modem status input signal. ttl i u1cts gpio port g bit 6. ttl i/o pg6 l7 pwm fault 1. ttl i fault1 i 2 s module 0 receive word select. ttl i/o i2s0rxws qei module 1 phase a. ttl i pha1 uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port f bit 5. ttl i/o pf5 l8 analog comparator 1 output. ttl o c1o capture/compare/pwm 2. ttl i/o ccp2 ssi module 1 transmit. ttl o ssi1tx gpio port f bit 4. ttl i/o pf4 l9 analog comparator 0 output. ttl o c0o capture/compare/pwm 0. ttl i/o ccp0 pwm fault 0. ttl i fault0 ssi module 1 receive. ttl i ssi1rx ground reference for logic and i/o pins. power - gnd l10 main oscillator crystal input or an external clock reference input. analog i osc0 l11 march 20, 2011 938 texas instruments-advance information signal tables table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply. power - vbat l12 gpio port c bit 5. ttl i/o pc5 m1 analog comparator 0 output. ttl o c0o analog comparator 1 positive input. analog i c1+ analog comparator 1 output. ttl o c1o capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 3. ttl i/o ccp3 pwm fault 2. ttl i fault2 gpio port c bit 6. ttl i/o pc6 m2 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 qei module 0 phase b. ttl i phb0 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port a bit 1. ttl i/o pa1 m3 i 2 c module 1 data. od i/o i2c1sda uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o u0tx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port a bit 2. ttl i/o pa2 m4 i 2 s module 0 receive data. ttl i/o i2s0rxsd pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 0 clock. ttl i/o ssi0clk gpio port a bit 5. ttl i/o pa5 m5 i 2 s module 0 transmit word select. ttl i/o i2s0txws ssi module 0 transmit. ttl o ssi0tx gpio port a bit 7. ttl i/o pa7 m6 capture/compare/pwm 3. ttl i/o ccp3 capture/compare/pwm 4. ttl i/o ccp4 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 1 data carrier detect modem status input signal. ttl i u1dcd gpio port g bit 5. ttl i/o pg5 m7 capture/compare/pwm 5. ttl i/o ccp5 pwm fault 1. ttl i fault1 i 2 s module 0 receive clock. ttl i/o i2s0rxsck qei module 0 index. ttl i idx0 uart module 1 data terminal ready modem status input signal. ttl o u1dtr 939 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port f bit 6. ttl i/o pf6 m8 capture/compare/pwm 1. ttl i/o ccp1 i 2 s module 0 transmit master clock. ttl i/o i2s0txmclk qei module 0 phase a. ttl i pha0 uart module 1 request to send modem output control line. ttl o u1rts gpio port f bit 0. ttl i/o pf0 m9 i 2 s module 0 transmit data. ttl i/o i2s0txsd pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 qei module 0 phase b. ttl i phb0 uart module 1 data set ready modem output control line. ttl i u1dsr an external input that brings the processor out of hibernate mode when asserted. ttl i wake m10 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o osc1 m11 an output that indicates the processor is in hibernate mode. od o hib m12 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 21-8. signals by signal name description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 0. analog i pe7 b1 ain0 analog-to-digital converter input 1. analog i pe6 a1 ain1 analog-to-digital converter input 2. analog i pe5 b3 ain2 analog-to-digital converter input 3. analog i pe4 b2 ain3 analog-to-digital converter input 4. analog i pd7 a2 ain4 analog-to-digital converter input 5. analog i pd6 a3 ain5 analog-to-digital converter input 6. analog i pd5 c6 ain6 analog-to-digital converter input 7. analog i pd4 b5 ain7 analog-to-digital converter input 8. analog i pe3 b4 ain8 analog-to-digital converter input 9. analog i pe2 a4 ain9 analog-to-digital converter input 10. analog i pb4 a6 ain10 analog-to-digital converter input 11. analog i pb5 b7 ain11 analog-to-digital converter input 12. analog i pd3 h1 ain12 analog-to-digital converter input 13. analog i pd2 h2 ain13 analog-to-digital converter input 14. analog i pd1 g2 ain14 analog-to-digital converter input 15. analog i pd0 g1 ain15 analog comparator 0 positive input. analog i pb6 a7 c0+ analog comparator 0 negative input. analog i pb4 a6 c0- analog comparator 0 output. ttl o pc5 (3) pf4 (2) pb6 (3) pb5 (1) pd7 (2) m1 l9 a7 b7 a2 c0o march 20, 2011 940 texas instruments-advance information signal tables table 21-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name analog comparator 1 positive input. analog i pc5 m1 c1+ analog comparator 1 negative input. analog i pb5 b7 c1- analog comparator 1 output. ttl o pe6 (2) pc7 (7) pc5 (2) pf5 (2) ph2 (2) a1 l2 m1 l8 d11 c1o capture/compare/pwm 0. ttl i/o pd3 (4) pc7 (4) pc6 (6) pj2 (9) pf4 (1) pb0 (1) pb2 (5) pb5 (4) pd4 (1) h1 l2 m2 k6 l9 e12 a11 b7 b5 ccp0 capture/compare/pwm 1. ttl i/o pc5 (1) pc4 (9) pa6 (2) pf6 (1) pb1 (4) pb6 (1) pe3 (1) pd7 (3) m1 l1 l6 m8 d12 a7 b4 a2 ccp1 capture/compare/pwm 2. ttl i/o pe4 (6) pd1 (10) pc4 (5) pf5 (1) pb1 (1) pe1 (4) pb5 (6) pe2 (5) pd5 (1) b2 g2 l1 l8 d12 a12 b7 a4 c6 ccp2 capture/compare/pwm 3. ttl i/o pe4 (1) pc6 (1) pc5 (5) pa7 (7) pg4 (1) pf1 (10) pb2 (4) pe0 (3) pd4 (2) b2 m2 m1 m6 k3 h12 a11 b11 b5 ccp3 capture/compare/pwm 4. ttl i/o pc7 (1) pc4 (6) pa7 (2) pf7 (1) pe2 (1) pd5 (2) l2 l1 m6 k4 a4 c6 ccp4 capture/compare/pwm 5. ttl i/o pe5 (1) pd2 (4) pc4 (1) pg7 (8) pg5 (1) pb6 (6) pb5 (2) b3 h2 l1 c10 m7 a7 b7 ccp5 941 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 6. ttl i/o pd0 (6) pd2 (2) pe1 (5) ph0 (1) pb5 (3) g1 h2 a12 c9 b7 ccp6 capture/compare/pwm 7. ttl i/o pd1 (6) pd3 (2) ph1 (1) pb6 (2) pe3 (5) g2 h1 c8 a7 b4 ccp7 pwm fault 0. ttl i pe4 (4) pg3 (8) pg2 (4) pj2 (10) pf4 (4) pb3 (2) pe1 (3) ph3 (2) pd6 (1) b2 j2 j1 k6 l9 e11 a12 d10 a3 fault0 pwm fault 1. ttl i pg6 (8) pg5 (5) pg4 (4) pf7 (9) pb6 (4) l7 m7 k3 k4 a7 fault1 pwm fault 2. ttl i pg3 (4) pc5 (4) ph5 (10) j2 m1 f10 fault2 pwm fault 3. ttl i pb3 (4) ph2 (4) e11 d11 fault3 ground reference for logic and i/o pins. power - fixed c4 c5 j3 k5 l10 k10 j10 f11 f12 gnd the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - fixed a5 gnda an output that indicates the processor is in hibernate mode. od o fixed m12 hib i 2 c module 0 clock. od i/o pb2 (1) a11 i2c0scl i 2 c module 0 data. od i/o pb3 (1) e11 i2c0sda i 2 c module 1 clock. od i/o pj0 (11) pg0 (3) pa0 (8) pa6 (1) f3 k1 l3 l6 i2c1scl march 20, 2011 942 texas instruments-advance information signal tables table 21-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 c module 1 data. od i/o pg1 (3) pa1 (8) pa7 (1) pj1 (11) k2 m3 m6 b6 i2c1sda i 2 s module 0 receive master clock. ttl i/o pg3 (9) pa3 (9) pd5 (8) j2 l4 c6 i2s0rxmclk i 2 s module 0 receive clock. ttl i/o pd0 (8) pg5 (9) g1 m7 i2s0rxsck i 2 s module 0 receive data. ttl i/o pg2 (9) pa2 (9) pd4 (8) j1 m4 b5 i2s0rxsd i 2 s module 0 receive word select. ttl i/o pd1 (8) pg6 (9) g2 l7 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o pf6 (9) pf1 (8) m8 h12 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o pa4 (9) pb6 (9) pd6 (8) l5 a7 a3 i2s0txsck i 2 s module 0 transmit data. ttl i/o pe5 (9) pf0 (8) b3 m9 i2s0txsd i 2 s module 0 transmit word select. ttl i/o pe4 (9) pa5 (9) pd7 (8) b2 m5 a2 i2s0txws qei module 0 index. ttl i pd0 (3) pg5 (4) pb2 (2) pb6 (5) pb4 (6) pd7 (1) g1 m7 a11 a7 a6 a2 idx0 qei module 1 index. ttl i pg2 (8) pf1 (2) ph2 (1) j1 h12 d11 idx1 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - fixed e3 ldo no connect. leave the pin electrically unconnected/isolated. - - fixed c11 c12 b12 c1 c2 d2 d1 e1 e2 f1 f2 nc non-maskable interrupt. ttl i pb7 (4) a8 nmi 943 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name main oscillator crystal input or an external clock reference input. analog i fixed l11 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed m11 osc1 gpio port a bit 0. ttl i/o - l3 pa0 gpio port a bit 1. ttl i/o - m3 pa1 gpio port a bit 2. ttl i/o - m4 pa2 gpio port a bit 3. ttl i/o - l4 pa3 gpio port a bit 4. ttl i/o - l5 pa4 gpio port a bit 5. ttl i/o - m5 pa5 gpio port a bit 6. ttl i/o - l6 pa6 gpio port a bit 7. ttl i/o - m6 pa7 gpio port b bit 0. ttl i/o - e12 pb0 gpio port b bit 1. ttl i/o - d12 pb1 gpio port b bit 2. ttl i/o - a11 pb2 gpio port b bit 3. ttl i/o - e11 pb3 gpio port b bit 4. ttl i/o - a6 pb4 gpio port b bit 5. ttl i/o - b7 pb5 gpio port b bit 6. ttl i/o - a7 pb6 gpio port b bit 7. ttl i/o - a8 pb7 gpio port c bit 0. ttl i/o - a9 pc0 gpio port c bit 1. ttl i/o - b9 pc1 gpio port c bit 2. ttl i/o - b8 pc2 gpio port c bit 3. ttl i/o - a10 pc3 gpio port c bit 4. ttl i/o - l1 pc4 gpio port c bit 5. ttl i/o - m1 pc5 gpio port c bit 6. ttl i/o - m2 pc6 gpio port c bit 7. ttl i/o - l2 pc7 gpio port d bit 0. ttl i/o - g1 pd0 gpio port d bit 1. ttl i/o - g2 pd1 gpio port d bit 2. ttl i/o - h2 pd2 gpio port d bit 3. ttl i/o - h1 pd3 gpio port d bit 4. ttl i/o - b5 pd4 gpio port d bit 5. ttl i/o - c6 pd5 gpio port d bit 6. ttl i/o - a3 pd6 gpio port d bit 7. ttl i/o - a2 pd7 gpio port e bit 0. ttl i/o - b11 pe0 gpio port e bit 1. ttl i/o - a12 pe1 gpio port e bit 2. ttl i/o - a4 pe2 gpio port e bit 3. ttl i/o - b4 pe3 gpio port e bit 4. ttl i/o - b2 pe4 march 20, 2011 944 texas instruments-advance information signal tables table 21-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name gpio port e bit 5. ttl i/o - b3 pe5 gpio port e bit 6. ttl i/o - a1 pe6 gpio port e bit 7. ttl i/o - b1 pe7 gpio port f bit 0. ttl i/o - m9 pf0 gpio port f bit 1. ttl i/o - h12 pf1 gpio port f bit 2. ttl i/o - j11 pf2 gpio port f bit 3. ttl i/o - j12 pf3 gpio port f bit 4. ttl i/o - l9 pf4 gpio port f bit 5. ttl i/o - l8 pf5 gpio port f bit 6. ttl i/o - m8 pf6 gpio port f bit 7. ttl i/o - k4 pf7 gpio port g bit 0. ttl i/o - k1 pg0 gpio port g bit 1. ttl i/o - k2 pg1 gpio port g bit 2. ttl i/o - j1 pg2 gpio port g bit 3. ttl i/o - j2 pg3 gpio port g bit 4. ttl i/o - k3 pg4 gpio port g bit 5. ttl i/o - m7 pg5 gpio port g bit 6. ttl i/o - l7 pg6 gpio port g bit 7. ttl i/o - c10 pg7 gpio port h bit 0. ttl i/o - c9 ph0 gpio port h bit 1. ttl i/o - c8 ph1 gpio port h bit 2. ttl i/o - d11 ph2 gpio port h bit 3. ttl i/o - d10 ph3 gpio port h bit 4. ttl i/o - b10 ph4 gpio port h bit 5. ttl i/o - f10 ph5 gpio port h bit 6. ttl i/o - g3 ph6 gpio port h bit 7. ttl i/o - h3 ph7 qei module 0 phase a. ttl i pd1 (3) pc4 (2) pf6 (4) pe2 (4) g2 l1 m8 a4 pha0 qei module 1 phase a. ttl i pg6 (1) pe3 (3) l7 b4 pha1 qei module 0 phase b. ttl i pc7 (2) pc6 (2) pf7 (4) pf0 (2) ph3 (1) pe3 (4) l2 m2 k4 m9 d10 b4 phb0 qei module 1 phase b. ttl i pd1 (11) pg7 (1) pe2 (3) g2 c10 a4 phb1 gpio port j bit 0. ttl i/o - f3 pj0 gpio port j bit 1. ttl i/o - b6 pj1 945 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name gpio port j bit 2. ttl i/o - k6 pj2 pwm 0. this signal is controlled by pwm generator 0. ttl o pd0 (1) pj0 (10) pg2 (1) pg0 (2) pa6 (4) pf0 (3) g1 f3 j1 k1 l6 m9 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o pd1 (1) pg3 (1) pg1 (2) pa7 (4) pf1 (3) pj1 (10) g2 j2 k2 m6 h12 b6 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o pd2 (3) pf2 (4) pb0 (2) ph0 (2) h2 j11 e12 c9 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o pd3 (3) pf3 (4) pb1 (2) ph1 (2) h1 j12 d12 c8 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o pe6 (1) pg0 (4) pa2 (4) pa6 (5) pf2 (2) ph6 (10) pe0 (1) ph0 (9) a1 k1 m4 l6 j11 g3 b11 c9 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o pe7 (1) ph7 (10) pg1 (4) pa3 (4) pa7 (5) pf3 (2) pe1 (1) ph1 (9) b1 h3 k2 l4 m6 j12 a12 c8 pwm5 system reset input. ttl i fixed h11 rst ssi module 0 clock. ttl i/o pa2 (1) m4 ssi0clk ssi module 0 frame. ttl i/o pa3 (1) l4 ssi0fss ssi module 0 receive. ttl i pa4 (1) l5 ssi0rx ssi module 0 transmit. ttl o pa5 (1) m5 ssi0tx ssi module 1 clock. ttl i/o pf2 (9) pe0 (2) ph4 (11) j11 b11 b10 ssi1clk ssi module 1 frame. ttl i/o pf3 (9) ph5 (11) pe1 (2) j12 f10 a12 ssi1fss ssi module 1 receive. ttl i pf4 (9) ph6 (11) pe2 (2) l9 g3 a4 ssi1rx march 20, 2011 946 texas instruments-advance information signal tables table 21-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name ssi module 1 transmit. ttl o ph7 (11) pf5 (9) pe3 (2) h3 l8 b4 ssi1tx jtag/swd clk. ttl i pc0 (3) a9 swclk jtag tms and swdio. ttl i/o pc1 (3) b9 swdio jtag tdo and swo. ttl o pc3 (3) a10 swo jtag/swd clk. ttl i pc0 (3) a9 tck jtag tdi. ttl i pc2 (3) b8 tdi jtag tdo and swo. ttl o pc3 (3) a10 tdo jtag tms and swdio. ttl i pc1 (3) b9 tms uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i pa0 (1) l3 u0rx uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o pa1 (1) m3 u0tx uart module 1 clear to send modem status input signal. ttl i pe6 (9) pd0 (9) pa6 (9) a1 g1 l6 u1cts uart module 1 data carrier detect modem status input signal. ttl i pe7 (9) pd1 (9) pa7 (9) b1 g2 m6 u1dcd uart module 1 data set ready modem output control line. ttl i pf0 (9) m9 u1dsr uart module 1 data terminal ready modem status input signal. ttl o pg5 (10) pd7 (9) m7 a2 u1dtr uart module 1 ring indicator modem status input signal. ttl i pg6 (10) pg4 (10) pd4 (9) l7 k3 b5 u1ri uart module 1 request to send modem output control line. ttl o pf6 (10) pf1 (9) m8 h12 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (5) pd2 (1) pc6 (5) pa0 (9) pb0 (5) pb4 (7) g1 h2 m2 l3 e12 a6 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o pd1 (5) pd3 (1) pc7 (5) pa1 (9) pb1 (5) pb5 (7) g2 h1 l2 m3 d12 b7 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (4) pg0 (1) pb4 (4) pd5 (9) g1 k1 a6 c6 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o pe4 (5) pd1 (4) pg1 (1) pd6 (9) b2 g2 k2 a3 u2tx 947 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply. power - fixed l12 vbat positive supply for i/o and some logic. power - fixed k7 g12 k8 k9 h10 g10 e10 g11 vdd the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be connected to 3.3 v, regardless of system implementation. power - fixed c7 vdda positive supply for most of the logic function, including the processor core and most peripherals. power - fixed d3 c3 vddc this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 1023. the vrefa input is limited to the range specified in table 23-29 on page 981. analog i pb6 a7 vrefa an external input that brings the processor out of hibernate mode when asserted. ttl i fixed m10 wake hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.194304-mhz crystal or a 32.768-khz oscillator for the hibernation module rtc. see the clksel bit in the hibctl register. analog i fixed k11 xosc0 hibernation module oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed k12 xosc1 a. the ttl designation indicates the pin has ttl-compatible voltage levels. march 20, 2011 948 texas instruments-advance information signal tables table 21-9. signals by function, except for gpio description buffer type a pin type pin number pin name function analog-to-digital converter input 0. analog i b1 ain0 adc analog-to-digital converter input 1. analog i a1 ain1 analog-to-digital converter input 2. analog i b3 ain2 analog-to-digital converter input 3. analog i b2 ain3 analog-to-digital converter input 4. analog i a2 ain4 analog-to-digital converter input 5. analog i a3 ain5 analog-to-digital converter input 6. analog i c6 ain6 analog-to-digital converter input 7. analog i b5 ain7 analog-to-digital converter input 8. analog i b4 ain8 analog-to-digital converter input 9. analog i a4 ain9 analog-to-digital converter input 10. analog i a6 ain10 analog-to-digital converter input 11. analog i b7 ain11 analog-to-digital converter input 12. analog i h1 ain12 analog-to-digital converter input 13. analog i h2 ain13 analog-to-digital converter input 14. analog i g2 ain14 analog-to-digital converter input 15. analog i g1 ain15 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 1023. the vrefa input is limited to the range specified in table 23-29 on page 981. analog i a7 vrefa analog comparator 0 positive input. analog i a7 c0+ analog comparators analog comparator 0 negative input. analog i a6 c0- analog comparator 0 output. ttl o m1 l9 a7 b7 a2 c0o analog comparator 1 positive input. analog i m1 c1+ analog comparator 1 negative input. analog i b7 c1- analog comparator 1 output. ttl o a1 l2 m1 l8 d11 c1o 949 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function capture/compare/pwm 0. ttl i/o h1 l2 m2 k6 l9 e12 a11 b7 b5 ccp0 general-purpose timers capture/compare/pwm 1. ttl i/o m1 l1 l6 m8 d12 a7 b4 a2 ccp1 capture/compare/pwm 2. ttl i/o b2 g2 l1 l8 d12 a12 b7 a4 c6 ccp2 capture/compare/pwm 3. ttl i/o b2 m2 m1 m6 k3 h12 a11 b11 b5 ccp3 capture/compare/pwm 4. ttl i/o l2 l1 m6 k4 a4 c6 ccp4 capture/compare/pwm 5. ttl i/o b3 h2 l1 c10 m7 a7 b7 ccp5 capture/compare/pwm 6. ttl i/o g1 h2 a12 c9 b7 ccp6 capture/compare/pwm 7. ttl i/o ccp7 march 20, 2011 950 texas instruments-advance information signal tables table 21-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function g2 h1 c8 a7 b4 an output that indicates the processor is in hibernate mode. od o m12 hib hibernate power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply. power - l12 vbat an external input that brings the processor out of hibernate mode when asserted. ttl i m10 wake hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.194304-mhz crystal or a 32.768-khz oscillator for the hibernation module rtc. see the clksel bit in the hibctl register. analog i k11 xosc0 hibernation module oscillator crystal output. leave unconnected when using a single-ended clock source. analog o k12 xosc1 i 2 c module 0 clock. od i/o a11 i2c0scl i2c i 2 c module 0 data. od i/o e11 i2c0sda i 2 c module 1 clock. od i/o f3 k1 l3 l6 i2c1scl i 2 c module 1 data. od i/o k2 m3 m6 b6 i2c1sda i 2 s module 0 receive master clock. ttl i/o j2 l4 c6 i2s0rxmclk i2s i 2 s module 0 receive clock. ttl i/o g1 m7 i2s0rxsck i 2 s module 0 receive data. ttl i/o j1 m4 b5 i2s0rxsd i 2 s module 0 receive word select. ttl i/o g2 l7 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o m8 h12 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o l5 a7 a3 i2s0txsck i 2 s module 0 transmit data. ttl i/o b3 m9 i2s0txsd i 2 s module 0 transmit word select. ttl i/o b2 m5 a2 i2s0txws 951 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function jtag/swd clk. ttl i a9 swclk jtag/swd/swo jtag tms and swdio. ttl i/o b9 swdio jtag tdo and swo. ttl o a10 swo jtag/swd clk. ttl i a9 tck jtag tdi. ttl i b8 tdi jtag tdo and swo. ttl o a10 tdo jtag tms and swdio. ttl i b9 tms march 20, 2011 952 texas instruments-advance information signal tables table 21-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function pwm fault 0. ttl i b2 j2 j1 k6 l9 e11 a12 d10 a3 fault0 pwm pwm fault 1. ttl i l7 m7 k3 k4 a7 fault1 pwm fault 2. ttl i j2 m1 f10 fault2 pwm fault 3. ttl i e11 d11 fault3 pwm 0. this signal is controlled by pwm generator 0. ttl o g1 f3 j1 k1 l6 m9 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o g2 j2 k2 m6 h12 b6 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o h2 j11 e12 c9 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o h1 j12 d12 c8 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o a1 k1 m4 l6 j11 g3 b11 c9 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o b1 h3 k2 l4 m6 j12 a12 c8 pwm5 953 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function ground reference for logic and i/o pins. power - c4 c5 j3 k5 l10 k10 j10 f11 f12 gnd power the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - a5 gnda low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - e3 ldo positive supply for i/o and some logic. power - k7 g12 k8 k9 h10 g10 e10 g11 vdd the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be connected to 3.3 v, regardless of system implementation. power - c7 vdda positive supply for most of the logic function, including the processor core and most peripherals. power - d3 c3 vddc march 20, 2011 954 texas instruments-advance information signal tables table 21-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function qei module 0 index. ttl i g1 m7 a11 a7 a6 a2 idx0 qei qei module 1 index. ttl i j1 h12 d11 idx1 qei module 0 phase a. ttl i g2 l1 m8 a4 pha0 qei module 1 phase a. ttl i l7 b4 pha1 qei module 0 phase b. ttl i l2 m2 k4 m9 d10 b4 phb0 qei module 1 phase b. ttl i g2 c10 a4 phb1 ssi module 0 clock. ttl i/o m4 ssi0clk ssi ssi module 0 frame. ttl i/o l4 ssi0fss ssi module 0 receive. ttl i l5 ssi0rx ssi module 0 transmit. ttl o m5 ssi0tx ssi module 1 clock. ttl i/o j11 b11 b10 ssi1clk ssi module 1 frame. ttl i/o j12 f10 a12 ssi1fss ssi module 1 receive. ttl i l9 g3 a4 ssi1rx ssi module 1 transmit. ttl o h3 l8 b4 ssi1tx non-maskable interrupt. ttl i a8 nmi system control & clocks main oscillator crystal input or an external clock reference input. analog i l11 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o m11 osc1 system reset input. ttl i h11 rst 955 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i l3 u0rx uart uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o m3 u0tx uart module 1 clear to send modem status input signal. ttl i a1 g1 l6 u1cts uart module 1 data carrier detect modem status input signal. ttl i b1 g2 m6 u1dcd uart module 1 data set ready modem output control line. ttl i m9 u1dsr uart module 1 data terminal ready modem status input signal. ttl o m7 a2 u1dtr uart module 1 ring indicator modem status input signal. ttl i l7 k3 b5 u1ri uart module 1 request to send modem output control line. ttl o m8 h12 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i g1 h2 m2 l3 e12 a6 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o g2 h1 l2 m3 d12 b7 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i g1 k1 a6 c6 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o b2 g2 k2 a3 u2tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 21-10. gpio pins and alternate functions digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1rx i2c1scl ------ u0rx -l3 pa0 -- u1tx i2c1sda ------ u0tx -m3 pa1 -- i2s0rxsd ---- pwm4 -- ssi0clk -m4 pa2 -- i2s0rxmclk ---- pwm5 -- ssi0fss -l4 pa3 -- i2s0txsck ------- ssi0rx -l5 pa4 -- i2s0txws ------- ssi0tx -m5 pa5 march 20, 2011 956 texas instruments-advance information signal tables table 21-10. gpio pins and alternate functions (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1cts --- pwm4 pwm0 - ccp1 i2c1scl -l6 pa6 -- u1dcd - ccp3 - pwm5 pwm1 - ccp4 i2c1sda -m6 pa7 ------ u1rx -- pwm2 ccp0 -e12 pb0 ------ u1tx ccp1 - pwm3 ccp2 -d12 pb1 ------ ccp0 ccp3 - idx0 i2c0scl -a11 pb2 ------- fault3 - fault0 i2c0sda -e11 pb3 ---- u1rx idx0 - u2rx --- ain10 c0- a6 pb4 ---- u1tx ccp2 - ccp0 ccp6 ccp5 c0o ain11 c1- b7 pb5 -- i2s0txsck -- ccp5 idx0 fault1 c0o ccp7 ccp1 vrefa c0+ a7 pb6 ------- nmi ----a8 pb7 -------- tck swclk ---a9 pc0 -------- tms swdio ---b9 pc1 -------- tdi ---b8 pc2 -------- tdo swo ---a10 pc3 -- ccp1 -- ccp4 ccp2 -- pha0 ccp5 -l1 pc4 ------ ccp3 fault2 c0o c1o ccp1 c1+ m1 pc5 ----- ccp0 u1rx -- phb0 ccp3 -m2 pc6 ---- c1o - u1tx ccp0 - phb0 ccp4 -l2 pc7 -- u1cts i2s0rxsck - ccp6 u1rx u2rx idx0 - pwm0 ain15 g1 pd0 phb1 ccp2 u1dcd i2s0rxws - ccp7 u1tx u2tx pha0 - pwm1 ain14 g2 pd1 ------- ccp5 pwm2 ccp6 u1rx ain13 h2 pd2 ------- ccp0 pwm3 ccp7 u1tx ain12 h1 pd3 -- u1ri i2s0rxsd ----- ccp3 ccp0 ain7 b5 pd4 -- u2rx i2s0rxmclk ----- ccp4 ccp2 ain6 c6 pd5 -- u2tx i2s0txsck ------ fault0 ain5 a3 pd6 -- u1dtr i2s0txws ---- ccp1 c0o idx0 ain4 a2 pd7 -------- ccp3 ssi1clk pwm4 -b11 pe0 ------ ccp6 ccp2 fault0 ssi1fss pwm5 -a12 pe1 ------ ccp2 pha0 phb1 ssi1rx ccp4 ain9 a4 pe2 ------ ccp7 phb0 pha1 ssi1tx ccp1 ain8 b4 pe3 -- i2s0txws -- ccp2 u2tx fault0 -- ccp3 ain3 b2 pe4 -- i2s0txsd ------- ccp5 ain2 b3 pe5 -- u1cts ------ c1o pwm4 ain1 a1 pe6 -- u1dcd ------- pwm5 ain0 b1 pe7 -- u1dsr i2s0txsd ---- pwm0 phb0 --m9 pf0 - ccp3 u1rts i2s0txmclk ---- pwm1 idx1 --h12 pf1 957 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-10. gpio pins and alternate functions (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- ssi1clk ---- pwm2 - pwm4 --j11 pf2 -- ssi1fss ---- pwm3 - pwm5 --j12 pf3 -- ssi1rx ---- fault0 - c0o ccp0 -l9 pf4 -- ssi1tx ------ c1o ccp2 -l8 pf5 - u1rts i2s0txmclk ---- pha0 -- ccp1 -m8 pf6 -- fault1 ---- phb0 -- ccp4 -k4 pf7 ------- pwm4 i2c1scl pwm0 u2rx -k1 pg0 ------- pwm5 i2c1sda pwm1 u2tx -k2 pg1 -- i2s0rxsd idx1 --- fault0 -- pwm0 -j1 pg2 -- i2s0rxmclk fault0 --- fault2 -- pwm1 -j2 pg3 - u1ri ----- fault1 -- ccp3 -k3 pg4 - u1dtr i2s0rxsck --- fault1 idx0 -- ccp5 -m7 pg5 - u1ri i2s0rxws fault1 ------ pha1 -l7 pg6 --- ccp5 ------ phb1 -c10 pg7 -- pwm4 ------ pwm2 ccp6 -c9 ph0 -- pwm5 ------ pwm3 ccp7 -c8 ph1 ------- fault3 - c1o idx1 -d11 ph2 --------- fault0 phb0 -d10 ph3 ssi1clk -----------b10 ph4 ssi1fss fault2 ----------f10 ph5 ssi1rx pwm4 ----------g3 ph6 ssi1tx pwm5 ----------h3 ph7 i2c1scl pwm0 ----------f3 pj0 i2c1sda pwm1 ----------b6 pj1 - fault0 ccp0 ---------k6 pj2 a. the digital signals that are shaded gray are the power-on default values for the corresponding gpio pin. march 20, 2011 958 texas instruments-advance information signal tables table 21-11. possible pin assignments for alternate functions gpio function alternate function # of possible assignments pe7 ain0 one pe6 ain1 pb4 ain10 pb5 ain11 pd3 ain12 pd2 ain13 pd1 ain14 pd0 ain15 pe5 ain2 pe4 ain3 pd7 ain4 pd6 ain5 pd5 ain6 pd4 ain7 pe3 ain8 pe2 ain9 pb6 c0+ pb4 c0- pc5 c1+ pb5 c1- pb2 i2c0scl pb3 i2c0sda pb7 nmi pa2 ssi0clk pa3 ssi0fss pa4 ssi0rx pa5 ssi0tx pc0 swclk pc1 swdio pc3 swo pc0 tck pc2 tdi pc3 tdo pc1 tms pa0 u0rx pa1 u0tx pf0 u1dsr pb6 vrefa 959 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-11. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments pb3 ph2 fault3 two pd0 pg5 i2s0rxsck pd1 pg6 i2s0rxws pf6 pf1 i2s0txmclk pe5 pf0 i2s0txsd pg6 pe3 pha1 pg5 pd7 u1dtr pf6 pf1 u1rts pg3 pc5 ph5 fault2 three pg3 pa3 pd5 i2s0rxmclk pg2 pa2 pd4 i2s0rxsd pa4 pb6 pd6 i2s0txsck pe4 pa5 pd7 i2s0txws pg2 pf1 ph2 idx1 pd1 pg7 pe2 phb1 pf2 pe0 ph4 ssi1clk pf3 ph5 pe1 ssi1fss pf4 ph6 pe2 ssi1rx ph7 pf5 pe3 ssi1tx pe6 pd0 pa6 u1cts pe7 pd1 pa7 u1dcd pg6 pg4 pd4 u1ri pj0 pg0 pa0 pa6 i2c1scl four pg1 pa1 pa7 pj1 i2c1sda pd2 pf2 pb0 ph0 pwm2 pd3 pf3 pb1 ph1 pwm3 pd1 pc4 pf6 pe2 pha0 pd0 pg0 pb4 pd5 u2rx pe4 pd1 pg1 pd6 u2tx pc5 pf4 pb6 pb5 pd7 c0o five pe6 pc7 pc5 pf5 ph2 c1o pd0 pd2 pe1 ph0 pb5 ccp6 pd1 pd3 ph1 pb6 pe3 ccp7 pg6 pg5 pg4 pf7 pb6 fault1 pc7 pc4 pa7 pf7 pe2 pd5 ccp4 six pd0 pg5 pb2 pb6 pb4 pd7 idx0 pd0 pj0 pg2 pg0 pa6 pf0 pwm0 pd1 pg3 pg1 pa7 pf1 pj1 pwm1 pc7 pc6 pf7 pf0 ph3 pe3 phb0 pd0 pd2 pc6 pa0 pb0 pb4 u1rx pd1 pd3 pc7 pa1 pb1 pb5 u1tx march 20, 2011 960 texas instruments-advance information signal tables table 21-11. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments pe5 pd2 pc4 pg7 pg5 pb6 pb5 ccp5 seven pc5 pc4 pa6 pf6 pb1 pb6 pe3 pd7 ccp1 eight pe6 pg0 pa2 pa6 pf2 ph6 pe0 ph0 pwm4 pe7 ph7 pg1 pa3 pa7 pf3 pe1 ph1 pwm5 pd3 pc7 pc6 pj2 pf4 pb0 pb2 pb5 pd4 ccp0 nine pe4 pd1 pc4 pf5 pb1 pe1 pb5 pe2 pd5 ccp2 pe4 pc6 pc5 pa7 pg4 pf1 pb2 pe0 pd4 ccp3 pe4 pg3 pg2 pj2 pf4 pb3 pe1 ph3 pd6 fault0 21.3 connections for unused signals table 21-12 on page 961 show how to handle signals for functions that are not used in a particular system implementation for devices that are in a 100-pin lqfp package. two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved emc characteristics. if a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the rcgcx register. table 21-12. connections for unused signals (100-pin lqfp) preferred practice acceptable practice pin number signal name function gnd nc - all unused gpios gpio nc nc 51 hib hibernate gnd nc 55 vbat gnd nc 50 wake gnd nc 52 xosc0 nc nc 53 xosc1 nc nc - nc no connects gnd nc 48 osc0 system control nc nc 49 osc1 connect through a capacitor to gnd as close to pin as possible pull up as shown in figure 5-1 on page 184 48 rst table 21-13 on page 961 show how to handle signals for functions that are not used in a particular system implementation for devices that are in a 108-pin bga package. two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved emc characteristics. if a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the rcgcx register. table 21-13. connections for unused signals, 108-pin bga preferred practice acceptable practice pin number signal name function gnd nc - all unused gpios gpio 961 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 21-13. connections for unused signals, 108-pin bga (continued) preferred practice acceptable practice pin number signal name function nc nc m12 hib hibernate gnd nc l12 vbat gnd nc m10 wake gnd nc k11 xosc0 nc nc k12 xosc1 nc nc - nc no connects gnd nc l11 osc0 system control nc nc m11 osc1 connect through a capacitor to gnd as close to pin as possible pull up as shown in figure 5-1 on page 184 h11 rst march 20, 2011 962 texas instruments-advance information signal tables 22 operating characteristics table 22-1. temperature characteristics unit value symbol characteristic c -40 to +85 t a industrial operating temperature range c -65 to +150 t s unpowered storage temperature range table 22-2. thermal characteristics unit value symbol characteristic c/w 32 ja thermal resistance (junction to ambient) a c t a + (p ? ja ) t j junction temperature b a. junction to ambient thermal resistance ja numbers are determined by a package simulator. b. power dissipation is a function of temperature. table 22-3. esd absolute maximum ratings a unit max nom min parameter name kv 2.0 - - v esdhbm kv 1.0 - - v esdcdm v 100 - - v esdmm a. all stellaris parts are esd tested following the jedec standard. 963 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 23 electrical characteristics 23.1 dc characteristics 23.1.1 maximum ratings the maximum ratings are the limits to which the device can be subjected without permanently damaging the device. note: the device is not guaranteed to operate properly at the maximum ratings. table 23-1. maximum ratings unit value parameter name a parameter max min v 4 0 i/o supply voltage (v dd ) v dd v 4 0 analog supply voltage (v dda ) v dda v 4 0 battery supply voltage (v bat ) v bat v 5.5 -0.3 input voltage v in v v dd + 0.3 -0.3 input voltage for a gpio configured as an analog input v v dd + 0.3 -0.3 input voltage for pb0 and pb1 when configured as gpio ma 25 - maximum current per output pins i mv 300 - maximum input voltage on a non-power pin when the microcontroller is unpowered v non a. voltages are measured with respect to gnd. important: this device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either gnd or v dd ). 23.1.2 recommended dc operating conditions for special high-current applications, the gpio output buffers may be used with the following restrictions. with the gpio pins configured as 8-ma output drivers, a total of four gpio outputs may be used to sink current loads up to 18 ma each. at 18-ma sink current loading, the v ol value is specified as 1.2 v. the high-current gpio package pins must be selected such that there are only a maximum of two per side of the physical package or bga pin group with the total number of high-current gpio outputs not exceeding four for the entire package. table 23-2. recommended dc operating conditions unit max nom min parameter name parameter v 3.6 3.3 3.0 i/o supply voltage v dd v 3.6 3.3 3.0 analog supply voltage v dda v 1.32 1.2 1.08 core supply voltage v ddc a v 5.0 - 2.0 high-level input voltage v ih v 3.6 - v dd - 0.5 high-level input voltage - osc0, xosc0 single-ended clock source march 20, 2011 964 texas instruments-advance information electrical characteristics table 23-2. recommended dc operating conditions (continued) unit max nom min parameter name parameter v 1.3 - -0.3 low-level input voltage v il v 0.5 - -0.3 low-level input voltage - osc0, xosc0 single-ended clock source v - - 2.4 high-level output voltage v oh b v 0.4 - - low-level output voltage v ol a high-level source current, v oh =2.4 v i oh ma - - 2.0 2-ma drive ma - - 4.0 4-ma drive ma - - 8.0 8-ma drive low-level sink current, v ol =0.4 v i ol ma - - 2.0 2-ma drive ma - - 4.0 4-ma drive ma - - 8.0 8-ma drive a. v ddc is supplied from the output of the ldo. b. v ol and v oh shift to 1.2 v when using high-current gpios. 23.1.3 on-chip low drop-out (ldo) regulator characteristics table 23-3. ldo regulator characteristics unit max nom min parameter name parameter f 3.0 - 1.0 external filter capacitor size for internal power supply c ldo v 1.32 1.2 1.08 ldo output voltage v ldo 23.1.4 hibernation module characteristics table 23-4. hibernation module dc characteristics unit max nominal min parameter name parameter v 3.6 3.0 2.4 battery supply voltage v bat v - 2.35 - low battery detect voltage v lowbat 23.1.5 flash memory characteristics table 23-5. flash memory characteristics unit max nom min parameter name parameter cycles - - 15,000 number of guaranteed mass program/erase cycles before failure a pe cyc years - - 10 data retention at average operating temperature of 125?c t ret ms 1 - - word program time t prog ms 1 - - buffer program time t bprog ms 12 - - page erase time t erase 965 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 23-5. flash memory characteristics (continued) unit max nom min parameter name parameter ms 16 - - mass erase time t me a. a program/erase cycle is defined as switching the bits from 1-> 0 -> 1. caution should be used when performing block erases, as repeated block erases can shorten the number of guaranteed erase cycles, see flash memory programming on page 315. 23.1.6 gpio module characteristics table 23-6. gpio module dc characteristics unit max nom min parameter name parameter k? 110 - 50 gpio internal pull-up resistor r gpiopu k? 180 - 55 gpio internal pull-down resistor r gpiopd a 2 - - gpio input leakage current a i lkg a. the leakage current is measured with gnd or v dd applied to the corresponding pin(s). the leakage of digital port pins is measured individually. the port pin is configured as an input and the pullup/pulldown resistor is disabled. 23.1.7 current specifications this section provides information on typical and maximum power consumption under various conditions. unless otherwise indicated, current consumption numbers include use of the on-chip ldo regulator and therefore include i ddc . 23.1.7.1 nominal power consumption the following table provides nominal figures for current consumption. table 23-7. nominal power consumption unit nom conditions parameter name parameter ma 56 v dd = 3.3 v code= while(1){} executed out of flash peripherals = all on system clock = 50 mhz (with pll) temp = 25c run mode 1 (flash loop) i dd_run ma 8 v dd = 3.3 v peripherals = all clock gated system clock = 50 mhz (with pll) temp = 25c sleep mode i dd_sleep a 550 peripherals = all off system clock = iosc30khz/64 temp = 25c deep-sleep mode i dd_deepsleep a 24 v bat = 3.0 v v dd = 0 v v dda = 0 v peripherals = all off system clock = off hibernate module = 0 khz hibernate mode (external wake, rtc disabled, i/o not powered a ) i hib_nortc march 20, 2011 966 texas instruments-advance information electrical characteristics table 23-7. nominal power consumption (continued) unit nom conditions parameter name parameter a 34 v bat = 3.0 v v dd = 0 v v dda = 0 v peripherals = all off system clock = off hibernate module = 32 khz hibernate mode (rtc enabled, i/o not powered a ) i hib_rtc a. the vdd3on mode must be disabled for the i/o ring to be unpowered. 23.1.7.2 maximum current specifications the current measurements specified in the table that follows are maximum values under the following conditions: v dd = 3.6 v v ddc = 1.2 v v bat = 3.25 v v dda = 3.6 v temperature = 25c clock source (mosc) =3.579545-mhz crystal oscillator table 23-8. detailed current specifications unit max conditions parameter name parameter ma 97 v dd = 3.6 v code= while(1){} executed out of flash peripherals = all on system clock = 80 mhz (with pll) temperature = 25c run mode 1 (flash loop) i dd_run ma 19 v dd = 3.6 v peripherals = all clock gated system clock = 80 mhz (with pll) temperature = 25c sleep mode i dd_sleep ma 1.4 v dd = 3.6 v peripherals = all clock gated system clock = 80 mhz temperature = 25c deep-sleep mode i dd_deepsleep ma pending v dd = 3.6 v peripherals = all off system clock = 80 mhz temperature = 25c programming flash memory i dd_program ma pending v dd = 3.6 v peripherals = all off system clock = 80 mhz temperature = 25c erasing flash memory i dd_erase 967 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 23-9. hibernation detailed current specifications unit max conditions parameter name parameter a 40 v bat = 3.25 v v dd = 0 v v dda = 0 v peripherals = all off system clock = off hibernate module = 0 khz temperature = 25c hibernate mode (external wake, rtc disabled, i/o not powered a ) hib_nortc a 59 v bat = 3.25 v v dd = 0 v v dda = 0 v peripherals = all off system clock = off hibernate module = 32.768 khz temperature = 25c hibernate mode (rtc enabled, i/o not powered a ) i hib_rtc a pending v bat = 3.0 v v dd = 3.3 v v dda = 3.3 v peripherals = all off system clock = off hibernate module = 32.768 khz temperature = 25c hibernate mode (rtc enabled, i/o powered) i hib_vdd3on a. the vdd3on mode must be disabled for the i/o ring to be unpowered. table 23-10. external v ddc source current specifications unit max conditions parameter name parameter ma 94 v dd = 3.6 v v ddc = 1.2 v code= while(1){} executed out of flash peripherals = all on system clock = 80 mhz (with pll) temperature = 25c run mode 1 (flash loop), v ddc current i ddc_run 23.1.7.3 typical current consumption vs. frequency figure 23-1 on page 969 shows how typical current varies with frequency when bypassing the pll. conditions are as follows: executing while (1) out of flash memory all peripherals on v dd = 3.3 v v ddc = 1.2 v v dda = 3.3 v temperature = 25c march 20, 2011 968 texas instruments-advance information electrical characteristics table 23-11. current consumption vs. frequency, pll bypassed i dd_run (ma) frequency (mhz) 21 1 21 8 28 16 figure 23-1. typical current across frequency, pll bypassed figure 23-2 on page 970 shows how typical current varies with frequency when using the pll. conditions are as follows: executing while (1) out of flash memory all peripherals on v dd = 3.3 v v ddc = 1.2 v v dda = 3.3 v temperature = 25c clock source (mosc) = 16-mhz crystal oscillator table 23-12. current consumption vs. frequency, using pll i dd_run (ma) frequency (mhz) 23 6.25 28 12.5 38 25 57 50 969 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 0 5 10 15 20 25 30 0 4 8 12 16 system cloc k (mhz) current consumption (ma) table 23-12. current consumption vs. frequency, using pll (continued) i dd_run (ma) frequency (mhz) 81 80 figure 23-2. typical current across frequency, using pll 23.2 ac characteristics 23.2.1 load conditions unless otherwise specified, the following conditions are true for all timing measurements. figure 23-3. load conditions 23.2.2 clocks the following sections provide specifications on the various clock sources and mode. 23.2.2.1 pll specifications the following tables provide specifications for using the pll. march 20, 2011 970 texas instruments-advance information electrical characteristics & / * 1 ' s l q s ) i r u ( 3 , 6 > @ v l j q d o v s ) i r u r w k h u g l j l w d o , 2 v l j q d o v 0 10 20 30 40 50 60 70 80 90 0 20 40 60 80 system cloc k (mhz) current consumption (ma) table 23-13. phase locked loop (pll) characteristics unit max nom min parameter name parameter mhz 16.384 - 3.579545 crystal reference a f ref_xtal mhz 16.384 - 3.579545 external clock reference a f ref_ext mhz - 400 - pll frequency b f pll ms 1.38 d - 0.562 c pll lock time t ready a. the exact value is determined by the crystal value programmed into the xtal field of the run-mode clock configuration (rcc) register. b. pll frequency is automatically calculated by the hardware based on the xtal field of the rcc register. c. using a 16.384-mhz crystal d. using 3.5795-mhz crystal table 23-14 on page 971 shows the actual frequency of the pll based on the crystal frequency used (defined by the xtal field in the rcc register). table 23-14. actual pll frequency error pll frequency (mhz) crystal frequency (mhz) xtal 0.0023% 400.904 3.5795 0x04 0.0047% 398.1312 3.6864 0x05 - 400 4.0 0x06 0.0035% 401.408 4.096 0x07 0.0047% 398.1312 4.9152 0x08 - 400 5.0 0x09 0.0016% 399.36 5.12 0x0a - 400 6.0 0x0b 0.0016% 399.36 6.144 0x0c 0.0047% 398.1312 7.3728 0x0d 0.0047% 400 8.0 0x0e 0.0033% 398.6773333 8.192 0x0f - 400 10.0 0x10 - 400 12.0 0x11 0.0035% 401.408 12.288 0x12 0.0056% 397.76 13.56 0x13 0.0023% 400.90904 14.318 0x14 - 400 16.0 0x15 0.010% 404.1386667 16.384 0x16 23.2.2.2 piosc specifications table 23-15. piosc clock characteristics unit max nom min parameter name parameter - 1% 0.25% - internal 16-mhz precision oscillator frequency variance, factory calibrated at 25 c f piosc25 - 3% - - internal 16-mhz precision oscillator frequency variance, factory calibrated at 25 c, across specified temperature range f piosct 971 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller table 23-15. piosc clock characteristics (continued) unit max nom min parameter name parameter - 1% 0.25% - internal 16-mhz precision oscillator frequency variance, user calibrated at a chosen temperature f pioscucal 23.2.2.3 internal 30-khz oscillator specifications table 23-16. 30-khz clock characteristics unit max nom min parameter name parameter khz 45 30 15 internal 30-khz oscillator frequency f iosc30khz 23.2.2.4 hibernation clock source specifications table 23-17. hibernation clock characteristics unit max nom min parameter name parameter mhz - 4.194304 - hibernation module oscillator frequency f hibosc mhz - 4.194304 - crystal reference for hibernation oscillator f hibosc_xtal khz - 32.768 - external clock reference for hibernation module f hibosc_ext ms 10 - - hibernation oscillator settling time a t hibosc_settle a. this parameter is highly sensitive to pcb layout and trace lengths, which may make this parameter time longer. care must be taken in pcb design to minimize trace lengths and rlc (resistance, inductance, capacitance). table 23-18. hib oscillator input characteristics condition value name mhz 4.194304 frequency ppm 100 frequency tolerance - parallel oscillation mode ? 200 equivalent series resistance (max) pf 12 - 22 load capacitance, c 1 and c 2 a w 100 drive level (typ) a. refer to the cyrstal manufacturer's recommended load capacitance. 23.2.2.5 main oscillator specifications table 23-19. main oscillator clock characteristics unit max nom min parameter name parameter mhz 16.384 - 1 main oscillator frequency f mosc ns 1000 - 61 main oscillator period t mosc_per ms 20 - 17.5 main oscillator settling time t mosc_settle mhz 16.384 - 1 crystal reference using the main oscillator (pll in bypass mode) a f ref_xtal_bypass mhz 80 - 0 external clock reference (pll in bypass mode) a f ref_ext_bypass a. the adc must be clocked from the pll or directly from a 16-mhz clock source to operate properly. march 20, 2011 972 texas instruments-advance information electrical characteristics table 23-20. mosc oscillator input characteristics condition value name mhz 3.5 4 6 8 12 16 frequency ppm 100 100 100 100 100 100 frequency tolerance ? 220 200 160 120 90 70 equivalent series resistance (max) pf 16 16 16 16 16 16 load capacitance w 100 100 100 100 100 100 drive level (typ) 23.2.2.6 system clock specifications with adc operation table 23-21. system clock characteristics with adc operation unit max nom min parameter name parameter mhz - - 16 system clock frequency when the adc module is operating (when pll is bypassed) f sysadc 23.2.3 power and brown-out characteristics table 23-22. power characteristics unit max nom min parameter name parameter parameter no. v - 2- power-on reset threshold v th p1 v 2.95 2.9 2.85 brown-out reset threshold v bth p2 ms 18 -6 power-on reset timeout t por p3 s - 500 - brown-out timeout t bor p4 ms 2 -- internal reset timeout after por t irpor p5 ms 2 -- internal reset timeout after bor t irbor p6 ms 10 -- supply voltage (v dd ) rise time (0v-3.0v) t vddrise p7 ms 6 -- supply voltage (v dd ) rise time (2.0v-3.0v) t vdd2_3 p8 v 0.2 -- v dd and v ddc voltage ramp start v start p10 a v - - 1.0 v ddc voltage minimum when v dd reaches 1.5 v v vddc_req p11 a a. this specification only applies when supplying v ddc using an external regulator. figure 23-4. power-on reset timing 973 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 9 ' ' 3 2 5 , q w h u q d o 5 h v h w , q w h u q d o 3 3 3 figure 23-5. brown-out reset timing figure 23-6. power-on reset and voltage parameters march 20, 2011 974 texas instruments-advance information electrical characteristics 9 ' ' 3 3 9 ' ' % 2 5 , q w h u q d o 5 h v h w , q w h u q d o 3 3 3 figure 23-7. voltage requirements when using an external v ddc source 23.2.4 jtag and boundary scan table 23-23. jtag characteristics unit max nom min parameter name parameter parameter no. mhz 10 - 0 tck operational clock frequency a f tck j1 ns - - 100 tck operational clock period t tck j2 ns - t tck - tck clock low time t tck_low j3 ns - t tck - tck clock high time t tck_high j4 ns 10 - 0 tck rise time t tck_r j5 ns 10 - 0 tck fall time t tck_f j6 ns - - 20 tms setup time to tck rise t tms_su j7 ns - - 20 tms hold time from tck rise t tms_hld j8 ns - - 25 tdi setup time to tck rise t tdi_su j9 ns - - 25 tdi hold time from tck rise t tdi_hld j10 ns 35 23 - 2-ma drive tck fall to data valid from high-z j11 t tdo_zdv ns 26 15 4-ma drive ns 25 14 8-ma drive ns 29 18 8-ma drive with slew rate control 975 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 9 9 9 9 ' ' 9 ' ' & 9 3 3 table 23-23. jtag characteristics (continued) unit max nom min parameter name parameter parameter no. ns 35 21 - 2-ma drive tck fall to data valid from data valid j12 t tdo_dv ns 25 14 4-ma drive ns 24 13 8-ma drive ns 28 18 8-ma drive with slew rate control ns 11 9 - 2-ma drive tck fall to high-z from data valid j13 t tdo_dvz ns 9 7 4-ma drive ns 8 6 8-ma drive ns 9 7 8-ma drive with slew rate control a. a ratio of at least 8:1 must be kept between the system clock and tck. figure 23-8. jtag test clock input timing figure 23-9. jtag test access port (tap) timing 23.2.5 reset table 23-24. reset characteristics unit max nom min parameter name parameter parameter no. ms 2-- internal reset timeout after hardware reset ( rst pin) t irhwr r1 ms 2-- internal reset timeout after software-initiated system reset t irswr r2 march 20, 2011 976 texas instruments-advance information electrical characteristics 7 ' 2 2 x w s x w 9 d o l g 7 & . 7 ' 2 2 x w s x w 9 d o l g - 7 ' 2 7 ' , 7 0 6 7 ' , , q s x w 9 d o l g 7 ' , , q s x w 9 d o l g - - - 7 0 6 , q s x w 9 d o l g - - 7 0 6 , q s x w 9 d o l g - - - - - 7 & . - - - - - table 23-24. reset characteristics (continued) unit max nom min parameter name parameter parameter no. ms 2-- internal reset timeout after watchdog reset t irwdr r3 ms 2-- internal reset timeout after mosc failure reset t irmfr r4 s --2 minimum rst pulse width t min r5 figure 23-10. external reset timing (rst ) figure 23-11. software reset timing figure 23-12. watchdog reset timing figure 23-13. mosc failure reset timing 23.2.6 sleep modes table 23-25. sleep modes ac characteristics a unit max nom min parameter name parameter parameter no system clocks 7-- time to wake from interrupt in sleep or deep-sleep mode, not using the pll t wake_s d1 977 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 5 6 : 5 h v h w 5 h v h w , q w h u q d o 0 2 6 & ) d l o 5 h v h w , q w h u q d o 5 h v h w , q w h u q d o 5 : ' 2 * 5 h v h w , q w h u q d o 5 h v h w , q w h u q d o 5 5 6 7 5 h v h w , q w h u q d o 5 5 5 table 23-25. sleep modes ac characteristics (continued) unit max nom min parameter name parameter parameter no ms t ready -- time to wake from interrupt in sleep or deep-sleep mode when using the pll t wake_pll_s d2 ms 16 b 0- time to enter deep-sleep mode from sleep request t enter_ds d3 a. values in this table assume the iosc is the clock source during sleep or deep-sleep mode. b. nominal specification occurs 99.9995% of the time. 23.2.7 hibernation module the hibernation module requires special system implementation considerations because it is intended to power down all other sections of its host device, refer to hibernation module on page 282. table 23-26. hibernation module ac characteristics unit max nom min parameter name parameter parameter no s --20 internal 32.768 khz clock reference rising edge to hib asserted t hib_low h1 s -30- internal 32.768 khz clock reference rising edge to hib deasserted t hib_high h2 s 124-62 wake assert to hib desassert (wake up time), internal hibernation oscillator running during hibernation a t wake_to_hib h3 ms 10-- wake assert to hib desassert (wake up time), internal hibernation oscillator stopped during hibernation a t wake_to_hib h4 s --62 wake assertion time, internal hibernation oscillator running during hibernation t wake_clock h5 ms --10 wake assertion time, internal hibernation oscillator stopped during hibernation b t wake_noclock h6 s --92 access time to or from a non-volatile register in hib module to complete t hib_reg_access h7 ms --100 hib high time between assertions t hib_to_hib h8 ms 50 c 0- time to enter hibernation mode from hibernation request t enter_hib h9 ms 1.5-- supply voltage (v dd ) rise time when waking from hibernation (1.8v-3.0v) t vddrise_hib h10 a. code begins executing after the time period specified by t irpor following the deassertion of hib . b. this mode is used when the pinwen bit is set and the rtcen bit is clear in the hibctl register. c. nominal specification occurs 99.998% of the time. figure 23-14. hibernation module timing with internal oscillator running in hibernation march 20, 2011 978 texas instruments-advance information electrical characteristics . + ] l q w h u q d o + , % + + : $ . ( + + + figure 23-15. hibernation module timing with internal oscillator stopped in hibernation figure 23-16. vdd ramp when waking from hibernation 23.2.8 general-purpose i/o (gpio) note: all gpios are 5-v tolerant. table 23-27. gpio characteristics unit max nom min condition parameter name parameter ns 20 14 - 2-ma drive gpio rise time (from 20% to 80% of v dd ) t gpior ns 10 7 4-ma drive ns 5 4 8-ma drive ns 8 6 8-ma drive with slew rate control ns 21 14 - 2-ma drive gpio fall time (from 80% to 20% of v dd ) t gpiof ns 11 7 4-ma drive ns 6 4 8-ma drive ns 8 6 8-ma drive with slew rate control 979 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 9 ' ' + . + ] l q w h u q d o + , % + + : $ . ( + + + 23.2.9 analog-to-digital converter (adc) table 23-28. adc characteristics a unit max nom min parameter name parameter v 3.0 - - maximum single-ended, full-scale analog input voltage, using internal reference v adcin v v refa - - maximum single-ended, full-scale analog input voltage, using external reference v - - 0.0 minimum single-ended, full-scale analog input voltage v 1.5 - - maximum differential, full-scale analog input voltage, using internal reference v v refa /2 - - maximum differential, full-scale analog input voltage, using external reference v - - 0.0 minimum differential, full-scale analog input voltage bits 10 resolution n mhz 18 16 14 adc internal clock frequency b f adc s 1 conversion time c t adcconv k samples/s 1000 conversion rate c f adcconv ns - - 187.5 sample time t adcsamp system clocks - 2 - latency from trigger to start of conversion t lt a 1.0 - - adc input leakage i l k? 10 - - adc equivalent resistance r adc pf 1.1 1.0 0.9 adc equivalent capacitance c adc lsb 1 - - integral nonlinearity error e l lsb 1 - - differential nonlinearity error e d lsb 1 - - offset error e o lsb 3 - - full-scale gain error e g c 5 - - temperature sensor accuracy e ts a. the adc reference voltage is 3.0 v. this reference voltage is internally generated from the 3.3 vdda supply by a band gap circuit. b. the adc must be clocked from the pll or directly from an external clock source to operate properly. c. the conversion time and rate scale from the specified number if the adc internal clock frequency is any value other than 16 mhz. march 20, 2011 980 texas instruments-advance information electrical characteristics figure 23-17. adc input equivalency diagram table 23-29. adc module external reference characteristics a unit max nom min parameter name parameter v 3.06 - 2.4 external voltage reference for adc b v refa a - 1.0 - external voltage reference leakage current i l a. care must be taken to supply a reference voltage of acceptable quality. b. ground is always used as the reference level for the minimum conversion value. table 23-30. adc module internal reference characteristics unit max nom min parameter name parameter v - 3.0 - internal voltage reference for adc v refi % 2.5 - - variation across temperature for a given device e ir 23.2.10 synchronous serial interface (ssi) table 23-31. ssi characteristics unit max nom min parameter name parameter parameter no. system clocks 65024 -2 ssiclk cycle time t clk_per s1 t clk_per - 0.5- ssiclk high time t clk_high s2 t clk_per - 0.5- ssiclk low time t clk_low s3 ns 64- ssiclk rise/fall time a t clkrf s4 system clocks 1-0 data from master valid delay time t dmd s5 system clocks --1 data from master setup time t dms s6 system clocks --2 data from master hold time t dmh s7 system clocks --1 data from slave setup time t dss s8 system clocks --2 data from slave hold time t dsh s9 a. note that the delays shown are using 8-ma drive strength. 981 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 w h o o d u l v ? 0 l f u r f r q w u r o o h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u & $ ' & 5 $ ' & 9 ' ' e l w f r q y h u w h u , / 9 , 1 ( 6 ' & o d p s ( 6 ' & o d p s figure 23-18. ssi timing for ti frame format (frf=01), single transfer timing measurement figure 23-19. ssi timing for microwire frame format (frf=10), single transfer march 20, 2011 982 texas instruments-advance information electrical characteristics 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ 0 6 % / 6 % 0 6 % / 6 % 6 6 6 e l w f r q w u r o w r e l w v r x w s x w g d w d 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ 0 6 % / 6 % 6 6 6 6 w r e l w v figure 23-20. ssi timing for spi frame format (frf=00), with sph=1 23.2.11 inter-integrated circuit (i 2 c) interface table 23-32. i 2 c characteristics unit max nom min parameter name parameter parameter no. system clocks --36 start condition hold time t sch i1 a system clocks --36 clock low period t lp i2 a ns (see note b) -- i2cscl/ i2csda rise time (v il =0.5 v to v ih =2.4 v) t srt i3 b system clocks --2 data hold time t dh i4 a ns 10 9- i2cscl/ i2csda fall time (v ih =2.4 v to v il =0.5 v) t sft i5 c system clocks --24 clock high time t ht i6 a system clocks --18 data setup time t ds i7 a system clocks --36 start condition setup time (for repeated start condition only) t scsr i8 a system clocks --24 stop condition setup time t scs i9 a a. values depend on the value programmed into the tpr bit in the i 2 c master timer period (i2cmtpr) register; a tpr programmed for the maximum i2cscl frequency (tpr=0x2) results in a minimum output timing as shown in the table above. the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2cscl low period. the actual position is affected by the value programmed into the tpr ; however, the numbers given in the above values are minimum values. b. because i2cscl and i2csda are open-drain-type outputs, which the controller can only actively drive low, the time i2cscl or i2csda takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. specified at a nominal 50 pf load. 983 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 6 6 , & o n 6 3 2 6 6 , 7 [ p d v w h u 6 6 , 5 [ v o d y h / 6 % 6 6 , & o n 6 3 2 6 6 6 6 6 , ) v v / 6 % 6 0 6 % 6 6 6 6 6 0 6 % figure 23-21. i 2 c timing 23.2.12 inter-integrated circuit sound (i 2 s) interface table 23-33. i 2 s master clock (receive and transmit) unit max nom min parameter name parameter parameter no. ns - - 20.3 cycle time t mclk_per m1 ns see table 23-27 on page 979. rise/fall time t mclkrf m2 ns - - 10 high time t mclk_high m3 ns - - 10 low time t mclk_low m4 % 52 - 48 duty cycle t mdc m5 ns 2.5 - - jitter t mjitter m6 table 23-34. i 2 s slave clock (receive and transmit) unit max nom min parameter name parameter parameter no. ns - - 80 cycle time t sclk_per m7 ns - - 40 high time t sclk_high m8 ns - - 40 low time t sclk_low m9 % - 50 - duty cycle t sdc m10 table 23-35. i 2 s master mode unit max nom min parameter name parameter parameter no. ns 10 -- sck fall to ws valid t msws m11 ns 10 -- sck fall to txsd valid t msd m12 ns - - 10 rxsd setup time to sck rise t msds m13 ns - - 10 rxsd hold time from sck rise t msdh m14 figure 23-22. i 2 s master mode transmit timing march 20, 2011 984 texas instruments-advance information electrical characteristics ' d w d 6 & . : 6 7 ; 6 ' 0 0 , & 6 & / , & 6 ' $ , , , , , , , , , figure 23-23. i 2 s master mode receive timing table 23-36. i 2 s slave mode unit max nom min parameter name parameter parameter no. ns -- 80 cycle time t sclk_per m15 ns -- 40 high time t sclk_high m16 ns -- 40 low time t sclk_low m17 % - 50 - duty cycle t sdc m18 ns 25 -- ws setup time to sck rise t ssetup m19 ns 10 -- ws hold time from sck rise t shold m20 ns 20 -- sck fall to txsd valid t ssd m21 ns 20 -- left-justified mode, ws to txsd t slsd m22 ns -- 10 rxsd setup time to sck rise t ssds m23 ns -- 10 rxsd hold time from sck rise t ssdh m24 figure 23-24. i 2 s slave mode transmit timing figure 23-25. i 2 s slave mode receive timing 23.2.13 analog comparator table 23-37. analog comparator characteristics unit max nom min parameter name parameter mv 25 10 - input offset voltage v os v v dd -1.5 - 0 input common mode voltage range v cm 985 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller ' d w d 6 & . : 6 7 ; 6 ' 0 0 0 0 ' d w d 6 & . 5 ; 6 ' 0 0 ' d w d 6 & . 5 ; 6 ' 0 0 table 23-37. analog comparator characteristics (continued) unit max nom min parameter name parameter db - - 50 common mode rejection ratio c mrr s 1 - - response time t rt s 10 - - comparator mode change to output valid t mc table 23-38. analog comparator voltage reference characteristics unit max nom min parameter name parameter lsb - v dd /31 - resolution high range r hr lsb - v dd /23 - resolution low range r lr lsb 1/2 - - absolute accuracy high range a hr lsb 1/4 - - absolute accuracy low range a lr march 20, 2011 986 texas instruments-advance information electrical characteristics a register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 the cortex-m3 processor r0, type r/w, , reset - (see page 67) data data r1, type r/w, , reset - (see page 67) data data r2, type r/w, , reset - (see page 67) data data r3, type r/w, , reset - (see page 67) data data r4, type r/w, , reset - (see page 67) data data r5, type r/w, , reset - (see page 67) data data r6, type r/w, , reset - (see page 67) data data r7, type r/w, , reset - (see page 67) data data r8, type r/w, , reset - (see page 67) data data r9, type r/w, , reset - (see page 67) data data r10, type r/w, , reset - (see page 67) data data r11, type r/w, , reset - (see page 67) data data r12, type r/w, , reset - (see page 67) data data sp, type r/w, , reset - (see page 68) sp sp lr, type r/w, , reset 0xffff.ffff (see page 69) link link pc, type r/w, , reset - (see page 70) pc pc 987 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 psr, type r/w, , reset 0x0100.0000 (see page 71) thumb ici / it q v c z n isrnum ici / it primask, type r/w, , reset 0x0000.0000 (see page 75) primask faultmask, type r/w, , reset 0x0000.0000 (see page 76) faultmask basepri, type r/w, , reset 0x0000.0000 (see page 77) basepri control, type r/w, , reset 0x0000.0000 (see page 78) tmpl asp cortex-m3 peripherals system timer (systick) registers base 0xe000.e000 stctrl, type r/w, offset 0x010, reset 0x0000.0004 count enable inten clk_src streload, type r/w, offset 0x014, reset 0x0000.0000 reload reload stcurrent, type r/wc, offset 0x018, reset 0x0000.0000 current current cortex-m3 peripherals nested vectored interrupt controller (nvic) registers base 0xe000.e000 en0, type r/w, offset 0x100, reset 0x0000.0000 int int en1, type r/w, offset 0x104, reset 0x0000.0000 int int dis0, type r/w, offset 0x180, reset 0x0000.0000 int int dis1, type r/w, offset 0x184, reset 0x0000.0000 int int pend0, type r/w, offset 0x200, reset 0x0000.0000 int int pend1, type r/w, offset 0x204, reset 0x0000.0000 int int unpend0, type r/w, offset 0x280, reset 0x0000.0000 int int march 20, 2011 988 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 unpend1, type r/w, offset 0x284, reset 0x0000.0000 int int active0, type ro, offset 0x300, reset 0x0000.0000 int int active1, type ro, offset 0x304, reset 0x0000.0000 int int pri0, type r/w, offset 0x400, reset 0x0000.0000 intc intd inta intb pri1, type r/w, offset 0x404, reset 0x0000.0000 intc intd inta intb pri2, type r/w, offset 0x408, reset 0x0000.0000 intc intd inta intb pri3, type r/w, offset 0x40c, reset 0x0000.0000 intc intd inta intb pri4, type r/w, offset 0x410, reset 0x0000.0000 intc intd inta intb pri5, type r/w, offset 0x414, reset 0x0000.0000 intc intd inta intb pri6, type r/w, offset 0x418, reset 0x0000.0000 intc intd inta intb pri7, type r/w, offset 0x41c, reset 0x0000.0000 intc intd inta intb pri8, type r/w, offset 0x420, reset 0x0000.0000 intc intd inta intb pri9, type r/w, offset 0x424, reset 0x0000.0000 intc intd inta intb pri10, type r/w, offset 0x428, reset 0x0000.0000 intc intd inta intb pri11, type r/w, offset 0x42c, reset 0x0000.0000 intc intd inta intb pri12, type r/w, offset 0x430, reset 0x0000.0000 intc intd inta intb pri13, type r/w, offset 0x434, reset 0x0000.0000 intc intd inta intb 989 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 swtrig, type wo, offset 0xf00, reset 0x0000.0000 intid cortex-m3 peripherals system control block (scb) registers base 0xe000.e000 actlr, type r/w, offset 0x008, reset 0x0000.0000 dismcyc diswbuf disfold cpuid, type ro, offset 0xd00, reset 0x412f.c230 con var imp rev partno intctrl, type r/w, offset 0xd04, reset 0x0000.0000 vecpend isrpend isrpre pendstclr pendstset unpendsv pendsv nmiset vecact retbase vecpend vtable, type r/w, offset 0xd08, reset 0x0000.0000 offset base offset apint, type r/w, offset 0xd0c, reset 0xfa05.0000 vectkey vectreset vectclract sysresreq prigroup endianess sysctrl, type r/w, offset 0xd10, reset 0x0000.0000 sleepexit sleepdeep sevonpend cfgctrl, type r/w, offset 0xd14, reset 0x0000.0200 basethr mainpend unaligned div0 bfhfnmign stkalign syspri1, type r/w, offset 0xd18, reset 0x0000.0000 usage mem bus syspri2, type r/w, offset 0xd1c, reset 0x0000.0000 svc syspri3, type r/w, offset 0xd20, reset 0x0000.0000 pendsv tick debug syshndctrl, type r/w, offset 0xd24, reset 0x0000.0000 mem bus usage mema busa usga svca mon pndsv tick usagep memp busp svc faultstat, type r/w1c, offset 0xd28, reset 0x0000.0000 undef invstat invpc nocp unalign div0 ierr derr mustke mstke mmarv ibus precise impre bustke bstke bfarv hfaultstat, type r/w1c, offset 0xd2c, reset 0x0000.0000 forced dbg vect mmaddr, type r/w, offset 0xd34, reset - addr addr faultaddr, type r/w, offset 0xd38, reset - addr addr march 20, 2011 990 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cortex-m3 peripherals memory protection unit (mpu) registers base 0xe000.e000 mputype, type ro, offset 0xd90, reset 0x0000.0800 iregion separate dregion mpuctrl, type r/w, offset 0xd94, reset 0x0000.0000 enable hfnmiena privdefen mpunumber, type r/w, offset 0xd98, reset 0x0000.0000 number mpubase, type r/w, offset 0xd9c, reset 0x0000.0000 addr region valid addr mpubase1, type r/w, offset 0xda4, reset 0x0000.0000 addr region valid addr mpubase2, type r/w, offset 0xdac, reset 0x0000.0000 addr region valid addr mpubase3, type r/w, offset 0xdb4, reset 0x0000.0000 addr region valid addr mpuattr, type r/w, offset 0xda0, reset 0x0000.0000 b c s tex ap xn enable size srd mpuattr1, type r/w, offset 0xda8, reset 0x0000.0000 b c s tex ap xn enable size srd mpuattr2, type r/w, offset 0xdb0, reset 0x0000.0000 b c s tex ap xn enable size srd mpuattr3, type r/w, offset 0xdb8, reset 0x0000.0000 b c s tex ap xn enable size srd system control base 0x400f.e000 did0, type ro, offset 0x000, reset - (see page 200) class ver minor major pborctl, type r/w, offset 0x030, reset 0x0000.7ffd (see page 202) borior ris, type ro, offset 0x050, reset 0x0000.0000 (see page 203) borris plllris moscpupris imc, type r/w, offset 0x054, reset 0x0000.0000 (see page 205) borim plllim moscpupim 991 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 misc, type r/w1c, offset 0x058, reset 0x0000.0000 (see page 207) bormis plllmis moscpupmis resc, type r/w, offset 0x05c, reset - (see page 209) moscfail ext por bor wdt0 sw wdt1 rcc, type r/w, offset 0x060, reset 0x078e.3ad1 (see page 211) pwmdiv usepwmdiv usesysdiv sysdiv acg moscdis ioscdis oscsrc xtal bypass pwrdn pllcfg, type ro, offset 0x064, reset - (see page 215) r f gpiohbctl, type r/w, offset 0x06c, reset 0x0000.0000 (see page 216) porta portb portc portd porte portf portg porth portj rcc2, type r/w, offset 0x070, reset 0x07c0.6810 (see page 218) sysdiv2lsb sysdiv2 div400 usercc2 oscsrc2 bypass2 pwrdn2 moscctl, type r/w, offset 0x07c, reset 0x0000.0000 (see page 221) cval dslpclkcfg, type r/w, offset 0x144, reset 0x0780.0000 (see page 222) dsdivoride dsoscsrc piosccal, type r/w, offset 0x150, reset 0x0000.0000 (see page 224) uten ut update cal pioscstat, type ro, offset 0x154, reset 0x0000.0040 (see page 226) dt ct result i2smclkcfg, type r/w, offset 0x170, reset 0x0000.0000 (see page 227) rxf rxi rxen txf txi txen did1, type ro, offset 0x004, reset - (see page 229) partno fam ver qual rohs pkg temp pincount dc0, type ro, offset 0x008, reset 0x005f.001f (see page 231) sramsz flashsz dc1, type ro, offset 0x010, reset - (see page 232) adc0 adc1 pwm wdt1 jtag swd swo wdt0 pll tempsns hib mpu maxadc0spd maxadc1spd minsysdiv dc2, type ro, offset 0x014, reset 0x130f.5337 (see page 234) timer0 timer1 timer2 timer3 comp0 comp1 i2s0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 dc3, type ro, offset 0x018, reset 0xbfff.8fff (see page 236) adc0ain0 adc0ain1 adc0ain2 adc0ain3 adc0ain4 adc0ain5 adc0ain6 adc0ain7 ccp0 ccp1 ccp2 ccp3 ccp4 ccp5 32khz pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 c0minus c0plus c0o c1minus c1plus c1o pwmfault dc4, type ro, offset 0x01c, reset 0x0004.f1ff (see page 238) pical gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj rom udma ccp6 ccp7 march 20, 2011 992 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dc5, type ro, offset 0x020, reset 0x0f30.003f (see page 240) pwmesync pwmeflt pwmfault0 pwmfault1 pwmfault2 pwmfault3 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 dc6, type ro, offset 0x024, reset 0x0000.0000 (see page 242) dc7, type ro, offset 0x028, reset 0xffff.ffff (see page 243) dmach16 dmach17 dmach18 dmach19 dmach20 dmach21 dmach22 dmach23 dmach24 dmach25 dmach26 dmach27 dmach28 dmach29 dmach30 dmach0 dmach1 dmach2 dmach3 dmach4 dmach5 dmach6 dmach7 dmach8 dmach9 dmach10 dmach11 dmach12 dmach13 dmach14 dmach15 dc8, type ro, offset 0x02c, reset 0xffff.ffff (see page 247) adc1ain0 adc1ain1 adc1ain2 adc1ain3 adc1ain4 adc1ain5 adc1ain6 adc1ain7 adc1ain8 adc1ain9 adc1ain10 adc1ain11 adc1ain12 adc1ain13 adc1ain14 adc1ain15 adc0ain0 adc0ain1 adc0ain2 adc0ain3 adc0ain4 adc0ain5 adc0ain6 adc0ain7 adc0ain8 adc0ain9 adc0ain10 adc0ain11 adc0ain12 adc0ain13 adc0ain14 adc0ain15 dc9, type ro, offset 0x190, reset 0x00ff.00ff (see page 249) adc1dc0 adc1dc1 adc1dc2 adc1dc3 adc1dc4 adc1dc5 adc1dc6 adc1dc7 adc0dc0 adc0dc1 adc0dc2 adc0dc3 adc0dc4 adc0dc5 adc0dc6 adc0dc7 nvmstat, type ro, offset 0x1a0, reset 0x0000.0001 (see page 251) fwb rcgc0, type r/w, offset 0x100, reset 0x00000040 (see page 252) adc0 adc1 pwm wdt1 wdt0 hib maxadc0spd maxadc1spd scgc0, type r/w, offset 0x110, reset 0x00000040 (see page 255) adc0 adc1 pwm wdt1 wdt0 hib maxadc0spd maxadc1spd dcgc0, type r/w, offset 0x120, reset 0x00000040 (see page 258) adc0 adc1 pwm wdt1 wdt0 hib rcgc1, type r/w, offset 0x104, reset 0x00000000 (see page 260) timer0 timer1 timer2 timer3 comp0 comp1 i2s0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 scgc1, type r/w, offset 0x114, reset 0x00000000 (see page 263) timer0 timer1 timer2 timer3 comp0 comp1 i2s0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 dcgc1, type r/w, offset 0x124, reset 0x00000000 (see page 266) timer0 timer1 timer2 timer3 comp0 comp1 i2s0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 rcgc2, type r/w, offset 0x108, reset 0x00000000 (see page 269) gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj udma scgc2, type r/w, offset 0x118, reset 0x00000000 (see page 271) gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj udma dcgc2, type r/w, offset 0x128, reset 0x00000000 (see page 273) gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj udma srcr0, type r/w, offset 0x040, reset 0x00000000 (see page 275) adc0 adc1 pwm wdt1 wdt0 hib srcr1, type r/w, offset 0x044, reset 0x00000000 (see page 277) timer0 timer1 timer2 timer3 comp0 comp1 i2s0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 993 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 srcr2, type r/w, offset 0x048, reset 0x00000000 (see page 280) gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj udma hibernation module base 0x400f.c000 hibrtcc, type ro, offset 0x000, reset 0x0000.0000 (see page 294) rtcc rtcc hibrtcm0, type r/w, offset 0x004, reset 0xffff.ffff (see page 295) rtcm0 rtcm0 hibrtcm1, type r/w, offset 0x008, reset 0xffff.ffff (see page 296) rtcm1 rtcm1 hibrtcld, type r/w, offset 0x00c, reset 0xffff.ffff (see page 297) rtcld rtcld hibctl, type r/w, offset 0x010, reset 0x8000.0000 (see page 298) wrc rtcen hibreq clksel rtcwen pinwen lowbaten clk32en vabort vdd3on hibim, type r/w, offset 0x014, reset 0x0000.0000 (see page 301) rtcalt0 rtcalt1 lowbat extw hibris, type ro, offset 0x018, reset 0x0000.0000 (see page 303) rtcalt0 rtcalt1 lowbat extw hibmis, type ro, offset 0x01c, reset 0x0000.0000 (see page 305) rtcalt0 rtcalt1 lowbat extw hibic, type r/w1c, offset 0x020, reset 0x0000.0000 (see page 307) rtcalt0 rtcalt1 lowbat extw hibrtct, type r/w, offset 0x024, reset 0x0000.7fff (see page 308) trim hibdata, type r/w, offset 0x030-0x12c, reset - (see page 309) rtd rtd internal memory flash memory registers (flash control offset) base 0x400f.d000 fma, type r/w, offset 0x000, reset 0x0000.0000 offset fmd, type r/w, offset 0x004, reset 0x0000.0000 data data fmc, type r/w, offset 0x008, reset 0x0000.0000 wrkey write erase merase comt march 20, 2011 994 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fcris, type ro, offset 0x00c, reset 0x0000.0000 aris pris fcim, type r/w, offset 0x010, reset 0x0000.0000 amask pmask fcmisc, type r/w1c, offset 0x014, reset 0x0000.0000 amisc pmisc fmc2, type r/w, offset 0x020, reset 0x0000.0000 wrkey wrbuf fwbval, type r/w, offset 0x030, reset 0x0000.0000 fwb[n] fwb[n] fctl, type r/w, offset 0x0f8, reset 0x0000.0000 usdreq usdack fwbn, type r/w, offset 0x100 - 0x17c, reset 0x0000.0000 data data internal memory memory registers (system control offset) base 0x400f.e000 rmctl, type r/w1c, offset 0x0f0, reset - ba fmpre0, type r/w, offset 0x130 and 0x200, reset 0xffff.ffff read_enable read_enable fmppe0, type r/w, offset 0x134 and 0x400, reset 0xffff.ffff prog_enable prog_enable bootcfg, type r/w, offset 0x1d0, reset 0xffff.fffe nw dbg0 dbg1 en pol pin port user_reg0, type r/w, offset 0x1e0, reset 0xffff.ffff data nw data user_reg1, type r/w, offset 0x1e4, reset 0xffff.ffff data nw data user_reg2, type r/w, offset 0x1e8, reset 0xffff.ffff data nw data user_reg3, type r/w, offset 0x1ec, reset 0xffff.ffff data nw data fmpre1, type r/w, offset 0x204, reset 0x0000.0000 read_enable read_enable 995 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fmpre2, type r/w, offset 0x208, reset 0x0000.0000 read_enable read_enable fmpre3, type r/w, offset 0x20c, reset 0x0000.0000 read_enable read_enable fmppe1, type r/w, offset 0x404, reset 0x0000.0000 prog_enable prog_enable fmppe2, type r/w, offset 0x408, reset 0x0000.0000 prog_enable prog_enable fmppe3, type r/w, offset 0x40c, reset 0x0000.0000 prog_enable prog_enable micro direct memory access (dma) dma channel control structure (offset from channel control table base) base n/a dmasrcendp, type r/w, offset 0x000, reset - addr addr dmadstendp, type r/w, offset 0x004, reset - addr addr dmachctl, type r/w, offset 0x008, reset - arbsize srcsize srcinc dstsize dstinc xfermode nxtuseburst xfersize arbsize micro direct memory access (dma) dma registers (offset from dma base address) base 0x400f.f000 dmastat, type ro, offset 0x000, reset 0x001f.0000 dmachans masten state dmacfg, type wo, offset 0x004, reset - masten dmactlbase, type r/w, offset 0x008, reset 0x0000.0000 addr addr dmaaltbase, type ro, offset 0x00c, reset 0x0000.0200 addr addr dmawaitstat, type ro, offset 0x010, reset 0xffff.ffc0 waitreq[n] waitreq[n] dmaswreq, type wo, offset 0x014, reset - swreq[n] swreq[n] dmauseburstset, type r/w, offset 0x018, reset 0x0000.0000 set[n] set[n] march 20, 2011 996 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dmauseburstclr, type wo, offset 0x01c, reset - clr[n] clr[n] dmareqmaskset, type r/w, offset 0x020, reset 0x0000.0000 set[n] set[n] dmareqmaskclr, type wo, offset 0x024, reset - clr[n] clr[n] dmaenaset, type r/w, offset 0x028, reset 0x0000.0000 set[n] set[n] dmaenaclr, type wo, offset 0x02c, reset - clr[n] clr[n] dmaaltset, type r/w, offset 0x030, reset 0x0000.0000 set[n] set[n] dmaaltclr, type wo, offset 0x034, reset - clr[n] clr[n] dmaprioset, type r/w, offset 0x038, reset 0x0000.0000 set[n] set[n] dmaprioclr, type wo, offset 0x03c, reset - clr[n] clr[n] dmaerrclr, type r/w, offset 0x04c, reset 0x0000.0000 errclr dmachasgn, type r/w, offset 0x500, reset 0x0000.0000 chasgn[n] chasgn[n] dmaperiphid0, type ro, offset 0xfe0, reset 0x0000.0030 pid0 dmaperiphid1, type ro, offset 0xfe4, reset 0x0000.00b2 pid1 dmaperiphid2, type ro, offset 0xfe8, reset 0x0000.000b pid2 dmaperiphid3, type ro, offset 0xfec, reset 0x0000.0000 pid3 dmaperiphid4, type ro, offset 0xfd0, reset 0x0000.0004 pid4 dmapcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 997 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dmapcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 dmapcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 dmapcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 general-purpose input/outputs (gpios) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 gpiodata, type r/w, offset 0x000, reset 0x0000.0000 (see page 418) data gpiodir, type r/w, offset 0x400, reset 0x0000.0000 (see page 419) dir gpiois, type r/w, offset 0x404, reset 0x0000.0000 (see page 420) is gpioibe, type r/w, offset 0x408, reset 0x0000.0000 (see page 421) ibe gpioiev, type r/w, offset 0x40c, reset 0x0000.0000 (see page 422) iev gpioim, type r/w, offset 0x410, reset 0x0000.0000 (see page 423) ime gpioris, type ro, offset 0x414, reset 0x0000.0000 (see page 424) ris gpiomis, type ro, offset 0x418, reset 0x0000.0000 (see page 425) mis gpioicr, type w1c, offset 0x41c, reset 0x0000.0000 (see page 427) ic gpioafsel, type r/w, offset 0x420, reset - (see page 428) afsel march 20, 2011 998 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpiodr2r, type r/w, offset 0x500, reset 0x0000.00ff (see page 430) drv2 gpiodr4r, type r/w, offset 0x504, reset 0x0000.0000 (see page 431) drv4 gpiodr8r, type r/w, offset 0x508, reset 0x0000.0000 (see page 432) drv8 gpioodr, type r/w, offset 0x50c, reset 0x0000.0000 (see page 433) ode gpiopur, type r/w, offset 0x510, reset - (see page 434) pue gpiopdr, type r/w, offset 0x514, reset 0x0000.0000 (see page 436) pde gpioslr, type r/w, offset 0x518, reset 0x0000.0000 (see page 438) srl gpioden, type r/w, offset 0x51c, reset - (see page 439) den gpiolock, type r/w, offset 0x520, reset 0x0000.0001 (see page 441) lock lock gpiocr, type -, offset 0x524, reset - (see page 442) cr gpioamsel, type r/w, offset 0x528, reset 0x0000.0000 (see page 444) gpioamsel gpiopctl, type r/w, offset 0x52c, reset - (see page 446) pmc4 pmc5 pmc6 pmc7 pmc0 pmc1 pmc2 pmc3 gpioperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 (see page 448) pid4 gpioperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 (see page 449) pid5 gpioperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 (see page 450) pid6 gpioperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 (see page 451) pid7 gpioperiphid0, type ro, offset 0xfe0, reset 0x0000.0061 (see page 452) pid0 999 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 (see page 453) pid1 gpioperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 (see page 454) pid2 gpioperiphid3, type ro, offset 0xfec, reset 0x0000.0001 (see page 455) pid3 gpiopcellid0, type ro, offset 0xff0, reset 0x0000.000d (see page 456) cid0 gpiopcellid1, type ro, offset 0xff4, reset 0x0000.00f0 (see page 457) cid1 gpiopcellid2, type ro, offset 0xff8, reset 0x0000.0005 (see page 458) cid2 gpiopcellid3, type ro, offset 0xffc, reset 0x0000.00b1 (see page 459) cid3 general-purpose timers timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 gptmcfg, type r/w, offset 0x000, reset 0x0000.0000 (see page 476) gptmcfg gptmtamr, type r/w, offset 0x004, reset 0x0000.0000 (see page 477) tamr tacmr taams tacdir tamie tawot tasnaps gptmtbmr, type r/w, offset 0x008, reset 0x0000.0000 (see page 479) tbmr tbcmr tbams tbcdir tbmie tbwot tbsnaps gptmctl, type r/w, offset 0x00c, reset 0x0000.0000 (see page 481) taen tastall taevent rtcen taote tapwml tben tbstall tbevent tbote tbpwml gptmimr, type r/w, offset 0x018, reset 0x0000.0000 (see page 484) tatoim camim caeim rtcim tamim tbtoim cbmim cbeim tbmim gptmris, type ro, offset 0x01c, reset 0x0000.0000 (see page 486) tatoris camris caeris rtcris tamris tbtoris cbmris cberis tbmris gptmmis, type ro, offset 0x020, reset 0x0000.0000 (see page 489) tatomis cammis caemis rtcmis tammis tbtomis cbmmis cbemis tbmmis gptmicr, type w1c, offset 0x024, reset 0x0000.0000 (see page 492) tatocint camcint caecint rtccint tamcint tbtocint cbmcint cbecint tbmcint gptmtailr, type r/w, offset 0x028, reset 0xffff.ffff (see page 494) tailr tailr march 20, 2011 1000 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gptmtbilr, type r/w, offset 0x02c, reset 0x0000.ffff (see page 495) tbilr tbilr gptmtamatchr, type r/w, offset 0x030, reset 0xffff.ffff (see page 496) tamr tamr gptmtbmatchr, type r/w, offset 0x034, reset 0x0000.ffff (see page 497) tbmr tbmr gptmtapr, type r/w, offset 0x038, reset 0x0000.0000 (see page 498) tapsr gptmtbpr, type r/w, offset 0x03c, reset 0x0000.0000 (see page 499) tbpsr gptmtapmr, type r/w, offset 0x040, reset 0x0000.0000 (see page 500) tapsmr gptmtbpmr, type r/w, offset 0x044, reset 0x0000.0000 (see page 501) tbpsmr gptmtar, type ro, offset 0x048, reset 0xffff.ffff (see page 502) tar tar gptmtbr, type ro, offset 0x04c, reset 0x0000.ffff (see page 503) tbr tbr gptmtav, type rw, offset 0x050, reset 0xffff.ffff (see page 504) tav tav gptmtbv, type rw, offset 0x054, reset 0x0000.ffff (see page 505) tbv tbv watchdog timers wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 wdtload, type r/w, offset 0x000, reset 0xffff.ffff (see page 510) wdtload wdtload wdtvalue, type ro, offset 0x004, reset 0xffff.ffff (see page 511) wdtvalue wdtvalue wdtctl, type r/w, offset 0x008, reset 0x0000.0000 (wdt0) and 0x8000.0000 (wdt1) (see page 512) wrc inten resen wdticr, type wo, offset 0x00c, reset - (see page 514) wdtintclr wdtintclr wdtris, type ro, offset 0x010, reset 0x0000.0000 (see page 515) wdtris 1001 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtmis, type ro, offset 0x014, reset 0x0000.0000 (see page 516) wdtmis wdttest, type r/w, offset 0x418, reset 0x0000.0000 (see page 517) stall wdtlock, type r/w, offset 0xc00, reset 0x0000.0000 (see page 518) wdtlock wdtlock wdtperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 (see page 519) pid4 wdtperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 (see page 520) pid5 wdtperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 (see page 521) pid6 wdtperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 (see page 522) pid7 wdtperiphid0, type ro, offset 0xfe0, reset 0x0000.0005 (see page 523) pid0 wdtperiphid1, type ro, offset 0xfe4, reset 0x0000.0018 (see page 524) pid1 wdtperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 (see page 525) pid2 wdtperiphid3, type ro, offset 0xfec, reset 0x0000.0001 (see page 526) pid3 wdtpcellid0, type ro, offset 0xff0, reset 0x0000.000d (see page 527) cid0 wdtpcellid1, type ro, offset 0xff4, reset 0x0000.00f0 (see page 528) cid1 wdtpcellid2, type ro, offset 0xff8, reset 0x0000.0006 (see page 529) cid2 wdtpcellid3, type ro, offset 0xffc, reset 0x0000.00b1 (see page 530) cid3 analog-to-digital converter (adc) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 adcactss, type r/w, offset 0x000, reset 0x0000.0000 (see page 553) asen0 asen1 asen2 asen3 march 20, 2011 1002 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adcris, type ro, offset 0x004, reset 0x0000.0000 (see page 554) inrdc inr0 inr1 inr2 inr3 adcim, type r/w, offset 0x008, reset 0x0000.0000 (see page 556) dconss0 dconss1 dconss2 dconss3 mask0 mask1 mask2 mask3 adcisc, type r/w1c, offset 0x00c, reset 0x0000.0000 (see page 558) dcinss0 dcinss1 dcinss2 dcinss3 in0 in1 in2 in3 adcostat, type r/w1c, offset 0x010, reset 0x0000.0000 (see page 561) ov0 ov1 ov2 ov3 adcemux, type r/w, offset 0x014, reset 0x0000.0000 (see page 563) em0 em1 em2 em3 adcustat, type r/w1c, offset 0x018, reset 0x0000.0000 (see page 568) uv0 uv1 uv2 uv3 adcsspri, type r/w, offset 0x020, reset 0x0000.3210 (see page 569) ss0 ss1 ss2 ss3 adcspc, type r/w, offset 0x024, reset 0x0000.0000 (see page 571) phase adcpssi, type r/w, offset 0x028, reset - (see page 573) syncwait gsync ss0 ss1 ss2 ss3 adcsac, type r/w, offset 0x030, reset 0x0000.0000 (see page 575) avg adcdcisc, type r/w1c, offset 0x034, reset 0x0000.0000 (see page 576) dcint0 dcint1 dcint2 dcint3 dcint4 dcint5 dcint6 dcint7 adcctl, type r/w, offset 0x038, reset 0x0000.0000 (see page 578) vref adcssmux0, type r/w, offset 0x040, reset 0x0000.0000 (see page 579) mux4 mux5 mux6 mux7 mux0 mux1 mux2 mux3 adcssctl0, type r/w, offset 0x044, reset 0x0000.0000 (see page 581) d4 end4 ie4 ts4 d5 end5 ie5 ts5 d6 end6 ie6 ts6 d7 end7 ie7 ts7 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssfifo0, type ro, offset 0x048, reset - (see page 584) data adcssfifo1, type ro, offset 0x068, reset - (see page 584) data adcssfifo2, type ro, offset 0x088, reset - (see page 584) data 1003 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adcssfifo3, type ro, offset 0x0a8, reset - (see page 584) data adcssfstat0, type ro, offset 0x04c, reset 0x0000.0100 (see page 585) tptr hptr empty full adcssfstat1, type ro, offset 0x06c, reset 0x0000.0100 (see page 585) tptr hptr empty full adcssfstat2, type ro, offset 0x08c, reset 0x0000.0100 (see page 585) tptr hptr empty full adcssfstat3, type ro, offset 0x0ac, reset 0x0000.0100 (see page 585) tptr hptr empty full adcssop0, type r/w, offset 0x050, reset 0x0000.0000 (see page 587) s4dcop s5dcop s6dcop s7dcop s0dcop s1dcop s2dcop s3dcop adcssdc0, type r/w, offset 0x054, reset 0x0000.0000 (see page 589) s4dcsel s5dcsel s6dcsel s7dcsel s0dcsel s1dcsel s2dcsel s3dcsel adcssmux1, type r/w, offset 0x060, reset 0x0000.0000 (see page 591) mux0 mux1 mux2 mux3 adcssmux2, type r/w, offset 0x080, reset 0x0000.0000 (see page 591) mux0 mux1 mux2 mux3 adcssctl1, type r/w, offset 0x064, reset 0x0000.0000 (see page 592) d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssctl2, type r/w, offset 0x084, reset 0x0000.0000 (see page 592) d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssop1, type r/w, offset 0x070, reset 0x0000.0000 (see page 594) s0dcop s1dcop s2dcop s3dcop adcssop2, type r/w, offset 0x090, reset 0x0000.0000 (see page 594) s0dcop s1dcop s2dcop s3dcop adcssdc1, type r/w, offset 0x074, reset 0x0000.0000 (see page 595) s0dcsel s1dcsel s2dcsel s3dcsel adcssdc2, type r/w, offset 0x094, reset 0x0000.0000 (see page 595) s0dcsel s1dcsel s2dcsel s3dcsel adcssmux3, type r/w, offset 0x0a0, reset 0x0000.0000 (see page 597) mux0 adcssctl3, type r/w, offset 0x0a4, reset 0x0000.0002 (see page 598) d0 end0 ie0 ts0 march 20, 2011 1004 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adcssop3, type r/w, offset 0x0b0, reset 0x0000.0000 (see page 599) s0dcop adcssdc3, type r/w, offset 0x0b4, reset 0x0000.0000 (see page 600) s0dcsel adcdcric, type r/w, offset 0xd00, reset 0x0000.0000 (see page 601) dctrig0 dctrig1 dctrig2 dctrig3 dctrig4 dctrig5 dctrig6 dctrig7 dcint0 dcint1 dcint2 dcint3 dcint4 dcint5 dcint6 dcint7 adcdcctl0, type r/w, offset 0xe00, reset 0x0000.0000 (see page 606) cim cic cie ctm ctc cte adcdcctl1, type r/w, offset 0xe04, reset 0x0000.0000 (see page 606) cim cic cie ctm ctc cte adcdcctl2, type r/w, offset 0xe08, reset 0x0000.0000 (see page 606) cim cic cie ctm ctc cte adcdcctl3, type r/w, offset 0xe0c, reset 0x0000.0000 (see page 606) cim cic cie ctm ctc cte adcdcctl4, type r/w, offset 0xe10, reset 0x0000.0000 (see page 606) cim cic cie ctm ctc cte adcdcctl5, type r/w, offset 0xe14, reset 0x0000.0000 (see page 606) cim cic cie ctm ctc cte adcdcctl6, type r/w, offset 0xe18, reset 0x0000.0000 (see page 606) cim cic cie ctm ctc cte adcdcctl7, type r/w, offset 0xe1c, reset 0x0000.0000 (see page 606) cim cic cie ctm ctc cte adcdccmp0, type r/w, offset 0xe40, reset 0x0000.0000 (see page 609) comp1 comp0 adcdccmp1, type r/w, offset 0xe44, reset 0x0000.0000 (see page 609) comp1 comp0 adcdccmp2, type r/w, offset 0xe48, reset 0x0000.0000 (see page 609) comp1 comp0 adcdccmp3, type r/w, offset 0xe4c, reset 0x0000.0000 (see page 609) comp1 comp0 adcdccmp4, type r/w, offset 0xe50, reset 0x0000.0000 (see page 609) comp1 comp0 adcdccmp5, type r/w, offset 0xe54, reset 0x0000.0000 (see page 609) comp1 comp0 1005 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adcdccmp6, type r/w, offset 0xe58, reset 0x0000.0000 (see page 609) comp1 comp0 adcdccmp7, type r/w, offset 0xe5c, reset 0x0000.0000 (see page 609) comp1 comp0 universal asynchronous receivers/transmitters (uarts) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 uartdr, type r/w, offset 0x000, reset 0x0000.0000 (see page 624) data fe pe be oe uartrsr/uartecr, type ro, offset 0x004, reset 0x0000.0000 (read-only status register) (see page 626) fe pe be oe uartrsr/uartecr, type wo, offset 0x004, reset 0x0000.0000 (write-only error clear register) (see page 626) data uartfr, type ro, offset 0x018, reset 0x0000.0090 (see page 629) cts dsr dcd busy rxfe txff rxff txfe ri uartilpr, type r/w, offset 0x020, reset 0x0000.0000 (see page 632) ilpdvsr uartibrd, type r/w, offset 0x024, reset 0x0000.0000 (see page 633) divint uartfbrd, type r/w, offset 0x028, reset 0x0000.0000 (see page 634) divfrac uartlcrh, type r/w, offset 0x02c, reset 0x0000.0000 (see page 635) brk pen eps stp2 fen wlen sps uartctl, type r/w, offset 0x030, reset 0x0000.0300 (see page 637) uarten siren sirlp smart eot hse lin lbe txe rxe dtr rts rtsen ctsen uartifls, type r/w, offset 0x034, reset 0x0000.0012 (see page 641) txiflsel rxiflsel uartim, type r/w, offset 0x038, reset 0x0000.0000 (see page 643) riim ctsim dcdim dsrim rxim txim rtim feim peim beim oeim lmsbim lme1im lme5im uartris, type ro, offset 0x03c, reset 0x0000.000f (see page 647) riris ctsris dcdris dsrris rxris txris rtris feris peris beris oeris lmsbris lme1ris lme5ris uartmis, type ro, offset 0x040, reset 0x0000.0000 (see page 650) rimis ctsmis dcdmis dsrmis rxmis txmis rtmis femis pemis bemis oemis lmsbmis lme1mis lme5mis uarticr, type w1c, offset 0x044, reset 0x0000.0000 (see page 653) rimic ctsmic dcdmic dsrmic rxic txic rtic feic peic beic oeic lmsbmic lme1mic lme5mic march 20, 2011 1006 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uartdmactl, type r/w, offset 0x048, reset 0x0000.0000 (see page 655) rxdmae txdmae dmaerr uartlctl, type r/w, offset 0x090, reset 0x0000.0000 (see page 656) master blen uartlss, type ro, offset 0x094, reset 0x0000.0000 (see page 657) tss uartltim, type ro, offset 0x098, reset 0x0000.0000 (see page 658) timer uartperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 (see page 659) pid4 uartperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 (see page 660) pid5 uartperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 (see page 661) pid6 uartperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 (see page 662) pid7 uartperiphid0, type ro, offset 0xfe0, reset 0x0000.0060 (see page 663) pid0 uartperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 (see page 664) pid1 uartperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 (see page 665) pid2 uartperiphid3, type ro, offset 0xfec, reset 0x0000.0001 (see page 666) pid3 uartpcellid0, type ro, offset 0xff0, reset 0x0000.000d (see page 667) cid0 uartpcellid1, type ro, offset 0xff4, reset 0x0000.00f0 (see page 668) cid1 uartpcellid2, type ro, offset 0xff8, reset 0x0000.0005 (see page 669) cid2 uartpcellid3, type ro, offset 0xffc, reset 0x0000.00b1 (see page 670) cid3 1007 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 synchronous serial interface (ssi) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 ssicr0, type r/w, offset 0x000, reset 0x0000.0000 (see page 687) dss frf spo sph scr ssicr1, type r/w, offset 0x004, reset 0x0000.0000 (see page 689) lbm sse ms sod eot ssidr, type r/w, offset 0x008, reset 0x0000.0000 (see page 691) data ssisr, type ro, offset 0x00c, reset 0x0000.0003 (see page 692) tfe tnf rne rff bsy ssicpsr, type r/w, offset 0x010, reset 0x0000.0000 (see page 694) cpsdvsr ssiim, type r/w, offset 0x014, reset 0x0000.0000 (see page 695) rorim rtim rxim txim ssiris, type ro, offset 0x018, reset 0x0000.0008 (see page 696) rorris rtris rxris txris ssimis, type ro, offset 0x01c, reset 0x0000.0000 (see page 698) rormis rtmis rxmis txmis ssiicr, type w1c, offset 0x020, reset 0x0000.0000 (see page 700) roric rtic ssidmactl, type r/w, offset 0x024, reset 0x0000.0000 (see page 701) rxdmae txdmae ssiperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 (see page 702) pid4 ssiperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 (see page 703) pid5 ssiperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 (see page 704) pid6 ssiperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 (see page 705) pid7 ssiperiphid0, type ro, offset 0xfe0, reset 0x0000.0022 (see page 706) pid0 ssiperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 (see page 707) pid1 march 20, 2011 1008 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ssiperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 (see page 708) pid2 ssiperiphid3, type ro, offset 0xfec, reset 0x0000.0001 (see page 709) pid3 ssipcellid0, type ro, offset 0xff0, reset 0x0000.000d (see page 710) cid0 ssipcellid1, type ro, offset 0xff4, reset 0x0000.00f0 (see page 711) cid1 ssipcellid2, type ro, offset 0xff8, reset 0x0000.0005 (see page 712) cid2 ssipcellid3, type ro, offset 0xffc, reset 0x0000.00b1 (see page 713) cid3 inter-integrated circuit (i 2 c) interface i 2 c master i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 i2cmsa, type r/w, offset 0x000, reset 0x0000.0000 r/s sa i2cmcs, type ro, offset 0x004, reset 0x0000.0000 (read-only status register) busy error adrack datack arblst idle busbsy i2cmcs, type wo, offset 0x004, reset 0x0000.0000 (write-only control register) run start stop ack i2cmdr, type r/w, offset 0x008, reset 0x0000.0000 data i2cmtpr, type r/w, offset 0x00c, reset 0x0000.0001 tpr i2cmimr, type r/w, offset 0x010, reset 0x0000.0000 im i2cmris, type ro, offset 0x014, reset 0x0000.0000 ris i2cmmis, type ro, offset 0x018, reset 0x0000.0000 mis i2cmicr, type wo, offset 0x01c, reset 0x0000.0000 ic i2cmcr, type r/w, offset 0x020, reset 0x0000.0000 lpbk mfe sfe 1009 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 inter-integrated circuit (i 2 c) interface i 2 c slave i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 i2csoar, type r/w, offset 0x800, reset 0x0000.0000 oar i2cscsr, type ro, offset 0x804, reset 0x0000.0000 (read-only status register) rreq treq fbr i2cscsr, type wo, offset 0x804, reset 0x0000.0000 (write-only control register) da i2csdr, type r/w, offset 0x808, reset 0x0000.0000 data i2csimr, type r/w, offset 0x80c, reset 0x0000.0000 dataim startim stopim i2csris, type ro, offset 0x810, reset 0x0000.0000 dataris startris stopris i2csmis, type ro, offset 0x814, reset 0x0000.0000 datamis startmis stopmis i2csicr, type wo, offset 0x818, reset 0x0000.0000 dataic startic stopic inter-integrated circuit sound (i 2 s) interface base 0x4005.4000 i2stxfifo, type wo, offset 0x000, reset 0x0000.0000 (see page 764) txfifo txfifo i2stxfifocfg, type r/w, offset 0x004, reset 0x0000.0000 (see page 765) lrs css i2stxcfg, type r/w, offset 0x008, reset 0x1400.7df0 (see page 766) msl fmt wm lrp scp dly jst sdsz ssz i2stxlimit, type r/w, offset 0x00c, reset 0x0000.0000 (see page 768) limit i2stxism, type r/w, offset 0x010, reset 0x0000.0000 (see page 769) ffi ffm i2stxlev, type ro, offset 0x018, reset 0x0000.0000 (see page 770) level i2srxfifo, type ro, offset 0x800, reset 0x0000.0000 (see page 771) rxfifo rxfifo march 20, 2011 1010 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i2srxfifocfg, type r/w, offset 0x804, reset 0x0000.0000 (see page 772) lrs css fmm i2srxcfg, type r/w, offset 0x808, reset 0x1400.7df0 (see page 773) msl rm lrp scp dly jst sdsz ssz i2srxlimit, type r/w, offset 0x80c, reset 0x0000.7fff (see page 775) limit i2srxism, type r/w, offset 0x810, reset 0x0000.0000 (see page 776) ffi ffm i2srxlev, type ro, offset 0x818, reset 0x0000.0000 (see page 777) level i2scfg, type r/w, offset 0xc00, reset 0x0000.0000 (see page 778) txen rxen txslv rxslv i2sim, type r/w, offset 0xc10, reset 0x0000.0000 (see page 780) txsrim txweim rxsrim rxreim i2sris, type ro, offset 0xc14, reset 0x0000.0000 (see page 782) txsrris txweris rxsrris rxreris i2smis, type ro, offset 0xc18, reset 0x0000.0000 (see page 784) txsrmis txwemis rxsrmis rxremis i2sic, type wo, offset 0xc1c, reset 0x0000.0000 (see page 786) txweic rxreic analog comparators base 0x4003.c000 acmis, type r/w1c, offset 0x000, reset 0x0000.0000 (see page 793) in0 in1 acris, type ro, offset 0x004, reset 0x0000.0000 (see page 794) in0 in1 acinten, type r/w, offset 0x008, reset 0x0000.0000 (see page 795) in0 in1 acrefctl, type r/w, offset 0x010, reset 0x0000.0000 (see page 796) vref rng en acstat0, type ro, offset 0x020, reset 0x0000.0000 (see page 797) oval acstat1, type ro, offset 0x040, reset 0x0000.0000 (see page 797) oval acctl0, type r/w, offset 0x024, reset 0x0000.0000 (see page 798) cinv isen islval tsen tslval asrcp toen 1011 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 acctl1, type r/w, offset 0x044, reset 0x0000.0000 (see page 798) cinv isen islval tsen tslval asrcp toen pulse width modulator (pwm) pwm0 base: 0x4002.8000 pwmctl, type r/w, offset 0x000, reset 0x0000.0000 (see page 815) globalsync0 globalsync1 globalsync2 pwmsync, type r/w, offset 0x004, reset 0x0000.0000 (see page 816) sync0 sync1 sync2 pwmenable, type r/w, offset 0x008, reset 0x0000.0000 (see page 817) pwm0en pwm1en pwm2en pwm3en pwm4en pwm5en pwminvert, type r/w, offset 0x00c, reset 0x0000.0000 (see page 819) pwm0inv pwm1inv pwm2inv pwm3inv pwm4inv pwm5inv pwmfault, type r/w, offset 0x010, reset 0x0000.0000 (see page 821) fault0 fault1 fault2 fault3 fault4 fault5 pwminten, type r/w, offset 0x014, reset 0x0000.0000 (see page 823) intfault0 intfault1 intfault2 intfault3 intpwm0 intpwm1 intpwm2 pwmris, type ro, offset 0x018, reset 0x0000.0000 (see page 825) intfault0 intfault1 intfault2 intfault3 intpwm0 intpwm1 intpwm2 pwmisc, type r/w1c, offset 0x01c, reset 0x0000.0000 (see page 827) intfault0 intfault1 intfault2 intfault3 intpwm0 intpwm1 intpwm2 pwmstatus, type ro, offset 0x020, reset 0x0000.0000 (see page 829) fault0 fault1 fault2 fault3 pwmfaultval, type r/w, offset 0x024, reset 0x0000.0000 (see page 831) pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwmenupd, type r/w, offset 0x028, reset 0x0000.0000 (see page 833) enupd0 enupd1 enupd2 enupd3 enupd4 enupd5 pwm0ctl, type r/w, offset 0x040, reset 0x0000.0000 (see page 836) fltsrc minfltper latch enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd pwm1ctl, type r/w, offset 0x080, reset 0x0000.0000 (see page 836) fltsrc minfltper latch enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd pwm2ctl, type r/w, offset 0x0c0, reset 0x0000.0000 (see page 836) fltsrc minfltper latch enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd pwm0inten, type r/w, offset 0x044, reset 0x0000.0000 (see page 841) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd pwm1inten, type r/w, offset 0x084, reset 0x0000.0000 (see page 841) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd march 20, 2011 1012 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm2inten, type r/w, offset 0x0c4, reset 0x0000.0000 (see page 841) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd pwm0ris, type ro, offset 0x048, reset 0x0000.0000 (see page 844) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm1ris, type ro, offset 0x088, reset 0x0000.0000 (see page 844) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm2ris, type ro, offset 0x0c8, reset 0x0000.0000 (see page 844) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm0isc, type r/w1c, offset 0x04c, reset 0x0000.0000 (see page 846) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm1isc, type r/w1c, offset 0x08c, reset 0x0000.0000 (see page 846) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm2isc, type r/w1c, offset 0x0cc, reset 0x0000.0000 (see page 846) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm0load, type r/w, offset 0x050, reset 0x0000.0000 (see page 848) load pwm1load, type r/w, offset 0x090, reset 0x0000.0000 (see page 848) load pwm2load, type r/w, offset 0x0d0, reset 0x0000.0000 (see page 848) load pwm0count, type ro, offset 0x054, reset 0x0000.0000 (see page 849) count pwm1count, type ro, offset 0x094, reset 0x0000.0000 (see page 849) count pwm2count, type ro, offset 0x0d4, reset 0x0000.0000 (see page 849) count pwm0cmpa, type r/w, offset 0x058, reset 0x0000.0000 (see page 850) compa pwm1cmpa, type r/w, offset 0x098, reset 0x0000.0000 (see page 850) compa pwm2cmpa, type r/w, offset 0x0d8, reset 0x0000.0000 (see page 850) compa pwm0cmpb, type r/w, offset 0x05c, reset 0x0000.0000 (see page 851) compb 1013 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm1cmpb, type r/w, offset 0x09c, reset 0x0000.0000 (see page 851) compb pwm2cmpb, type r/w, offset 0x0dc, reset 0x0000.0000 (see page 851) compb pwm0gena, type r/w, offset 0x060, reset 0x0000.0000 (see page 852) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm1gena, type r/w, offset 0x0a0, reset 0x0000.0000 (see page 852) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm2gena, type r/w, offset 0x0e0, reset 0x0000.0000 (see page 852) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm0genb, type r/w, offset 0x064, reset 0x0000.0000 (see page 855) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm1genb, type r/w, offset 0x0a4, reset 0x0000.0000 (see page 855) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm2genb, type r/w, offset 0x0e4, reset 0x0000.0000 (see page 855) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm0dbctl, type r/w, offset 0x068, reset 0x0000.0000 (see page 858) enable pwm1dbctl, type r/w, offset 0x0a8, reset 0x0000.0000 (see page 858) enable pwm2dbctl, type r/w, offset 0x0e8, reset 0x0000.0000 (see page 858) enable pwm0dbrise, type r/w, offset 0x06c, reset 0x0000.0000 (see page 859) risedelay pwm1dbrise, type r/w, offset 0x0ac, reset 0x0000.0000 (see page 859) risedelay pwm2dbrise, type r/w, offset 0x0ec, reset 0x0000.0000 (see page 859) risedelay pwm0dbfall, type r/w, offset 0x070, reset 0x0000.0000 (see page 860) falldelay pwm1dbfall, type r/w, offset 0x0b0, reset 0x0000.0000 (see page 860) falldelay pwm2dbfall, type r/w, offset 0x0f0, reset 0x0000.0000 (see page 860) falldelay march 20, 2011 1014 texas instruments-advance information register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0fltsrc0, type r/w, offset 0x074, reset 0x0000.0000 (see page 861) fault0 fault1 fault2 fault3 pwm1fltsrc0, type r/w, offset 0x0b4, reset 0x0000.0000 (see page 861) fault0 fault1 fault2 fault3 pwm2fltsrc0, type r/w, offset 0x0f4, reset 0x0000.0000 (see page 861) fault0 fault1 fault2 fault3 pwm0fltsrc1, type r/w, offset 0x078, reset 0x0000.0000 (see page 863) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm1fltsrc1, type r/w, offset 0x0b8, reset 0x0000.0000 (see page 863) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm2fltsrc1, type r/w, offset 0x0f8, reset 0x0000.0000 (see page 863) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm0minfltper, type r/w, offset 0x07c, reset 0x0000.0000 (see page 866) mfp pwm1minfltper, type r/w, offset 0x0bc, reset 0x0000.0000 (see page 866) mfp pwm2minfltper, type r/w, offset 0x0fc, reset 0x0000.0000 (see page 866) mfp pwm0fltsen, type r/w, offset 0x800, reset 0x0000.0000 (see page 867) fault0 fault1 fault2 fault3 pwm1fltsen, type r/w, offset 0x880, reset 0x0000.0000 (see page 867) fault0 fault1 fault2 fault3 pwm2fltsen, type r/w, offset 0x900, reset 0x0000.0000 (see page 867) fault0 fault1 fault2 fault3 pwm3fltsen, type r/w, offset 0x980, reset 0x0000.0000 (see page 867) fault0 fault1 fault2 fault3 pwm0fltstat0, type -, offset 0x804, reset 0x0000.0000 (see page 868) fault0 fault1 fault2 fault3 pwm1fltstat0, type -, offset 0x884, reset 0x0000.0000 (see page 868) fault0 fault1 fault2 fault3 pwm2fltstat0, type -, offset 0x904, reset 0x0000.0000 (see page 868) fault0 fault1 fault2 fault3 pwm0fltstat1, type -, offset 0x808, reset 0x0000.0000 (see page 870) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 1015 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm1fltstat1, type -, offset 0x888, reset 0x0000.0000 (see page 870) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm2fltstat1, type -, offset 0x908, reset 0x0000.0000 (see page 870) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 quadrature encoder interface (qei) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 qeictl, type r/w, offset 0x000, reset 0x0000.0000 (see page 880) filtcnt enable swap sigmode capmode resmode velen veldiv inva invb invi stallen filten qeistat, type ro, offset 0x004, reset 0x0000.0000 (see page 883) error direction qeipos, type r/w, offset 0x008, reset 0x0000.0000 (see page 884) position position qeimaxpos, type r/w, offset 0x00c, reset 0x0000.0000 (see page 885) maxpos maxpos qeiload, type r/w, offset 0x010, reset 0x0000.0000 (see page 886) load load qeitime, type ro, offset 0x014, reset 0x0000.0000 (see page 887) time time qeicount, type ro, offset 0x018, reset 0x0000.0000 (see page 888) count count qeispeed, type ro, offset 0x01c, reset 0x0000.0000 (see page 889) speed speed qeiinten, type r/w, offset 0x020, reset 0x0000.0000 (see page 890) intindex inttimer intdir interror qeiris, type ro, offset 0x024, reset 0x0000.0000 (see page 892) intindex inttimer intdir interror qeiisc, type r/w1c, offset 0x028, reset 0x0000.0000 (see page 894) intindex inttimer intdir interror march 20, 2011 1016 texas instruments-advance information register quick reference b ordering and contact information b.1 ordering information table b-1. part ordering information description orderable part number stellaris ? lm3s1p51 microcontroller industrial temperature 100-pin lqfp lm3s1p51-iqc80-c5 stellaris lm3s1p51 microcontroller industrial temperature 108-ball bga lm3s1p51-ibz80-c5 stellaris lm3s1p51 microcontroller industrial temperature 100-pin lqfp tape-and-reel lm3s1p51-iqc80-c5t stellaris lm3s1p51 microcontroller industrial temperature 108-ball bga tape-and-reel lm3s1p51-ibz80-c5t b.2 part markings the stellaris microcontrollers are marked with an identifying number. this code contains the following information: the first line indicates the part number. in the example figure below, this is the lm3s9b90. in the second line, the first seven characters indicate the temperature, package, speed, and revision. in the example below, this is an industrial temperature (i), 100-pin lqfp package (qc), 80-mhz (80), revision c0 (c0) device. the remaining characters contain internal tracking numbers. 1017 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller / 0 6 q q q q j s s v v u u p 3 d u w 1 x p e h u 7 h p s h u d w x u h 3 d f n d j h 6 s h h g 5 h y l v l r q 6 k l s s l q j 0 h g l x p ( ? & w r ? & , ? & w r ? & 7 7 d s h d q g u h h o 2 p l w w h g ' h i d x o w v k l s s l q j w u d \ r u w x e h % = e d o o % * $ 4 & s l q / 4 ) 3 4 1 s l q / 4 ) 3 4 5 s l q / 4 ) 3 * = s l q 4 ) 1 0 + ] 0 + ] 0 + ] 0 + ] q q q 6 d q g v w r u p f o d v v s d u w v q q q q $ o o r w k h u 6 w h o o d u l v ? s d u w v b.3 kits the stellaris family provides the hardware and software tools that engineers need to begin development quickly. reference design kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files evaluation kits provide a low-cost and effective means of evaluating stellaris microcontrollers before purchase development kits provide you with all the tools you need to develop and prototype embedded applications right out of the box see the website at www.ti.com/stellaris for the latest tools available, or ask your distributor. b.4 support information for support on stellaris products, contact the ti worldwide product information center nearest you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm. march 20, 2011 1018 texas instruments-advance information ordering and contact information c package information c.1 100-pin lqfp package c.1.1 package dimensions figure c-1. 100-pin lqfp package dimensions note: the following notes apply to the package drawing. 1. all dimensions shown in mm. 2. dimensions shown are nominal with tolerances indicated. 3. foot length 'l' is measured at gage plane 0.25 mm above seating plane. 1019 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller body +2.00 mm footprint, 1.4 mm package thickness 100l leads symbols 1.60 max. a 0.05 min./0.15 max. - a 1 1.40 0.05 a 2 16.00 0.20 d 14.00 0.05 d 1 16.00 0.20 e 14.00 0.05 e 1 0.60 +0.15/-0.10 l 0.50 basic e 0.22 +0.05 b 0?-7? - 0.08 max. ddd 0.08 max. ccc ms-026 jedec reference drawing bed variation designator march 20, 2011 1020 texas instruments-advance information package information c.1.2 tray dimensions figure c-2. 100-pin lqfp tray dimensions c.1.3 tape and reel dimensions note: in the figure that follows, pin 1 is located in the top right corner of the device. 1021 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller figure c-3. 100-pin lqfp tape and reel dimensions march 20, 2011 1022 texas instruments-advance information package information printed on must not be reproduced without written permission from sumicarrier (s) pte ltd 06.01.2003 this is a computer generated uncontrolled document 06.01.2003 06.01.2003 06.01.2003 06.01.2003 c.2 108-ball bga package c.2.1 package dimensions figure c-4. 108-ball bga package dimensions 1023 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller note: the following notes apply to the package drawing. max nom min symbols 1.50 1.36 1.22 a 0.39 0.34 0.29 a1 0.75 0.70 0.65 a3 0.36 0.32 0.28 c 10.15 10.00 9.85 d 8.80 bsc d1 10.15 10.00 9.85 e 8.80 bsc e1 0.53 0.48 0.43 b .20 bbb .12 ddd 0.80 bsc e - 0.60 - f 12 m 108 n ref: jedec mo-219f march 20, 2011 1024 texas instruments-advance information package information c.2.2 tray dimensions figure c-5. 108-ball bga tray dimensions 1025 march 20, 2011 texas instruments-advance information stellaris? lm3s1p51 microcontroller c.2.3 tape and reel dimensions figure c-6. 108-ball bga tape and reel dimensions march 20, 2011 1026 texas instruments-advance information package information c-pak pte ltd package option addendum www.ti.com 21-may-2011 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) LM3S1P51-IBZ80-C3 active lqfp pz 100 184 tbd call ti call ti LM3S1P51-IBZ80-C3t active lqfp pz 100 1500 tbd call ti call ti lm3s1p51-ibz80-c5 active nfbga zcr 108 184 green (rohs & no sb/br) snagcu level-3-260c-168 hr lm3s1p51-ibz80-c5t active nfbga zcr 108 1500 green (rohs & no sb/br) snagcu level-3-260c-168 hr lm3s1p51-iqc80-c1 active lqfp pz 100 tbd call ti call ti lm3s1p51-iqc80-c3 active lqfp pz 100 90 green (rohs & no sb/br) level-3-260c-168 hr lm3s1p51-iqc80-c3t active lqfp pz 100 1000 green (rohs & no sb/br) level-3-260c-168 hr lm3s1p51-iqc80-c5 active lqfp pz 100 90 green (rohs & no sb/br) level-3-260c-168 hr lm3s1p51-iqc80-c5t active lqfp pz 100 1000 green (rohs & no sb/br) level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. package option addendum www.ti.com 21-may-2011 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. mechanical data mtqf013a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pz (s-pqfp-g100) plastic quad flatpack 4040149 /b 11/96 50 26 0,13 nom gage plane 0,25 0,45 0,75 0,05 min 0,27 51 25 75 1 12,00 typ 0,17 76 100 sq sq 15,80 16,20 13,80 1,35 1,45 1,60 max 14,20 0 7 seating plane 0,08 0,50 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti ? s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or " enhanced plastic. " only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer ' s risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications audio www.ti.com/audio communications and telecom www.ti.com/communications amplifiers amplifier.ti.com computers and peripherals www.ti.com/computers data converters dataconverter.ti.com consumer electronics www.ti.com/consumer-apps dlp ? products www.dlp.com energy and lighting www.ti.com/energy dsp dsp.ti.com industrial www.ti.com/industrial clocks and timers www.ti.com/clocks medical www.ti.com/medical interface interface.ti.com security www.ti.com/security logic logic.ti.com space, avionics and defense www.ti.com/space-avionics-defense power mgmt power.ti.com transportation and www.ti.com/automotive automotive microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com wireless www.ti.com/wireless-apps rf/if and zigbee ? solutions www.ti.com/lprf ti e2e community home page e2e.ti.com mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2011, texas instruments incorporated |
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