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motorola semiconductor technical data order number: mpc962308 rev 2, 02/2004 ? motorola, inc. 2004 3.3v zero delay buffer the mpc962308 is a 3.3v zero delay buffer designed to distribute high- speed clocks in pc, workstation, datacom, telecom and other high-perfor- mance applications. the mpc962308 uses an internal pll and an external feedback path to lock its low?skew clock output phase to the reference clock phase, providing virtually zero propagation delay. the input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guar- anteed to be less than 200 ps. features 1:8 outputs lvcmos zero-delay buffer zero input-output propagation delay, adjustable by the capacitive load on fbk input multiple configurations, see ?available mpc962308 configurations? table multiple low-skew outputs ? 200 ps max output-output skew ? 700 ps max device-device skew ? two banks of four outputs, output tristate control by two select inputs supports a clock i/o frequency range of 10mhz to 133mhz low jitter, 200 ps max cycle-cycle (-1, -1h, -4, -5h) 250 ps static phase offset (spo) 16-pin soic package or 16-pin tssop package single 3.3v supply ambient temperature range: -40 c to +85 c compatible with the cy2308 and cy23s08 spread spectrum compatible functional description the mpc962308 has two banks of four outputs each which can be controlled by the select inputs as shown in the table ?selected input decoding.? bank b can be tristated if all of the outputs are not required. the select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. the mpc962308 pll en- ters a power down state when there are no rising edges on the ref input. during this state, all of the outputs are in tristate and there is less than 50 a of current draw. the pll shuts down in two additional cases explained in the ?select input decoding? table. multiple mpc962308 devices can accept and distribute the same input clock throughout the system. in this situation, the difference between the output skews of two devices will be less than 700 ps. the mpc962308 is available in five different configurations as shown in the ?available mpc962308 configurations? table. in the mpc962308-1, the reference frequency is reproduced by the pll and provided at the outputs. a high drive version of this configuration, the mpc962308-1h, is available to provide faster rise and fall times of the device. the mpc962308-2 provides 2x and 1x the reference frequency at the output banks. in addition, the mpc962308-3 provides 4x and 2x the reference frequency at the output banks. the output banks driving the feedback will determine the different configurations of the above devices. the mpc962308-4 provides outputs 2x the reference frequency.the mpc962308-5h is a high drive version with outputs of ref/2. the mpc962308 is fully 3.3v compatible and requires no external components for the internal pll. all inputs accept lvcmos signals while the outputs provide lvcmos compatible levels with the capability to drive terminated 50 ? trans- mission lines on the incident edge. depending on the configuration, the device is offered in a 16-lead soic or 16-lead tssop package. mpc962308 dt suffix 16 lead tssop package case 948f d suffix 16 lead soic package case 751b
mpc962308 2 3.3v zero delay buffer motorola notes: 1. outputs inverted on mpc962308-2 in bypass mode, s2=1 and s1=0. notes: 2. output phase is indeterminant (0 or 180 from input clock). if phase integrity is required, use the mpc962308-2. table 1. select input decoding s2 s1 clock a1?a4 clock b1?b4 output source pll shutdown 0 0 three-state three-state pll y 0 1 driven three-state pll n 10 driven [1] driven [1] reference y 1 1 driven driven pll n table 2. available mpc962308 configurations device feedback from bank a frequency bank b frequency mpc962308?1 bank a or bank b reference reference mpc962308?1h bank a or bank b reference reference mpc962308?2 bank a reference reference/2 mpc962308?2 bank b 2 x reference reference mpc962308?3 bank a 2 x reference reference or reference [2] mpc962308?3 bank b 4 x reference 2 x reference mpc962308?4 bank a or bank b 2 x reference 2 x reference mpc962308?5h bank a or bank b reference /2 reference /2 soic/tssop top view pin configuration clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 fbk pll mux /2 select input decoding /2 /2 s2 s1 ref extra divider (-3, -4) extra divider (-5h) extra divider (-2, -3) block diagram 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 fbk clka4 clka3 v dd gnd clkb4 clkb3 s1 ref clka1 clka2 v dd gnd clkb1 clkb2 s2
mpc962308 motorola 3.3v zero delay buffer 3 notes: 3. weak pull-down. 4. weak pull-down on all outputs. 5. weak pull-ups on these inputs. table 3. pin description pin signal description 1 ref [3] input reference frequency, 5v tolerant input 2 clka1 [4] clock output, bank a 3 clka2 [4] clock output, bank a 4 v dd 3.3v supply 5 gnd ground 6 clkb1 [4] clock output, bank b 7 clkb2 [4] clock output, bank b 8 s2 [5] select input, bit 2 9 s1 [5] select input, bit 1 10 clkb3 [4] clock output, bank b 11 clkb4 [4] clock output, bank b 12 gnd ground 13 v dd 3.3v supply 14 clka3 [4] clock output, bank a 15 clka4 [4] clock output, bank a 16 fbk pll feedback input table 4. maximum ratings characteristics value unit supply voltage to ground potential ?0.5 to +3.9 v dc input voltage (except ref) ?0.5 to v dd +0.5 v dc input voltage ref ?0.5 to 5.5 v storage temperature ?65 to +150 c junction 150 c static discharge voltage (per mil-std-883, method 3015) >2000 v
mpc962308 4 3.3v zero delay buffer motorola notes: 6. applies to both ref clock and fbk. notes: 7. parameter is guaranteed by design and characterization. not 100% tested in production. 8. all parameters are specified with loaded outputs. table 5. operating conditions for mpc962308-xx industrial temperature devices parameter description min. max. unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) -40 85 c c l load capacitance, below 100 mhz 30 pf load capacitance, from 100 mhz to 133 mhz 15 pf c in input capacitance [6] 7pf table 6. electrical characteristics for mpc962308-xx industrial temperature devices [8] parameter description test conditions min. max. unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage [7] i ol = 8 ma (-1, -2, -3, -4) i ol = 12 ma (-1h, -5h) 0.4 v v oh output high voltage [7] i oh = -8 ma (-1, -2, -3, -4) i oh = -12 ma (-1h, -5h) 2.4 v i dd (pd mode) power down supply current ref = 0 mhz 25.0 a i dd supply current unloaded outputs, 100 mhz, select inputs at v dd or gnd 45.0 ma 70(-1h, -5h) ma unloaded outputs, 66-mhz ref (-1, -2, -3, -4) 35.0 ma unloaded outputs, 35-mhz ref (-1, -2, -3, -4) 20.0 ma
mpc962308 motorola 3.3v zero delay buffer 5 notes: 9. parameter is guaranteed by design and characterization. not 100% tested in production. 10. all parameters are specified with loaded outputs. table 7. switching characteristics for mpc962308-xx industrial temperature devices [10] parameter name test conditions min. typ. max. unit t 1 output frequency 30-pf load, all devices 10 100 mhz t 1 output frequency 20-pf load, -1h, -5h devices [9] 10 133.3 mhz t 1 output frequency 15-pf load, -1, -2, -3, -4 devices [9] 10 133.3 mhz duty cycle = t 2 b t 1 (-1, -2, -3, -4, -1h, -5h) measured at 1.4v, f out =66.66 mhz 30-pf load [9] 40.0 60.0 % duty cycle = t 2 b t 1 ( -1, -2, -3, -4, -1h, -5h) measured at 1.4v, f out <50.0 mhz 15-pf load [9] 40.0 60.0 % t 3 rise time ( -1, -2, -3, -4) measured between 0.8v and 2.0v, 30-pf load [9] 2.50 ns rise time ( -1, -2, -3, -4) measured between 0.8v and 2.0v, 15-pf load [9] 1.50 ns rise time ( -1h, -5h) measured between 0.8v and 2.0v, 30-pf load [9] 1.50 ns t 4 fall time ( -1, -2, -3, -4) measured between 0.8v and 2.0v, 30-pf load [9] 2.50 ns fall time ( -1, -2, -3, -4) measured between 0.8v and 2.0v, 15-pf load [9] 1.50 ns fall time ( -1h, -5h) measured between 0.8v and 2.0v, 30-pf load [9] 1.25 ns output to output skew on same bank ( -1, -2, -3, -4) all outputs equally loaded [9] 200 ps t 5 output to output skew ( -1h, -5h) all outputs equally loaded 200 ps output bank a to output bank b skew ( -1, -4, -5h) all outputs equally loaded 200 ps output bank a to output bank b skew ( -2, -3) all outputs equally loaded 400 ps t 6 delay, ref rising edge to fbk rising edge measured at v dd /2 [9] 0 " 250 ps t 7 device to device skew measured at v dd /2 on the fbk pins of devices [9] 0 700 ps t 8 output slew rate measured between 0.8v and 2.0v on -1h, -5h device using test circuit # 2 [9] 1 v/ns t j cycle to cycle jitter ( -1, -1h, -4, -5h) measured at 66.67 mhz, loaded outputs, 15-pf load [9] 200 ps measured at 66.67 mhz, loaded outputs, 30-pf load [9] 200 ps measured at 133.3 mhz, loaded outputs, 15 pf load [9] 100 ps t j cycle to cycle jitter ( -2, -3) measured at 66.67 mhz, loaded outputs 30-pf load [9] 400 ps measured at 66.67 mhz, loaded outputs 15-pf load [9] 400 ps t lock pll lock time stable power supply, valid clocks presented on ref and fbk pins [9] 1.0 ms
mpc962308 6 3.3v zero delay buffer motorola applications information figure 1. output-to-output skew t sk(o) figure 2. propagation delay (t pd , static phase offset) test reference figure 3. output duty cycle (dc) figure 4. i/o jitter the pin-to-pin skew is defined as the worst case dif- ference in propagation delay between any similar de- lay path within a single device the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc v cc b 2 gnd v cc v cc b 2 gnd t sk(o) v cc v cc b 2 gnd t p t 0 dc = t p /t 0 x 100% v cc v cc b 2 gnd v cc v cc b 2 gnd t ( ? ) cclk fb_in t jit( ? ) = | t 0 -t 1 mean | cclk fb_in the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles figure 5. cycle-to-cycle jitter table 6. period jitter the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs the deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles t n t jit(cc) = | t n -t n+1 | t n+1 t jit(per) = | t n -1 / f 0 | t 0 t f t r v cc =3.3v 2.4 0.55 figure 7. output transition time test reference figure 8. setup and hold time (t s , t h ) test reference v cc v cc b 2 gnd t s cclk clk_stop v cc v cc b 2 gnd t h
mpc962308 motorola 3.3v zero delay buffer 7 ordering information (available) ordering code package name package type mpc962308d?1 d16 16-pin 150-mil soic mpc962308d?1r2 d16 16-pin 150-mil soic - tape and reel mpc962308d?1h d16 16-pin 150-mil soic mpc962308d?1hr2 d16 16-pin 150-mil soic - tape and reel mpc962308dt?1h dt16 16-pin 150-mil tssop mpc962308dt?1hr2 dt16 16-pin 150-mil tssop - tape and reel mpc962308d?2 d16 16-pin 150-mil soic mpc962308d?2r2 d16 16-pin 150-mil soic - tape and reel ordering information (planned) ordering code package name package type mpc962308d?3 d16 16-pin 150-mil soic mpc962308d?3r2 d16 16-pin 150-mil soic - tape and reel mpc962308d?4 d16 16-pin 150-mil soic mpc962308d?4r2 d16 16-pin 150-mil soic - tape and reel mpc962308d?5h d16 16-pin 150-mil soic mpc962308d?5hr2 d16 16-pin 150-mil soic - tape and reel mpc962308dt?5h dt16 16-pin 150-mil tssop mpc962308dt?5hr2 dt16 16-pin 150-mil tssop - tape and reel 0.1 f 0.1 f clk out c load v dd v dd outputs gnd gnd test circuit #1 test circuit for all parameters ex- cept t 8 0.1 f 0.1 f clk out 10 pf v dd v dd outputs gnd gnd test circuit #2 test circuit for t 8 , output slew rate on -1h, -5 device 1 k ? 1 k ?
mpc962308 8 3.3v zero delay buffer motorola package dimensions seating plane 0.49 16x b m 0.25 a t 0.35 1.75 1.35 0.25 0.10 6 t 16x 0.1 t 1.27 14x 89 116 8x 6.2 5.8 m 0.25 b 4 10.0 9.8 a 4.0 3.8 b pin 1 index pin's number 5 a a 0.50 x45? 0.25 7? 1.25 0.40 0? 0.25 0.19 section a-a notes: 1. dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. datums a and b to be determined at the plane where the bottom of the leads exit the plastic body. 4. this dimension does not include mold flash, protrusion or gate burrs. mold flash, protrusion or gate burrs shall not exceed 0.15mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 5. this dimension does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 6. this dimension does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed 0.62mm. d suffix 16 lead soic package case 751b-05 issue k
mpc962308 motorola 3.3v zero delay buffer 9 package dimensions section n-n j j1 k k1 dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0? 8? 0? 8? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. seating plane c d h g 0.10 (0.004) -t- ident. pin 1 1 8 16 9 b a l 2x l/2 -u- s u 0.15 (0.006) t u 0.15 (0.006) t u m 0.10 (0.004) v t -v- 16x ref k detail e -w- detail e f m 0.25 (0.010) n n s s s dt suffix 16 lead tssop package case 948f-01 issue o
mpc962308 10 3.3v zero delay buffer motorola notes
mpc962308 motorola 3.3v zero delay buffer 11 notes
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