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july 2005 asm5i961p rev 0.2 alliance semiconductor 2575, augustine drive ? santa clara, ca ? tel: 408.855.4900 ? fax: 408.855.4999 ? www.alsc.com notice: the information in this document is subject to change without notice. low voltage zero delay buffer features ? fully integrated pll ? up to 200mhz i/o frequency ? lvcmos outputs ? outputs disable in high impedance ? lvpecl reference clock options ? lqfp packaging ? 50ps cycle?cycle jitter ? 150ps output skews functional description the asm5i961p is a 2.5v or 3.3v compatible, 1:18 pll based zero delay buffer. with output frequencies of up to 200mhz, output skews of 150ps the device meets the needs of the most demanding clock tree applications. the asm5i961p is offered with two different input configurations. the asm5i 961p offers an lvcmos reference clock while the asm5i961p offers an lvpecl reference clock. when pulled high the oe pin will force all of the outputs (except qfb) into a high impedance state. because the oe pin does not affect the qfb output, down stream clocks can be disabled without the internal pll losing lock. the asm5i961p is fully 2.5v or 3.3v compatible and requires no external loop filter components. all control inputs accept lvcmos compat ible levels and the outputs provide low impedance lvcmos outputs capable of driving terminated 50 ? transmission lines. for series terminated lines the asm5i961p can drive two lines per output giving the device an e ffective fanout of 1:36. the device is packaged in a 32 lead lqfp package to provide the optimum combinatio n of board density and performance. block diagram figure 1. asm5i961p logic diagram
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 2 of 14 notice: the information in this document is subject to change without notice. pin configuration figure 2. asm5i961p 32-lead package pinout (top view) table 1: pin configuration pin # pin name i/o type function 2,3 pclk, pclk input lvcmos pll reference clock signal 7 fb_in input lvcmos pll feedback signal input, connect to a qfb output 4 f_range input lvcmos p ll frequency range select 6 oe input lvcmos output enable/disable 31,30,29,27,26,25,23,22,21 ,19,18,17,15, 14,13,11,10 q0 - q16 output lvcmos clock outputs 9 qfb output lvcmos pll feedback signal output, connect to a fb_in 1,12,20,28 gnd supply power negative power supply 5 vcca supply power pll positive power supply (analog power supply). the asm5i961p requires an external rc filter for the analog power supply pin vcca. please see applications section for details. 8,16,24,32 vcc supply power positive power supply for i/o and core asm5i961p
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 3 of 14 notice: the information in this document is subject to change without notice. table 2: function table control default 0 1 f_range 0 pll high frequency range. asm5i961p input reference and output clock frequency range is 100 ? 200 mhz pll low frequency range. asm5i961p input reference and output clock frequency range is 50 ? 100 mhz oe 0 outputs enabled outputs di sabled (high?impedance state) table 3: absolute maximum ratings symbol parameter min max unit v cc supply voltage ?0.3 3.6 v v in dc input voltage ?0.3 v cc + 0.3 v v out dc output voltage ?0.3 v cc + 0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature range ?40 125 c t dv static discharge voltage (as per jedec std 22- a114-b) 2 kv note: these are stress ratings only and are not implied for functional use. exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. table 4: dc characteristics (v cc = 3.3v 5%, t a = -40c to +85c) symbol characteristic min typ max unit condition v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage ?0.3 0.8 v lvcmos v pp peak?to?peak input voltage 1 pecl_clk, pecl_clk 500 1000 mv lvpecl v cmr common mode range 1 pecl_clk, pecl_clk 1.2 v cc ? 0.8 v lvpecl v oh output high voltage 2.4 v i oh = ?20ma 2 v ol output low voltage 0.55 v i ol = 20ma 2 z out output impedance 14 20 ? i in input current 120 ma c in input capacitance 4.0 pf c pd power dissipation capacitance 8.0 10 pf per output i cca maximum pll supply current 2.0 5.0 ma v cca pin i cc maximum quiescent supply current ma all v cc pins v tt output termination voltage v cc 2 v notes: 1. exceeding the specified v cmr /v pp window results in a t pd changes of approx. 250ps. 2. the asm5i961p is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, the device drives up two 50 ? series terminated transmission lines.
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 4 of 14 notice: the information in this document is subject to change without notice. table 5: ac characteristics (v cc = 3.3v 5%, t a = -40c to +85c) 1 symbol characteristic min typ max unit condition f ref input frequency f_range = 0 f_range = 1 100 50 200 100 mhz f max maximum output frequency f_range = 0 f_range = 1 100 50 200 100 mhz f refdc reference input duty cycle 25 75 % t ( ) propagation delay 2 (static phase offset) pecl_clk to fb_in ?50 225 ps pll locked t sk(o) output to output skew 3 90 150 ps dc o output duty cycle f_range = 0 f_range = 1 42 45 50 50 55 55 % t r , t f output rise/fall time 0.1 1.0 ns 0.55 to 2.4v t plz,hz output disable time 10 ns t pzl,lz output enable time 10 ns t jit(cc) cycle to cycle jitter rms (1 ) 4 15 ps t jit(per) period jitter rms (1 ) 7.0 10 ps t jit( ) i/o phase jitter rms (1 ) f_range = 0 f_range = 1 0.0015 ? t 0.0010 ? t ns t = clock signal period t lock maximum pll lock time 10 ms notes: 1. ac characteristics apply for parallel output termination of 50 ? to v tt . 2. t pd applies for v cmr = v cc ?1.3v and v pp = 800mv 3. see applications section for part to part skew calculation 4. see applications section for calculat ion for other confidence factors than 1 table 6: dc characteristics (v cc = 2.5v 5%, t a = ?40 to 85c) symbol characteristic min typ max unit condition v ih input high voltage 1.7 v cc + 0.3 v lvcmos v il input low voltage ?0.3 0.7 v lvcmos v pp peak?to?peak input voltage 1 pecl_clk, pecl_clk 500 1000 mv lvpecl v cmr common mode range 1 pecl_clk, pecl_clk 1.2 v cc ? 0.7 v lvpecl v oh output high voltage 1.8 v i oh = ?15ma 2 v ol output low voltage 0.6 v i ol = 15ma 2 z out output impedance 18 26 ? i in input current 120 ma c in input capacitance 4.0 pf c pd power dissipation capacitance 8.0 10 pf per output i cca maximum pll supply current 2.0 5.0 ma v cca pin i cc maximum quiescent supply current ma all v cc pins v tt output termination voltage v cc 2 v notes: 1. exceeding the specified v cmr /v pp window results in a t pd changes of < 250 ps. 2. the asm5i961p is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, the device drives up two 50 ? series terminated transmission lines.
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 5 of 14 notice: the information in this document is subject to change without notice. table 7: ac characteristics (v cc = 2.5v 5%, t a = -40c to +85c) 1 symbol characteristic min typ max unit condition f ref input frequency f_range = 0 f_range = 1 100 50 200 100 mhz f max maximum output frequency f_range = 0 f_range = 1 100 50 200 100 mhz f refdc reference input duty cycle 25 75 % t ( ) propagation delay 2 (static phase offset) pecl_clk to fb_in ?50 175 ps pll locked t sk(o) output?to?output skew 3 90 150 ps dc o output duty cycle f_range = 0 f_range = 1 40 45 50 50 60 55 % t r , t f output rise/fall time 0.1 1.0 ns 0.6 to 1.8v t plz,hz output disable time 10 ns t pzl,lz output enable time 10 ns t jit(cc) cycle?to?cycle jitter rms (1 ) 4 15 ps t jit(per) period jitter rms (1 ) 7.0 10 ps t jit( ) i/o phase jitter rms (1 ) f_range = 0 f_range = 1 0.0015 ? t 0.0010 ? t ns t = clock signal period t lock maximum pll lock time 10 ms notes: 1. ac characteristics apply for parallel output termination of 50 ? to v tt . 2. t pd applies for v cmr = v cc ?1.3v and v pp = 800mv 3. see applications section for part?to?part skew calculation 4. see applications section for calculat ion for other confidence factors than 1
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 6 of 14 notice: the information in this document is subject to change without notice. applications information power supply filtering the asm5i961p is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the asm5i961p provides separate power supplies for the output buffers (v cc ) and the phase?locked loop (v cca ) of the device. the purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase?locked loop. in a controlled environment such as an evaluation board this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is power supply filter on the v cca pin for the asm5i961p. figure 3. illustrates a typical power supply filter scheme. the asm5i961p is most susceptible to noise with spectral content in the 10khz to 5mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the v cca pin of the asm5i961p. from the data sheet the i cca current(the current sourced through the v cca pin) is typically 2ma(5ma maximum), assuming that a minimum of 2.375v (v cc =3.3v or v cc = 2.5v) must be maintained on the v cca pin. the resistor rf shown in figure 3. must have a resistance of270 (v cc = 3.3v) or 5 to 15 (v cc = 2.5v) to meet the voltage drop criteria. the rc filter pict ured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20khz. as the noise frequency crosses the series resonant point of an individual capacitor it?s overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. figure 3. power supply filter although the asm5i961p has se veral design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. driving transmission lines the asm5i961p clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 15 ? the drivers can drive either parallel or series terminated transmission lines. in most high performance clock networks point to point distribution of signals is the method of choice. in a point to point scheme either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 ? resistance to v cc /2. this technique draws a fairly high level of dc current and thus only a single terminated line can be driven by eac h output of the asm5i961p clock driver. for the series terminated case however there is no dc current draw , thus the outputs can drive multiple series terminated lines. figure 4. illustrates an output driving a single series terminated line vs two series terminated lines in parallel. when taken to its extreme the fanout of the asm5i961p clo ck driver is effectively doubled due to its capability to drive multiple lines. figure 4. single versus dual transmission lines the waveform plots of figure 5. show the simulation results of an output driving a single line vs two lines. in both cases the drive capabilit y of the asm5i961p output buffer is more than sufficient to drive 50 ? transmission lines on the incident edge. note from the delay measurements in the simulati ons a delta of only 43ps exists between the two differ ently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the ti ght output?to?out put skew of asm5i961p output buffer 14 ? in outa z 0 =50 ? r s =36 ? asm5i961p output buffer 14 ? in outb1 z 0 =50 ? r s =36 ? outb0 z 0 =50 ? r s =36 ? asm5i961p
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 7 of 14 notice: the information in this document is subject to change without notice. the asm5i961p. the output waveform in figure 5. shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 36 ? series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: vl = vs ( zo / (rs + ro +zo)) zo = 50 ? || 50 ? rs = 36 ? || 36 ? ro = 14 ? vl = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31v at the load end the voltage will double, due to the near unity reflection coefficient, to 2.62v. it will then increment towards the quiescent 3.0v in steps separated by one round trip delay (in this case 4.0ns). figure 5. single versus dual waveforms since this step is well abov e the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multiple lines the situation in figure 6. should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the li ne impedance is perfectly matched. 14 ? + 22 ? || 22 ? = 50 ? || 50 ? 25 ? = 25 ? figure 6. optimized dual line termination using the asm5i961p in zero-delay applications nested clock trees are typical applications for the asm5i961p. designs using the asm5i961p, as lvcmos pll fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from cmos fanout buffers. the external feedback option of the asm5i961p clock driver allows for its use as a zero delay buffer. by using the qfb output as a feedback to the pll the propagation delay through the device is virtually eliminated. the pll aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. the maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. this effective delay consists of the static phase offset, i/o jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. calculation of part-to-part skew the asm5i961p zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. if the reference clock inputs of two or more asm5i961p are connected together, the maximum overall timing uncertainty from the common pclk input to any output is: t sk(pp) = t ( ) + t sk(o) + t pd, line(fb) + t jit( ) ? cf this maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and i/o (phase) jitter: figure 7. asm5i961p max. device-to-device skew due to the statistical nature of i/o jitter a rms value (1 ) is specified. i/o jitter numbers fo r other confidence factors (cf) can be derived from table 8. asm5i961p output buffer 14 ? in z 0 =50 ? r s =22 ? z 0 =50 ? r s =22 ?
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 8 of 14 notice: the information in this document is subject to change without notice. table 8: confidence factor cf cf probability of clock edge within the distribution 1 0.68268948 2 0.95449988 3 0.99730007 4 0.99993663 5 0.99999943 6 0.99999999 the feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. in the following example calculation a i/o jitter confidence factor of 99.7% ( 3 ) is assumed, resulting in a worst case timing uncertainty from input to any output of -236ps to 361ps relative to pclk (f=125 mhz, v cc =2.5v): t sk(pp) = [?50ps...175ps] + [?150ps...150ps] + [(12ps ? ?3)...(12ps ? 3)] + t pd , line(fb) t sk(pp) = [?236ps...361ps] + t pd , line(fb) due to the frequency dependenc e of the i/o jitter, figure 8. ?max. i/o jitter versus frequency? can be used for a more precise timing performance analysis. figure 8. max. i/o jitter versus frequency power consumption of the asm5i961p and thermal management the asm5i961p ac specificat ion is guaranteed for the entire operating frequency range up to 200 mhz. the asm5i961p power consumption and the associated long- term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convec tion and thermal conductivity of package and board. this section describes the impact of these parameters on th e junction temperature and gives a guideline to estimate the asm5i961p die junction temperature and the associated device reliability. table 9: die junction temperature and junction temperature ( c) mtbf (years) 100 20.4 110 9.1 120 4.2 130 2.0 increased power consumption will increase the die junction temperature and impact the device reliability (mtbf). according to the system-defined tolerable mtbf, the die junction te mperature of the asm5i961p needs to be controlled and the thermal impedance of the board/package should be optimized. the power dissipated in the asm5i961p is represented in equation 1. where i ccq is the static current consumption of the asm5i961p, cpd is the power dissipation capacitance per output, (m) c l represents the external capacitive output load, n is the number of active outputs (n is always 27 in case of the asm5i961p). the asm5i961p supports driving transmission lines to maintain high signal integrity and tight timing parameters. any transmission line will hide the lumped capacit ive load at the end of the board trace, therefore, c l is zero for controlled transmission line systems and can be eliminated from equation 1. using parallel termination output termination results in equation 2 for power dissipation. in equation 2, p stands for the number of outputs with a parallel or thevenin termination, v ol , i ol , v oh and i oh are a function of the output termination tec hnique and dcq is the clock signal duty cycle. if transmission lines are used c l is zero in equation 2 and can be eliminated. in general, the use of controlled transmission line techniques eliminates the impact of the lumped capaci tive loads at the end lines and greatly reduces the power dissipation of the device. equation 3 describes the die junction temperature t j as a function of the po wer consumption.
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 9 of 14 notice: the information in this document is subject to change without notice. where r thja is the thermal impedance of the package (junction to ambient) and t a is the ambient temperature. according to table 9, the junction temperature can be used to estimate the long-ter m device reliability. further, combining equation 1 and equation 2 results in a maximum operating frequency for the asm5i961p in a series terminated transmission line system. table 10: thermal package impedance of the 32 lqfp convection, lfpm r thja (1p2s board), k/w still air 80 100 lfpm 70 200 lfpm 61 300 lfpm 57 400 lfpm 56 500 lfpm 55 t j,max should be selected according to the mtbf system requirements and table 9. r thja can be derived from table 10. the r thja represent data based on 1s2p boards, using 2s2p boards will result in a lower thermal impedance than indicated below. if the calculated maximum frequency is below 200 mhz, it becomes the upper clock speed limit for the given application conditions. the following two derating charts describe the safe frequency operation range for the asm5i961p. the charts were calculated for a maximum tolerable die junction temperature of 110 c, corresponding to an estimated mtbf of 9.1 years, a supply voltage of 3.3v and series terminated transmission line or capacitive loading. depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. there are no operating frequency limitations if a 2.5v power supply or the system specifications allow for a mtbf of 4 years (corresponding to a max. junction temperature of 120 c.
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 10 of 14 notice: the information in this document is subject to change without notice. figure 9. maximum asm5i961p f r equency, v cc = 3.3v, mtbf 9.1 years, driving series te rminated transmission lines figure 10. maximum asm5i961p frequency, v cc = 3.3v, mtbf figure 11. tclk asm5i961p ac test reference for v cc = 3.3v and v cc = 2.5v
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 11 of 14 notice: the information in this document is subject to change without notice.
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 12 of 14 notice: the information in this document is subject to change without notice. package information 32-lead lqfp package section a-a dimensions inches millimeters symbol min max min max a ?. 0.0630 ? 1.6 a1 0.0020 0.0059 0.05 0.15 a2 0.0531 0.0571 1.35 1.45 d 0.3465 0.3622 8.8 9.2 d1 0.2717 0.2795 6.9 7.1 e 0.3465 0.3622 8.8 9.2 e1 0.2717 0.2795 6.9 7.1 l 0.0177 0.0295 0.45 0.75 l1 0.03937 ref 1.00 ref t 0.0035 0.0079 0.09 0.2 t1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 r0 0.0031 0.0079 0.08 0.20 e 0.031 base 0.8 base a 0 7 0 7
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 13 of 14 notice: the information in this document is subject to change without notice. ordering information part number marking package type temperature asm5i961p-32lr asm5i961p 32 pin lqfp industrial asm5i961p-32lr asm5i961p 32 pin lq fp ? tape and reel industrial ASM5I961PG-32LR asm5i961pg 32 pi n lqfp, green industrial ASM5I961PG-32LR asm5i961pg 32 pin lqfp ? tape and reel, green industrial device ordering information asm 5i961p f-32-lr licensed under us patent #5,488, 627, #6,646,463 and #5,631,920. o = sot u = msop s = soic e = tqfp t = tssop l = lqfp a = ssop u = msop v = tvsop p = pdip b = bga d = qsop q = qfn x = sc - 70 device pin count x= automotive i= industrial p or n/c = commercial (-40c to +125c) (-40c to +85c) (0c to +70c) 1 = reserved 6 = power management 2 = non pll based 7 = power management 3 = emi reduction 8 = power management 4 = ddr support products 9 = hi performance 5 = std zero dela y buffe r 0 = reserved alliance semiconductor mixed signal product part number f = lead free and rohs compliant part g = green package r = tape & reel, t = tube or tray
july 2005 asm5i961p rev 0.2 low voltage zero delay buffer 14 of 14 notice: the information in this document is subject to change without notice. ? copyright 2003 alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make ch anges to this document and its products at any time without notice. alliance assumes no responsibility for any errors t hat may appear in this document. the data contained herein represents alliance's best data and/or estimate s at the time of issuance. alliance rese rves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not in tended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or lia bility arising out of the applic ation or use of any product described herein, and disclaims any express or implied warrant ies related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, mercha ntability, or infringement of any intellec tual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any pa tent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alli ance or third parties. alliance does not aut horize its products for use as critical components in life-supporting systems where a malfunction or fa ilure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel# 408-855-4900 fax: 408-855-4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: asm5i961p document version: 0.2 note: this product utilizes us patent # 6,646,463 impedance emulator patent issued to alliance semiconductor, dated 11-11-2003

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