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?2005 by catalyst semiconductor, inc. characteristics subject to change without notice 1 doc. no. 2121, rev. b cat5120, cat5121, cat5122 16-tap minipot digitally programmable potentiometers with 2-wire interface features 0.3 a ultra-low supply current single-supply operation: 2.7 v to 5.5 v glitchless switching between resistor taps power-on reset to midscale applications lcd screen adjustment volume control mechanical potentiometer replacement pin configure description cat5120/5121/5122 linear-taper digitally programmable potentiometers perform the same function as a mechanical potentiometer or a variable resistor. these devices consist of a fixed resistor and a wiper contact with 32-tap points that are digitally controlled through a 2-wire up/down serial interface. the cat5120 is configured as a potentiometer. the cat5121 and cat5122 are configured as variable resistors. see pin configurations for part functionality. three resistance values are available: 10k ? , 50k ? and 100k ? . these are available in space-saving 5-pin and 6-pin sc70 and sot-23 packages. 2-wire up/down serial interface resistance values: 10k ?, ?, ?, ?, ?, 50k ? ? ? ? ? and 100k ? ? ? ? ? available in sc70 and sot-23 p ackages gain adjustment line impedance matching functional diagram gnd cs u/d 15h v dd 2 cat5122 34 gnd cs u/d 16h v dd 2 34 w 5 cat5120 gnd cs u/d 16h v dd 2 l 5 cat5121 34 top view v dd gnd cs h l w u/d up/dn counter 16-position decoder
cat5120/5121/5122 2 doc. no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice pin description r e b m u n n i p e m a n n i pn o i t c n u f n i p 0 2 1 5 t a c1 2 1 5 t a c2 2 1 5 t a c 111v d d y l p p u s r e w o p 222 d n gd n u o r g 333/ u d / p u n w o d h t i w . t u p n i l o r t n o c s c a , w o l r o s t n e m e r c n i n o i t i s n a r t h g i h - o t - w o l . n o i t i s o p r e p i w e h t s t n e m e r c e d 444 s c w o l - o t - h g i h a . t u p n i t c e l e s p i h c s c t n e m e r c n i : e d o m e h t s e n i m r e t e d n o i t i s n a r t f i/ u d f i t n e m e r c e d r o , h g i h s i/ u d . w o l s i -5-l r o t s i s e r f o l a n i m r e t w o l 5- -w r o t s i s e r f o l a n i m r e t r e p i w 665h r o t s i s e r f o l a n i m r e t h g i h
cat5120/5121/5122 3 doc no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice ordering information r e b m u n t r a p g n i r e d r ok r o t s i s e rk r a m p o te g a k c a p n i pl e e r r e p s t r a p t - 0 1 - i b s 0 2 1 5 t a c0 1_ e j0 7 c s d a e l 6k 3 0 1 t - 0 1 - i b s 0 2 1 5 t a c0 1_ e j0 7 c s d a e l 6k 0 1 t - 0 1 - i p t 0 2 1 5 t a c0 1m y e j3 2 - t o s d a e l 6k 3 0 1 t - 0 1 - i p t 0 2 1 5 t a c0 1m y e j3 2 - t o s d a e l 6k 0 1 t - 0 5 - i b s 0 2 1 5 t a c0 5_ f j0 7 c s d a e l 6k 3 0 1 t - 0 5 - i b s 0 2 1 5 t a c0 5_ f j0 7 c s d a e l 6k 0 1 t - 0 5 - i p t 0 2 1 5 t a c0 5m y f j3 2 - t o s d a e l 6k 3 0 1 t - 0 5 - i p t 0 2 1 5 t a c0 5m y f j3 2 - t o s d a e l 6k 0 1 t - 0 0 - i b s 0 2 1 5 t a c0 0 1m y g j0 7 c s d a e l 6k 3 0 1 t - 0 0 - i b s 0 2 1 5 t a c0 0 1_ g j0 7 c s d a e l 6k 0 1 t - 0 0 - i p t 0 2 1 5 t a c0 0 1m y g j3 2 - t o s d a e l 6k 3 0 1 t - 0 0 - i p t 0 2 1 5 t a c0 0 1m y g j3 2 - t o s d a e l 6k 0 1 t - 0 1 - i b s 1 2 1 5 t a c0 1_ h j0 7 c s d a e l 6k 3 0 1 t - 0 1 - i b s 1 2 1 5 t a c0 1_ h j0 7 c s d a e l 6k 0 1 t - 0 1 - i p t 1 2 1 5 t a c0 1m y h j3 2 - t o s d a e l 6k 3 0 1 t - 0 1 - i p t 1 2 1 5 t a c0 1m y h j3 2 - t o s d a e l 6k 0 1 t - 0 5 - i b s 1 2 1 5 t a c0 5_ j j0 7 c s d a e l 6k 3 0 1 t - 0 5 - i b s 1 2 1 5 t a c0 5_ j j0 7 c s d a e l 6k 0 1 t - 0 5 - i p t 1 2 1 5 t a c0 5m y j j3 2 - t o s d a e l 6k 3 0 1 t - 0 5 - i p t 1 2 1 5 t a c0 5m y j j3 2 - t o s d a e l 6k 0 1 t - 0 0 - i b s 1 2 1 5 t a c0 0 1_ k j0 7 c s d a e l 6k 3 0 1 t - 0 0 - i b s 1 2 1 5 t a c0 0 1_ k j0 7 c s d a e l 6k 0 1 t - 0 0 - i p t 1 2 1 5 t a c0 0 1m y k j3 2 - t o s d a e l 6k 3 0 1 t - 0 0 - i p t 1 2 1 5 t a c0 0 1m y k j3 2 - t o s d a e l 6k 0 1 t - 0 1 - i b s 2 2 1 5 t a c0 1_ b j0 7 c s d a e l 5k 3 0 1 t - 0 1 - i b s 2 2 1 5 t a c0 1_ b j0 7 c s d a e l 5k 0 1 t - 0 1 - i p t 2 2 1 5 t a c0 1m y b j3 2 - t o s d a e l 5k 3 0 1 t - 0 1 - i p t 2 2 1 5 t a c0 1m y b j3 2 - t o s d a e l 5k 0 1 t - 0 5 - i b s 2 2 1 5 t a c0 5_ c j0 7 c s d a e l 5k 3 0 1 t - 0 5 - i b s 2 2 1 5 t a c0 5_ c j0 7 c s d a e l 5k 0 1 t - 0 5 - i p t 2 2 1 5 t a c0 5m y c j3 2 - t o s d a e l 5k 3 0 1 t - 0 5 - i p t 2 2 1 5 t a c0 5m y c j3 2 - t o s d a e l 5k 0 1 t - 0 0 - i b s 2 2 1 5 t a c0 0 1_ d j0 7 c s d a e l 5k 3 0 1 t - 0 0 - i b s 2 2 1 5 t a c0 0 1_ d j0 7 c s d a e l 5k 0 1 t - 0 0 - i p t 2 2 1 5 t a c0 0 1m y d j3 2 - t o s d a e l 5k 3 0 1 t - 0 0 - i p t 2 2 1 5 t a c0 0 1m y d j3 2 - t o s d a e l 5k 0 1
cat5120/5121/5122 4 doc. no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice ordering information (con t) r e b m u n t r a p g n i r e d r ok r o t s i s e rk r a m p o te g a k c a p n i pl e e r r e p s t r a p t - 0 1 - i d s 0 2 1 5 t a c0 1_ c kn e e r g 0 7 c s d a e l 6k 3 0 1 t - 0 1 - i d s 0 2 1 5 t a c0 1_ c kn e e r g 0 7 c s d a e l 6k 0 1 t - 0 1 - i b t 0 2 1 5 t a c0 1m y c kn e e r g 3 2 - t o s d a e l 6k 3 0 1 t - 0 1 - i b t 0 2 1 5 t a c0 1m y c kn e e r g 3 2 - t o s d a e l 6k 0 1 t - 0 5 - i d s 0 2 1 5 t a c0 5_ d kn e e r g 0 7 c s d a e l 6k 3 0 1 t - 0 5 - i d s 0 2 1 5 t a c0 5_ d kn e e r g 0 7 c s d a e l 6k 0 1 t - 0 5 - i b t 0 2 1 5 t a c0 5m y d kn e e r g 3 2 - t o s d a e l 6k 3 0 1 t - 0 5 - i b t 0 2 1 5 t a c0 5m y d kn e e r g 3 2 - t o s d a e l 6k 0 1 t - 0 0 - i d s 0 2 1 5 t a c0 0 1_ e kn e e r g 0 7 c s d a e l 6k 3 0 1 t - 0 0 - i d s 0 2 1 5 t a c0 0 1_ e kn e e r g 0 7 c s d a e l 6k 0 1 t - 0 0 - i b t 0 2 1 5 t a c0 0 1m y e kn e e r g 3 2 - t o s d a e l 6k 3 0 1 t - 0 0 - i b t 0 2 1 5 t a c0 0 1m y e kn e e r g 3 2 - t o s d a e l 6k 0 1 t - 0 1 - i d s 1 2 1 5 t a c0 1_ f kn e e r g 0 7 c s d a e l 6k 3 0 1 t - 0 1 - i d s 1 2 1 5 t a c0 1_ f kn e e r g 0 7 c s d a e l 6k 0 1 t - 0 1 - i b t 1 2 1 5 t a c0 1m y f kn e e r g 3 2 - t o s d a e l 6k 3 0 1 t - 0 1 - i b t 1 2 1 5 t a c0 1m y f kn e e r g 3 2 - t o s d a e l 6k 0 1 t - 0 5 - i d s 1 2 1 5 t a c0 5_ g kn e e r g 0 7 c s d a e l 6k 3 0 1 t - 0 5 - i d s 1 2 1 5 t a c0 5_ g kn e e r g 0 7 c s d a e l 6k 0 1 t - 0 5 - i b t 1 2 1 5 t a c0 5m y g kn e e r g 3 2 - t o s d a e l 6k 3 0 1 t - 0 5 - i b t 1 2 1 5 t a c0 5m y g kn e e r g 3 2 - t o s d a e l 6k 0 1 t - 0 0 - i d s 1 2 1 5 t a c0 0 1_ h kn e e r g 0 7 c s d a e l 6k 3 0 1 t - 0 0 - i d s 1 2 1 5 t a c0 0 1_ h kn e e r g 0 7 c s d a e l 6k 0 1 t - 0 0 - i b t 1 2 1 5 t a c0 0 1m y h kn e e r g 3 2 - t o s d a e l 6k 3 0 1 t - 0 0 - i b t 1 2 1 5 t a c0 0 1m y h kn e e r g 3 2 - t o s d a e l 6k 0 1 t - 0 1 - i d s 2 2 1 5 t a c0 1_ y kn e e r g 0 7 c s d a e l 5k 3 0 1 t - 0 1 - i d s 2 2 1 5 t a c0 1_ y kn e e r g 0 7 c s d a e l 5k 0 1 t - 0 1 - i b t 2 2 1 5 t a c0 1m y y kn e e r g 3 2 - t o s d a e l 5k 3 0 1 t - 0 1 - i b t 2 2 1 5 t a c0 1m y y kn e e r g 3 2 - t o s d a e l 5k 0 1 t - 0 5 - i d s 2 2 1 5 t a c0 5_ a kn e e r g 0 7 c s d a e l 5k 3 0 1 t - 0 5 - i d s 2 2 1 5 t a c0 5_ a kn e e r g 0 7 c s d a e l 5k 0 1 t - 0 5 - i b t 2 2 1 5 t a c0 5m y a kn e e r g 3 2 - t o s d a e l 5k 3 0 1 t - 0 5 - i b t 2 2 1 5 t a c0 5m y a kn e e r g 3 2 - t o s d a e l 5k 0 1 t - 0 0 - i d s 2 2 1 5 t a c0 0 1_ b kn e e r g 0 7 c s d a e l 5k 3 0 1 t - 0 0 - i d s 2 2 1 5 t a c0 0 1_ b kn e e r g 0 7 c s d a e l 5k 0 1 t - 0 0 - i b t 2 2 1 5 t a c0 0 1m y b kn e e r g 3 2 - t o s d a e l 5k 3 0 1 t - 0 0 - i b t 2 2 1 5 t a c0 0 1m y b kn e e r g 3 2 - t o s d a e l 5k 0 1
cat5120/5121/5122 5 doc no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice operating temperature range ........... -40 c to +85?c junction temperature ...................................... +150?c storage temperature range ............ -65?c to +150?c soldering temperature (soldering, 10s) .......... +300?c *(derate 3.1mw/?c above t a = +70?c) comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. absolute maximum ratings v dd to gnd........................................... -0.3 v to +6 v all other pins to gnd .............. -0.3 v to (v dd + 0.3) v input and output latch-up immunity ............ +200 ma maximum continuous current into h, l and w 100k ? ................................................................... +0.6 ma 50k ? ...................................................................... +1.3 ma 10k ? ...................................................................... +1.3 ma continuous power dissipation (t a = +70?c) 5-pin sc70* .................................................... 247 mw 6-pin sc70* .................................................... 245 mw electrical characteristics (v dd = 2.7 v to 5.5 v, v h = v dd , v l = 0, t a = -40?c to 85?c. typical values are at v dd = 2.7 v, t a = 25?c, unless otherwise noted). l o b m y sr e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u e c n a m r o f r e p c d n o i t u l o s e r 6 1s p a t e c n a t s i s e r d n e - o t - d n e 0 2 1 5 t a c5 70 0 15 2 1 k ? 1 2 1 5 t a c5 . 7 30 55 . 2 6 2 2 1 5 t a c5 . 70 15 . 2 1 c t r o c p m e t e c n a t s i s e r d n e - o t - d n e 0 0 2c ? / m p p o c p m e t e c n a t s i s e r c i r t e m o i t a r 5c ? / m p p l n iy t i r a e n i l n o n l a r g e t n i + 5 . 0b s l l n dy t i r a e n i l n o n l a i t n e r e f f i d + 5 . 0b s l r o r r e e l a c s - l l u f / o r e z + 1 . 0+ 5 . 0b s l r w e c n a t s i s e r r e p i w 0 0 20 0 6 ? s t u p n i l a t i g i d v h i e g a t l o v h g i h t u p n i v x 7 . 0 d d v v l i e g a t l o v w o l t u p n i v x 3 . 0 d d v ) 2 , 1 s e r u g i f ( s c i t s i r e t c a r a h c g n i m i t t u c / u d p u t e s s c o t e d o m 5 2s n t i c / u o t s c d p u t e s p e t s0 5s n t c i / u o t s c d d l o h p e t s5 2s n t l i / u d d o i r e p w o l p e t s 5 2s n t h i / u d d o i r e p h g i h p e t s 5 2s n f e l g g o t / p u n w o d e t a r e l g g o t ) 1 ( 1z h m t e l t t e s e m i t g n i l t t e s t u p t u o ) 2 ( k 0 0 1 ? , n o i t a r u g i f n o c r o t s i s e r e l b a i r a v f p 0 1 = l c 1 s k 0 0 1 ? , n o i t a r u g i f n o c r e t e m o i t n e t o p f p 0 1 = l c 5 2 . 0
cat5120/5121/5122 6 doc. no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice electrical characteristics v dd = 2.7 v to 5.5 v, v h = v dd , v l = 0, t a = -40?c to 85?c. typical values are at v dd = 2.7 v, t a = 25?c, unless otherwise noted. l o b m y sr e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u s e i l p p u s r e w o p v d d e g a t l o v y l p p u s7 . 25 . 5v i d d t n e r r u c y l p p u s e v i t c a ) 3 ( 5 2a i d s t n e r r u c y l p p u s y b d n a t s ) 4 ( v d d v 5 + =3 . 01a notes: 1. up/down toggle rate: 2. typical setting times are dependant on end-to-end resistance. 3. supply current taken while changing wiper tap, f toggle = 1mhz. 4. supply current taken while wiper position is fixed. f toggle = 1 t settle typical operating characteristics t a = 25?c, unless otherwise noted. v dd = 5.5v v dd = 2.7v 08 4 10121416 wiper position v dd = 2.7v v dd = 5.5v
cat5120/5121/5122 7 doc no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice functional description the cat5120/5121/5122 consist of a fixed resistor and a wiper contact with 16-tap points that are digitally controlled through a 2-wire up/down serial interface. three end-to-end resistance values are available: 10k ? , 50k ? and 100k ? . the cat5120 is designed to operate as a potentiometer. in this configuration, the low terminal of the resistor array is connected to ground (pin 2). the cat5122 performs as a variable resistor. in this device, the wiper terminal and high terminal of the resistor array is connected at pin 5. the cat5121 is a similar variable resistor, except the low terminal is connected to pin 5. digital interface operation the minipots have two modes of operation when the serial interface is active: increment and decrement mode. the serial interface is only active when cs is low. the cs and u/ d inputs control the position of the wiper along the resistor array. when cs transitions from high to low, the part will go into increment mode if u/ d input is high, and into decrement mode when u/ d input is low. once the mode is set, the device will remain in that mode until cs goes high again. a low-to-high transition at the u/ d pin will increment or decrement the wiper position depending on the current mode (figures 1 and 2). when the cs input transitions to high (serial interface inactive), the value of the counter is stored and the wiper position is maintained. note that when the wiper reaches the maximum (or minimum) tap position, the wiper will not wrap around to the minimum (or maximum) position. power-on reset all parts in this family feature power-on reset (por) circuitry that sets the wiper position to midscale at power-up. by default, the chip is in the increment mode. cs u/d w t cu t il t ih t ic t settle t ci t settle note: "w" is not a digital signal. it represents wiper transitions. cs u/d w t cu t il t ih t settle t ic t ci t settle note: "w" is not a digital signal. it represents wiper transitions. figure 2. serial interface timing diagram, decrement mode figure 1. serial interface timing diagram, increment mode
cat5120/5121/5122 8 doc. no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice applications information the minipots are intended for circuits requiring digitally controlled adjustable resistance, such as lcd contrast control, where voltage biasing adjusts the display con- trast. alternative positive lcd bias control use an op amp to provide buffering and gain on the output of the cat5120. connect the mechanical potentiometer to the positive input of a noninverting op amp (figure 3) to select a portion of the input signal by digitally controlling the wiper terminal. figure 4 shows a similar circuit for the cat5121. adjustable gain figure 5 shows how to use the variable resistor to digitally adjust the gain of a noninverting op amp configuration. connect the cat5121 in series with a resistor to ground to form the adjustable gain control of a noninverting amplifier. the minipots have a low 5ppm/ ?c ratiometric tempco that allows for a very stable adjustable gain configuration over temperature. figure 3. positive lcd bias control figure 4. positive lcd bias control figure 5a. adjustable gain circuit figure 5b. adjustable gain circuit 30v w l h +5v v out 30v l h +5v v out v cc l h v in v out v cc l h w v in v out cat5120 cat5121 cat5121 cat5120
cat5120/5121/5122 9 doc no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice sc70 package outlines u see detail a aa e e/2 e1/2 e1 pin #1 b d 0.15(.006) c e n1 n2 0.15(.006) c a2 a seating plane c a1 .10(.004) c (b) b1 base metal section a-a c1 c detail a gage plane u1 h 015(.0059) lead count 5 6 2 2 3 3 4 4 - 5 5 6 pin code n1 n2 n3 n4 n5 note: 1. controlling dimension: millimeter. converted inch dimension are not necessarily exact. 2. dimension "d" does not include mold flash, protrusion or gate burr. mold flash, protrusion or gate burr shall not exceed 0.15mm (0.006") per end. dimension "e1" does not include inter-lead flash or protrusion shall not exceed 0.15mm (0.006") per side. 3. the package top is smaller than the package bottom. dimension d and e1 are determined at the outermost exptremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs adn interlead flash, but including any mismatch between the top and bottom of the plastic body. common dimensions millimeter dimensions inch min nom max min nom max a a1 a2 b b1 c c1 d e e1 e e1 l u u1 0.80 0 0.80 0.15 0.15 0.08 0.08 1.90 2.00 1.15 - - 0.90 - 0.20 - 0.13 2.10 2.10 1.25 1.10 0.10 1.00 0.30 0.25 0.25 0.20 2.15 2.20 1.35 0.031 0 0.031 0.006 0.006 0.003 0.003 0.074 0.078 0.045 - - 0.035 - 0.008 - 0.005 0.082 0.082 0.050 0.043 0.004 0.040 0.012 0.010 0.010 0.008 0.084 0.086 0.055 0.65 bsc 1.30 bsc 0.0255 bsc 0.0512 bsc 0.26 0? 4? 0.36 - - 0.46 8? 10? 0.010 0 - 4 - 0.014 - - 0.018 8 - 10 - s y m b o l
cat5120/5121/5122 10 doc. no. 2121, rev. b ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice sot-23 (aa option) aaa c 2x aaa c d 2x 3 4 3 4 5 bbb c 2x n/2 tips nx b 5 1 2n/2 n/2 +1 n ddd c m a b d d e1 a b e e1 e1/2 e/2 e d ccc c c seating plane a2 a nx a a a1 h b b see view c view a-a l2 r r1 gauge plane l c seating plane view c base metal section b - b c1 with metal b1 (b) c 7 b 5 8 x x=a &/or b odd lead sides top view 5 x x=a &/or b even lead sides top view e/2 (l1) notes: 1. dimensions and tolerancing per asme y14.5m - 1994 2. dimension are in mm. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.15mm per side. d and e1 dimensions are determined at datum h. all dimensions are in millimeters min nom max notes a 1.00 a1 0.01 0.05 0.10 a2 0.84 0.87 0.90 c 0.12 0.15 0.20 7 c1 0.08 0.13 0.16 7 d 2.90bsc 3,4 e 2.80bsc 3,4 e1 1.60bsc 3,4 l 0.30 0.40 0.50 l1 0.60ref l2 0.25bsc r 0.10 r1 0.10 0.25 0 4 8 14 10 12 tolerances of form and position notes aaa 0.15 1,2 bbb 0.25 1,2 ccc 0.10 1,2 variations aa 6 ab ba min nom max min nom max min nom max notes b 0.30 0.45 0.30 0.45 0.22 0.36 7,8 b1 0.31 0.35 0.39 0.31 0.35 0.39 0.22 0.26 0.30 e 0.95bsc 0.95bsc 0.65bsc e1 1.90bsc 1.90bsc 1.95bsc n6 5 8 tolerances of form and position ddd 0.20 0.20 0.13 1,2 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outermost extremes of the plastic body exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. d and e1 dime nsions are determined at datum h. 5. datums a & b to be determined at datum h. 6. package varation "ab" is a 5 lead version of the 6 lead variation "aa" where lead #5 has been removed from the 6 lead "aa" v ariation. 7. these dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the "b" dim ension at maximum material condition. the dambar cannot be located on the lower radius of the foot. minimum space between protrusion and an adjacent lead shall not be less than 0.07mm.
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.caalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 minipot catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history date rev. reason 03/10/2005 a initial release 11/16/2005 b update electrical characteristics publication #: 2121 revison: b issue date: 11/16/05

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