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features description/ordering information sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 available in the texas instruments nanostar? and nanofree? packages operates at 0.8 v to 2.7 v sub-1-v operable max t pd of 0.5 ns at 1.8 v low power consumption, 10 m a at 2.7 v high on-off output voltage ratio high degree of linearity latch-up performance exceeds 100 ma per jesd 78, class ii esd performance tested per jesd 22 ? 2000-v human-body model (a114-b, class ii) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) this dual analog switch is operational at 0.8-v to 2.7-v v cc , but is designed specifically for 1.1-v to 2.7-v v cc operation. the sn74auc2g66 can handle both analog and digital signals. it permits signals with amplitudes of up to 2.7-v (peak) to be transmitted in either direction. nanostar? and nanofree? package technology is a major breakthrough in ic packaging concepts, using the die as the package. applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ordering information t a package (1) orderable part number top-side marking (2) nanostar? ? wcsp (dsbga) tape and reel SN74AUC2G66YEPR 0.23-mm large bump ? yep _ _ _u6_ nanofree? ? wcsp (dsbga) tape and reel sn74auc2g66yzpr ?40 c to 85 c 0.23-mm large bump ? yzp (pb-free) ssop ? dct tape and reel sn74auc2g66dctr u66_ _ _ vssop ? dcu tape and reel sn74auc2g66dcur u66_ (1) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. (2) dct: the actual top-side marking has three additional characters that designate the year, month, and assembly/test site. dcu: the actual top-side marking has one additional character that designates the assembly/test site. yep/yzp: the actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. pin 1 identifier indicates solder-bump composition (1 = snpb, = pb-free). function table control input switch (c) l off h on please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. nanostar, nanofree are trademarks of texas instruments. production data information is current as of publication date. copyright ? 2003?2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com dct or dcu p ackage (t op view) 12 3 4 87 6 5 1a1b 2c gnd v c c 1c2b 2a 43 2 1 56 7 8 gnd 2c 1b1a 2a2b 1c v c c yep or yzp p ackage (bott om view)
absolute maximum ratings (1) sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 logic diagram (positive logic) over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range (2) ?0.5 3.6 v v i input voltage range (2) (3) ?0.5 3.6 v v i/o switch i/o voltage range (2) (3) ?0.5 v cc + 0.5 v i ik control input clamp current v i < 0 ?50 ma i iok i/o port diode current v i/o < 0 or v i/o > v cc 50 ma i t on-state switch current v i/o = 0 to v cc 50 ma continuous current through v cc or gnd 100 ma dct package 220 q ja package thermal impedance (4) dcu package 227 c/w yep/yzp package 102 t stg storage temperature range ?65 150 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to ground unless otherwise specified. (3) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (4) the package thermal impedance is calculated in accordance with jesd 51-7. 2 www .ti.com b c a 14 2
recommended operating conditions (1) electrical characteristics sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 min max unit v cc supply voltage 0.8 2.7 v v cc = 0.8 v v cc v ih high-level input voltage v cc = 1.1 v to 1.95 v 0.65 v cc v v cc = 2.3 v to 2.7 v 1.7 v cc = 0.8 v 0 v il low-level input voltage v cc = 1.1 v to 1.95 v 0.35 v cc v v cc = 2.3 v to 2.7 v 0.7 v i/o i/o port voltage 0 v cc v v i control input voltage 0 3.6 v v cc = 0.8 v to 1.65 v (2) 20 d t/ d v input transition rise or fall rate v cc = 1.65 v to 2.3 v (3) 20 ns/v v cc = 2.3 v to 2.7 v (3) 20 t a operating free-air temperature ?40 85 c (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs, literature number scba004. (2) the data was taken at c l = 15 pf, r l = 2 k w (see figure 1 ). (3) the data was taken at c l = 30 pf, r l = 500 w (see figure 1 ). over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit 1.1 v 17 40 v i = v cc or gnd, i s = 4 ma r on on-state switch resistance v c = v ih 1.65 v 7 20 w (see figure 1 and figure 2 ) i s = 8 ma 2.3 v 4 15 1.1 v 131 180 v i = v cc to gnd, i s = 4 ma r on(p) peak on resistance v c = v ih 1.65 v 32 80 w (see figure 1 and figure 2 ) i s = 8 ma 2.3 v 15 20 1.1 v 3 difference of v i = v cc to gnd, i s = 4 ma d r on on-state resistance v c = v ih 1.65 v 1 w between switches (see figure 1 and figure 2 ) i s = 8 ma 2.3 v 1 v i = v cc and v o = gnd, or 1 i s(off) off-state switch leakage current v i = gnd and v o = v cc , 2.7 v m a 0.1 (2) v c = v il (see figure 3 ) 1 v i = v cc or gnd, v c = v ih , v o = open i s(on) on-state switch leakage current 2.7 v m a (see figure 4 ) 0.1 (2) i i control input current v i = v cc or gnd 0 to 2.7 v 5 m a i cc supply current v i = v cc or gnd, i o = 0 0.8 v to 2.7 v 10 m a c ic control input capacitance 2.5 v 2.5 pf c io(off) switch input/output capacitance 2.5 v 3 pf c io(on) switch input/output capacitance 2.5 v 7 pf (1) t a = 25 c (2) the data was taken at c l = 15 pf, r l = 2 k w (see figure 1 ). 3 www .ti.com
switching characteristics switching characteristics analog switch characteristics sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 over recommended operating free-air temperature range, c l = 15 pf (unless otherwise noted) (see figure 5 ) v cc = 1.2 v v cc = 1.5 v v cc = 1.8 v v cc = 2.5 v v cc = 0.8 v from to 0.1 v 0.1 v 0.15 v 0.2 v parameter unit (input) (output) typ min max min max min typ max min max t pd (1) a or b b or a 1 0.6 0.5 0.5 0.4 ns t en c a or b 5 0.5 3 0.5 2.1 0.5 0.9 1.6 0.5 1.4 ns t dis c a or b 5.3 0.5 4 0.5 3 0.5 2.6 3.3 0.5 2.7 ns (1) the propagation delay is the calculated rc time constant of the typical on-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). over recommended operating free-air temperature range, c l = 30 pf (unless otherwise noted) (see figure 5 ) v cc = 1.8 v v cc = 2.5 v from to 0.15 v 0.2 v parameter unit (input) (output) min typ max min max t pd (1) a or b b or a 0.7 0.7 ns t en c a or b 0.5 1.6 2.7 0.5 2.3 ns t dis c a or b 0.5 2.7 3.4 0.5 2 ns (1) the propagation delay is the calculated rc time constant of the typical on-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). t a = 25 c from to parameter test conditions v cc typ unit (input) (output) 0.8 v 101 1.1 v 150 c l = 50 pf, r l = 600 w , f in = sine wave 1.4 v 175 (see figure 6 ) 1.65 v 250 2.3 v 400 frequency response a or b b or a mhz (switch on) 0.8 v 450 1.1 v >500 c l = 5 pf, r l = 50 w , f in = sine wave 1.4 v >500 (see figure 6 ) 1.65 v >500 2.3 v >500 0.8 v ?60 1.1 v ?60 c l = 50 pf, r l = 600 w , f in = 1 mhz (sine wave) 1.4 v ?60 (see figure 7 ) 1.65 v ?60 2.3 v ?60 crosstalk a or b b or a db (between switches) 0.8 v ?65 1.1 v ?65 c l = 5 pf, r l = 50 w , f in = 1 mhz (sine wave) 1.4 v ?65 (see figure 7 ) 1.65 v ?65 2.3 v ?65 4 www .ti.com
operating characteristics sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 analog switch characteristics (continued) t a = 25 c from to parameter test conditions v cc typ unit (input) (output) 0.8 v 9 1.1 v 14 crosstalk c l = 50 pf, r l = 600 w , (control input to signal c a or b f in = 1 mhz (square wave) 1.4 v 15 mv output) (see figure 8 ) 1.65 v 16 2.3 v 20 0.8 v ?50 1.1 v ?50 c l = 50 pf, r l = 600 w , f in = 1 mhz (sine wave) 1.4 v ?50 (see figure 9 ) 1.65 v ?50 2.3 v ?50 feedthrough attenuation a or b b or a db (switch off) 0.8 v ?60 1.1 v ?60 c l = 5 pf, r l = 50 w , f in = 1 mhz (sine wave) 1.4 v ?60 (see figure 9 ) 1.65 v ?60 2.3 v ?60 0.8 v 7 1.1 v 0.256 c l = 50 pf, r l = 10 k w , a or b b or a f in = 1 khz (sine wave) 1.4 v 0.04 (see figure 10 ) 1.65 v 0.03 2.3 v 0.01 sine-wave distortion % 0.8 v 3.7 1.1 v 0.4 c l = 50 pf, r l = 10 k w , a or b b or a f in = 10 khz (sine wave) 1.4 v 0.04 (see figure 10 ) 1.65 v 0.02 2.3 v 0.02 t a = 25 c v cc = 0.8 v v cc = 1.2 v v cc = 1.5 v v cc = 1.8 v v cc = 2.5 v test parameter unit conditions typ typ typ typ typ power dissipation c pd f = 10 mhz 2.5 2.5 2.5 2.5 2.5 pf capacitance 5 www .ti.com
parameter measurement information sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 figure 1. on-state resistance test circuit figure 2. typical r on as a function of voltage (v i ) for v i = 0 to v cc 6 www .ti.com v c c v i = v c c or gnd v o r o n v i v o i s v i v o gnd (on) v b or a c a or b v c c v i h v c i s 0 20 40 60 80 100 120 0 1 2 3 v c c = 1.65 v v c c = 1.1 v v c c = 2.3 v
parameter measurement information sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 figure 3. off-state switch leakage-current test circuit figure 4. on-state leakage-current test circuit 7 www .ti.com condition 1: v i = gnd, v o = v c c condition 2: v i = v c c , v o = gnd v c c v i v o gnd (off) b or a c a or b v c c v i l v c a v c c v o gnd (on) b or a c a or b v c c v i h v c a v i = v c c or gnd v o = open
parameter measurement information sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 figure 5. load circuit and voltage waveforms 8 www .ti.com v m t h t s u from output under t est c l (see note a) load circuit s1 v l o a d open gnd r l r l data input t iming input v i 0 vv i 0 v 0 v t w input vol t age w a veforms setup and hold times vol t age w a veforms prop aga tion dela y times inverting and noninverting outputs vol t age w a veforms pulse dura tion t p l h t p h l t p h l t p l h v o h v o h v o l v o l v i 0 v input output w aveform 1 s1 at v l o a d (see note b) output w aveform 2 s1 at gnd (see note b) v o l v o h t p z l t p z h t p l z t p h z v l o a d /2 0 v v o l + v d v o h ? v d 0 v v i vol t age w a veforms enable and disable times low - and high-level enabling outputoutput t p l h /t p h l t p l z /t p z l t p h z /t p z h open v l o a d gnd test s1 notes: a. c l includes probe and jig capacitance. b. w aveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. w aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , slew rate 1 v/ns . d. the outputs are measured one at a time, with one transition per measurement. e. t p l z and t p h z are the same as t d i s . f. t p z l and t p z h are the same as t e n . g. t p l h and t p h l are the same as t p d . h. all parameters and waveforms are not applicable to all devices. output control v m v m v m v m v m v m v m v m v m v m v m v m v i v m v m 0.8 v 1.2 v 0.1 v 1.5 v 0.1 v 1.8 v 0.15 v 2.5 v 0.2 v 1.8 v 0.15 v 2.5 v 0.2 v 2 k w 2 k w 2 k w 2 k w 2 k w 1 k w 500 w v c c r l 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c v l o a d c l 15 pf15 pf 15 pf 15 pf 15 pf 30 pf 30 pf 0.1 v0.1 v 0.1 v 0.15 v0.15 v 0.15 v 0.15 v v d v c c v c c v c c v c c v c c v c c v c c v i v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v m t r /t f 2 ns 2 ns 2 ns 2 ns 2 ns 2 ns 2 ns inputs
parameter measurement information sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 figure 6. frequency response (switch on) figure 7. crosstalk (between switches) 9 www .ti.com v c c v o gnd b or a c a or b v c c v c v i h r l c l 50 w 0.1 m f (on) v c c /2 r l /c l : 600 w / 50 pf r l /c l : 50 w / 5 pf f i n v c c v o 1 1b or 1a c 1a or 1b v c c v c v i h c l 50 pf 50 w 0.1 m f (on) v c c /2 20log 1 0 (v o 2 /v i 1 ) or 20log 1 0 (v o 1 /v i 2 ) f i n r l 600 w r i n 600 w v o 2 gnd 2b or 2a c 2a or 2b v c v i l r i n 600 w (off) v c c /2 r l 600 w c l 50 pf
parameter measurement information sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 figure 8. crosstalk (control input ? switch output) figure 9. feedthrough, switch off 10 www .ti.com v c c v o gnd b or a c a or b v c c v c c l 50 pf 50 w v c c /2 v c c /2 r i n 600 w r l 600 w v c c v o gnd b or a c a or b v c c v c v i l r l c l 50 w 0.1 m f (off) v c c /2 r l /c l : 600 w / 50 pf r l /c l : 50 w / 5 pf f i n r l v c c /2
parameter measurement information sn74auc2g66 dual bilateral analog switch sces507 ? november 2003 ? revised december 2005 figure 10. sine-wave distortion 11 www .ti.com v c c v o gnd b or a c a or b v c c v c v i h r l 10 k w c l 50 pf 600 w 10 m f (on) v c c /2 v c c = 0.8 v , v i = 0.7 v p - p v c c = 1.1 v , v i = 1 v p - p v c c = 1.4 v , v i = 1.2 v p - p v c c = 1.65 v , v i = 1.4 v p - p v c c = 2.3 v , v i = 2 v p - p f i n 10 m f
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) sn74auc2g66dctr active sm8 dct 8 3000 pb-free (rohs) cu nipdau level-1-260c-unlim sn74auc2g66dctre4 active sm8 dct 8 3000 pb-free (rohs) cu nipdau level-1-260c-unlim sn74auc2g66dcur active us8 dcu 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74auc2g66dcure4 active us8 dcu 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74auc2g66yzpr active wcsp yzp 8 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 10-jan-2007 addendum-page 1
mechanical data mpds049b ? may 1999 ? revised october 2002 post office box 655303 ? dallas, texas 75265 dct (r-pdso-g8) plastic small-outline package ????? ????? ????? ????? 0,60 0,20 0,25 0 ? 8 0,15 nom gage plane 4188781/c 09/02 4,25 5 0,30 0,15 2,90 3,75 2,70 8 4 3,15 2,75 1 0,10 0,00 1,30 max seating plane 0,10 m 0,13 0,65 pin 1 index area notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion d. falls within jedec mo-187 variation da.

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