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products and specifications discussed herein ar e subject to change by micron without notice. 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm features pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 1 ?2001 micron technology, inc. all rights reserved. sdram rdimm mt18lsdt3272d ? 256mb mt18lsdt6472d ? 512mb mt18lsdt12872d ? 1gb for component data sheets, refer to micron?s web site: www.micron.com features ? 168-pin, pc133-compliant registered dual in-line memory module (rdimm) ? phase-lock loop (pll) clock driver to reduce loading ? uses 133 mhz sdram components ? supports ecc error detection and correction ? 256mb (32 meg x 72), 512mb (64 meg x 72), and 1gb (128 meg x 72) ? single +3.3v power supply ? fully synchronous; all signals are registered on the positive edge of the pll clock ? internal pipelined operatio n; column address can be changed every clock cycle ?dual rank ? internal sdram banks for hiding row access/ precharge ? programmable burst lengths (bl): 1, 2, 4, 8, or full page ? auto precharge option ? auto and self refresh modes: 15.625s (256mb) or 7.81s (512mb, 1gb) maximum periodic refresh interval ? lvttl-compatible inputs and outputs ? serial presence-det ect (spd) with eeprom ? gold edge contacts figure 1: 168-pin rdimm (mo-161 r/c e) notes: 1. cl = cas (read) latency; registered mode will add one clock cycle to cl. options marking ?package 168-pin dimm g 168-pin dimm (pb-free) y ? frequency/cas latency 1 133 mhz/cl = 2 -13e 133 mhz/cl = 3 -133 pcb height: 43.18mm (1.7in) table 1: key timing parameters speed grade data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 3 cl = 2 -13e ? 133 15 15 60 -133 133 ? 20 20 66
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 2 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm features notes: 1. data sheets for the base device s can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. consult factory for curre nt revision codes: example: mt18lsdt6472dg-133d1 . 3. end of life. table 2: addressing parameter 256mb 512mb 1gb refresh count 4k 8k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) device configuration 128mb (16 meg x 8) 256mb (32 meg x 8) 512mb (64 meg x 8) row address 4k (a0?a11) 8k (a0?a12) 8k (a0?a12) column address 1k (a0?a9) 1k (a0?a9) 4k (a0?a9, a11) module ranks 2 (s0#?s3#) 2 (s0#?s3#) 2 (s0#?s3#) table 3: part numbers and timing parameters ? 256mb modules base device: mt48lc16m8a2, 1 128mb sdram part number 2 module density configuration memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18lsdt3272dg-13e__ 256mb 32 meg x 72 7.5ns/133 mt/s 2-2-2 mt18lsdt3272dg-133__ 3 256mb 32 meg x 72 7.5ns/133 mt/s 3-3-3 mt18lsdt3272dy-133__ 256mb 32 meg x 72 7.5ns/133 mt/s 3-3-3 table 4: part numbers and timing parameters ? 512mb modules base device: mt48lc32m8a2, 1 256mb sdram part number 2 module density configuration memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18lsdt6472dg-13e__ 512mb 64 meg x 72 7.5ns/133 mt/s 2-2-2 mt18lsdt6472dy-13e__ 512mb 64 meg x 72 7.5ns/133 mt/s 2-2-2 mt18lsdt6472dg-133__ 512mb 64 meg x 72 7.5ns/133 mt/s 3-3-3 mt18lsdt6472dy-133__ 512mb 64 meg x 72 7.5ns/133 mt/s 3-3-3 table 5: part numbers and timing parameters ? 1gb modules base device: mt48lc64m8a2, 1 512mb sdram part number 2 module density configuration memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18lsdt12872dg-133__ 1gb 128 meg x 72 7.5ns/133 mt/s 3-3-3 mt18lsdt12872dy-133__ 1gb 128 meg x 72 7.5ns/133 mt/s 3-3-3
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 3 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm pin assignments and descriptions pin assignments and descriptions notes: 1. pin 126 is nf for 256mb and a12 for 512mb and 1gb. figure 2: pin assignments 168-pin sdram rdimm front 168-pin sdram rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ss 22 cb1 43 v ss 64 v ss 85 v ss 106 cb5 127 v ss 148 v ss 2dq023v ss 44 nc 65 dq21 86 dq32 107 v ss 128 cke0 149 dq53 3 dq1 24 nc 45 s2# 66 dq22 87 dq33 108 nc 129 s3# 150 dq54 4 dq2 25 nc 46 dqmb2 67 dq23 88 dq34 109 nc 130 dqmb6 151 dq55 5dq326v dd 47 dqmb3 68 v ss 89 dq35 110 v dd 131 dqmb7 152 v ss 6v dd 27 we# 48 nc 69 dq24 90 v dd 111 cas# 132 nc 153 dq56 7dq428dqmb049v dd 70 dq25 91 dq36 112 dqmb4 133 v dd 154 dq57 8 dq5 29 dqmb1 50 nc 71 dq26 92 dq37 113 dqmb5 134 nc 155 dq58 9 dq6 30 s0# 51 nc 72 dq27 93 dq38 114 s1# 135 nc 156 dq59 10 dq7 31 nc 52 cb2 73 v dd 94 dq39 115 ras# 136 cb6 157 v dd 11 dq8 32 v ss 53 cb3 74 dq28 95 dq40 116 v ss 137 cb7 158 dq60 12 v ss 33 a0 54 v ss 75 dq29 96 v ss 117 a1 138 v ss 159 dq61 13 dq9 34 a2 55 dq16 76 dq30 97 dq41 118 a3 139 dq48 160 dq62 14 dq10 35 a4 56 dq17 77 dq31 98 dq42 119 a5 140 dq49 161 dq63 15 dq11 36 a6 57 dq18 78 v ss 99 dq43 120 a7 141 dq50 162 v ss 16 dq12 37 a8 58 dq19 79 nf 100 dq44 121 a9 142 dq51 163 nf 17 dq13 38 a10 59 v dd 80 nc 101 dq45 122 ba0 143 v dd 164 nc 18 v dd 39 ba1 60 dq20 81 nc 102 v dd 123 a11 144 dq52 165 sa0 19 dq14 40 v dd 61 nc 82 sda 103 dq46 124 v dd 145 nc 166 sa1 20 dq15 41 v dd 62 nc 83 scl 104 dq47 125 nf 146 nc 167 sa2 21 cb0 42 ck0 63 cke1 84 v dd 105 cb4 126 nf/a12 1 147 rege 168 v dd
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 4 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm pin assignments and descriptions table 6: pin descriptions symbol type description a0?a12 input address inputs: sampled during the active and read/write commands, with a10 defining auto precharge, to select one location out of the memory array in the respective device bank. a10 is sampled during a precharge co mmand to determine whether both device banks are precharg ed (a10 high). the address inputs also provide the op-code during a load mode register co mmand. a0?a11 (256mb) and a0?a12 (512mb, 1gb). ba0, ba1 input bank address: ba0 and ba1 define the device bank to which an active, read, write, or precharge command is being applied. ck0?ck3 input clock: ck0 is distributed through an on-board pll to all devices. ck1?ck3 are terminated. cke0, cke1 input clock enable: cke enables (register high) and disa bles (register low) the ck signal. deactivating the clock provid es power-down and self refr esh operation (all device banks idle) or clock suspend operation (burst access in prog ress). cke is synchronous except after the device enters power-do wn and self refres h modes, where cke becomes asynchronous until af ter exiting the same mode. th e input buffers, including ck, are disabled during power-down and se lf refresh modes, pr oviding low standby power. dqmb0?dqmb7 input input/output mask: dqmb is an input mask signal for write accesses and an output enable signal for read accesses. input da ta is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two clock latency) when dqmb is sampled high during a read cycle. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) defi ne the command being entered. rege input register enable. s0#?s3# input chip select: s# enables (registered low) and disa bles (registered high) the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. sa0?sa2 input presence-detect address inputs: these pins are used to configure the presence- detect device. scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. cb0?cb7 input/ output check bits. dq0?dq63 input/ output data input/output: data bus. sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and data out of the eeprom portion of the module. v dd supply power supply: +3.3v 0.3v. v ss supply ground. nc ? not connected: these pins are not connected on the module. nf ? no function: connected within the module but provides no functionality.
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 5 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm functional block diagram functional block diagram figure 3: functional block diagram ras# cas# cke0 cke1 we# a0?a11/a12 ba0 ba1 s0#?s3# dqmb0?dqmb7 rras#: sdram u1?u9, u15?u23 rcas#: sdram u1?u9, u15?u23 rcke0: sdram u1?u9 rcke1: sdram u15?u23 rwe#: sdram u1?u9, u15?u23 ra0?ra11/ra12: sdram u1?u9, u15?u23 rba0: sdram u1?u9, u15?u23 rba1: sdram u1?u9, u15?u23 rs0#?rs3# rdqmb0?rdqmb7 v dd v ss sdram sdram rege v dd r e g i s t e r s pll sdram x 3 sdram x 3 sdram x 3 sdram x 3 sdram x 3 sdram x 3 register x 3 ck0 ck1?ck3 dqm cs# u8 dq dq dq dq dq dq dq dq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 rdqmb7 dqm cs# u6 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 rdqmb6 dqm cs# u4 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 rdqmb5 dqm cs# u2 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 rdqmb4 dqm cs# u9 dq dq dq dq dq dq dq dq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 rdqmb3 dqm cs# u7 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 rdqmb2 dqm cs# u3 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 rdqmb1 dqm cs# u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 rdqmb0 rs2# rs0# dqm cs# u5 dq dq dq dq dq dq dq dq cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dqm cs# u16 dq dq dq dq dq dq dq dq dqm cs# u18 dq dq dq dq dq dq dq dq dqm cs# u20 dq dq dq dq dq dq dq dq dqm cs# u22 dq dq dq dq dq dq dq dq rs1# dqm cs# u15 dq dq dq dq dq dq dq dq dqm cs# u17 dq dq dq dq dq dq dq dq dqm cs# u21 dq dq dq dq dq dq dq dq dqm cs# u23 dq dq dq dq dq dq dq dq dqm cs# u19 dq dq dq dq dq dq dq dq rs3# u13 u10, u11, u24 u12 u14 a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp v ss v ss v ss
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 6 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm general description general description the mt18lsdt3272d, mt18lsdt6472d, and mt18lsdt12872d are high-speed, cmos dynamic random access 256mb, 512mb, and 1gb memory modules organized in a x72 (ecc) configuration. sdram modules use 4-bank sdram devices with a synchro- nous interface (all signals are registered on the positive edge of clock signal ck). read and write accesses to sdram module s are burst oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the devi ce bank and row to be accessed (ba0, ba1 select the device bank, a0?a11 select th e device row for the 256mb module; a0?a12 select the device row for the 512mb and 1gb mo dules). the address bits registered coin- cident with the read or write command are used to select the starting device column location for the burst access. sdram modules provide for programmable read or write burst lengths of 1, 2, 4, or 8 locations or full page, with a burst terminat e option. an auto precharge function may be enabled to provide a self-timed device row precharge that is initiated at the end of the burst sequence. sdram modules use an internal pipelined architecture. precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. sdram modules are designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a powe r-saving power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic device column-address generation, the ability to interleave between device banks to hide precharge time, and the capability to randomly change device column addresses on each clock cycle during a burst access. for more information regarding sdram opera- tion, refer to the 128mb, 256mb, and 512mb sdram component data sheets. pll and register operation these sdram modules either can be operated in registered mode (rege pin high), where the control/address input signals are latched in the register on one rising clock edge and sent to the sdram devices on the following rising clock edge (data access is delayed by one clock), or in buffered mode (rege pin low), where the input signals pass through the register/buffer to the sdra m devices on the same clock. a phase-lock loop (pll) on the modules is used to redrive the clock signals to the sdram devices to minimize system clock loading (ck0 is conne cted to the pll, and ck1, ck2, and ck3 are terminated).
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 7 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm general description serial presence-d etect operation sdram modules incorporate serial presence-d etect. the spd function is implemented using a 2,048-bit eeprom. this nonvolatile stor age device contains 256 bytes. the first 128 bytes are programmed by micron to id entify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, to gether with sa (2:0), which provide eight unique dimm/eeprom addresses. writ e protect (wp) is tied to v ss on the module, permanently disabling hardware write protect.
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 8 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm electrical specifications electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. design considerations micron memory modules are designed to op timize signal integr ity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good sign al integrity starts at the system level. micron encourages designers to simulate the signal characteristics of their systems? memory bus to ensure adequate signal integrity of the entire memory system. component ac timing an d operating conditions recommended ac operating conditions are given in the sdram component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 8. table 7: minimum and maximum ratings symbol parameter/condition min max units ? voltage on v dd supply relative to v ss ? absolute ?1.0 +4.6 v ? voltage on inputs, nc, or i/o pins relative to v ss ? absolute ?1.0 +4.6 v v dd , v dd q supply voltage ? operating +3.0 +3.6 v v ih input high voltage: logic 1; all inputs +2.0 v dd + 0.3 v v il input low voltage: logic 0; all inputs ?0.3 0.8 v i i input leakage current: any input 0v v in v dd (all other pins not under test = 0v) address inputs, ras#, cas#, we#, ba, ck ?10 +10 a cke, dqmb, s# ?5 +5 a i oz output leakage current: dq pins are disabled; 0v v out v dd q dq ?5 +5 a v oh output high voltage (i out = ?4ma) +2.4 ? v v ol output low voltage (i out = 4ma) ? 0.4 v t opr ambient operating temper ature (commercial) 0 +55 c table 8: module and component speed grades sdram components meet or exceed the listed module speed grades module speed grade component speed grade -13e -7e -133 -75
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 9 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm electrical specifications i dd specifications notes: 1. this value is calculated with one module rank in this op erating condition. all others ranks are in power-down mode. 2. the value calculated reflects all modu le ranks in this operating condition. notes: 1. this value is calculated with one module rank in this op erating condition. all other ranks are in power-down mode. 2. the value calculated reflects all modu le ranks in this operating condition. ta bl e 9 : i dd specifications and conditions ? 256mb values are shown for the mt48lc16m8a2 sdram compon ents only and are computed from values specified in the 128mb (16 meg x 8) component data sheet parameter/condition symbol -13e -133 units operating current: active mode; bl = 2; read or write; t rc = t rc (min) i dd 1 1 1,458 1,368 ma standby current: power-down mode; all device banks idle; cke = low i dd 2 2 36 36 ma standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 1 468 468 ma operating current: burst mode; page burst; read or write; all device banks active i dd 4 1 1,503 1,368 ma auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 2 5,940 5,580 ma t rfc = 15.625s i dd 6 2 54 54 ma self refresh current: cke 0.2v i dd 7 2 36 36 ma table 10: i dd specifications and conditions ? 512mb values are shown for the mt48lc32m8a2 sdram compon ents only and are computed from values specified in the 256mb (32 meg x 8) component data sheet parameter/condition symbol -13e -133 units operating current: active mode; bl = 2; read or write; t rc = t rc (min) i dd 1 1 1,233 1,143 ma standby current: power-down mode; all device banks idle; cke = low i dd 2 2 36 36 ma standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 1 378 378 ma operating current: burst mode; page burst; read or write; all device banks active i dd 4 1 1,233 1,233 ma auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 2 5,130 4,860 ma t rfc = 7.8125s i dd 6 2 63 63 ma self refresh current: cke 0.2v i dd 7 2 45 45 ma
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 10 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm electrical specifications notes: 1. this value is calculated with one module rank in this op erating condition. all other ranks are in power-down mode. 2. the value calculated reflects all modu le ranks in this operating condition. table 11: i dd specifications an d conditions ? 1gb values are shown for the mt48lc64m8a2 sdram compon ents only and are computed from values specified in the 512mb (64 meg x 8) component data sheet parameter/condition symbol -133 units operating current: active mode; bl = 2; read or write; t rc = t rc (min) i dd 1 1 1,121 ma standby current: power-down mode; all device banks idle; cke = low i dd 2 2 63 ma standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 1 423 ma operating current: burst mode; page burst; read or write; all device banks active i dd 4 1 1,066 ma auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 2 4,590 ma t rfc = 7.8125s i dd 6 2 108 ma self refresh current: cke 0.2v i dd 7 2 108 ma
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 11 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm register and pll specifications register and pll specifications notes: 1. ssc = spread spectrum cloc k. the use of ssc synthesizers on the system motherboard will reduce emi. 2. skew is defined as the total clock skew betw een any two outputs and, therefore, is speci- fied as a maximum only. table 12: register timing requirements and switching characteristics 162835a device or equivalent jesd82-2 parameter symbol condition min max units max clock pulse frequency f max ? 150 240 mhz propagation delay, single rank (ck to output) t pd1 50pf to gnd and 50 to v tt 1.4 3.5 ns propagation delay, dual rank (ck to output) t pd2 30pf to gnd and 50 to v tt 0.7 2.5 ns pulse duration t w ck, high or low 3.3 ? ns setup time t su data before ck high 1.0 ? ns hold time t h data after ck high 0.6 ? ns table 13: pll clock driver timing requirements and switching characteristics cdc2510 device or equivalent jesd82-5 parameter symbol min max units notes operating clock frequency f ck 50 140 mhz input duty cycle t dc 44 55 % cycle-to-cycle jitter t jit cc ?75 75 ps static phase offset t ? ?150 150 ps ssc induced skew t ssc ? 150 ps 1, 2 output-to-output skew t sk o ?150ps
pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 12 ?2001 micron technology, inc. all rights reserved 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. serial presence-detect data for the latest serial presence-detec t data, refer to micron?s spd page: www.micron.com/spd . table 14: serial presence-detect eeprom dc operating conditions parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li 0.10 3.0 a output leakage current: v out = gnd to v dd i lo 0.05 3.0 a standby current i sb 1.6 4.0 a power supply current, read: scl clock frequency = 100 khz i cc r 0.4 1.0 ma power supply current, write: scl clock frequency = 100 khz i cc w 2.0 3.0 ma table 15: serial presence-detect eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns clock/data fall time t f ? 300 ns 2 clock/data rise time t r ? 300 ns 2 data-in hold time t hd:dat 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of thei r respec- tive owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 256mb, 512mb, 1gb (x72, ecc, dr) 168-pin sdram rdimm module dimensions pdf: 09005aef809b1694/source: 09005aef809b166a micron technology, inc., reserves the right to change products or specifications without notice. sd18c32_64_128x72d.fm - rev. g 12/07 en 13 ?2001 micron technology, inc. all rights reserved. module dimensions figure 4: 168-pin sdram rdimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is fo r reference only. refer to the jedec mo document for addi- tional design dimensions. u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u14 u15 u16 u17 u18 u19 u20 u21 u22 u23 u24 43.31 (1.705) 43.05 (1.695) 3.25 (0.128) 3.0 (0.118) pin 1 17.78 (0.7) typ 3.0 (0.118) d (2x) 3.0 (0.118) typ 6.35 (0.25) typ 115.57 (4.55) typ 1.2 (0.05) typ 3.0 (0.118) typ 1.02 (0.04) typ 2.0 (0.079) r (2x) 1.0 (0.039) r (2x) pin 84 front view back view pin 168 pin 85 66.68 (2.625) typ 42.18 (1.661) typ 1.37 (0.054) 1.17 (0.046) 133.50 (5.256) 133.20 (5.244) 4.0 (0.157) max

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