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products and specifications discussed herein ar e subject to change by micron without notice. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__1.fm - rev. h 9/07 en 1 ?2004 micron technology, inc. all rights reserved. async/page/burst cellularram tm 1.5 mt45w8mw16bgx features ? single device supports asynchronous, page, and burst operations ?v cc , v cc q voltages ? 1.70?1.95v v cc ? 1.7?3.6v 1 v cc q ? random access time: 70ns ? burst mode read and write access ? 4, 8, 16, or 32 words, or continuous burst ? burst wrap or sequential ? max clock rate: 133 mhz ( t clk = 7.5ns) ? burst initial latency: 35ns (5 clocks) at 133 mhz ? t aclk: 5.5ns at 133 mhz ?page mode read access ? sixteen-word page size ? interpage read access: 70ns ? intrapage read access: 20ns ?low power consumption ? asynchronous read: <25ma ? intrapage read: <15ma ? initial access, burst read: (37.5ns [5 clocks] at 133 mhz) <45ma ? continuous burst read: <40ma ? standby: <50a (typ at 25 c) ? deep power-down: <3a (typ) ?low-power features ? on-chip temperature-compensated refresh (tcr) ? partial-array refresh (par) ? deep power-down (dpd) mode options designator ?configuration ? 8 meg x 16 mt45w8mw16b ? v cc core voltage: 1.70?1.95v ? v cc q i/o voltage: 1.7?3.6v 1 ?package ? 54-ball vfbga??green? gx ? timing ? 70ns access ?70 ? 85ns access ?85 figure 1: 54-ball vfbga ball assignment notes: 1. the 3.6v i/o and the 133mhz clock fre- quency exceed the cellularram 1.5 work- group specification. part number example: mt45w8mw16bgx-7013lwt options (continued) designator ?frequency ? 66 mhz 6 ? 80 mhz 8 ? 104 mhz 1 ? 133 mhz 13 ? standby power at 85c ? standard: 200a (max) none ? low power: 160a (max) l ? operating temperature range ? wireless (?30c to +85c) wt ? industrial (?40c to +85c) it a b c d e f g h j 1 2 3 4 5 6 top view (ball down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 wait oe# ub# dq10 dq11 dq12 dq13 a19 a8 clk a0 a3 a5 a17 a21 a14 a12 a9 adv# a2 ce# dq1 dq3 dq4 dq5 we# a11 rfu cre dq0 dq2 v cc v ss dq6 dq7 a20 rfu a1 a4 a6 a7 a16 a15 a13 a10 a22
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26ztoc.fm - rev. h 9/07 en 2 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/burst cellularram 1.5 table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 part-numbering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 burst mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 mixed-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 wait operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 temperature-compensated refresh (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 partial-array refresh (par) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 deep power-down mode (dpd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 access using cre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 software access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 bus configuration register (bcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 burst length (bcr[2:0]) default = continuous burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 burst wrap (bcr[3]) default = no wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 drive strength (bcr[5:4]) default = outputs use half-drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 wait configuration (bcr[8]) default = wait transitions on e clock before data valid/invalid . . . . . . . . .27 wait polarity (bcr[10]) default = wait active high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 latency counter (bcr[13:11]) default = three clock latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 initial access latency (bcr[14]) default = variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 operating mode (bcr[15]) default = asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 refresh configuration register (rcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 par (rcr[2:0]) default = full array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 dpd (rcr[4]) default = dpd disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 page mode operation (rcr[7]) default = disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 device identification register (didr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26zlof.fm - rev. h 9/07 en 3 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/burst cellularram 1.5 list of figures list of figures figure 1: 54-ball vfbga ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diagram ? 8 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: power-up initialization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: read operation (adv# low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: write operation (adv# low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: page mode read operation (adv# low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: burst mode read (4-wor d burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: burst mode write (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: wired-or wait configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 11: refresh collision during variable -latency read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 12: configuration register write, asynchronous mode, followed by read array operation . . . . .18 figure 13: configuration register write, synchronous mode followed by read array operation . . . . . . .19 figure 14: register read, asynchronous mode followed by read array operation . . . . . . . . . . . . . . . . . . . .20 figure 15: register read, synchronous mode followed by read array operation . . . . . . . . . . . . . . . . . . . . .21 figure 16: load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 17: read configuration regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 18: bus configuration register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 19: wait configuration (bcr[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 20: wait configuration (bcr[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 22: latency counter (variable initial latency, no refresh collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 24: refresh configuration register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 25: typical refresh current vs. temperature (i tcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 26: ac input/output reference wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 27: ac output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 28: initialization period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 29: dpd entry and exit timing parame ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 30: asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 31: asynchronous read using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 32: page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 33: single-access burst read operation ? variable latenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 34: 4-word burst read operation ? variable latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 35: single-access burst read operation ? fixed latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 36: 4-word burst read operation ? fi xed latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 37: read burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 38: burst read at end of row (wrap off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 39: ce#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 40: lb#/ub#-controlled asyn chronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 41: we#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 42: asynchronous write using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 43: burst write operation ? variable latency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 44: burst write operation ? fixed la tency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 45: burst write at end of row (wrap off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 46: burst write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 47: burst read interrupted by burst read or write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 48: burst write interrupted by burst write or read ? variable latency mode . . . . . . . . . . . . . . . . . .60 figure 49: burst write interrupted by burs t write or read ? fixed latency mode . . . . . . . . . . . . . . . . . . . . .61 figure 50: asynchronous write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 51: asynchronous write (adv# low) followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 52: burst read followed by asynchro nous write (we#-controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 53: burst read followed by asynchro nous write using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 54: asynchronous write followed by asynchronous read ? adv# low . . . . . . . . . . . . . . . . . . . . . . . .66 figure 56: 54-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26zlot.fm - rev. h 9/07 en 4 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/burst cellularram 1.5 list of tables list of tables table 1: vfbga ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 2: bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 3: sequence and burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 4: drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 5: variable latency configuration code s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 6: fixed latency configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 7: 128mb address patterns for par (rcr[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 8: device identification register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 9: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 10: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 11: par specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 12: deep power-down specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 13: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 14: asynchronous read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 15: burst read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 16: asynchronous write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 17: burst write cycle timing requiremen ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 18: initialization and dpd timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 5 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory general description micron ? cellularram? is a high-speed, cmos pseudo-static random access memory developed for low-power, portable applic ations. the mt45w8mw16bgx device has a 128mb dram core, organized as 8 meg x 16 bits. these devices include an industry- standard burst mode flash interface that dr amatically increases read/write bandwidth compared with other low-power sram or pseudo-sram offerings. to operate seamlessly on a burst flash bus, cellularram products incorporate a trans- parent self refresh mechanism. the hidden re fresh requires no addi tional support from the system memory controller and has no significant impact on device read/write performance. two user-accessible control registers define device operation. the bus configuration register (bcr) defines how the cellularram device interacts with the system memory bus and is nearly identical to its counterpar t on burst mode flash devices. the refresh configuration register (rcr) is used to co ntrol how refresh is performed on the dram array. these registers are automatically load ed with default settings during power-up and can be updated anytime during normal operation. special attention has been focused on standby current consumption during self refresh. cellularram products include three mechanisms to minimize standby current. partial- array refresh (par) enables the system to limi t refresh to only that part of the dram array that contains essential data. temperat ure-compensated refresh (tcr) uses an on- chip sensor to adjust the refresh rate to match the device temperature?the refresh rate decreases at lower temperatures to minimize current consumption during standby. deep power-down (dpd) enables the system to halt the refresh operation altogether when no vital information is stored in the device. the system-configurable refresh mechanisms are accessed through the rcr. this cellularram device is compliant wi th the industry-standard cellularram 1.5 feature set established by the cellularram work group. it includes support for both vari- able and fixed latency, with three output-device drive-streng th settings, additional wrap options, and a device id register (didr).
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 6 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 2: functional block diagram ? 8 meg x 16 notes: 1. functional block diagrams illustrate simplified device op eration. see ball descriptions (table 1 on page 7), bus operations table (table 2 on page 8), and timing diagrams for detailed information. a[22:0] input/ output mux and buffers control logic 8,192k x 16 dram memory array ce# we# oe# clk adv# cre wait lb# ub# dq[7:0] dq[15:8] refresh configuration register (rcr) device id register (didr) bus configuration register (bcr) address decode logic
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 7 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory notes: 1. the clk and adv# inputs can be tied to v ss if the device is always operating in asynchro- nous or page mode. wait will be asserted but should be ignored during asynchronous and page mode operations. table 1: vfbga ball descriptions note 1 vfbga assignment symbol type description j4, e3, h6, g2, h1, d3, e4, f4, f3, g4, g3, h5, h4, h3, h2, d4, c4, c3, b4, b3, a5, a4, a3 a[22:0] input address inputs: inputs for addresses during read and write operations. addresses are internally latched during read and write cycles. the address lines are also used to define the value to be loaded into the bcr or the rcr. j2 clk input clock: synchronizes the memory to th e system operating frequency during synchronous operations. when config ured for synchronous operation, the address is latched on the first rising clk edge when adv# is active. clk is static low during asyn chronous access read and write operations and during page read access operations. j3 adv# input address valid: indicates that a valid ad dress is present on the address inputs. addresses can be latched on the rising edge of adv# during asynchronous read and write operations. adv# can be held low during asynchronous read and write operations. a6 cre input control register enable: when cre is high, write operations load the rcr or bcr, and read operations access the rcr, bcr, or didr. b5 ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby or deep power-down mode. a2 oe# input output enable: enables the output buffers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: determines if a given cycl e is a write cycle. if we# is low, the cycle is a write to either a conf iguration register or to the memory array. a1 lb# input lower byte enable. dq[7:0] b2 ub# input upper byte enable. dq[15:8] g1, f1, f2, e2, d2, c2, c1, b1, g6, f6, f5, e5, d5, c6, c5, b6 dq[15:0] input/ output data inputs/outputs. j1 wait output wait: provides data-valid feedba ck during burst read and write operations. the signal is gated by ce#. wait is used to arbitrate collisions between refresh and read/write operations. wait is also asserted at the end of a row unless wrapping within th e burst length. wait is asserted and should be ignored during asynchronous and page mode operations. wait is high-z when ce# is high. j5, j6 rfu ? reserved for future use. d6 v cc supply device power supply: (1.7 ?1.95v) power supply for device core operation. e1 v cc q supply i/o power supply: (1.7?3.6v) power supply for input/ output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground.
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 8 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory notes: 1. clk must be low during as ync read and async write modes; and to achieve standby power during standby and dpd modes. clk must be static (high or low) during burst suspend. 2. the wait polarity is configured throug h the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are af fected. when only lb# is in select mode, dq[7:0] ar e affected. when only ub# is in the select mode, dq[15:8] are affected. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, addres s inputs and data inputs /outputs are internally isolated from any external influence. 6. v in = v cc q or 0v; all device balls must be static (uns witched) in order to achieve standby cur- rent. 7. dpd is initiated when ce# transitions from lo w to high after writing rcr[4] to 0. dpd is maintained until ce# transitions from high to low. 8. burst mode operation is initialized through the bus configuration register (bcr[15]). 9. initial cycle. following cycles are the same as burst continue. ce# must stay low for the equivalent of a single-word burst (as indicated by wait). table 2: bus operations asynchronous mode bcr[15] = 1 power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes read active l l l l h l l low-z data-out 4 write active l l l x l l l low-z data-in 4 standby standby l x h x x l x high-z high-z 5, 6 no operation idle l x l x x l x low-z x 4, 6 configuration register write active l l l h l h x low-z high-z configuration register read active l l l l h h l low-z config. reg. out dpd deep power-down lxhxxxxhigh-zhigh-z 7 burst mode bcr[15] = 0 power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes async read active l l l l h l l low-z data-out 4 async write active l l l x l l l low-z data-in 4 standby standby l x h x x l x high-z high-z 5, 6 no operation idle l x l x x l x low-z x 4, 6 initial burst read active l l x h l l low-z x 4, 8 initial burst write active l l h l l x low-z x 4, 8 burst continue active h l x x x l low-z data-in or data-out 4, 8 burst suspend active x x l h x x x low-z high-z 4, 8 configuration register write active l l h l h x low-z high-z 8, 9 configuration register read active l l l h h l low-z config. reg. out 8, 9 dpd deep power-down lxhxxxxhigh-zhigh-z7
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 9 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory part-numbering information micron cellularram devices are available in several different configurations and densities. (see figure 3.) figure 3: part number chart notes: 1. valid part number combinations: after bu ilding the part number from the part numbering chart above, please go to the micron parametric part search web site at http://www.micron.com/support/de signsupport/tools/fb ga/decoder to verify that the part number is offered and valid. if the device requ ired is not on this list, please contact the factory. 2. device marking: due to the si ze of the package, the micron standard part number is not printed on the top of the device. instead, an ab breviated device mark consisting of a five- digit alphanumeric code is us ed. the abbreviated device mark s are cross-referenced to the micron part numbers at http://www.micro n.com/support/de signsupport/tools/fbga/decoder . to view the location of the abbreviated mark on the devi ce, please refer to customer service note csn-11, ?product mark/label,? at http://www.micron.com/csn . 3. the 3.6v i/o exceeds the cellularram 1.5 workgroup specif ication of 1.95v. mt 45 w 8m w 16 b gx -70 8 wt es micron technology product family 45 = psram/cellularram memory operating core voltage w = 1.70?1.95v address locations m = megabits operating voltage w = 1.7?3.6v 3 bus configuration 16 = x16 read/write operation mode b = asynchronous/page/burst package codes gx = 54-ball ?green? vfbga (6 x 9 grid, 0.75mm pitch, 8.0mm x 10.0mm x 1.0mm) production status blank = production es = engineering sample ms = mechanical sample operating temperature wt = ?30c to +85c it = ?40c to +85c standby power options blank = standard l = low power frequency 6 = 66 mhz 8 = 80 mhz 1 = 104 mhz 13 = 133 mhz access/cycle time 70 = 70ns 85 = 85ns
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 10 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory functional description in general, the mt45w8mw16bgx device is a high-density alternative to sram and pseudo-sram products, popular in low-power, portable applications. the mt45w8mw16bgx contains a 134,217,728-bit dram core, organized as 8,388,608 addresses by 16 bits. the device implements the same high-speed bus interface found on burst mode flash products. the cellularram bus interface supports both asynchronous and burst mode transfers. page mode accesses are also included as a bandwidth-enhancing extension to the asyn- chronous read protocol. power-up initialization cellularram products include an on-chip volt age sensor used to launch the power-up initialization process. initialization will co nfigure the bcr and the rcr with their default settings. (see figure 18 on page 24 and figure 24 on page 31.) v cc and v cc q must be applied simultaneously. when they reach a stable level at or above 1.7v, the device will require 150s to complete its self-initializatio n process. during the initialization period, ce# should remain high. when initialization is complete, the device is ready for normal operation. figure 4: power-up initialization timing bus operating modes the mt45w8mw16bgx cellularram product incorporates a burst mode interface found on flash products targeting low-power, wireless applications. this bus interface supports asynchronous, page mode, and burst mode read and write transfers. the specific interface supported is defined by the value loaded into the bcr. page mode is controlled by the refresh configuration register (rcr[7]). asynchronous mode cellularram 1.5 products power up in the asynchronous operating mode. this mode uses the industry-standard sram control bus (ce#, oe#, we#, lb#/ub#). read opera- tions (figure 5 on page 11) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (see figure 6 on page 11) occur when ce#, we#, and lb#/ub# are driven low. during asynchronous write operations, the oe# level is a ?don't care,? and we# will override oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). asynchronous operations (page mode disabled) can either use the adv# inpu t to latch the address, or adv# can be driven low during the entire read/write operation. during asynchronous operation, the clk input must be held static low. wait will be driven while the device is enabled and its st ate should be ignored. we# low time must be limited to t cem. v cc v cc q device initialization v cc = 1.7v device ready for normal operation t pu > 150s
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 11 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 5: read operation (adv# low) notes: 1. adv# must remain low for page mode operation. figure 6: write operation (adv# low) address valid data ce# don?t care data valid oe# we# lb#/ub# t rc = read cycle time address address valid data ce# don?t care data valid oe# we# lb#/ub# t wc = write cycle time address < t cem
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 12 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory page mode read operation page mode is a performance-enhancing exte nsion to the legacy asynchronous read operation. in page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low- order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. any change in addresse s a[4] or higher will initiate a new t aa access time. figure 7 shows the timing for a page mo de access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write operations do not incl ude comparable page mode functionality. during asynchronous page mode operation, the clk input must be held low. ce# must be driven high upon completion of a page mode access. wait will be driven while the device is enabled and its state should be ignored. page mode is enabled by setting rcr[7] to high. adv# must be driven low during all page mode read accesses. due to refresh considerations, ce# must not be low longer than t cem. figure 7: page mode read operation (adv# low) data ce# don?t care oe# we# lb#/ub# address add 0 add 1 add 2 add 3 d1 d2 d3 t aa t apa < t cem t apa t apa d0
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 13 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory burst mode operation burst mode operations enable high-speed synchronous read and write operations. burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. after ce# goes low, the addres s to access is latched on the rising edge of the next clock that adv# is low. during this first clock rising edge, we# indicates whether the operation is going to be a read (we# = high, in figure 8 on page 14) or write (we# = low, in figure 9 on page 14). the size of a burst can be specified in the bcr either as a fixed length or as continuous. fixed-length bursts consist of four, eight, sixteen, or thirty-two words. continuous bursts have the ability to start at a specifie d address and burst to the end of the 128-word row. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is transferred between the processor and cellularram device. the initial latency for read operations can be configured as fixed or variable (write operations always use fixed latency) . variable latency enables the cellularram to be configured for minimum latency at high clock frequencies, but the controller must monitor wait to detect any conflict with refresh cycles. fixed latency outputs the first data word af ter the worst-case access delay, including allowance for refresh collisions. the initial latency time and clock speed determine the latency count setting. fixed latency is used when the controller cannot monitor wait. fixed latency also provides improved performance at lower clock frequencies. the wait output asserts when a burst is initia ted and de-asserts to indicate when data is to be transferred into (or out of ) the memo ry. wait will again be asserted at the boundary of the 128-word row unless wrapping within the burst length. to access other devices on the same bus with out the timing penalty of the initial latency for a new burst, burst mode can be suspended. bursts are suspended by stopping clk. clk can be stopped high or low. if another device will use the data bus while the burst is suspended, oe# should be taken high to disable the cellularram outputs; otherwise, oe# can remain low. note that the wait outp ut will continue to be active, and as a result, no other devices should directly shar e the wait connection to the controller. to continue the burst sequence, oe# is taken low, then clk is restarted after valid data is available on the bus. the ce# low time is limited by refresh considerations. ce# must not stay low longer than t cem. if a burst suspension will cause ce# to remain low for longer than t cem, ce# should be taken high and the burst restarted with a new ce# low/adv# low cycle.
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 14 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 8: burst mode read (4-word burst) notes: 1. non-default bcr settings for burst mode read (4-word burst): fixed or variable latency; latency code two (three clocks); wait active low; wait asserted during delay. the diagram above is representative of variable latency wi th no refresh collision or fixed-latency access. figure 9: burst mode write (4-word burst) notes: 1. non-default bcr settings for burst mode wr ite (4-word burst): fixed or variable latency; latency code two (three clocks); wait ac tive low; wait asserted during delay. a[22:0] d0 adv# ce# oe# d1 d2 d3 we# wait dq[15:0] lb#/ub# latency code 2 (3 clocks) clk undefined don?t care read burst identified (we# = high) address valid a[22:0] d0 adv# ce# oe# d1 d2 d3 we# wait dq[15:0] lb#/ub# address valid latency code 2 (3 clocks) clk don?t care write burst identified (we# = low)
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 15 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory mixed-mode operation the device supports a combination of sync hronous read and asynchronous read and write operations when the bcr is configur ed for synchronous operation. the asyn- chronous read and write operations require that the clock (clk) remain low during the entire sequence. the adv# signal can be used to latch the target address, or it can remain low during the entire write operation. ce# can remain low when transi- tioning between mixed-mode operations with fixed latency enabled; however, the ce# low time must not exceed t cem. mixed-mode operation faci litates a seamless interface to legacy burst mode flash memory controllers. see figure 50 on page 62 for the ?asyn- chronous write followed by burst read? timing diagram. wait operation the wait output on a cellularram device is typically connected to a shared, system- level wait signal. (see figure 10.) the shared wait signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. figure 10: wired-or wait configuration once a read or write operation has been initiated, wait goes active to indicate that the cellularram device requires additional time before data can be transferred. for read operations, wait will remain active until valid data is output from the device. for write operations, wait will indicate to th e memory controller when data will be accepted into the cellularram device. when wa it transitions to an inactive state, the data burst will progress on successive clock edges. during a burst cycle, ce# must remain asserted until the first data is valid. bringing ce# high during this initial latency may cause data corruption. when using variable initial access latency (b cr[14] = 0), the wait output performs an arbitration role for read operations launched while an on-chip refresh is in progress. if a collision occurs, wait is asserted for additional clock cycles until the refresh has completed. (see figure 11 on page 16.) when the refresh operation has completed, the read operation will continue normally. wait will be asserted but should be igno red during asynchronous read, write, and page read operations. by using fixed initial latency (bcr[14] = 1), this cellularram device can be used in burst mode without monitoring the wait signal. ho wever, wait can still be used to deter- mine when valid data is available at the star t of the burst and at the end of the row. if wait is not monitored, the controller must st op burst accesses at row boundaries on its own. cellularram external pull-up/ pull-down resistor processor ready other device wait other device wait wait
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 16 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory lb#/ub# operation the lb# enable and ub# enable signals supp ort byte-wide data writes. during write operations, any disabled bytes will not be transferred to the ram array and the internal value will remain unchanged. during an as ynchronous write cycle, the data to be written is latched on the rising edge of ce #, we#, lb#, or ub#, whichever occurs first. lb# and ub# must be low during read cycles. when both the lb# and ub# are disabled (hig h) during an operation, the device will disable the data bus from receiving or transm itting data. although the device will seem to be deselected, it remains in an ac tive mode as long as ce# remains low. figure 11: refresh collision during variable-latency read operation notes: 1. non-default bcr settings for refresh co llision during variable-l atency read operation: latency code two (three clocks); wait ac tive low; wait asserted during delay. a[22:0] adv# ce# oe# we# wait dq[15:0] clk v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol d2 d1 d3 valid address additional wait states inserted to allow refresh completion. lb#/ub# undefined don?t care d0 high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 17 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory low-power operation standby mode during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. stan dby operation occurs when ce# is high. the device will enter a reduced power state upon completion of a read or write oper- ation, or when the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature-compensa ted refresh (tcr) tcr allows for adequate refr esh at different temperatures. this cellularram device includes an on-chip temperature sensor th at automatically adjusts the refresh rate according to the operating temperature. the device continually adjusts the refresh rate to match that temperature. partial-array refresh (par) par restricts refresh operation to a portion of the total memory array. this feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one- quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map. (see table 7 on page 32.) read and write operations to address ranges receiving refresh will not be affected. data stored in addresses not receiving refres h will become corrupted. when re-enabling additional portions of the array, the ne w portions are availa ble immediately upon writing to the rcr. deep power-down mode (dpd) dpd mode disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellu- larram device will require 150s to perform an initialization procedure before normal operations can resume. during this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. dpd can be enabled by writing to the rcr using cre or the software access sequence; dpd starts when ce# goes high. dpd is disa bled the next time ce# goes low and stays low for at least 10s. registers two user-accessible configuration registers de fine the device operation. the bcr defines how the cellularram interacts with the system memory bus and is nearly identical to its counterpart on burst mode flash devices. the rcr is used to control how refresh is performed on the dram array. these regist ers are automatically loaded with default settings during power-up, and can be update d any time the devices are operating in a standby state. a didr provides information on the device manufacturer, cellularram generation, and the specific device configuration. the didr is read-only.
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 18 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory access using cre the registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (cre) inpu t is high. (see figures 12 through 15 on pages 18 through 21.) when cre is low, a read or write operation will access the memory array. the configuration register valu es are written via addresses a[22:0]. in an asynchronous write, the values are latched in to the configuration register on the rising edge of adv#, ce#, or we#, whichever occurs first; lb# and ub# are ?don?t care.? the bcr is accessed when a[19:18] are 10b; the rcr is accessed when a[19:18] are 00b. the didr is read when a[19:18] are 01b. for reads, address inputs other than a[19:18] are ?don?t care,? and register bits 15:0 are ou tput on dq[15:0]. micron strongly recommends reading the memory array immediately after performing a configur ation register read or write operation. figure 12: configuration register write, asynchronous mode, followed by read array operation notes: 1. a[19:18] = 00b to load rcr, and 10b to load bcr. a[22:0] (except a[19:18]) opcode address address data valid a[19:18] 1 adv# ce# oe# we# lb#/ub# dq[15:0] initiate control register access write address bus value to control register cre t avs t avh t avh t avs t vp t cph t wp t cw don?t care select control register
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 19 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 13: configuration register write, syn chronous mode followed by read array operation notes: 1. non-default bcr settings for synchronou s mode configuration register write followed by read array operation: latency code two (three clocks); wait active low; wait asserted during delay. 2. a[19:18] = 00b to load rc r, and 10b to load bcr. 3. ce# must remain low to complete a burst-of -one write. wait must be monitored?addi- tional wait cycles caused by refresh collis ions require a corresponding number of addi- tional ce# low cycles. clk a[22:0] (except a[19:18]) a[19:18] 2 cre adv# ce# oe# we# lb#/ub# wait dq[15:0] t sp t sp t sp t hd t hd t hd t csp t sp t hd high-z don?t care opcode address high-z t cew latch control register address t cbph 3 data valid address latch control register value
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 20 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 14: register read, asynchronous mode followed by read array operation notes: 1. a[19:18] = 00b to read rcr, 10b to read bcr, and 01b to read didr. a[22:0] (except a[19:18]) address address data valid cr valid a[19:18] 1 adv# ce# oe# we# lb#/ub# dq[15:0] initiate register access cre t avh t avs t aa t vp t cph t co t olz t ba t lz t oe t lz undefined don?t care select register t aavd t avs t aa t hz t ohz t bhz t avh
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 21 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 15: register read, synchronous mode followed by read array operation notes: 1. non-default bcr settings for synchron ous mode register read followed by read array operation: latency code two (thr ee clocks); wait active low; wait asserted during delay. 2. a[19:18] = 00b to read rcr, 10b to read bcr, and 01b to read didr. 3. ce# must remain low to complete a burst- of-one read. wait must be monitored?addi- tional wait cycles caused by refresh collis ions require a corresponding number of addi- tional ce# low cycles. clk a[22:0] (except a[19:18]) a[19:18] 2 cre adv# ce# oe# we# lb#/ub# wait dq[15:0] t sp t sp t sp t hd t hd t hd t hz t csp t koh undefined don?t care t sp t hd address t cew latch control register value t olz latch control register address t cbph 3 t boe data valid address t aclk t ohz high-z high-z t aba cr valid
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 22 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory software access software access of the registers uses a sequence of asynchronous read and asynchro- nous write operations. the contents of the configuration registers can be modified and all registers can be read using the software sequence. the configuration registers are loaded using a four-step sequence consisting of two asynchronous read operations followed by two asynchronous write operations. (see figure 16.) the read sequence is virtually iden tical except that an asynchronous read is performed during the fourth operation. (s ee figure 17 on page 23.) the address used during all read and write operations is th e highest address of the cellularram device being accessed (7fffffh for 128mb); the conten ts of this address are not changed by using this sequence. the data value presented during the third operation (write) in the sequence defines whether the bcr, rcr, or the didr is to be accessed. if the data is 0000h, the sequence will access the rcr; if the data is 0001h, the sequence will access the bcr; if the data is 0002h, the sequence will access the didr. during the fourth operation, dq[15:0] transfer data in to or out of bits 15?0 of the registers. the use of the software sequence does not affect the ability to perform the standard (cre-controlled) method of loading the conf iguration registers. however, the software nature of this access mechanism eliminates the need for cre. if the software mecha- nism is used, cre can simply be tied to v ss . the port line often used for cre control purposes is no longer required. figure 16: load configuration register notes: 1. it is possible that the data stored at the hi ghest memory location will be altered if the data at the falling edge of we# is not 0000h or 0001h. address (max) address (max) address (max) address (max) xxxxh xxxxh rcr: 0000h bcr: 0001h cr value in a ddress ce# oe# we# lb#/ub# data don?t care read read write write 0ns (min) note 1
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 23 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 17: read configuration register notes: 1. it is possible that the data stored at the hi ghest memory location will be altered if the data at the falling edge of we# is not 0000h, 0001h, or 0002h. address (max) address (max) address (max) address (max) xxxxh xxxxh cr value out address ce# oe# we# lb#/ub# data don't care read read write read rcr: 0000h bcr: 0001h didr: 000 2h 0ns (min) note 1
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 24 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory bus configuration register (bcr) the bcr defines how the cellularram device interacts with the system memory bus. page mode operation is enabled by a bit contained in the rcr. figure 18 describes the control bits in the bcr. at power-up, the bcr is set to 9d1fh. the bcr is accessed with cre high and a[19:18] = 10b or through the register access software sequence with dq = 0001h on the third cycle. figure 18: bus configuration register definition notes: 1. burst wrap and length apply to both read and write operations. a13 13 12 11 0 latency counter initial latency 3 2 1 wait polarity 4 5 wait configuration (wc) 6 7 8 drive strength burst wrap (bw) 14 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 operating mode synchronous burst access mode asynchronous access mode (default) bcr[12] bcr[11] latency counter bcr[13] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 code 8 code 1?reserved code 2 code 3 (default) code 4 code 5 code 6 code 7?reserved 0 1 wait polarity active low active high (default) bcr[10] 0 1 wait configuration asserted during delay asserted one data cycle before delay (default) drive strength full 1/2 (default) 1/4 reserved bcr[5] 0 0 1 1 bcr[4] 0 1 0 1 0 1 initial access latency variable (default) fixed bcr[14] burst wrap (note 1) burst wraps within the burst length burst no wrap (default) bcr[3] bcr[1] bcr[0] burst length (note 1) bcr[2] 15 burst length (bl) reserved reserved 9 10 operating mode reserved 22?20 a14 a15 a[17:16] 0 1 0 register select select rcr select bcr select didr 19?18 17?16 register select reserved a [ 19:18 ] a [ 22:20 ] reserved must be set to ?0? must be set to ?0? must be set to ?0? all must be set to ?0? bcr[8] bcr[15] bcr[19] 0 0 1 bcr[18] 0 1 0 0 0 1 1 0 1 1 0 1 others 1 0 1 0 1 4 words 8 words 16 words 32 words continuous burst (default) reserved setting is ignored (default to ?0?) 1 1
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 25 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory burst length (bcr[2:0]) default = continuous burst burst lengths define the number of words the device outputs during burst read and write operations. the device supports a burst length of 4, 8, 16, or 32 words. the device can also be set in continuous burst mode wher e data is accessed sequentially up to the end of the row. burst wrap (bcr[3]) default = no wrap the burst-wrap option determines if a 4-, 8-, 16-, or 32-word read or write burst wraps within the burst length or steps throug h sequential addresses. if the wrap option is not enabled, the device accesses data from sequential addresses up to the end of the row. ta bl e 3 : sequence and burst length burst wrap starting address 4-word burst length 8-word burst length 16-word burst length 32-word burst length continuous burst bcr [3] wrap (decimal) linear linear linear linear linear 0yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1 -2-3-4-5-6-7-8-9-10-11-12- 13-14-15 0-1-2-...-29-30- 31 0-1-2-3-4-5-6-? 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13- 14-15-0 1-2-3-...-30-31-0 1-2-3-4-5-6-7-? 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13- 14-15-0-1 2-3-4-...-31-0-1 2-3-4-5-6-7-8-? 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14- 15-0-1-2 3-4-5-...-0-1-2 3-4-5-6-7-8-9-? 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15- 0-1-2-3 4-5-6-...-1-2-3 4-5-6-7-8-9-10-? 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0- 1-2-3-4 5-6-7-...-2-3-4 5-6-7-8-9-10-11-? 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1- 2-3-4-5 6-7-8-...-3-4-5 6-7-8-9-10-11-12- 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2- 3-4-5-6 7-8-9-...-4-5-6 7-8-9-10-11-12-13- ? ... ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10- 11-12-13 14-15-16-...-11- 12-13 14-15-16-17-18-19- 20-... 15 15-0-1-2-3-4-5-6-7-8-9-10-11- 12-13-14 15-16-17-...-12- 13-14 15-16-17-18-19-20- 21-... ... ... ... 30 30-31-0-...-27- 28-29 30-31-32-33-34-... 31 31-0-1-...-28-29- 30 31-32-33-34-35-...
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 26 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory drive strength (bcr[5:4]) default = outputs use half-drive strength the output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. the reduced-strength options are intended for stacked chip (flash + cellularram) environments when there is a dedicated memory bus. the reduced-drive-strength option minimizes the noise generated on the data bus during read operations. full output drive strength should be selected when using a discrete cellularram device in a more heavily lo aded data bus environment. outputs are configured at half-drive strength during testing. see table 4 for additional information. 1no 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1 -2-3-4-5-6-7-8-9-10-11-12- 13-14-15 0-1-2...--29-30- 31 0-1-2-3-4-5-6-? 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13- 14-15-16 1-2-3-...-30-31- 32 1-2-3-4-5-6-7-? 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13- 14-15-16-17 2-3-4-...-31-32- 33 2-3-4-5-6-7-8-? 3 3-4-5-6 3-4-5-6-7-8-9-10 3- 4-5-6-7-8-9-10-11-12-13-14- 15-16-17-18 3-4-5-...-32-33- 34 3-4-5-6-7-8-9-? 4 4-5-6-7-8-9-10- 11 4-5-6-7-8-9-10-11-12-13-14-15- 16-17-18-19 4-5-6-...-33-34- 35 4-5-6-7-8-9-10-? 5 5-6-7-8-9-10-11- 12 5-6-7-8-9-10-11-12-13-...-15- 16-17-18-19-20 5-6-7-...-34-35- 36 5-6-7-8-9-10-11? 6 6-7-8-9-10-11- 12-13 6-7-8-9-10-11-12-13-14-...-16- 17-18-19-20-21 6-7-8-...-35-36- 37 6-7-8-9-10-11-12? 7 7-8-9-10-11-12- 13-14 7-8-9-10-11-12-13-14-...-17-18- 19-20-21-22 7-8-9-...-36-37- 38 7-8-9-10-11-12- 13? ... ... ... ... 14 14-15-16-17-18-19-...-23-24- 25-26-27-28-29 14-15-16-...-43- 44-45 14-15-16-17-18-19- 20-? 15 15-16-17-18-19-20-...-24-25- 26-27-28-29-30 15-16-17-...-44- 45-46 15-16-17-18-19-20- 21-? ... ... ... 30 30-31-32-...-59- 60-61 30-31-32-33-34-35- 36-... 31 31-32-33-...-60- 61-62 31-32-33-34-35-36- 37-... table 4: drive strength bcr[5] bcr[4] drive strength impedance typ ( ) use recommendation 0 0 full 25?30 cl = 30pf to 50pf 01 1/2 (default) 50 cl = 15pf to 30pf 104 mhz at light load 1 0 1/4 100 cl = 15pf or lower 1 1 reserved ta bl e 3 : sequence and burst length (continued) burst wrap starting address 4-word burst length 8-word burst length 16-word burst length 32-word burst length continuous burst bcr [3] wrap (decimal) linear linear linear linear linear
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 27 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory wait configuration (bcr[8]) default = wait tran sitions one clock before data valid/invalid the wait configuration bit is used to de termine when wait transitions between the asserted and the de-asserted state with respec t to valid data presented on the data bus. the memory controller will use the wait si gnal to coordinate data transfer during synchronous read and write operations. when bc r[8] = 0, data will be valid or invalid on the clock edge immediately after wait transitions to the de-asserted or asserted state, respectively. (see figures 19 and 21.) when bcr[8] = 1, the wait signal transitions one clock period prior to the data bus going valid or invalid. (see figures 20 and 21.) wait polarity (bcr[10]) default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether the wait signal requires a pull-up or pull-down resistor to maintain the de-asserted state. figure 19: wait configuration (bcr[8] = 0) notes: 1. data valid/invalid immediately after wa it transitions (bcr[8] = 0). (see figure 21.) figure 20: wait configuration (bcr[8] = 1) notes: 1. valid/invalid data delaye d for one clock after wait transit ions (bcr[8] = 1). (see figure 21.) wait dq[15:0] clk data 0 data 1 data immediately valid (or invalid) high-z wait dq[15:0] clk data 0 data valid (or invalid) after one clock delay high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 28 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 21: wait configuration during burst operation notes: 1. non-default bcr setting: wait active low. latency counter (bcr[13:11]) default = three clock latency the latency counter bits determine how many clocks occur between the beginning of a read or write operation and the first data value transferred. for allowable latency codes, see table 5, figure 22 on page 29, table 6 on page 29, and figure 23 on page 30. initial access latency (bcr[14]) default = variable variable initial access latency outputs data after the number of clocks set by the latency counter. however, wait must be monitored to detect delays caused by collisions with refresh operations. fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. the latency counter must be configured to match the initial latency and the clock frequency. it is not necessary to monitor wait with fixed initial latency. the burst begins after the number of clock cycles configured by the latency counter. (see table 6 and figure 23.) notes: 1. latency is the number of clock cycles from the initiation of a burst operation until data appears. data is transferred on the next clock cycle. table 5: variable latency configuration codes bcr[13:11] latency configuration code latency 1 max input clk frequency (mhz) normal refresh collision -7013 -701 -708 -856 010 2 (3 clocks) 2 4 66 (15.0ns) 66 (15n s) 52 (19.2ns) 40 (25ns) 011 3 (4 clocks)?default 3 6 104 (9.62ns) 104 (9. 62ns) 80 (12.5ns) 66 (15ns) 100 4 (5 clocks) 4 8 133 (7.5ns) ? ? ? others reserved ?? ? ? ?? wait wait dq[15:0] clk d0 bcr[8] = 0 data valid in current cycle. bcr[8] = 1 data valid in next cycle. don?t care d1 d2 d3 end of row
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 29 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 22: latency counter (variable initial latency, no refresh collision) table 6: fixed latenc y configuration codes bcr[13:11] latency configuration code latency count (n) max input clk frequency (mhz) -7013 -701 -708 -856 010 2 (3 clocks) 2 33 (30ns) 33 (30ns) 33 (30ns) 20 (50ns) 011 3 (4 clocks)?default 3 52 (19.2ns) 52 (19.2ns) 52 (19.2ns) 33 (30ns) 100 4 (5 clocks) 4 66 (15ns) 66 (15ns) 66 (15ns) 40 (25ns) 101 5 (6 clocks) 5 75 (13.3ns) 75 (13.3ns) 75 (13.3ns) 52 (19.2ns) 110 6 (7 clocks) 6 104 (9.62ns) 104 (9.62ns) 80 (12.5ns) 66 (15ns) 000 8 (9 clocks) 8133 (7.5ns) others reserved ????? a[22:0] adv# dq[15:0] clk code 2 valid output valid output valid output valid output valid output valid output valid output valid output valid output code 3 (default) dq[15:0] don?t care undefined v ih v il v ih v il v ih v il v oh v ol v oh v ol valid address
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 30 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 23: latency counter (fixed latency) operating mode (bcr[15]) default = asynchronous operation the operating mode bit selects either synchr onous burst operation or the default asyn- chronous mode of operation. a[22:0] adv# dq[15:0] (read) clk valid output valid output valid output valid output valid output don?t care undefined v ih v il v ih v il v ih v il ce# v ih v il v oh v ol t aadv t aa t co t aclk t sp t hd dq[15:0] (write) v oh v ol n-1 cycles cycle n valid input valid input valid input valid input valid input burst identified (adv# = low) valid address
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 31 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory refresh configuration register (rcr) the rcr defines how the cellularram device performs its transparent self refresh. altering the refresh parameters can dramat ically reduce curren t consumption during standby mode. page mode control is also em bedded into the rcr. figure 24 describes the control bits used in the rcr. at power-up, the rcr is set to 0010h. the rcr is accessed with cre high and a[19: 18] = 00b or through the register access software sequence with dq = 0000h on the third cycle. (see ?registers? on page 17.) par (rcr[2:0]) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the device to reduce standby cu rrent by refreshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map. (see table 12 on page 36.) figure 24: refresh configuration register mapping par a4 a3 a2 a1 a0 address bus 4 5 1 2 3 0 6 a5 0 1 deep power-down dpd enable dpd disable (default) rcr[4] a6 all must be set to ?0? a[17:8] 17?8 19?18 22?20 register select reserved reserved reserved reserved a[22:20] a[19:18] register select select rcr select bcr select didr rcr[19] all must be set to ?0? rcr[1] 0 0 1 1 rcr[0] 0 1 0 1 refresh coverage full array (default) bottom 1/2 array bottom 1/4 array bottom 1/8 array rcr[2] 0 0 0 0 00 1 0 1 1 1 0 1 11 1 none of array top 1/2 array top 1/4 array top 1/8 array dpd must be set to ?0? setting is ignored (default 00b) a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enable rcr[7] 0 1 0 rcr[18] 0 0 1
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 32 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory dpd (rcr[4]) default = dpd disabled the deep power-down bit enables and disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initialization proce- dure before normal operations can resume. deep power-down is enabled by setting rc r[4] = 0 and taking ce# high. dpd can be enabled using cre or the software sequence to access the rcr. taking ce# low for at least 10s disables dpd and sets rcr[4] = 1; it is not necessary to writ e to the rcr to disable dpd. bcr and rcr values (other than bcr[4]) are preserved during dpd. page mode operation (rcr[7]) default = disabled the page mode operation bit determines wh ether page mode is enabled for asynchro- nous read operations. in the power-up default state, page mode is disabled. device identificatio n register (didr) the didr provides information on the devi ce manufacturer, cellularram generation, and the specific device configuration. table 8 describes the bit fields in the didr. this register is read-only. the didr is accessed with cre high and a[ 19:18] = 01b, or through the register access software sequence with dq = 0002h on the third cycle. notes: 1. vendors with 256-word ro w lengths for cellularram 1.5 devi ces will set didr[15] to 1b. table 7: 128mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?7fffffh 8 meg x 16 128mb 0 0 1 one-half of die 000000h?3fffffh 4 meg x 16 64mb 0 1 0 one-quarter of die 000000h?1fffffh 2 meg x 16 32mb 0 1 1 one-eighth of die 000000h?0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 400000h?7fffffh 4 meg x 16 64mb 1 1 0 one-quarter of die 600000h?7fffffh 2 meg x 16 32mb 1 1 1 one-eighth of die 700000h?7fffffh 1 meg x 16 16mb table 8: device identifi cation register mapping bit field didr[15] didr[14:11] didr[10:8] didr[7:5] didr[4:0] field name row length device version d evice density cellularram generation vendor id bit setting 0b bit setting version 011b 010b 00011b 0000b 1st 0001b 2nd 0010b 3rd (etc.) (etc.) meaning 128 words 128mb cellularram 1.5 micron
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 33 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory electrical specifications notes: 1. the 4.0v maximum v cc q voltage exceeds the 2.45v cellularram 1.5 workgroup specification. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. table 9: absolute maximum ratings parameter rating voltage to any ball except v cc , v cc q relative to v ss ?0.5v to (4.0v or v cc q + 0.3v, whichever is less) voltage on v cc supply relative to v ss ?0.2v to +2.45v voltage on v cc q supply relative to v ss ?0.2v to +4.0v 1 storage temperature (plastic) ?55oc to +150oc operating temperature (case) wireless ?30oc to +85oc industrial ?40oc to +85oc soldering temperature and time 10s (solder ball only) +260oc
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 34 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory notes: 1. the 3.6v i/o exceeds the cellular ram 1.5 workgroup spec ification of 1.95v. 2. input signals may overshoot to v cc q + 1.0v for periods less than 2ns during transitions. 3. input signals ma y undershoot to v ss - 1.0v for periods less than 2ns during transitions. 4. bcr[5:4] = 01b (default setting of one-half drive strength). 5. this parameter is specified wi th the outputs disabl ed to avoid external loading effects. the user must add the current required to driv e output capacitance expected in the actual system. 6. micron devices are fully compatible with the cellularram workgroup specification for i cc 1p: ?70 max of 18; ?85 max of 15. 7. i sb (max) values measured with par set to fu ll array and at +85c. in order to achieve low standby current, all inputs must be driven to either v cc q or v ss . i sb might be slightly higher for up to 500ms after power- up or when entering standby mode. 8. i sb (typ) is the average i sb at 25c and v cc = v cc q = 1.8v. this parameter is verified during characterization and is not 100-percent tested. 9. i cc 1p specifications are less than the cr1.5 limits of 18ma and 15ma. table 10: electrical characteristics and operating conditions wireless temperature (?30oc < t c < +85oc); industrial temperature (?40oc < t c < +85oc) description conditions symbol min max unit notes supply voltage v cc 1.7 1.95 v i/o supply voltage v cc q 1.7 3.6v v 1 input high voltage v ih v cc q - 0.4 v cc q + 0.2 v 2 input low voltage v il ?0.2 0.4 v 3 output high voltage i oh = ?0.2ma v oh 0.8 v cc qv4 output low voltage i ol = +0.2ma v ol 0.2 v cc qv 4 input leakage current v in = 0 to v cc qi li 1a output leakage current oe# = v ih or chip disabled i lo 1a operating current conditions symbol typ max unit notes asynchronous random read/write v in = v cc q or 0v chip enabled, i out = 0 i cc 1 ?70 25 ma 5 ?85 22 asynchronous page read i cc 1p ?70 15 ma 5, 6, 9 ?85 12 initial access, burst read/write i cc 2133 mhz 45 ma 5 104 mhz 35 80 mhz 30 66 mhz 25 continuous burst read i cc 3r 133 mhz 40 ma 5 104 mhz 30 80 mhz 25 66 mhz 20 continuous burst write i cc 3w 133 mhz 40 ma 5 104 mhz 35 80 mhz 30 66 mhz 25 standby current v in = v cc q or 0v ce# = v cc q i sb standard 50 200 a 7, 8 low-power (l) 160
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 35 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory notes: 1. i par (max) values measured at 85c. in order to achieve low standb y current, all inputs must be driven to either v cc q or v ss . i par might be slightly high er for up to 500ms after power-up or when entering standby mode. figure 25: typical refresh current vs. temperature (i tcr ) table 11: par specifications and conditions description conditions symbol array partition max units partial-array re fresh standby current v in = v cc q or 0v, ce# = v cc q i par standard power (no designation) full 200 a 1/2 170 1/4 155 1/8 150 0 140 low-power option (l) full 160 a 1/2 130 1/4 115 1/8 110 0 100 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 typical current temperature (c) par = full array par = 1/2 of array par = 1/4 of array par = 1/8 of array par = none of array 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 36 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 26: ac input/output reference waveform notes: 1. ac test inputs are driven at v cc q for a logic 1 and v ss q for a logic 0. input rise and fall times (10 percent to 90 percent) <1.6ns. 2. input timing begins at v cc q/2. 3. output timing ends at v cc q/2. figure 27: ac output load circuit notes: 1. all tests are performed with the outputs configured for default setting of half drive strength (bcr[5:4] = 01b). table 12: deep power-down specifications typical (typ) i zz value applies across all oper ating temperatures and voltages description conditions symbol typ max unit deep power-down v in = v cc q or 0v; v cc , v cc q = 1.95v; +85c i zz 310a table 13: capacitance these parameters are verified in device char acterization and are not 100-percent tested description conditions symbol min max units input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in 2.0 6 pf input/output capacitance (dq) c io 3.5 6 pf output test points input 1 v cc q v ss q v cc q/2 3 v cc q/2 2 dut vccq/2 30pf test point 50
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 37 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory timing requirements notes: 1. low-z to high-z timings are tested with the circuit show n in figure 27 on page 36. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. 2. high-z to low-z timi ngs are tested with the circuit shown in figure 27 on page 36. the low- z timings measure a 100mv trans ition away from the high-z (v cc q/2) level toward either v oh or v ol . 3. page mode en abled only. table 14: asynchronous read cycle timing requirements all tests performed with outputs configured for default setting of one-half drive strength, (bcr[5:4] = 01b) parameter symbol 70ns 85ns unit notes min max min max address access time t aa 70 85 ns adv# access time t aadv 70 85 ns page access time t apa 20 25 ns address hold from adv# high t avh 22ns address setup to adv# high t avs 55ns lb#/ub# access time t ba 70 85 ns lb#/ub# disable to dq high-z output t bhz 88ns1 lb#/ub# enable to low-z output t blz 10 10 ns 2 maximum ce# pulse width t cem 44s3 ce# low to wait valid t cew 17.517.5ns chip select access time t co 70 85 ns ce# low to adv# high t cvs 77ns chip disable to dq and wait high-z output t hz 88ns1 chip enable to low-z output t lz 10 10 ns 2 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to dq high-z output t ohz 88ns1 output enable to low-z output t olz 33ns2 page read cycle time t pc 20 25 ns read cycle time t rc 70 85 ns adv# pulse width low t vp 57ns
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 38 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory notes: 1. values are valid for t clk (min) with no refresh collision: lc= 4 for -7013; lc = 3 for -701, -708, and -856. 2. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. 3. low-z to high-z timings are tested with the circuit shown in figure 27 on page 36. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. 4. high-z to low-z timings are tested with the circuit shown in figure 27 on page 36. the low-z timings measure a 100mv tra nsition away from the high-z (v cc q/2) level toward either v oh or v ol . table 15: burst read cycle timing requirements all tests performed with outputs configured for default setting of one-half drive streng th (bcr[5:4 ] = 01b). parameter symbol -7013 (133 mhz) -701 (104 mhz) -708 (80 mhz) -856 (66 mhz) unit notes min max min max min max min max address access time (fixed latency) t aa 70 70 70 85 ns adv# access time (fixed latency) t aadv 70 70 70 85 ns burst to read access time (variable latency) t aba 35.5 35.9 46.5 55 ns 1 clk to output delay variable lc = 4 fixed lc = 8 t aclk 5.5 7 9 11 ns all other lcs 77911ns address hold from adv# high (fixed latency) t avh 2222 ns burst oe# low to output delay t boe 20 20 20 20 ns ce# high between subsequent burst or mixed-mode operations t cbph 55 68 ns 2 maximum ce# pulse width t cem 444 4s2 ce# low to wait valid t cew 1 7.5 1 7.5 1 7.5 1 7.5 ns clk period t clk 7.5 9.62 12.5 15 ns chip select access time (fixed latency) t co 70 70 70 85 ns ce# setup time to active clk edge t csp 2.5 3 4 5 ns hold time from active clk edge t hd 1.5 2 2 2 ns chip disable to dq and wait high-z output t hz 78 8 8ns 4 clk rise or fall time t khkl 1.2 1.6 1.8 2.0 ns clk to wait valid variable lc = 4 fixed lc = 8 t khtl 5.5 7 9 11 ns all other lcs 77911ns output hold from clk t koh 22 22 ns clk high or low time t kp 33 45 ns output disable to dq high-z output t ohz 788 8ns 3 output enable to low-z output t olz 3333 ns 4 setup time to active clk edge t sp 23 33 ns
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 39 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory notes: 1. low-z to high-z timings are tested with the circuit show n in figure 27 on page 36. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. 2. high-z to low-z timi ngs are tested with the circuit shown in figure 27 on page 36. the low- z timings measure a 100mv trans ition away from the high-z (v cc q/2) level toward either v oh or v ol . 3. we# low time must be limited to t cem (4s). table 16: asynchronous write cycle timing requirements parameter symbol 70ns 85ns unit notes min max min max address and adv# low setup time t as 00ns address hold from adv# going high t avh 22ns address setup to adv# going high t avs 55ns address valid to end of write t aw 70 85 ns lb#/ub# select to end of write t bw 70 85 ns ce# low to wait valid t cew 1 7.5 1 7.5 ns ce# high between subsequent async operations t cph 55ns ce# low to adv# high t cvs 77ns chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 20 20 ns chip disable to wait high-z output t hz 88ns1 chip enable to low-z output t lz 10 10 ns 2 end write to low-z output t ow 55ns2 adv# pulse width t vp 57ns adv# setup to end of write t vs 70 85 ns write cycle time t wc 70 85 ns write to dq high-z output t whz 88ns1 write pulse width t wp 45 55 ns 3 write pulse width high t wph 10 10 ns write recovery time t wr 00ns
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 40 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory . notes: 1. t as is required if t csp > 20ns. 2. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. 3. low-z to high-z timings are tested with the circuit shown in figure 27 on page 36. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. table 17: burst write cycle timing requirements parameter symbol -7013 (133 mhz) -701 (104 mhz) -708 (80 mhz) -856 (66 mhz) unit notes min max min max min max min max address and adv# low setup time t as 0000ns1 address hold from adv# high (fixed latency) t avh 2222ns ce# high between subsequent burst or mixed-mode operations t cbph 55 68ns2 maximum ce# pulse width t cem 4444s2 ce# low to wait valid t cew 1 7.5 1 7.5 1 7.5 1 7.5 ns clock period t clk 7.5 9.62 12.5 15 ns ce# setup to clk active edge t csp 2.5 3 4 5 ns hold time from active clk edge t hd 1.5 2 2 2 ns chip disable to wait high-z output t hz 7888ns3 clk rise or fall time t khkl 1.2 1.6 1.8 2.0 ns clk to wait valid variable lc = 4 fixed lc = 8 t khtl 5.5 7 9 11 ns all other lcs 77911ns clk high or low time t kp 3345ns setup time to active clk edge t sp 23 33ns
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 41 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory timing diagrams figure 28: initialization period figure 29: dpd entry and exit timing parameters notes: 1. the cellularram workgroup 1.5 specification is a minimum of 150s. table 18: initialization and dpd timing parameters parameter symbol -701/708 -856 unit notes min max min max time from dpd entry to dpd exit t dpd 10 10 s 1 ce# low time to exit dpd t dpdx 10 10 s initialization period (require d before normal operations) t pu 150 150 s t pu v cc , v cc q = 1.7v v cc (min) device ready for normal operation ce# dpd enabled write rcr[4] = 0 dpd exit device initialization device ready for normal operation t dpd t dpdx t pu
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 42 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 30: asynchronous read v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t aa t hz t ba high-z high-z t rc t co t bhz t ohz t hz t oe t cew valid output high-z undefined don?t care t blz t lz t olz
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 43 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 31: asynchro nous read using adv# a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t aadv t aa t vp t hz t ba high-z high-z t cvs t co t blz t bhz t ohz t hz t lz t oe t olz valid output t avh t avs high-z undefined don?t care t cew v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 44 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 32: page mode read a[3:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t aa t hz t ba high-z high-z t co t cem t blz t bhz t ohz t hz t lz t oe t olz t cew high-z undefined don?t care a[22:4] valid address valid address valid address valid address t rc valid output t apa t pc v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol t oh valid output valid output valid output
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 45 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 33: single-access burst read operation ? variable latency notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t cew t hd t aba t hd valid output valid address high-z t koh t ohz t sp lb#/ub# v ih v il t csp t cem high-z t olz t hd t hd t sp t hz t kp t kp t khkl t hd t sp undefined don?t care read burst identified (we# = high) t khtl t boe high-z t aclk
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 46 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 34: 4-word burst read operation ? variable latency notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t khkl t hd t aba valid address high-z t koh t hz t hd t sp lb#/ub# v ih v il high-z t olz high-z t cbph t csp t cem t sp t hd t sp t hd t ohz t hd t kp t kp undefined don?t care read burst identified (we# = high) t cew t aclk t khtl valid output valid output valid output valid output t boe
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 47 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 35: single-access burst read operation ? fixed latency notes: 1. non-default bcr settings: fixed latency; late ncy code four (five cloc ks); wait active low; wait asserted during delay. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t clk t cew t avh t co t aadv t aa t hd valid output valid address high-z t koh t ohz t sp t sp lb#/ub# v ih v il t csp t cem high-z t olz t hd t hd t sp t hz t kp t kp t khkl t hd t sp undefined don?t care read burst identified (we# = high) t khtl t boe high-z t aclk
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 48 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 36: 4-word burst read operation ? fixed latency notes: 1. non-default bcr settings: fixed latency; late ncy code two (three cloc ks); wait active low; wait asserted during delay. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t avh t clk t khkl t co t aadv t aa high-z t koh t hz t hd t sp t sp lb#/ub# v ih v il high-z t olz high-z t cbph t csp t cem t sp t hd t sp t hd t ohz t hd t kp t kp undefined don?t care read burst identified (we# = high) t cew t khtl t aclk valid output valid output valid output valid output t boe valid address
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 49 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 37: read burst suspend notes: 1. non-default bcr settings for read burst susp end: fixed or variable latency; latency code two (three clocks); wait active low; wait asserted during delay. 2. clk can be stopped low or high, but must be static, with no low-to-high transitions dur- ing burst suspend. 3. oe# can stay low during burst su spend. if oe# is low, dq[15: 0] will continue to output valid data. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t hd high-z t olz t aclk lb#/ub# v ih v il t clk t sp t csp t sp t hd t hd t sp t hd t koh valid output valid output undefined don?t care valid address high-z t cbph t cem t hz t ohz valid output valid output valid output valid output t boe t ohz t boe t olz valid address note 3 note 2 high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 50 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 38: burst read at end of row (wrap off) notes: 1. non-default bcr settings for burst read at end of row: fixed or variable latency; wait active low; wait asserted during delay. 2. for burst reads, ce# must go high before th e third clk after the wait period begins (before the third clk after wait asserts with bcr[8] = 0, or before the fourth clk after wait asserts with bcr[8] = 1). micron device s are fully compatible with the cellularram workgroup specification that re quires ce# to go high one cycle sooner than shown here. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t khtl t hz t clk lb#/ub# v ih v il valid output don?t care valid output end of row t hz high-z note 2
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 51 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 39: ce#-controlled asynchronous write a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in valid address high-z high-z t wc t cew t hz valid input t aw don?t care t wr t cw t cph t dw dq[15:0] out t whz t bw t lz t dh t as t wp t wph v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 52 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 40: lb#/ub#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address high-z t wc t cew t hz valid input t aw don?t care t wr t cw t dw dq[15:0] out v oh v ol t whz t bw t lz t dh t as t wp t wph high-z high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 53 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 41: we#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address t wc t cew t hz valid input t aw don?t care t wr t dw dq[15:0] out v oh v ol t whz t bw t cw t lz t wp t dh t ow t as t wph high-z high-z high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 54 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 42: asynchronous write using adv# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address high-z high-z t cew t hz valid input t vs don?t care t cw t dw dq[15:0] out v oh v ol t whz t bw t lz t wp t dh t ow t as t wph t as t avh t avs t vp t aw high-z t cvs
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 55 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 43: burst write operation ? variable latency mode notes: 1. non-default bcr settings for burst write op eration in variable latency mode: latency code two (three clocks); wait active low; wait asserted during delay; burst length of four; burst-wrap enabled. 2. wait asserts for lc cycles for both fixe d and variable latency. lc = latency code (bcr[13:11]). 3. t as required if t csp > 20ns. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t clk t kp t sp t as 3 t csp d0 d3 d2 d1 valid address t hd t sp t hd t sp t hd t hd t sp high-z high-z lb#/ub# v ih v il t sp t hd t hd don?t care write burst identified (we# = low) t cbph t khtl t as 3 t hz t cew t kp t khkl note 2 t cem
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 56 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 44: burst write operation ? fixed latency mode notes: 1. non-default bcr settings for burst write operation in fixed latenc y mode: fixed latency; latency code two (three cl ocks); wait active low; wait as serted during delay; burst length four; burst wrap enabled. 2. wait asserts for lc cycles for both fixe d and variable latency. lc = latency code (bcr[13:11]). 3. t as required if t csp > 20ns. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t clk t kp t sp t as 3 t csp d0 d3 d2 d1 valid address t hd t sp t hd t sp t hd t sp high-z high-z lb#/ub# v ih v il t sp t hd t hd don?t care write burst identified (we# = low) t cbph t khtl t as 3 t hz t cew t kp t khkl note 2 t cem t avh
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 57 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 45: burst write at end of row (wrap off) notes: 1. non-default bcr settings for burst write at end of row: fixed or variable latency; wait active low; wait asserted during delay. 2. for burst writes, ce# must go high before the third clk after the wait period begins (before the third clk after wait asserts with bcr[8] = 0, or before the fourth clk after wait asserts with bcr[8] = 1). 3. devices from different cellularram vendors can assert wait so that the end-of-row data is input one cycle before the wait period begins (a s shown, solid line), or the same cycle that asserts wait. this difference in behavior will not be noticed by controllers that monitor wait, or that use wait to abort on an end-of-row condition. 4. micron devices are fully compatible with the cellularram workgro up specification that requires ce# to go high one cycle sooner than shown here. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t khtl t hz t hz t clk t sp t hd end of row (a[6:0] = 7fh) valid input valid input don?t care v ih v il lb#/ub# high-z note 2 note 3
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 58 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 46: burst write followed by burst read notes: 1. non-default bcr settings fo r burst write followed by burst read : fixed or variable latency; latency code two (three clocks); wait ac tive low; wait asserted during delay. 2. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. ce# can stay low between burst read an d burst write operatio ns, but ce# must not remain low longer than t cem. see burst interrupt diagra ms (figures 47 th rough 49, on pages 59 through 61) for cases where ce# stays low between bursts. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il t clk t sp t sp t csp d3 d2 d1 d0 valid address t hd t sp t hd t sp t sp t hd valid address t csp t ohz t koh t aclk valid output valid output valid output valid output high-z high-z v oh v ol lb#/ub# v ih v il t hd t sp t hd t sp t hd t hd high-z undefined don?t care t boe t cbph high-z t hd t hd t sp note 2
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 59 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 47: burst read interrupted by burst read or write notes: 1. non-default bcr settings for burst read inte rrupted by burst read or write: fixed or vari- able latency code two (three clocks); wait ac tive low; wait asserted during delay. all bursts shown for variable late ncy; no refresh collision. 2. burst interrupt shown on first allowable clock (for example, after the first data received by the controller). 3. ce# can stay low between burst operations, but ce# must not remain low longer than t cem. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# 2nd cycle read v ih v il oe# 2nd cycle write v ih v il we# v ih v il wait dq[15:0] out 2nd cycle read v oh v ol clk v ih v il dq[15:0] in 2nd cycle write v ih v il t hd t sp t sp t hd t clk t ohz t koh t aclk valid output valid output valid output valid output lb#/ub# 2nd cycle read v ih v il lb#/ub# 2nd cycle write v ih v il t sp t hd undefined don?t care t hd t sp t csp t sp t hd valid address t ohz t koh t aclk valid output high-z t boe t cew t sp t hd t hd t sp v oh v ol t boe d2 d3 d1 d0 high-z t cem (note 3) valid address read burst interrupted with new read or write. see note 2. high-z t khtl t hd high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 60 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 48: burst write interrupted by bur st write or read ? variable latency mode notes: 1. non-default bcr settings for burst write interrupted by burst writ e or read in variable latency mode: variable latency; latency code two (three clocks); wait active low; wait asserted during delay. all bursts shown fo r variable latency; no refresh collision. 2. burst interrupt shown on first allowable cl ock (i.e., after first data word written). 3. ce# can stay low between burst operations, but ce# must not remain low longer than t cem. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# 2nd cycle write v ih v il oe# 2nd cycle read v ih v il we# v ih v il wait dq[15:0] in 2nd cycle write dq[15:0] out 2nd cycle read v oh v ol clk v ih v il v ih v il t clk t sp t sp t csp d0 valid address t hd t sp t hd t sp t sp t hd valid address t hd high-z lb#/ub# 2nd cycle write lb#/ub# 2nd cycle read v ih v il v ih v il t hd t sp t hd t khtl t sp t hd undefined don?t care d2 d3 d1 d0 t hd t sp t hd t hd t sp t ohz t boe t sp t hd t koh t aclk valid output valid output valid output valid output high-z v oh v ol v oh v ol write burst interrupted with new write or read. see note 2. valid address t cem (note 3) t cew high-z high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 61 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 49: burst write interrupted by burst write or read ? fixed latency mode notes: 1. non-default bcr settings for burst wri te interrupted by burst write or read in fixed latency mode: fixed late ncy; latency code two (three cl ocks); wait active low; wait asserted during delay. 2. burst interrupt shown on first allowable cl ock (i.e., after first data word written). 3. ce# can stay low between burst operations, but ce# must not remain low longer than t cem. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# 2nd cycle write v ih v il oe# 2nd cycle read v ih v il we# v ih v il wait dq[15:0] in 2nd cycle write dq[15:0] out 2nd cycle read v oh v ol clk v ih v il v ih v il t clk t sp t sp t csp d0 valid address t hd t sp t hd t sp t sp t sp t hd high-z lb#/ub# 2nd cycle write lb#/ub# 2nd cycle read v ih v il v ih v il t sp t hd t sp t hd undefined don?t care t hd d2 d3 d1 d0 t hd t sp t hd t sp t ohz t boe t koh t aclk valid output valid output valid output valid output high-z v oh v ol v oh v ol t khtl write burst interrupted with new write or read. see note 2. valid address t cem ( note 3 ) t avh t avh t hd t cew high-z high-z
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 62 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 50: asynchronous wr ite followed by burst read notes: 1. non-default bcr settings for asynchronous write followed by burst read: fixed or variable latency; latency code two (three clocks); wa it active low; wait asserted during delay. 2. when transitioning be tween asynchronous and variable-l atency burst operations, ce# must go high. ce# can stay low when transitioning to fixed-latency burst reads. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. t clk t sp t hd t sp valid address t ohz t koh t aclk high-z high-z valid address valid address t avs t avh t aw t wr t vp t vs a[22:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t cvs t wph t as t as t wp t wc t dh t dw data data high-z t hd t sp t cew t sp t hd t csp t wc t wc t bw valid output valid output valid output valid output don?t care undefined t hd t boe t cbph note 2
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 63 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 51: asynchronous write (adv# low) followed by burst read notes: 1. non-default bcr settings for asynchrono us write, with adv# low, followed by burst read: fixed or variable latenc y; latency code two (three cloc ks); wait active low; wait asserted during delay. 2. when transitioning be tween asynchronous and variable-l atency burst operations, ce# must go high. ce# can stay low when transitioning to fixed-latency burst reads. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. t clk t sp t hd t hd valid address t csp t koh t aclk valid output high-z valid address valid address a[22:0] vih vil adv# vih vil oe# vih vil we# vih vil wait dq[15:0] in/out voh vol clk vih vil vih vil voh vol ce# vih vil lb#/ub# vih vil t cw t wph t wp t wc t dh t dw data data high-z t hd t sp t sp t hd t wc t wc t bw t aw t wr t sp valid output valid output valid output undefined don?t care t boe t ohz t cew t cbph high-z note 2
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 64 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 52: burst read followed by asynchronous write (we#-controlled) notes: 1. non-default bcr settings for burst read fo llowed by asynchronous we#-controlled write: fixed or variable latenc y; latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning be tween asynchronous and variable-l atency burst operations, ce# must go high. ce# can stay low when transitioning from fixed-latency burst reads; asynchro- nous operation begins at the falling edge of adv#. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol v ih v il t sp t clk t aclk t cew t hd t aw t cw t wr valid output valid address high-z t koh t dw t ohz t sp lb#/ub# v ih v il t csp high-z t olz t hd t wp t wph t as t dh t hd t bw t sp t hz t hd t sp undefined don?t care read burst identified (we# = high) t wc t hd t khtl t boe valid address valid input high-z t cew t hz t cbph note 2
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 65 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 53: burst read followed by asynchronous write using adv# notes: 1. non-default bcr settings for burst read followed by asynchronous write using adv#: fixed or variable latenc y; latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning be tween asynchronous and variable-l atency burst operations, ce# must go high. ce# can stay low when transitioning from fixed-latency burst reads; asynchro- nous operation begins at the falling edge of adv#. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. a[22:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t cew t hd t vs t avs t avh t aw t cw valid output valid address high-z t koh t dw t ohz t sp t hd t vp lb#/ub# v ih v il t csp high-z t olz t hd t wp t wph t as t dh t hd t bw t sp t hz t sp undefined don?t care read burst identified (we# = high) t khtl valid address valid input high-z t cew t hz t cbph t aclk t boe t as t hd note 2 v ih v il
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 66 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 54: asynchronous write follow ed by asynchronous read ? adv# low notes: 1. when configured for synchronous mode (b cr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the appropriat e refresh interval. otherwise, t cph is only required after ce#-contro lled writes. valid address valid address a[22:0] v ih v il adv# v ih v il oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# v ih v il v ih v il v ih v il v ih v il t cw t wph t wp t as t wc t dh t dw data high-z valid address t aa t bhz t cph valid output high-z t oe t olz t lz t blz t ohz t hz t aw t wr t bw t whz t hz t hz don?t care undefined data note 1
pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 67 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory figure 55: asynchronous write followed by asynchronous read notes: 1. when configured for synchronous mode (b cr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the appropriat e refresh interval. otherwise, t cph is only required after ce#-contro lled writes. valid address valid address t avs t avh t vp t vs a[22:0] v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il adv# oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# t cw t wph t as t wp t wc t dh t dw data data high-z valid address t aa t bhz t cph valid output high-z t cvs t olz t lz t as t blz t ohz t hz t aw t wr t bw t whz undefined don?t care t oe note 1
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. cellularram is a tra demark of micron technology, inc., inside the u.s. and a trademark of qimonda ag outside the u.s. all other trademarks are the property of their respective owners. this data shee t contains minimum and maximum limits specified over the power supply and tem- perature range set forth herein. although considered final, these specifications ar e subject to change, as further product development and data characte rization sometimes occur. 128mb: 8 meg x 16 async/page/ burst cellularram 1.5 async/ page/burst cellularram 1.5 memory pdf: 09005aef80ec6f79/source: 09005aef80ec6f65 micron technology, inc., reserves the right to change products or specifications without notice. 128mb_burst_cr1_5_p26z__2.fm - rev. h 9/07 en 68 ?2004 micron technology, inc. all rights reserved. package information figure 56: 54-ball vfbga notes: 1. all dimensions are in millimeters. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. the mt45w8mw16bgx uses ?green? packaging. ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 96.5% sn, 3% ag, 0.5% cu ball a6 ball a1 8.00 0.10 4.00 0.05 1.875 ball a1 id 54x ? 0.37 dimensions apply to solder balls post reflow. pre-reflow ball diameter is 0.35 on a 0.30 smd ball pad. c l c l 0.75 typ 5.00 0.05 3.00 6.00 10.00 0.10 0.70 0.05 0.10 a a seating plane 3.75 0.75 typ

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