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data sheet november 1997 revision 1.0 1 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh PDC8UV7284-103T-S 64mbyte (8m x 72) cmos, pc/100 synchronous dram module general description the PDC8UV7284-103T-S is a high performance, 64-megabyte synchronous, dynamic ram module organized as 8m words by 72 bits, in a 168-pin, dual-in-line memory module (dimm) package. the module utilizes nine fujitsu mb81f64842b-103 fn cmos 8mx8 synchronous dynamic rams in surface mount package (tsop) on an epoxy laminated substrate. each device is accompanied by a decoupling capacitor for improved noise immunity. a 256 byte serial eeprom contains the module configuration information. features ? high density 64mbyte ? cycle time: 10ns (100mhz) ? low power: active 7.1w (100mhz) ? lvttl-compatible inputs and outputs ? separate power and ground planes to improve noise immunity ? single power supply of 3.3v 0.3v ? height: 1.375 inch absolute maximum ratings recommended dc operating conditions (t a = 0 to +70 c) item symbol ratings unit voltage on any pin relative to v ss v t -0.5 to +4.6 v power dissipation p t 9.0 w operating temperature t opr 0 to +70 c storage temperate t stg -55 to +125 c short circuit output current i os 50 ma symbol parameter min typ max unit v cc supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih input high voltage 2.0 - v cc +0.5 v v il input low voltage -0.5 - 0.8 v
PDC8UV7284-103T-S november 1997 revision 1.0 2 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh functional diagram notes: 1. a0~a11 to all devices 2. we*, ras*, cas* to all devices. 3. data and clks are terminated using 10 ohm series resistors. 4. 8mx16 block comprises two 8mx8 sdram devices. 5. dqms vs. data i/os dqmb0 controls dq0~dq7 dqmb1 controls dq8~dq15,c0~c7 dqmb2 controls dq16~dq23 dqmb3 controls dq24~dq31 dqmb4 controls dq32~dq39 dqmb5 controls dq40~dq47 dqmb6 controls dq48~dq55 dqmb7 controls dq56~dq63 6. clock wiring 8mx8 sdram 8mx16 block 8mx8 sdram 8mx8 sdram 8mx8 sdram 8mx8 sdram 8mx8 sdram 8mx8 sdram dqmb0 cs0* dq0~dq7 dq0~dq63,c0~c7 v cc v ss decoupling capacitors to all devices dq8~dq15 dq40~dq47 dq16~dq23 dq48~dq55 dq24~dq31 dq56~dq63 dq32~dq39 cs2* (all specifications of the device are subject to change without notice.) dqmb7 dqmb6 dqmb3 dqmb2 dqmb5 dqmb4 dqmb1 cke0 clk0 clk2 0.1 m f ba0 ba1 c0~c7 sa0-sa2 scl a0-a2 scl sda eeprom sda 100k w v cc wp sdram1 sdram2 sdram3 sdram4 10 w clk0 sdram5 clk1 sdram1 sdram2 sdram3 sdram4 10 w 3.3pf clk2 clk1, clk3 10 w 10pf
november 1997 revision 1.0 PDC8UV7284-103T-S 3 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh pin name a0~a11 addresses cs0*, cs2* chip select ba0, ba1 bank select address we* write enable dq0~dq63, c0~c7 data inputs/outputs sa0~sa2 decode input clk0~clk3 clock inputs scl serial clock ras* row address strobes sda serial data input/output cas* column address strobes wp write protect cke0 clock enables v cc power supply dqmb0-dqmb7 dq mask enables v ss ground nc no connection pin no. pin designation pin no. pin designation pin no. pin designation pin no. pin designation 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 cs2* 87 dq33 129 nc 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v cc 48 nc 90 v cc 132 nc 7 dq4 49 v cc 91 dq36 133 v cc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 c2 94 dq39 136 c6 11 dq8 53 c3 95 dq40 137 c7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v cc 101 dq45 143 v cc 18 v cc 60 dq20 102 v cc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 c0 63 nc 105 c4 147 nc 22 c1 64 v ss 106 c5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v cc 68 v ss 110 v cc 152 v ss 27 we* 69 dq24 111 cas* 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0* 72 dq27 114 nc 156 dq59 31 nc 73 v cc 115 ras* 157 v cc 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 / ap (note) 80 nc 122 ba0 (note) 164 nc 39 ba1 (note) 81 wp 123 a11 165 sa0 40 v cc 82 sda 124 v cc 166 sa1 41 v cc 83 scl 125 clk1 167 sa2 42 clk0 84 v cc 126 nc 168 v cc note : 1. address a10 / ap : initiates auto precharge 2. address ba0,ba1 : bank select within the sdram devices
PDC8UV7284-103T-S november 1997 revision 1.0 4 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh serial pd information function supported hex value byte# function described 100 mhz 100 mhz 0 # bytes written into serial memory at module mfr 128 bytes 80h 1 total # bytes of spd memory device 256 bytes 08h 2 fundamental memory type sdram 04h 3 # row address on this assembly 12 0ch 4 # column addresses on this assembly 9 09h 5 # module banks on this assembly 1 01h 6 data width of this assembly x72 48h 7 data width of this assembly (continued) 00h 8 voltage interface standard of this assembly lvttl 01h 9 sdram cycle time at cl=3 (tclk) 10ns a0h 10 sdram access from clock at cl=3 (tac) 6ns 60h 11 dimm configuration type ecc 02h 12 refresh rate/type s/r, normal 15.6 ms 80h 13 sdram width primary dram x8 08h 14 ecc sdram data width x8 08h 15 min. clock delay, back to back random column addresses (iccd) 1clk 01h 16 burst length supported 1, 2, 4, 8 & full page 8fh 17 # banks on each sdram device 4 04h 18 cas# latency 2, 3 06h 19 cs# latency 0 01h 20 write latency 0 01h 21 sdram module attribute non-buffered/registered,non-pll 00h 22 sdram device attribute vcc +/-10%, b/r, s/w, p/a, a/p 0eh 23 min clock cycle time at cl=2 (tclk) 15ns f0h 24 max. data access time from clock at cl=2 (tac) 8.0ns 80h 25 min clock cycle time at cl=1 (tclk) n/a ffh 26 max. data access time from clock at cl=1 (tac) n/a ffh 27 min. row precharge time (trp) 20ns 14h 28 min. row active delay (trrd) 20ns 14h 29 min. ras to cas delay (trcd) 20ns 14h 30 min. ras pulse width (tras) 50ns 32h 31 module bank density 64mb 10h 32 add. & cmd input setup time (tsi) 2ns 20h 33 add. & cmd input hold time (thi) 1ns 10h 34 data input setup time (tsi) 2ns 20h 35 data input hold time (thi) 1ns 10h 36-61 superset information ff h 62 spd revision rev. 2 02h 63 checksum for bytes 0-62 jedec calculation jedec calculation
november 1997 revision 1.0 PDC8UV7284-103T-S 5 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh serial pd information (continued) function supported hex value byte# function described 100 mhz 100 mhz 64 manufacturers jedec id code per jep-106e continuation code 7fh 65 manufacturers jedec id code per jep-106e smart?s id 94h 66-71 manufacturers jedec id code per jep-106e none ffh 72 manufacturing location mfr specific data 73 manufacturer?s part number p 50h 74 manufacturer?s part number d 44h 75 manufacturer?s part number c 43h 76 manufacturer?s part number 8 38h 77 manufacturer?s part number u 55h 78 manufacturer?s part number v 56h 79 manufacturer?s part number 7 37h 80 manufacturer?s part number 2 32h 81 manufacturer?s part number 8 38h 82 manufacturer?s part number 4 34h 83 manufacturer?s part number 1 31h 84 manufacturer?s part number 0 30h 85 manufacturer?s part number 3 33h 86 manufacturer?s part number t 54h 87 manufacturer?s part number s 53h 88 manufacturer?s part number none ffh 89 manufacturer?s part number none ffh 90 manufacturer?s part number none ffh 91 revision code mfr specific data mfr specific data 92 revision code none ffh 93 manufacturing date date date 94 manufacturing date date date 95-98 assembly serial number serial number s.no. 99 manufacturer specific data s 53h 100 manufacturer specific data m 4dh 101 manufacturer specific data a 41h 102 manufacturer specific data r 52h 103 manufacturer specific data t 54h 104 manufacturer specific data m 4dh 105 manufacturer specific data o 6fh 106 manufacturer specific data d 64h 107 manufacturer specific data u 75h 108 manufacturer specific data l 6ch 109 manufacturer specific data a 61h 110 manufacturer specific data r 72h 111 manufacturer specific data t 54h 112 manufacturer specific data e 65h 113 manufacturer specific data c 63h 114 manufacturer specific data h 68h 115 manufacturer specific data n 6eh 116 manufacturer specific data o 6fh 117 manufacturer specific data l 6ch 118 manufacturer specific data o 6fh 119 manufacturer specific data g 67h 120 manufacturer specific data i 69h 121 manufacturer specific data e 65h 122 manufacturer specific data s 73h 123 manufacturer specific data none ffh 124 manufacturer specific data none ffh 125 manufacturer specific data none ffh 126 manufacturer specific data none ffh 127 manufacturer specific data none ffh 128-255 open for cpq use for read & write none ffh
PDC8UV7284-103T-S november 1997 revision 1.0 6 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh dc characteristics (at recommended operating conditions unless otherwise noted) notes 1,2 parameter symbol conditions value unit min. max. output high voltage v oh(dc) i oh = -2ma 2.4 - v output low voltage v ol(dc) i ol = 2ma - 0.4 v input leakage current (any input) i li 0v v in v cc ; all other pins not under test = 0v -40 40 m a output leakage current i lo 0v v in v cc d out = disable -5 5 m a operating current (average power supply current) i cc1s burst: length=4, t rc = min for bl=4, t ck = min. one bank- active, outputs open, addresses changed up to 3-times during t rc (min), 0v v in v cc - 1080 ma i cc1d burst: length=4 (each bank), t rc = min for bl=4 (each bank), t ck = min. 2 banks active, output open, addresses changed up to 3-times during t rc (min), 0v v in v cc - 1980 ma precharge standby current (power supply current) i cc2p cke=v il, all banks idle, t ck =min, power down mode, 0v v in v cc - 27 ma i cc2ps cke=v il, all banks idle, clk=h or l, power down mode, 0v v in v cc - 18 precharge standby current (power supply current) i cc2n cke=v ih, all banks idle, t ck =min, nop commands only, input signals (except to cmd) are changed one time during 3 clock cycles, 0v v in v cc - 180 ma precharge standby current (power supply current) i cc2ns cke=v ih, all banks idle, clk=h or l, input signals are stable, 0v v in v cc - 45
november 1997 revision 1.0 PDC8UV7284-103T-S 7 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh (continued) ?cl = cas* latency notes: 1. i cc depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; the specified values are obtained with the output open and no termination register. 2. an initial pause (desl or nop) of 200 m s is required after power-up followed by a minimum of eight auto-refresh cycles. parameter symbol test condition value unit min. max. active standby current (power supply current) i cc3p cke=v il, any bank active, t ck =min, 0v v in v cc - 45 ma i cc3ps cke=v il, any bank active, clk = h or l, 0v v in v cc - 36 ma active standby current (power supply current) i cc3n cke=v ih, any bank active, t ck =min, nop commands only, input signals (except to cmd) are changed one time during 3 clock cycles, 0v v in v cc - 270 ma active standby current (power supply current) i cc3ns cke=v ih, any bank active, clk = h or l, 0v v in v cc - 90 ma burst mode current (average power supply current) i cc4 t ck =min, burst length=4, outputs open, multiple-banks active, gapless data, 0v v in v cc - 1260 ma refresh current #1 (average power supply current) i cc5 auto-refresh; t ck =min, t rc =min, 0v v in v cc - 1800 ma refresh current #2 (average power supply current) i cc6 self-refresh; t ck =min, cke 0.2v, 0v v in v cc - 18 ma
PDC8UV7284-103T-S november 1997 revision 1.0 8 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh capacitance (ta =+25 c, vcc = 3.3v 0.3v) notes: 1. capacitance is measured with boonton meter or effective capacitance method. 2. cas* - v ih to disable d out . ac characteristics: mb81f64842b-103 (at recommended operating conditions unless otherwise noted) notes 2,3,4 parameter symbol max. unit note input capacitance (address, we*, cke, ras*, cas*) c i1 50 pf 1 input capacitance (dqmbs) c i2 10 pf 1 input capacitance (cs0*) c i3 30 pf 1 input capacitance (clk0, cs2*) c i4 25 pf 1 input capacitance (clk2) c i5 21 pf 1 input capacitance (clk1, clk3) c i6 15 pf 1 input/output capacitance (dq0~dq63) c i/o 12 pf 1, 2 parameter symbol unit -103 notes min. max. clock period cas latency=2 t ck2 ns 15 - cas latency=3 t ck3 10 - clock high time t ch ns 3 - clock low time t cl ns 3 - input setup time t si ns 2 - input hold time t hi ns 1 - access time from clock (t ck =min) cas latency=2 t ac2 ns - 8 5,6 cas latency=3 t ac3 - 6 output in low-z t lz ns 0 - output in high-z cas latency=2 t hz2 ns 3 8 7 cas latency=3 t hz3 3 6 output hold time cas latency=2 t oh ns 3 - cas latency=3 3 - time between auto-refresh command interval t refi m s - 15.6 transition time t t ns 0.5 2 cke set up time for power down exit t cksp ns 3 -
november 1997 revision 1.0 PDC8UV7284-103T-S 9 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh base values for clock count/latency: mb81f64842b-103 clock count formula (note 10) latency-fixed values: mb81f64842b-103 (the latency values on these parameters are fixed regardless of clock period) notes: 1. i cc depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; the specified values are obtained with the output open and no termination register. 2. an initial pause (desl or nop) of 200 m s is required after power-up followed by a minimum of eight auto-refresh cycles. 3. ac characteristics assume t t = 1 ns and 50 pf of capacitive load. 4. 1.4 v is the reference level for measuring timing of input signals. transition times are measured between v ih (min) and v il (max). 5. assumes t rcd is satisfied. 6. t ac also specifies the access time at burst mode. 7. specified where output buffer is no longer driven. 8. actual clock count of t rc ( i rc) will be sum of clock count of t ras ( i ras ) and t rp ( i rp ). 9. operation within the( t rcd ) (min) ensures that access time is determined by ( t rcd ) (min) + ( t ac ) (max); if t rcd is greater than the specified t rcd (min), access time is determined by t ac . 10. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock co unts are calculated by a simple formula: clock count equals base value divided by clock period (round off a whole number). parameter symbol unit -103 notes min. max. ras cycle time t rc ns 70 - 8 ras precharge time t rp ns 20 - ras active time t ras ns 50 100000 ras to cas delay time t rcd ns 20 - 9 write recovery time t wr ns 10 - data-in to precharge lead time t dpl ns 10 - data-in to active/refresh command period cas latency=2 t dal2 ns 1cyc+t rp - cas latency=3 t dal3 2cyc+t rp - mode register set cycle time t rsc ns 20 - ras to ras bank active delay time t rrd ns 20 - parameter symbol unit -103 notes cke to clock disable i cke cycle 1 dqm to output in high-z i dqz cycle 2 dqm to input data delay i dqd cycle 0 last output to write command delay i owd cycle 2 write command to input data delay i dwd cycle 0 precharge to output in high-z delay cl = 2 i roh2 cycle 2 cl = 3 i roh3 3 burst stop command to output in high-z delay cl = 2 i bsh2 cycle 2 cl = 3 i bsh3 3 cas to cas delay (min) i ccd cycle 1 cas bank delay (min) i cbd cycle 1 > base value clock period clock (round off a whole number)
PDC8UV7284-103T-S november 1997 revision 1.0 10 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh output c l = 50pf r 1 = 50 w fig. 4 - example of ac test load circuit 1.4v lvttl note: ac characteristics are measured in this condition. this load circuits are not applicable for v oh and v ol .
november 1997 revision 1.0 PDC8UV7284-103T-S 11 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh physical dimensions 168-pin (84x2) dimm notes: 1. all dimensions are in inches. 2. pin 85 is behind pin 1 on the back side. 5.250 5.171 5.014 1 . 3 7 5 0 . 7 0 0 0 . 1 1 8 0.158 ? 0.118 2.507 4.550 (ref.) 5.014 1.700 1.450 2.150 0.450 0.250 0.250 0.350 0.102 max 0.050 +0.004/-0.003 front view 0.123 0.079 detail ?a? ?a? ?a?
PDC8UV7284-103T-S november 1997 revision 1.0 12 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh (1) memory type s : sdram (pc/66) g : sgram p : sdram-fast (pc/100) (2) module shape s : simm d : dimm o : small outline dimm (3) module pin count a : 72-pin b : 144-pin c : 168-pin d : 200-pin (4) word depth 1 : 1m 2 : 2m 4 : 4m 8 : 8m 16 : 16m 256 : 256k 512 : 512k . (5) buffer type b : buffered u : unbuffered r : registered (6) operating voltage & power consumption v : 3.3v & lvttl & standard power l : 3.3v & lvttl & low power s : 3.3v & sstl & standard power (7) data width (ex. 64=x64, 72=x72 etc.) (8) device configuration 4 : x4 8 : x8 1 : x16 3 : x32 (9) refresh 2 : 2krf 4 : 4krf 8 : 8krf p d c 8 u v 72 8 4 - 103 t - s (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) ordering information (10) module revision / applied ?standard? *1 blank : rev. 0 a : rev. 1 b : rev. 2 (etc.) *1 when dram device or pcb is revised, the revision is changed (11) clock frequency sdram 100 : 100mhz sdram-fast (100mhz, pc/100) 102 : cl=2; t rcd =2 ; t rp =2 103 : cl=3; t rcd =2 ; t rp =2 10 : cl=3; t rcd =3 ; t rp =3 (12) package of component t : tsop (13) assembly & test site s : smart modular technologies
november 1997 revision 1.0 PDC8UV7284-103T-S 1 3 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh ? fujitsu limited 1997 mp-sdramm-ds-20633-11/97 japan north and south america europe asia fujitsu microelectronics, inc. 3545 north first street san jose, ca 95134-1804, usa. tel : +1-408-922-9000 fax : +1-408-922-9179 customer response center (mon-fri: 7am-5pm (pst)) tel : +1-800-866-8608 fax : +1-408-922-9179 internet: http://www.fujitsumicro.com/ fujitsu microelectronics asia pte limited #05-08, 151 lorong chuan newtechpark singapore 556741 tel : +65-281-0770 fax : +65-281-0220 internet: http://www.fsl.com.sg/ fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich?buchschlag germany tel : +49-6103-690-0 fax : +49-6103-690-122 internet: http://www.fujitsu-ede.com/ fujitsu limited memory marketing dept. 4-1-1, kamikodanaka nakahara-ku, kawasaki 211-88, japan tel : +81-44-754-3767 fax : +81-44-754-3343 internet: http://www.fujitsu.co.jp/ for further information please contact: fujitsu limited all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor appli- cations. complete information sufficient for construc- tion purposes is not necessarily given. the information given in this document have been carefully checked and is believed to be reliable. how- ever, fujitsu assumes no responsibility for inaccura- cies. the information contained in this document does not convey any licence under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifi- cations without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equip- ments, undersea repeaters, nuclear control systems or medical equipments for life support.

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