www.siliconstandard.com 1 of 6 SS8014G 15 0 ma lo w - noise ldo regulator f eat ures l ow o utput n oise of 170v (rms) ultra - l ow n o - l oad s upply c urrent of 52a l ow d ropout of 100mv at 50ma load guarantee d 150ma o utput c urrent ove r -t emperature and s hor t - c ircuit p rotection output voltage adjustable from 2.5v to 5.5 v max. supply current in shutdown mode < 1a a ppli cations o rder ing inf or mation notebook computers cellular phones pdas and other hand-helds digital still cameras an d video recorders bar-code scanners d escr i p tion the SS8014G is a low supply-current, low-dropout linear regulator that comes in a space-saving sot23-5 package. the supply current at no - load is 52a. in the shu t down mode, the maximum supply current is less than 1a. operating voltage range of the SS8014G is from 2.5v to 5.5v. the over - current protection limit is set at 370ma typical and 150ma minimum. an over-temperature pro- tection circuit is built-in to the SS8014G to prevent thermal overload. these power saving features make the SS8014G ideal for use in such ba t tery - powered applications as notebook co m puters, ce l lular phones, and pda?s. SS8014Gtr pin configuration typical circuit out 5 4 1 in 2 3 gnd shdn out adj sot23-5 SS8014G 5 4 1 in 2 3 gnd shdn 1/12/2005 rev.2.11 in out shdn adj gnd + - battery c in 1 f r1 r2 c out 1 f output voltage in out shdn adj gnd + - battery c in 1 f r1 r2 c out 1 f output voltage adjustable mode 470 pf v out =1.250 x ( r 2 /r 1 +1) in out shdn adj gnd SS8014G ss8014 in pb-free sot-23-5 shipped on tape and reel this device is only available with pb-free lead finish (second-level interconnect).
www.siliconstandard.com 2 of 6 absolute maximum ratings vin to gnd.............................................................. -0.3v to +7v output short - circuit dur a tion??????? . ?.infinite set to gnd . ???????????..? . . - 0.3v to +7v shdn to gnd???????..???? . - 0.3v to +7 v shdn to in? . ???????..????. . - 7v to +0.3v out to gnd? ????????? - 0.3v to (v in + 0.3v) continuous power dissipation (t a = +25c) sot23 - 5?????.?????????...?..568 mw operating temperature r ange???.... - 40c to +85c junction temper a ture?????????.??+150c q ja ?.?..??????.??.???.?..?..220c/watt storage temperature ra nge????. . - 65c to +160c lead temperature (soldering, 10sec)..????.+300c stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ra t ings only, and functional operation of the d e vice at these or any other conditions beyond those indicated in the operational sections of the spec i fications is not implied. exposure to absolute maximum rating conditions for e x tended periods may affect device reliability. electrical characteristics (v in = v out +1v ; shdn v = v in ; c in = c out = 1 f = t a = t j = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units input voltage (note 2) v in note2 5.5 v output v oltage accuracy v out variation from spec i fied v out , i out =1ma - 3 3 % adjustable output voltage range (note 3) v out 2.5 5.5 v maximum output current 1 5 0 ma current limit i lim v out = 0v 250 370 ma quiescent current i q i load = 0ma 52 80 a i out = 1ma 2 i out = 50m a 100 dropout voltage (note 3) v drop i out =150ma 340 410 m v line regulation d v l n r v in =v o +0.1v to 5.5v, i out = 1ma 0 .1 0.4 %/v load regulation d v ldr i out = 0ma to 150 m a 8 30 mv output voltage temperature coefficient d v o / d t i out = 40ma, t j = 25c to 125c 40 ppm/c c adj = 470pf 192 output voltage noise (10hz to 100khz) e n i l = 150ma c adj = 10nf 170 v rms shutdown v i h regulator enabled 2 shdn input threshold v il regulator shutdown 0.4 v shdn input bias current i shdn v shdn = v in t a = +25c 0.007 0.1 a shutdown supply current i qshdn v out = 0v t a = +25c 0.06 1 a adj input adj input leakage current i adj v adj = 1.3v t a = +25c 5 3 0 na thermal protection thermal shutdown temper a t ure t shdn 150 c thermal shutdown hysteresis d t shdn 15 c note 1: limits are 100% production tested at t a = +25c. low duty pulse techniques are used during tests to maintain junction temperatures as close to ambient as possible. note 2: v in (min) = v out +v drop . note 3: the dropout voltage is defined as (v in - v out ) when v out is 100m v below the value of v out for v in = v out +2v. 1/12/2005 rev.2.11 SS8014G
www.siliconstandard.com 3 of 6 1/12/2005 rev.2.11 SS8014G pin description pin name function 1 in r egulator input. supply voltage can range from +2.5v to +5.5v. bypass with 1f to g nd 2 gnd ground. this pin also functions as a heatsink. solder to large pads or the circuit board ground plane to max i- mize thermal dissipation. 3 shdn active - low shutdown input. a logic low reduces the supply current to less than 1 m a. connect to in for normal operation. 4 adj adjust (input): adjustable regulator feedback input. it can connect to an external resistor divider for a d jus t- able output voltage. a ceramic capacitor of at least 470pf must be connected from adj pin to gnd to reduce output noise. 5 out regulator output. fixed or adjustable from +2.5v to +5.5v. sources up to 150ma. bypass with a capacitor of 1f, < 0.2w typical esr to gnd. applications information the block diagram of the ss8014 is shown in figure 1. it consists of an error amplifier,1.25v bandgap reference, pmos output transistor, shutdown logic, over-current protection circuit, and over-temperature protection cir- cuit. the ss8014 can be adjusted to a specific output voltage by using two external resistors (figure 2). the res i s- tors set the output voltage based on the following equation: r2 v out =1.250v x r1 + 1 note that the bandgap voltage is relative to the output, as seen in the block diagram. because traditional regulators normally have the reference voltage relative to ground, they have a different v out equation. resistor values are not critical because adj (adjust) has a high input impedance, but for best results use resistors of 470k w or less. a capacitor from a dj to ground pr o- vides greatly improved noise performance. figure 1. fun c tional diagram shdn in out shutdown logic 1.25 v ref error amp. + gnd over temp. & over current protection adj shdn in out shutdown logic 1.25 v ref error amp. + gnd over temp. & over current protection adj
www.siliconstandard.com 4 of 6 1/12/2005 rev.2.11 SS8014G figure 2. adjustable output using external feedback resistors over current protection the ss8014 use a current mirror to monitor the output current. a small portion of the pmos output transi s- tor?s current is mirrored onto a resistor such that the voltage across this resistor is proportional to the ou t put current. this voltage is compared against the re f erence voltage. once the output current exceeds the limit , the pmos output transistor enters constant cu r rent mode. the cu r rent is set to 370ma typically. over temperature protection to prevent excess ive temperature s from occurring, the ss8014 has a built - in temperature monitoring circuit. when it detects the tempe rature is above 150 o c, the output transistor is turned off. when the te m perat ure d rops to below 135 o c, the output is turned on again. in this way, the ss8014 is protected against excessi ve junction temperature s during operation. shutdown mode when the shdn pin is connected to a logic - low voltage, the ss8014 enters shutdown mode. all the analog c i r- cuits are turned off completely, which reduces the cu r- rent consumption to only the leakage current. the output is disconnected from the input. when the ou t put has no load at all, the output voltage will be di s charged to ground through the internal r e sistor voltage divider. operating region and power dissipation since the ss8014 is a linear regulator, its power dissi p a- tion is always given by p = i out (v i n ? v out ). the max i mum power dissipation is given by: p d(max) = ( t j ? t a )/ q ja ,=150 o c - 25 o c/220 o c/w= 568mw where (t j ? t a ) is the temperature difference the ss8014 die and the ambient air, q ja , is the thermal re sistance of the chosen package to the ambient air. in the case of a sot23 - 5 package, the thermal resistance is typ i- cally 220 o c/watt. the die attachment area of the ss8014?s lead frame is connected to pin 2, which is the gnd pin. therefore, the gnd pin of ss8014 can carry away the heat of the ss8014 die very effectively. to improve the power d i ss i- pation, connect the gnd pin to ground u sing a large ground plane near the gnd pin. capacitor selection and regulator stability normally, use a 1f capacitor on the input and a 1f capacitor on the output of the ss8014. larger input c a- pacitor values and lower esr provide b etter su p- ply - noise rejection and transient response. a higher - value input capacitor (10f) may be necessary if large, fast transients are anticipated and the device is l o cated several inches from the power source. power - supply rejection and operation from sources other than batteries the ss8014 is designed to deliver low dropout voltages and low quiescent currents in battery powered sy s- tems. power - supply rejection is 42db at low freque n- cies. when operating from sources other than batteries, i m- prove supply - no ise rejection and transient response by increasing the values of the input and output c a pacitors, and using passive filtering techniques. load transient considerations the ss8014 load - transient response graphs show two components of the output response: a dc shift of the output voltage due to the different load currents, and the transient response. typical overshoot for step changes in the load current from 0ma to 100ma is 12mv. i n creasing the output capacitor's value and d e- creasing its esr attenuates transie nt spikes. input - output (dropout) voltage a regulator ' s minimum input - output voltage differential (or dropout voltage) determines the lowest usable su p- ply voltage. in battery - powered systems, this will d e- termine the useful end - of - life battery voltage. b e ca use the ss8014 use a p - channel mosfet pass tr a n sistor, the dropout voltage is a function of r ds(on) multiplied by the load cu r rent. in out shdn adj gnd + - battery c in 1 f r1 r2 c out 1 f output voltage 470 pf r l in out shdn adj gnd ss8014 + - battery c in 1 f r1 r2 c out 1 f output voltage 470 pf r l
www.siliconstandard.com 5 of 6 1/12/2005 rev.2.11 SS8014G layout guide an input capacitance of ~ 1f is required between the ss8014 input pin and ground (the amount of the capac i- tanc e may be increased without limit), this capacitor must be located a distance of not more than 1cm from the input and return to a clean analog ground. this input capacitor filters out the input voltage spike caused by the surge current due to the inductive e f fect of the package pin and the printed circuit board?s rout- ing wire. otherwise, the actual voltage at the in pin may exceed the a bsolute maximum rating. the output capacitor also must be located a distance of not more than 1cm from output to a clean analog ground. this capacitor filters out the output spike caused by the surge current due to the inductive effect of the package pin and the printed circuit board?s rout- ing wire. figure 3 is the suggested pcb layout of ss8014. figure 3. suggested pcb layout *distance between pin & capacitor must be no more than 1cm
www.siliconstandard.com 6 of 6 SS8014G physical dimensions note: 1. package body sizes exclude mold flash protrusions or gate burrs 2. tolerance 0.1000 mm (4mil) unless otherwise specified 3. coplanarity: 0.1000mm 4. dimension l is measured in gage plane dimensions in millimeters symbols min nom max a 1.00 1.10 1.30 a1 0.00 ----- 0.10 a2 0.70 0.80 0.90 b 0.35 0.40 0.50 c 0.10 0.15 0.25 d 2.70 2.90 3.10 e 1.40 1.60 1.80 e ----- 1.90(typ) ----- e1 ----- 0.95 ----- h 2.60 2.80 3.00 l 0.37 ------ ----- ?1 1o 5o 9o taping specification e e d h q1 l c b a2 a1 a e1 e e d h q1 l c b a2 a1 a e1 feed direction sot23-5 package orientation feed direction sot23-5 package orientation in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. 1/12/2005 rev.2.11
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