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l tc4253a-adj 1 4253a-adjf the ltc ? 4253a-adj negative voltage hot swap tm con- troller allows a board to be safely inserted and removed from a live backplane. output current is controlled by three stages of current-limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault condi- tions. the ltc4253a-adj latches off after a circuit fault. undervoltage and overvoltage detectors with adjustable thresholds and hystereses disconnect the load whenever the input supply exceeds the desired operating range. the ltc4253a-adj?s supply input is shunt-regulated, allowing safe operation with very high supply voltages. a multifunc- tion t imer d elays initial start-u p a n d con trols the cir cuit breaker?s response time. the circuit breaker?s response time can be accelerated by sensing excessive mosfet drain voltage. an adjustable soft-start circuit controls mosfet inrush current at start-up. three power good outputs can be sequenced to enable external power modules at start-up or disable them if the circuit breaker trips. the ltc4253a-adj is available in 20-pin ssop and 20-pin (4mm 4mm) qfn packages. ? 48v distributed power systems negative power supply control central office switching high availability servers disk arrays allows safe board insertion and removal from a live ? 48v backplane floating topology permits very high voltage operation adjustable analog current limit with breaker timer fast response time limits peak fault current adjustable undervoltage/overvoltage protection with 1% threshold accuracy three sequenced power good outputs adjustable soft-start current limit adjustable timer with drain voltage accelerated response latchoff after fault available in 20-pin ssop and 20-pin (4mm 4mm) qfn packages ? 48v hot swap contr oller with sequencer ? 48v/2.5a hot swap controller f e a t ures d esc r i p t i o u appli c a tio s u typi c a l a pplic a t i o u 5.6k 5.6k 5.6k ? pwrgd1 v in en2 en3 v in v ee sel ltc4253a-adj load1 pwrgd2 pwrgd3 ov ovl drain ss gate sqtimer sense timer en load2 en load3 en 2.5k 15k(1/4w)/6 uv reset uvl 4253a ta01 10? 1m 0.02? irf530s *diodes, inc. ? moc207 10nf 0.68f 0.1f 33nf 10nf + 100f 0.536k 1% b3100* 255k 1% ? 48v a ? 48v b ? 48v rtn ? 48v rtn 2.1k 1% 1.24k 1% b3100* ? ? 20k 1% 1f , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. patent pending. gate 10v ss 1v sense 50mv v out 50v 1ms/div 4253a ta01b start-up behavior for information purposes only obsolete: contact linear technology for potential replacement
ltc4253a-adj 2 4253a-adjf gn package 20-lead plastic ssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 en2 pwrgd2 pwrgd1 v in reset ss sel sense v ee v ee pwrgd3 en3 sqtimer timer uvl uv ovl ov drain gate current into v in (100 s pulse) ........................... 100ma current into drain (100 s pulse) ........................ 20ma v in , drain minimum voltage............................... C 0.3v input/output (except sense and drain) voltage ...................................C 0.3v to 16v sense voltage ..........................................C 0.6v to 16v current out of sense (20 s pulse) .................. C 200ma maximum junction temperature .......................... 125 c order part number t jmax = 125 c, ja = 95 c/w consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. ltc4253acgn-adj ltc4253aign-adj absolute axi u rati gs w ww u package/order i for atio uu w (note 1) all voltages referred to v ee operating temperature range ltc4253a-adjc ..................................... 0 c to 70 c ltc4253a-adji .................................. C 40 c to 85 c storage temperature range ssop ................................................ C 65 c to 150 c qfn .................................................. C 65 c to 125 c lead temperature (soldering, 10 sec) ssop ................................................................ 300 c order part number ltc4253acuf-adj ltc4253aiuf-adj 20 19 18 17 16 6 7 8 top view 21 uf package 20-lead (4mm 4mm) plastic qfn 9 10 5 4 3 2 1 11 12 13 14 15 v in reset ss sel sense sqtimer timer uvl uv ovl pwrgd1 pwrgd2 en2 pwrgd3 en3 nc v ee gate drain ov t jmax = 125 c, ja = 37 c/w exposed pad (pin 21) is v ee must be soldered to pcb uf part marking* 253aj electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 2) symbol parameter conditions min typ max units v z v in C v ee zener voltage i in = 2ma 11.5 13 14.5 v r z v in C v ee zener dynamic impedance i in = (2ma to 30ma) 5 ? i in v in supply current uv = uvl = ov = ovl = 4v, v in = (v z C 0.3v) 1.1 2 ma v lko v in undervoltage lockout coming out of uvlo (rising v in ) 910 v v lkh v in undervoltage lockout hysteresis 0.25 0.5 0.75 v v ih ttl input high voltage 2v v il ttl input low voltage 0.8 v v hyst ttl input buffer hysteresis 600 mv i reset reset input current v ee v reset v in 0.1 10 a i en en2, en3 input current v en = 4v (sinking) 60 120 180 a v en = 0v 0.1 10 a order options tape and reel: add #tr, lead free: add #pbf, lead free tape and reel: add #trpbf, lead free part marking: http://www.linear.co m/leadfree/
ltc4253a-adj 3 4253a-adjf i sel sel input current v sel = 0v (sourcing) 10 20 40 a v sel = v in 0.1 10 a v cb circuit breaker current limit voltage v cb = (v sense C v ee ) 45 50 55 mv v acl analog current limit voltage x% v acl = (v sense C v ee ), ss = open or 1.4v 105 120 138 % v cb circuit breaker current limit voltage v fcl fast current limit voltage v fcl = (v sense C v ee ) 150 200 300 mv v ss ss voltage after end of ss timing cycle 1.25 1.4 1.55 v i ss ss pin current uv = uvl = ov = ovl = 4v, 16 28 40 a v sense = v ee, v ss = 0v (sourcing) uv = uvl = ov = ovl = 0v, 28 ma v sense = v ee, v ss = 1v (sinking) r ss ss output impedance 50 k ? v os analog current limit offset voltage 10 mv v acl + v os ratio (v acl + v os ) to ss voltage 0.05 v/v v ss i gate gate pin output current uv = uvl = ov = ovl = 4v, v sense = v ee , 30 50 70 a v gate = 0v (sourcing) uv = uvl = ov = ovl = 4v, v sense C v ee = 0.15v, 17 ma v gate = 3v (sinking) uv = uvl = ov = ovl = 4v, v sense C v ee = 0.3v, 190 ma v gate = 1v (sinking) v gate external mosfet gate drive v gate C v ee, i in = 2ma 10 12 v z v v gatel gate low threshold (before gate ramp up) 0.5 v v gateh gate high threshold v gateh = v in C v gate , 2.8 v for pwrgd1, pwrgd2, pwrgd3 status v uvhi uv pin threshold uv low to high 3.05 3.08 3.11 v v uvlo uvl pin threshold uvl high to low 3.05 3.08 3.11 v v ovhi ov pin threshold ov low to high 5.04 5.09 5.14 v v ovlo ovl pin threshold ovl high to low 5.025 5.08 5.135 v i sense sense pin input current uv = uvl = ov = ovl = 4v, v sense = 50mv (sourcing) 15 30 a i inp uv, uvl, ov, ovl pin input current uv = uvl = ov = ovl = 4v 0.1 1 a v tmrh timer pin voltage high threshold 3.5 4 4.5 v v tmrl timer pin voltage low threshold 0.8 1 1.2 v i tmr timer pin current timer on (initial cycle/latchoff, sourcing), v tmr = 2v 357 a timer off (initial cycle, sinking), v tmr = 2v 28 ma timer on (circuit breaker, sourcing, 120 200 280 a i drn = 0 a), v tmr = 2v timer on (circuit breaker, sourcing, 600 a i drn = 50 a), v tmr = 2v timer off (circuit breaker, sinking), v tmr = 2v 357 a ? i tmracc (i tmr at i drn = 50 a C i tmr at i drn = 0 a) timer on (circuit breaker with i drn = 50 a) 789 a/ a ? i drn 50 a v sqtmrh sqtimer pin voltage high threshold 3.5 4 4.5 v v sqtmrl sqtimer pin voltage low threshold 0.33 v symbol parameter conditions min typ max units electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 2)
ltc4253a-adj 4 4253a-adjf note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ee unless otherwise specified. electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 2) symbol parameter conditions min typ max units i sqtmr sqtimer pin current sqtimer on (power good sequence, sourcing), 357 a v sqtmr = 2v sqtimer on (power good sequence, sinking), 28 ma v sqtmr = 2v v drnl drain pin voltage low threshold for pwrgd1, pwrgd2, pwrgd3 status 2 2.39 3 v i drnl drain leakage current v drain = 4v 0.1 1 a v drncl drain pin clamp voltage i drn = 50 a 5 6 7.5 v v pgl pwrgd1, pwrgd2, pwrgd3 signals i pg = 1.6ma 0.25 0.4 v output low voltage i pg = 5ma 1.2 v i pgh pwrgd1, pwrgd2, pwrgd3 v pg = 0v (sourcing) 30 50 70 a output high current t sq sq timer default ramp period sqtimer pin floating, 250 s v sqtmr ramps from 0.5v to 3.5v t ss ss default ramp period ss pin floating, v ss ramps from 0.2v to 1.25v 140 s t pllug uv low to gate low 15 s t phlog ov high to gate low 15 s typical perfor a ce characteristics uw i in vs v in v z vs temperature i in vs temperature temperature ( c) C50 C25 12.0 v z (v) 13.0 14.5 0 50 75 4253a g01 12.5 14.0 13.5 25 100 125 i in = 2ma v in (v) 0 i in (ma) 10 100 20 4253a g02 1 0.1 5 10 15 1000 t a = 125 c t a = 85 c t a = 25 c t a = C40 c temperature ( c) C50 0.5 i in (ma) 0.6 0.8 0.9 1.0 1.5 1.2 0 50 75 4253a g03 0.7 1.3 1.4 1.1 C25 25 100 125 v in = v z C 0.3v
ltc4253a-adj 5 4253a-adjf typical perfor a ce characteristics uw circuit breaker current limit voltage v cb vs temperature i en vs v en and i sel vs v sel analog current limit voltage v acl vs temperature i gate (source) vs temperature i gate (acl, sink) vs temperature fast current limit voltage v fcl vs temperature i gate (fcl, sink) vs temperature v gate vs temperature v gatel vs temperature v en /v sel (v) 0 0 i en /i sel ( a) 40 120 160 200 4 8 10 18 4253a g04 80 i en i sel 26 12 14 16 i in = 2ma t a = 25 c temperature ( c) C50 45 v cb (mv) 46 48 49 50 55 52 0 50 75 4253a g05 47 53 54 51 C25 25 100 125 i in = 2ma temperature ( c) C50 v acl (mv) 75 25 4253a g06 60 50 C25 0 50 45 40 80 70 65 55 75 100 125 i in = 2ma temperature ( c) C50 150 v fcl (mv) 160 180 190 200 250 220 0 50 75 4253a g07 170 230 240 210 C25 25 100 125 i in = 2ma temperature ( c) C50 40 i gate ( a) 42 46 48 50 60 54 0 50 75 4253a g08 44 56 58 52 C25 25 100 125 i in = 2ma uv/uvl/ov/ovl = 4v timer = 0v v sense = v ee v gate = 0v temperature ( c) C50 i gate (ma) 20 25 30 25 75 4253a g09 15 10 C25 0 50 100 125 5 0 i in = 2ma uv/uvl/ov/ovl = 4v timer = 0v v sense C v ee = 0.15v v gate = 3v temperature ( c) C50 C25 0 i gate (ma) 100 250 0 50 75 4253a g10 50 200 150 25 100 125 i in = 2ma uv/uvl/ov/ovl = 4v timer = 0v v sense C v ee = 0.3v v gate = 1v temperature ( c) C50 10.0 v gate (v) 10.5 11.5 12.0 12.5 50 14.5 4253a g11 11.0 0 C25 75 100 25 125 13.0 13.5 14.0 i in = 2ma uv/uvl/ov/ovl = 4v timer = 0v v sense = v ee temperature ( c) C50 0 v gatel (v) 0.1 0.3 0.4 0.5 1.0 0.7 0 50 75 4253a g12 0.2 0.8 0.9 0.6 C25 25 100 125 i in = 2ma uv/uvl/ov/ovl = 4v timer = 0v gate threshold before ramp up
ltc4253a-adj 6 4253a-adjf typical perfor a ce characteristics uw timer threshold vs temperature i sense vs temperature i sense vs (v sense ?v ee ) ov threshold vs temperature uv threshold vs temperature v gateh vs temperature i tmr (circuit breaker, sourcing) vs temperature i tmr (initial cycle, sourcing) vs temperature i tmr vs i drn temperature ( c) C50 v gateh (v) 3.4 25 4253a g13 2.8 2.4 C25 0 50 2.2 2.0 3.6 3.2 3.0 2.6 75 100 125 i in = 2ma uv/uvl/ov/ovl = 4v v gateh = v in C v gate temperature ( c) C50 uv threshold (v) 3.09 3.10 3.11 25 75 4253a g14 3.08 3.07 C25 0 50 100 125 3.06 3.05 i in = 2ma v uvhi and v uvlo temperature ( c) C50 0v threshold (v) 5.10 5.12 5.14 25 75 4253a g15 5.08 5.06 C25 0 50 100 125 5.04 5.02 i in = 2ma v ovhi v ovlo v sense C v ee (v) C1.5 1000 Ci sense (ma) 100 10 1 0.1 0.01 C1 C0.5 0 0.5 4253a g16 1 1.5 i in = 2ma uv/uvl/ov/ovl = 4v timer = 0v gate = high t a = 25 c temperature ( c) C50 i sense ( a) C10 C5 0 25 75 4253a g17 C15 C20 C25 0 50 100 125 C25 C30 i in = 2ma uv/uvl/ov/ovl = 4v timer = 0v v sense C v ee = 50mv v gate = high temperature ( c) C50 0 timer threshold (v) 0.5 1.5 2.0 2.5 5.0 3.5 0 50 75 4253a g18 1.0 4.0 4.5 3.0 C25 25 100 125 i in = 2ma v tmrh v tmrl temperature ( c) C50 0 i tmr ( a) 1 3 4 5 10 7 0 50 75 4253a g19 2 8 9 6 C25 25 100 125 i in = 2ma v tmr = 2v temperature ( c) C50 i tmr ( a) 230 25 4253a g20 200 180 C25 0 50 170 160 240 220 210 190 75 100 125 i in = 2ma i drn = 0 a i drn (ma) 0.001 0.1 i tmr (ma) 1 10 0.01 0.1 1 10 4253a g21 i in = 2ma t a = 25 c
ltc4253a-adj 7 4253a-adjf typical perfor a ce characteristics uw ? i tmracc / ? i drn vs temperature sqtimer threshold vs temperature v drncl vs temperature v drnl vs temperature v pgl vs temperature i drn vs v drain t ss vs temperature t sq vs temperature i pgh vs temperature temperature ( c) C50 7.0 ? i tmracc / ? i drn ( a/ a) 7.2 7.6 7.8 8.0 9.0 8.4 0 50 75 4253a g22 7.4 8.6 8.8 8.2 C25 25 100 125 i in = 2ma temperature ( c) C50 0 v sqtmr (v) 0.5 1.5 2.0 2.5 50 4.5 4253a g23 1.0 0 C25 75 100 25 125 3.0 3.5 4.0 i in = 2ma v sqtmrh v sqtmrl temperature ( c) C50 v drnl (v) 2.55 25 4253a g24 2.40 2.30 C25 0 50 2.25 2.20 2.60 2.50 2.45 2.35 75 100 125 i in = 2ma temperature ( c) C50 5.0 v drncl (v) 5.2 5.6 5.8 6.0 7.0 6.4 0 50 75 4253a g25 5.4 6.6 6.8 6.2 C25 25 100 125 i in = 2ma i drn = 50 a v drain (v) 1 i drn (ma) 0.01 0.1 1 16 4253a g26 0.001 0.0001 0.00001 0.00000001 4 8 12 2 6 10 14 0.0000001 100 10 t a = 125 c t a = 85 c t a = 25 c t a = C40 c i in = 2ma temperature ( c) C50 C25 0 v pgl (v) 1.0 2.2 0 50 75 4253a g27 0.5 2.0 1.5 25 100 125 i in = 2ma i pg = 10ma i pg = 5ma i pg = 1.6ma temperature ( c) C50 40 i pgh ( a) 42 46 48 50 60 54 0 50 75 4253a g28 44 56 58 52 C25 25 100 125 i in = 2ma v pwrgd = 0v temperature ( c) C50 100 t ss ( s) 110 130 140 150 200 170 0 50 75 4253a g29 120 180 190 160 C25 25 100 125 i in = 2ma ss pin floating v ss ramps from 0.2v to 1.25v temperature ( c) C50 200 t sq ( s) 210 230 240 250 300 270 0 50 75 4253a g30 220 280 290 260 C25 25 100 125 i in = 2ma sqtmr pin floating v sqtmr ramps from 0.5v to 3.5v
ltc4253a-adj 8 4253a-adjf en2 (pin 1/pin 18): power good status output two enable. this is a ttl compatible input that is used to control pwrgd2 and pwrgd3 outputs. when en2 is driven low, both pwrgd2 and pwrgd3 will go high. when en2 is driven high, pwrgd2 will go low provided pwrgd1 has been active for more than one power good sequence delay (t sqt ) provided by the sequencing timer. en2 can be used to control the power good sequence. this pin is internally pulled low by a 120 a current source. pwrgd2 (pin 2/pin 19): power good status output two. power good sequence starts with drain going below 2.39v and gate is within 2.8v on v in . pwrgd2 will latch active low after en2 goes high and after one power good sequence delay t sqt provided by the sequencing timer from the time pwrgd1 goes low, whichever comes later. pwrgd2 is reset by pwrgd1 going high or en2 going low. this pin is internally pulled high by a 50 a current source. pwrgd1 (pin 3/pin 20): power good status output one. at start-up, pwrgd1 latches active low one t sqt after both drain is below 2.39v and gate is within 2.8v of v in . pwrgd1 status is reset by undervoltage, v in (uvlo), reset going high or circuit breaker fault time-out. this pin is internally pulled high by a 50 a current source. v in (pin 4/pin 1): positive supply input. connect this pin to the positive side of the supply through a dropping resistor. a shunt regulator clamps v in at 13v above v ee . an internal undervoltage lockout (uvlo) circuit holds gate low until the v in pin is greater than v lko (9v), overriding undervoltage and overvoltage events. if there is no undervoltage, no overvoltage and v in comes out of uvlo, timer starts an initial timing cycle before initiating gate ramp up. if v in drops below approximately 8.5v, gate pulls low immediately. reset (pin 5/pin 2): circuit breaker reset pin. this is an asynchronous ttl compatible input. reset going high will pull gate, ss, timer, sqtimer low and the pwrgd outputs high. the reset pin has an internal glitch filter that rejects any pulse < 20 s. after the reset of a latched fault, the chip waits for the interlock conditions before recovering as described in interlock conditions in the operation section. ss (pin 6/pin 3): soft-start pin. this pin is used to ramp inrush current during start up, thereby effecting control over di/dt. a 20x attenuated version of the ss pin voltage is presented to the current limit amplifier. this attenuated voltage limits the mosfets drain current through the sense resistor during the soft-start current limiting. at the beginning of the start-up cycle, the ss capacitor (c ss ) is ramped by a 28 a current source. the gate pin is held low until ss exceeds 20 ? v os = 0.2v. ss is internally shunted by a 50k r ss which limits the ss pin voltage to 1.4v. this corresponds to an analog current limit sense voltage of 60mv. sel (pin 7/pin 4): soft-start mode select. this is an asynchronous ttl compatible input. sel has an internal pull-up of 20 a that will pull it high if it is floated. sel selects between two modes of ss ramp-up (see applica- tions information, soft-start section). sense (pin 8/pin 5): circuit breaker/current limit sense pin. load current is monitored by a sense resistor r s connected between sense and v ee , and controlled in three steps. if sense exceeds v cb (50mv), the circuit breaker comparator activates a (200 a+8?i drn ) timer pull-up current. if sense exceeds v acl (60mv), the analog current-limit amplifier pulls gate down to regulate the mosfet current at v acl /r s . in the event of a cata- strophic short-circuit, sense may overshoot v acl . if sense reaches v fcl (200mv), the fast current-limit com- parator pulls gate low with a strong pull-down. to disable the circuit breaker and current limit functions, connect sense to v ee . v ee (pins 9, 10/pin 7): negative supply voltage input. connect this pin to the negative side of the power supply. gate (pin 11/pin 8): n-channel mosfet gate drive output. this pin is pulled high by a 50 a current source. gate is pulled low by invalid conditions at v in (uvlo), undervoltage, overvoltage, during the initial timing cycle, a circuit breaker fault time-out or the reset pin going high. gate is actively servoed to control the fault current as measured at sense. compensation capacitor, c c , at gate stabilizes this loop. a comparator monitors gate to ensure that it is low before allowing an initial timing cycle, then the gate ramps up after an overvoltage event or pi fu ctio s uuu (ssop/qfn)
ltc4253a-adj 9 4253a-adjf restart after a current limit fault. during gate start-up, a second comparator detects gate within 2.8v of v in before power good sequencing starts. drain (pin 12/pin 9): drain sense input. connecting an external resistor, r d between this pin and the mosfets drain (v out ) allows voltage sensing below 5v and current feedback to timer. a comparator detects if drain is below 2.39v and together with the gate high comparator, starts the power good sequencing. if v out is above v drncl , the drain pin is clamped at approximately v drncl . r d current is internally multiplied by 8 and added to timers 200 a during a circuit breaker fault cycle. this reduces the fault time and mosfet heating. ov/ovl (pins 13, 14/pins 10, 11): overvoltage and overvoltage low inputs. the ov and ovl pins work together to implement the overvoltage function. ovl and ov must be tapped from an external resistive string across the input supply such that v ovl v ov under all circum- stances. as the input supply ramps up, the ov pin input is multiplexed to the internal overvoltage comparator input. if ov > 5.09v, gate pulls low and the overvoltage com- parator input is switched to ovl. when ovl returns below 5.08v, gate start-up begins without an initial timing cycle and the overvoltage comparator input is switched to ov. in this way, an external resistor between ovl and ov can set a low to high and high to low overvoltage threshold hysteresis that will add to the internal 10mv hysteresis. a 1nf to 10nf capacitor at ovl prevents transients and switching noise at both ovl and ov from causing glitches at the gate. uv/uvl (pins 15, 16/pins 12, 13): undervoltage and undervoltage low inputs. the uv and uvl pins work together to implement the undervoltage function. uvl and uv must be tapped from an external resistive string across the input supply such that v uvl v uv under all circum- stances. as the input supply ramps up, the uv pin input is multiplexed to the internal undervoltage comparator in- put. if uv > 3.08v, an initial timing cycle is initiated followed by gate start-up and input to the undervoltage comparator input is switched to uvl. when uvl returns below 3.08v, pwrgd1 pulls high, both gate and timer pull low and input to the undervoltage comparator input is switched to uv. in this way, an external resistor between uvl and uv can set the low to high and high to low undervoltage threshold hysteresis. a 1nf to 10nf capaci- tor at uvl prevents transients and switching noise at both uvl and uv from causing glitches at the gate pin. timer (pin 17/pin 14): timer input. timer is used to generate an initial timing delay at start-up, and to delay shutdown in the event of an output overload (circuit breaker fault). these delays are adjustable by connecting an appropriate capacitor to this pin. sqtimer (pin 18/pin 15): sequencing timer input. the sequencing timer provides a delay t sqt for the power good sequencing. this delay is adjusted by connecting an appropriate capacitor to this pin. if the sqtimer capacitor is omitted, the sqtimer pin ramps from 0v to 4v in about 300 s. en3 (pin 19/pin 16): power good status output three enable. this is a ttl compatible input that is used to control the pwrgd3 output. when en3 is driven low, pwrgd3 will go high. when en3 is driven high, pwrgd3 will go low provided pwrgd2 has been active for for more than one power good sequence delay (t sqt ). en3 can be used to control the power good sequence. this pin is internally pulled low by a 120 a current source. pwrgd3 (pin 20/pin 17): power good status output three. power good sequence starts with drain going below 2.39v and gate is within 2.8v of v in . pwrgd3 will latch active low after en3 goes high and after one power good sequence delay t sqt provided by the sequencing timer from the time pwrgd2 goes low, whichever comes later. pwrgd3 is reset by pwrgd1 going high or en3 going low. this pin is internally pulled high by a 50 a current source. pi fu ctio s uuu (ssop/qfn)
ltc4253a-adj 10 4253a-adjf block diagra w v ee 1 5v 1 8 1 v in v ee pwrgd3 50 a 5.09v ovin uvin v ee 120 a v ee 120 a v in v in v ee v in v ee 200 a ov ovl en3 v in v ee v ee 28 a 47.5k r ss 2.5k ss v in v in v ee v ee 50 a v in v in v ee pwrgd2 50 a en2 v ee pwrgd1 50 a v ee reset sel v in sqtimer delay sqtimer delay logic ovd uvd sqtimer delay + C 4v + C 1v timer + C 4v + C 0.33v + C uvl uv 3.08v + C + C 0.5v + C 2.39v + C C + v in v ee 5 a v in v ee 5 a 5 a 20 a + C 2.8v + C 200mv + C v os = 10mv v ee C + + C 50mv 4253a bd cb fcl C + acl v ee sense gate drain sqtimer
ltc4253a-adj 11 4253a-adjf operatio u hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient cur- rents from the power bus as they charge. the flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. the ltc4253a-adj is designed to turn on a circuit board supply in a controlled manner, allowing insertion or re- moval without glitches or connector damage. initial start-up the ltc4253a-adj resides on a removable circuit board and controls the path between the connector and load or power conversion circuitry with an external mosfet switch. both inrush control and short-circuit protection are pro- vided by the mosfet. a detailed schematic is shown in figure 1. C 48v and C 48rtn receive power through the longest connector pins and are the first to connect when the board is inserted. the gate pin holds the mosfet off during this time. uv/uvl/ov/ovl determines whether or not the mosfet should be turned on based upon internal high accuracy thresholds and an external divider. uv/uvl/ov/ ovl does double duty by also monitoring whether or not the connector is seated. the top of the divider detects C 48rtn by way of a short connector pin that is the last to mate during the insertion sequence. interlock conditions a start-up sequence commences once these interlock conditions are met: 1. the input voltage v in exceeds v lko (uvlo) 2. the voltage at uv > v uvhi 3. the voltage at ovl < v ovlo 4. the input voltage at reset < 0.8v 5. the (sense C v ee ) voltage < 50mv (v cb ) 6. the voltage at ss is < 0.2v (20 ? v os ) 7. the voltage on the timer capacitor (c t ) is < 1v (v tmrl ) 8. the voltage at gate is < 0.5v (v gatel ) the first four conditions are continuously monitored and the latter four are checked prior to initial timing or gate ramp-up. upon exiting an overvoltage condition, the timer pin voltage requirement is inhibited. details are described in the applications information, timing wave- forms section. figure 1. 48v/2.5a application with operating range from 43v to 82v r6 5.6k r7 5.6k r8 5.6k ? pwrgd1 v in reset v in v ee sel ltc4253a-adj power module 1 pwrgd2 pwrgd3 ov ovl drain ss gate sqtimer sense timer en power module 2 en power module 3 en r in 2.5k 15k(1/4w)/6 uv uvl r5 en3 en2 4253a f01 r c 10 ? r d 1m r s 0.02 ? v in v in en2 en3 power module 1 output power module 2 output q1 irf530s c c 10nf c t 0.68 f c1 10nf c sq 0.1 f c ss 33nf + c l 100 f c in 1 f r2 0.976k 1% 2.74k 1% C 48v rtn (short pin) C 48v rtn (long pin) C 48v (long pin) reset (long pin) r1 20k 1% r3 2.1k 1% r4 2.37k 1% 294k 1% ? moc207 ? ? ? ?
ltc4253a-adj 12 4253a-adjf operatio u if reset < 0.8v occurs after the ltc4253a-adj comes out of uvlo (interlock condition 1) and undervoltage (interlock condition 2), gate and ss are released without an initial timer cycle once the other interlock conditions are met (see figure 13a). if not, timer begins the start-up sequence by sourcing 5 a into c t . if v in , uvl/uv or ovl/ ov falls out of range or reset asserts, the start-up cycle stops and timer discharges c t to less than 1v, then waits until the aforementioned conditions are once again met. if c t successfully charges to 4v, timer pulls low and both ss and gate pins are released. gate sources 50 a (i gate ), charging the mosfet gate and associated capaci- tance. the ss voltage ramp limits v sense to control the inrush current. the sel pin selects between two different modes of ss ramp-up (refer to applications information, soft-start section). sqtimer starts its ramp-up when gate is within 2.8v of v in and drain is lower than v drnl . this sets off the power good sequence in which pwrgd1, pwrgd2 and then pwrgd3 is subsequently pulled low after a delay, adjustable through the sqtimer capacitor c sq or by external control inputs en2 and en3. in this way, external loads or power modules controlled by the three pwrgd signals are turned on in a controlled manner without overloading the power bus. two modes of operation are possible during the time the mosfet is first turned on, depending on the values of external components, mosfet characteristics and nomi- nal design current. one possibility is that the mosfet will turn on gradually so that the inrush into the load capacitance remains a low value. the output will simply ramp to C 48v and the ltc4253a-adj will fully enhance the mosfet. a second possibility is that the load current exceeds the soft- start current limit threshold of [v ss (t)/20 C v os ]/r s . in this case the ltc4253a-adj will ramp the output by sourcing soft-start limited current into the load capacitance. if the soft-start voltage is below 1.2v, the circuit breaker timer is held low. above 1.2v, timer ramps up. it is important to set the timer delay so that, regardless of which start-up mode is used, the timer ramp is less than one circuit breaker delay time. if this condition is not met, the ltc4253a-adj may shut down after one circuit breaker delay time. board removal when the board is withdrawn from the card cage, the uvl/ uv/ovl/ov divider is the first to lose connection. this shuts off the mosfet and commutates the flow of current in the connector. when the power pins subsequently separate there is no arcing. current control three levels of protection handle short-circuit and over- load conditions. load current is monitored by sense and resistor r s . there are three distinct thresholds at sense: 50mv for a timed circuit breaker function; 60mv for an analog current limit loop; and 200mv for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. if, due to an output overload, the voltage drop across r s exceeds 50mv, timer sources 200 a into c t . c t eventu- ally charges to a 4v threshold and the ltc4253a-adj shuts off. if the overload goes away before c t reaches 4v and sense measures less than 50mv, c t slowly dis- charges (5 a). in this way the ltc4253a-adjs circuit breaker function responds to low duty cycle overloads, and accounts for the fast heating and slow cooling char- acteristic of the mosfet. higher overloads are handled by an analog current limit loop. if the drop across r s reaches v acl , the current limiting loop servos the mosfet gate and maintains a constant output current of v acl /r s . in current limit mode, v out (mosfet drain-source voltage drop) typically rises and this increases mosfet heating. if v out > v drncl , connecting an external resistor, r d between v out and drain allows the fault timing cycle to be shortened by accelerating the charging of the timer capacitor. the timer pull-up current is increased by 8 ? i drn . note that because sense > 50mv, timer charges c t during this time, and the ltc4253a-adj will eventually shut down. l ow impedance failures on the load side of the ltc4253a- adj coupled with 48v or more driving potential can produce current slew rates well in excess of 50a/ s. under these conditions, overshoot is inevitable. a fast sense
ltc4253a-adj 13 4253a-adjf operatio u comparator with a threshold of 200mv detects overshoot and pulls gate low much harder and hence much faster than the weaker current limit loop. the v acl /r s current limit loop then takes over, and servos the current as previously described. as before, timer runs and shuts down ltc4253a-adj when c t reaches 4v. if c t reaches 4v, the ltc4253a-adj latches off with a 5 a pull-up current source. the ltc4253a-adj circuit breaker latch is reset by either pulling the reset pin active high for >20 s, pulling uvl/uv momentarily low, dropping the input voltage v in below the internal uvlo threshold or pulsing timer momentarily low with a switch. although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary de- tection of an overcurrent condition. the action of timer and c t rejects these events allowing the ltc4253a-adj to ride out temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse.
ltc4253a-adj 14 4253a-adjf enabled; below (v lko C v lkh ) it is disabled and gate is pulled low. the uvlo function at v in should not be confused with the uvl/uv and ovl/ov pins. these are completely separate functions. undervoltage and overvoltage comparators the undervoltage comparator has inputs multiplexed from uvl and uv. when comparator output uvd is high, uv is multiplexed to the comparator input uvin. when uvd is low, uvl is multiplexed to uvin. by tapping uvl and uv off a resistive string across the supply such as in the typi- cal application, the undervoltage function is implemented as shown in figure 2a. during uvlo, uvd is forced high so uv is multiplexed to uvin. at time point 1, v in ramps past v lko and the undervoltage comparator is enabled. uvin = uv is less than v uvhi (3.08v), so uvd is high and the part is in undervoltage shutdown. at time point 2, uv ramps past v uvhi (3.08v) and uvd goes low, bringing the part out of undervoltage and switching uvl to uvin. uvl is tied to uvin until time point 3 when uvl ramps past v uvlo (3.08v) and uvd goes high, bringing the part into undervoltage shutdown and switching uv to uvin. shunt regulator a fast responding regulator shunts the ltc4253a-adj v in pin. power is derived from C48rtn by an external current limiting resistor. the shunt regulator clamps v in to 13v (v z ). a 1 f decoupling capacitor at v in filters supply transients and contributes a short delay at start-up. r in should be chosen to accommodate both v in supply cur- rent and the drive required for three optocouplers used by the pwrgd signals. higher current through r in results in higher dissipation for r in and ltc4253a-adj as well as higher v in noise. alternative circuits are v in with an npn buffer as in figure 16, v in driving base resistors of npn cascodes as in figure 17 or v in driving the gates of mosfet cascodes replacing the npns in figure 17. an alternative is a separate npn buffer driving the optocoupler as shown in figure 16. multiple 1/4w resistors can replace a single higher power r in resistor. internal undervoltage lockout (uvlo) a hysteretic comparator, uvlo, monitors v in for undervoltage. the thresholds are defined by v lko and its hysteresis v lkh . when v in rises above v lko the chip is applicatio s i for atio wu u u (refer to block diagram) figure 2. undervoltage/overvoltage recovery and shutdown (all waveforms are referenced to v ee ) (2a) undervoltage (2b) overvoltage v uvhi 3.08v v uvlo 3.08v v ovlo 5.08v 4253a f02 v ovhi 5.09v v lko 12 34 12 34 v lko v in (C48v rtn) short pin uvl uv uvd uvin uvlo undervoltage shutdown undervoltage shutdown normal operation uvlo normal operation normal operation overvoltage shutdown v in (C48v rtn) short pin ovl ov ovd ovin uvl 0vl uv ov 36v (undervoltage shutdown voltage) 69v (overvoltage recovery voltage) 38v (undervoltage recovery voltage) 71v (overvoltage shutdown voltage)
ltc4253a-adj 15 4253a-adjf applicatio s i for atio wu u u figure 2b shows the implementation of the overvoltage function of the typical application. during uvlo, ovd is forced high so ovl is multiplexed to ovin. at time point 1, the part exits uvlo and the overvoltage comparator is enabled. ovin = ovl is less than v ovlo (5.08v) so ovd goes low, switching ov to ovin and bringing the part to normal mode. at time point 2, ov ramps past v ovhi (5.09v) and ovd goes high, switching ovl to ovin as well as turning on the internal 10mv hysteresis as the part goes into overvoltage. ovl is tied to ovin until time point 3 when ovl ramps past v ovlo (5.09v C 10mv = 5.08v) and ovd goes low, bringing the part into normal mode and switching ov to ovin. the undervoltage (uv) comparator has no internal hyster- esis to preserve the accuracy of the hysteresis set across uvl/uv while the overvoltage (ov) comparator has an internal low to high hysteresis of 10mv. this will add to the hysteresis set across ovl/ov and provide some noise immunity if ovl/ov is shorted together. any implementa- tion must ensure that v uvl v uv and v ovl v ov under all conditions. the various thresholds to note are: uv low-to-high (v uvhi ) = 3.08v uvl high-to-low (v uvlo ) = 3.08v ov low-to-high (v ovhi ) = 5.09v ovl high-to-low (v ovlo ) = 5.08v using these thresholds and an external resistive divider, any required supply operating range can be implemented. an example is shown in figure 1 where the required typical operating range is: undervoltage low-to-high (v 48uvhi ) = 43v undervoltage high-to-low (v 48uvlo ) = 39v overvoltage low-to-high (v 48ovhi ) = 82v overvoltage high-to-low (v 48ovlo ) = 78v a quick check of the resistive divider ratios required at uvl, uv, ovl and ov confirms that uvl is tapped between r5/r4, uv is tapped between r4/r3, ovl is tapped between r3/r2 and ov is tapped between r2/r1. from figure 1, by looking at the voltages at ov, ovl, uv and uvl, the following equations are obtained: r r v v where r rrrrr r rv v total ovhi ovhi total total ovhi ovhi 1 12 3 4 5 1 48 48 = = ++++ () = : ? (1a) r rr v v rr v v v v r total ovlo ovlo ovlo ovlo ovhi ovhi 12 21 1 48 48 48 + = = ? ? ? ? ? ? ?C (1b) r rr r v v rr v v v v rr total uvhi uvhi uvhi uvhi ovhi ovhi 12 3 31 12 48 48 48 ++ = = ? ? ? ? ? ? ?CC (1c) r rrrr v v rr v v v v rr r total uvlo uvlo uvlo uvlo ovhi ovhi 12 3 4 41 123 48 48 48 +++ = = ? ? ? ? ? ? ?CCC (1d) starting with a value of 20k for r1, equation 1b gives r2 = 0.984k (use closest 1% standard value of 0.976k). using r1 = 20k and r2 = 0.976k, equation 1c gives r3 = 2.103k (use the closest 1% standard value of 2.1k). using r1 = 20k, r2 = 0.976k and r3 = 2.1k, equation 1d gives r4 = 2.37k (use closest 1% standard value of 2.37k). using r1 = 20k, r2 = 0.976k, r3 = 2.1k and r4 = 2.37k in equation 1a, r5 = 296.754k (use 1% standard values of 294k in series with 2.74k). the divider values shown set a standing current of slightly more than 150 a and define an impedance at uvl/uv/ ovl/ov of approximately 20k. this impedance will work with the hysteresis set across uvl/uv and ovl/ov to provide noise immunity to the uv and ov comparators. if
ltc4253a-adj 16 4253a-adjf applicatio s i for atio wu u u more noise immunity is desired, add a 1nf to 10nf filter capacitor from uvl to v ee . uv/ov operation an undervoltage condition detected by the uv comparator immediately shuts down the ltc4253a-adj, pulls gate, ss and timer low and resets the three latched pwrgd signals high. recovery from an undervoltage will initiate an initial timing sequence if the other interlock conditions are met. an overvoltage condition is detected by the ov compara- tor and pulls gate low, thereby shutting down the load, but it will not reset the circuit breaker timer and pwrgd flags. returning from the overvoltage condition will restart the gate pin if all the interlock conditions except timer are met. only during the initial timing cycle does an overvoltage condition have an effect of resetting timer. the internal uvlo at v in always overrides an overvoltage or undervoltage. drain connecting an external resistor, r d , to this dual function drain pin allows v out (mosfet drain-source voltage drop) sensing without it being damaged by large voltage transients. below 5v, negligible pin leakage allows a drain low comparator to detect v out less than 2.39v (v drnl ). this, together with the gate low comparator, starts the power good sequencing. when v out > v drncl , the drain pin is clamped at v drncl and the current flowing in r d is given by: i vv r drn out drncl d ? (2) this current is scaled up 8 times during a circuit breaker fault before being added to the nominal 200 a. this accelerates the fault timer pull-up when the mosfets drain-source voltage exceeds v drncl and effectively short- ens the mosfet heating duration. timer the operation of the timer pin is somewhat complex as it handles several key functions. a capacitor c t is used at timer to provide timing for the ltc4253a-adj. four different charging and discharging modes are available at timer: 1. 5 a slow charge; initial timing delay. 2. (200 a+8?i drn ) fast charge; circuit breaker delay. 3. 5 a slow discharge; circuit breaker cool-off. 4. low impedance switch; resets the timer capacitor after an initial timing delay, in uvlo, in uv and in ov during initial timing and when reset is high. for initial timing delay, the 5 a pull-up is used. the low impedance switch is turned off and the 5 a current source is enabled when the interlock conditions are met. c t charges to 4v in a time period given by: t vc a t = 4 5 ? (3) when c t reaches v tmrh (4v), the low impedance switch turns on and discharges c t . a gate start-up cycle begins and both ss and gate outputs are released. circuit breaker timer operation i f the sense pin detects more than 50mv drop across r s , the timer pin charges c t with (200 a+8?i drn ). if c t charges to 4v, the gate pin pulls low and the ltc4253a-adj latches off. the ltc4253a-adj remains latched off until the reset pin is momentarily pulsed high, the uvl/uv pin is momentarily pulsed low, the timer pin is momentarily discharged low by an external switch or v in dips below uvlo and is then restored. the circuit breaker timeout period is given by: t vc ai t drn = + 4 200 8 ? ? (4) if v out < 5v, an internal pmos isolates drain pin leakage current and this makes i drn = 0 in equation 4. if v out is above v drncl during the circuit breaker fault period, the charging of c t is accelerated by 8 ? i drn of equation 2. intermittent overloads may exceed the 50mv threshold at sense but, if their duration is sufficiently short, timer will not reach 4v and the ltc4253a-adj will not shut the
ltc4253a-adj 17 4253a-adjf applicatio s i for atio wu u u external mosfet off. to handle this situation, the timer discharges c t slowly with a 5 a pull-down whenever the sense voltage is less than 50mv. therefore any intermit- tent overload with v out < 5v and an aggregate duty cycle of more than 2.5% will eventually trip the circuit breaker and shut down the ltc4253a-adj. figure 3 shows the circuit breaker response time in seconds normalized to 1 f. the asymmetric charging and discharging of c t is a fair gauge of mosfet heating. the normalized circuit response time is estimated by: t cf id for d t drn () ?? .% = + () ? [] > 4 205 8 5 25 (5) t sqt . when pwrgd2 successfully pulls low, sqtimer ramps up on another delay cycle. pwrgd3 asserts when en2 and en3 go high and pwrgd2 has asserted for more than one t sqt . all three pwrgd signals are reset in uvlo, in uv condi- tion, if reset is high or when c t charges up to 4v. in addition, pwrgd2 is reset by en2 going low. pwrgd3 is reset by en2 or en3 going low. an overvoltage condition has no effect on the pwrgd flags. a 50 a current pulls each pwrgd pin high when reset. as power modules signal common are different from pwrgd, optoisolation is recommended. these three pins can sink an optodiode current. figure 17 shows an npn configuration for the pwrgd interface. a limiting base resistor should be used for each npn and the module enable input should have protection from negative bias current. figure 17 also shows how the ltc4253a-adj can be used to sequence four power modules. soft-start soft-start is effective in limiting the inrush current during gate start-up. from the block diagram, the internal ss circuit consists of a current i ss (28 a) feeding into a resistive divider. the resistive divider (47.5k/2.5k) scales v ss (t) down by 20 times to give the analog current limit threshold: vt vt v acl ss os () () C = 20 (7) after the initial timing cycle, ss ramps up from 0v to 1.4v (28 a ? 50k), ramping v acl (t) from C10mv to 60mv. the acl amplifier will then limit the inrush current to v acl (t)/ r s . the offset voltage, v os (10mv) ensures c ss is suffi- ciently discharged and the acl amplifier is in current limit mode before gate start-up. there are two modes of ss ramp up. if sel is set high and the ss pin floats, an internal current source ramps ss from 0v to 1.4v in about 200 s. connecting an external capaci- tor, c ss , from ss to ground modifies the ramp to approxi- mate an rc response of: vt v e ss ss t rc ss ss () C ? ? ? ? ? ? ? ? ? 1 (8) figure 3. circuit breaker response time power good sequencing after the initial timer cycle, gate ramps up to turn on the external mosfet which in turn pulls drain low. when gate is within 2.8v of v in and drain is lower than v drnl , the power good sequence starts off a 5 a pull-up on the sqtimer pin which ramps up until it reaches the 4v threshold then pulls low. when the sqtimer pin floats, this delay t sqt is about 300 s. connecting an external capacitor c sq from sqtimer to v ee modifies the delay to: t vc a sqt sq = 4 5 ? (6) pwrgd1 asserts low after one t sqt and sqtimer ramps up on another delay cycle. pwrgd2 asserts when en2 goes high and pwrgd1 has asserted for more than one fault duty cycle, d (%) 20 40 60 80 0 normalized response time (s/ f) 10 1 0.1 0.01 100 4253a f03 t c t ( f) 4 (205 + 8 ? i drn ) ? d C 5 = i drn = 0 a
ltc4253a-adj 18 4253a-adjf applicatio s i for atio wu u u when v acl (t) exceeds v sense , the acl amplifier exits current limit mode and releases its pull-down on gate. v ss (t) = 20 ? (v os + v sense ) from equation 7. so when v ss (t) > 20 ? v os = 0.2v (since v sense = 0v), gate starts to ramp up and ss continues to ramp up. when gate clears the threshold of the external fet and inrush current starts flow- ing, v acl (t) = (v ss (t)/20 C v os ) will have a positive offset from zero. v sense will show an initial jump to clear this offset before going into analog current limit (figure 4a). if sel is set low during ss ramp-up, v ss is servoed when it exceeds 20 ? v os = 0.2v and gate starts its ramp-up. v ss is servoed at a voltage that is just above 20 ? v os to keep the acl amplifier off and gate ramping up freely. once gate clears the threshold of the external fet, inrush cur- rent starts flowing and v sense will jump above v acl (t). this will engage the acl amplifier and mask off v ss servo so v ss continues its rc ramp-up. in this way, the ltc4253a-adj enters analog current limit with v acl (t) = (v ss (t)/20 C v os ) ramping up from close to zero. the resultant inrush current profile presents a smooth ramp up from zero (figure 4b). if there is little inrush current so the ltc4253a-adj does not enter current limit, v ss servo will be masked off when drain goes below 2.39v (v drnl ) and latched off when gate goes within 2.8v of v in (v gateh ). a minimum c ss of 5nf is required for the stability of the v ss servo loop. ss is discharged low during uvlo, uv, ov, during the initial timing cycle, a latched circuit breaker fault or the reset pin going high. gate gate is pulled low to v ee under any of the following conditions: in uvlo, when reset pulls high, in an undervoltage condition, in an overvoltage condition, dur- ing the initial timing cycle or a latched circuit breaker fault. when gate turns on, a 50 a current source charges the mosfet gate and any associated external capacitance. v in limits the gate drive to no more than 14.5v. gate-drain capacitance (c gd ) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the mosfet. a unique circuit pulls gate low with practically no usable voltage at v in , and eliminates current spikes at insertion. a large external gate-source capacitor is thus unnecessary for the purpose of compensating c gd . instead, a smaller value ( 10nf) capacitor c c is adequate. c c also provides compensation for the analog current limit loop. gate has two comparators: the gate low comparator looks for < 0.5v threshold prior to initial timing; the gate high comparator looks for < 2.8v relative to v in and, together with drain low comparator, starts power good sequencing during gate start-up. sense the sense pin is monitored by the circuit breaker (cb) comparator, the analog current limit (acl) amplifier, and the fast current limit (fcl) comparator. each of these three measures the potential of sense relative to v ee . when figure 4. two modes of ss ramp up (4a) sel set high (4b) sel set low gate 10v ss 1v sense 50mv v out 50v 1ms/div 4253a f04a gate 10v ss 1v sense 50mv v out 50v 1ms/div 4253a f04b
ltc4253a-adj 19 4253a-adjf applicatio s i for atio wu u u sense exceeds 50mv, the cb comparator activates the 200 a timer pull-up. at 60mv the acl amplifier servos the mosfet current, and at 200mv the fcl comparator abruptly pulls gate low in an attempt to bring the mosfet current under control. if any of these conditions persists long enough for timer to charge c t to 4v (see equation 4), the ltc4253a-adj shuts down and pulls gate low. if the sense pin encounters a voltage greater than v acl , the acl amplifier will servo gate downwards in an attempt to control the mosfet current. since gate over- drives the mosfet in normal operation, the acl amplifier needs time to discharge gate to the threshold of the mosfet. for a mild overload the acl amplifier can control the mosfet current, but in the event of a severe overload the current may overshoot. at sense = 200mv the fcl comparator takes over, quickly discharging the gate pin to near v ee potential. fcl then releases, and the acl amplifier takes over. all the while timer is running. the effect of fcl is to add a nonlinear response to the control loop in favor of reducing mosfet current. owing to inductive effects in the system, fcl typically overcorrects the current limit loop, and gate under- shoots. a zero in the loop (resistor r c in series with the gate capacitor) helps the acl amplifier to recover. short-circuit operation circuit behavior arising from a load side low impedance short is shown in figure 5. initially the current overshoots the analog current limit level of v sense = 200mv (trace 2) as the gate pin works to bring v gs under control (trace 3). the overshoot glitches the backplane in the negative direc- tion and when the current is reduced to 60mv/r s , the backplane responds by glitching in the positive direction. timer commences charging c t (trace 4) while the analog current limit loop maintains the fault current at 60mv/r s , which in this case is 5a (trace 2). note that the backplane voltage (trace 1) sags under load. timer pull-up is accel- erated by v out . when c t reaches 4v, gate turns off, the pwrgd signals pull high, the load current drops to zero and the backplane rings up to over 100v. the transient associated with the gate turn-off can be controlled with a snubber to reduce ringing and a transient voltage suppressor (such as diodes inc. smat70a), to clip off large spikes. the choice of rc for the snubber is usually done experimentally. the value of the snubber capacitor is usually chosen between 10 to 100 times the mosfet c oss . the value of the snubber resistor is typically be- tween 3 ? to 100 ? . a low impedance short on one card may influence the behavior of others sharing the same backplane. the initial glitch and backplane sag as seen in figure 5 trace 1, can rob charge from output capacitors on the adjacent card. when the faulty card shuts down, current flows in to refresh the capacitors. if ltc4253a-adjs are used by the other cards, they respond by limiting the inrush current to a value of v acl /r s . if c t is sized correctly, the capacitors will recharge long before c t times out. mosfet selection the external mosfet switch must have adequate safe operating area (soa) to handle short-circuit conditions until timer times out. these considerations take prece- dence over dc current ratings. a mosfet with adequate soa for a given application can always handle the required current but the opposite may not be true. consult the manufacturers mosfet datasheet for safe operating area and effective transient thermal impedance curves. figure 5. output short-circuit behavior of ltc4253a-adj C48v rtn 50v trace 1 trace 2 trace 3 trace 4 sense 200mv gate 10v timer 5v 0.5ms/div 4253a f05 c timer ramp analog current limit fast current limit onset of output short circuit supply ring owing to current overshoot latch off supply ring owing to mosfet turn-off
ltc4253a-adj 20 4253a-adjf applicatio s i for atio wu u u mosfet selection is a 3-step process by assuming the absense of soft-start capacitor. first, r s is calculated and then the time required to charge the load capacitance is determined. this timing, along with the maximum short- circuit current and maximum input voltage, defines an operating point that is checked against the mosfets soa curve. to begin a design, first specify the required load current and ioad capacitance, i l and c l . the circuit breaker current trip point (v cb /r s ) should be set to accommodate the maximum load current. note that maximum input current to a dc/dc converter is expected at v supply(min) . r s is given by: r v i s cb min lmax = () () (9) where v cb(min) = 45mv represents the guaranteed mini- mum circuit breaker threshold. during the initial charging process, the ltc4253a-adj may operate the mosfet in current limit, forcing (v acl ) between 54mv to 66mv across r s . the minimum inrush current is given by: i v r inrush min acl min s () () = (10) maximum short-circuit current limit is calculated using the maximum v sense . this gives i v r shortcircuit max acl max s () () = (11) the timer capacitor, c t , must be selected based on the slowest expected charging rate; otherwise timer might time out before the load capacitor is fully charged. a value for c t is calculated based on the maximum time it takes the load capacitor to charge. that time is given by: t cv i cv i cl charge l supply max inrush min () () () ? ? == (12) the maximum current flowing in the drain pin is given by: i vv r drn max supply max drncl d () () = ? (13) approximating a linear charging rate, i drn drops from i drn(max) to zero, the i drn component in equation 4 can be approximated with 0.5 ? i drn(max) . rearranging the equation, timer capacitor c t is given by: c tai v t cl charge drn max = + () () ?( ? ) 200 4 4 (14) returning to equation 4, the timer period is calculated and used in conjunction with v supply(max) and i shortcircuit(max) to check the soa curves of a prospec- tive mosfet. as a numerical design example, consider a 30w load, which requires 1a input current at 36v. if v supply(max) = 72v and c l = 100 f, r d = 1m ? , equation 9 gives r s = 45m ? ; use r s = 40m ? for more margin. equation 14 gives c t = 619nf. to account for errors in r s , c t , timer current (200 a), timer threshold (4v), r d , drain cur- rent multiplier and drain voltage clamp (v drncl ), the calculated value should be multiplied by 1.5, giving the nearest standard value of c t =1 f. if a short-circuit occurs, a current of up to 66mv/45m ? = 1.65a will flow in the mosfet for 9.1ms as dictated by c t = 1 f in equation 4. the mosfet must be selected based on this criterion. the irf530s can handle 100v and 2a for 22.5ms and is safe to use in this application. computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear mosfets soa characteristics and the r ss c ss response. an overconservative but simple approach begins with the maximum circuit breaker current, given by: i v r cb max cb max s () () = (15) from the soa curves of a prospective mosfet, determine the time allowed, t soa(max) . c ss is given by: c t r ss soa max ss = () .? 248 (16) in the above example, 55mv/40m ? gives 1.375a. t soa for the irf530s is 47.6ms. from equation 16, c ss = 384nf.
ltc4253a-adj 21 4253a-adjf the analog current limit loop cannot control this current flow and therefore the loop undershoots. this effect cannot be eliminated by frequency compensation. a zener diode is required to clamp the input supply voltage and prevent mosfet avalanche. applicatio s i for atio wu u u actual board evaluation showed that c ss = 100nf was appropriate. the ratio (r ss ? c ss ) to t cl(charge) is a good gauge as large ratios may result in the time-out period expiring prematurely. this gauge is determined empiri- cally with board level evaluation. summary of design flow to summarize the design flow, consider the application shown in figure 1. it was designed for 80w and c l = 100 f. calculate maximum load current: 80w/43v = 1.86a; allowing for 83% converter efficiency, i in(max) = 2.2a. calculate r s : from equation 9 r s = 20m ? . calculate i short-circuit(max) : from equation 11 i shortcircuit(max) = 3.3a. select a mosfet that can handle 3.3a at 71v: irf530s. calculate c t : from equation 14 c t = 383nf. select c t = 680nf, which gives the circuit breaker time-out period t max = 5.9ms. consult mosfet soa curves: the irf530s can handle 3.3a at 100v for 8.3ms, so it is safe to use in this application. calculate c ss : using equations 15 and 16 select c ss = 33nf. frequency compensation the ltc4253a-adj typical frequency compensation net- work for the analog current limit loop is a series r c (10 ? ) and c c connected from gate to v ee . figure 6 depicts the relationship between the compensation capacitor c c and the mosfets c iss . the line in figure 6 is used to select a starting value for c c based upon the mosfets c iss specification. optimized values for c c are shown for several popular mosfets. differences in the optimized value of c c versus the starting value are small. neverthe- less, compensation values should be verified by board level short-circuit testing. as seen in figure 5, at the onset of a short-circuit event, the input supply voltage can ring dramatically due to series inductance. if this voltage avalanches the mosfet, cur- rent continues to flow through the mosfet to the output. figure 6. recommended compensation capacitor c c vs mosfet c iss mosfet c iss (pf) compensation capacitor c c (nf) 4253a f06 0 50 45 40 35 30 25 20 15 10 5 0 2000 4000 6000 8000 irf530s irf540s irf740 irf3710 nty100n10 sense resistor considerations for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc4253a- adjs v ee and sense pins are strongly recommended. the drawing in figure 7 illustrates the correct way of making connections between the ltc4253a-adj and the sense resistor. pcb layout should be balanced and sym- metrical to minimize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. figure 7. making pcb connections to the sense resistor w current flow from load current flow to C48v backplane sense resistor track width w: 0.03" per amp on 1 oz copper to sense to v ee 4253a f07
ltc4253a-adj 22 4253a-adjf applicatio s i for atio wu u u timing waveforms system power-up figure 8 details the timing waveforms for a typical power- up sequence in the case where a board is already installed in the backplane and system power is applied abruptly. at 4253a f08 gate start-up initial timing v lko v gatel gnd C v ee or (C48rtn) C (C48v) ovl ov v in timer gate sense v out 12 3456 789 ss drain pwrgd1 ab pwrgd2 pwrgd3 sqtimer en2 en3 cd v uvhi v ovlo v in clears v lko , check uv > v uvhi , ovl < v ovlo , reset < 0.8v, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl timer clears v tmrl , check gate < v gatel , sense < v cb and ss < 20 ? v os e v sqtmrl 5 a 5 a v sqtmrh v ih v ih v tmrh v acl v cb v tmrl 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 50 a 5 a 5 a 50 a 50 a v drncl v drnl v in C v gateh 200 a + 8 ? i drn uvl uv time point 1, the supply ramps up, together with uv/ov, v out and drain. v in and the pwrgd signals follow at a slower rate as set by the v in bypass capacitor. at time point 2, v in exceeds v lko and the internal logic checks for uv > v uvhi , ovl < v ovlo , reset < 0.8v, gate < v gatel , sense < v cb , ss < 20 ? v os , and timer < v tmrl . when figure 8. system power-up timing (all waveforms are referenced to v ee )
ltc4253a-adj 23 4253a-adjf applicatio s i for atio wu u u all conditions are met, initial timing starts and the timer capacitor is charged by a 5 a current source pull-up. at time point 3, timer reaches the v tmrh threshold and the initial timing cycle terminates. the timer capacitor is quickly discharged. at time point 4, the v tmrl threshold is reached and the conditions of gate < v gatel , sense < v cb and ss < 20 ? v os must be satisfied before the gate start- up cycle begins. ss ramps up as dictated by r ss ? c ss (as in equation 8); gate is held low by the analog current limit (acl) amplifier until ss crosses 20 ? v os . upon releasing gate, 50 a sources into the external mosfet gate and compensation network. when the gate voltage reaches the mosfets threshold, current flows into the load ca- pacitor at time point 5. at time point 6, load current reaches ss control level and the analog current limit loop activates. between time points 6 and 8, the gate voltage is servoed, the sense voltage is regulated at v acl (t) (equation 7) and soft-start limits the slew rate of the load current. if the sense voltage (v sense C v ee ) reaches the v cb threshold at time point 7, circuit breaker timer activates. the timer capacitor, c t is charged by a (200 a+8?i drn ) current pull-up. as the load capacitor nears full charge, load current begins to decline. at time point 8, the load current falls and the sense voltage drops below v acl (t). the analog current limit loop shuts off and the gate pin ramps further. at time point 9, the sense voltage drops below v cb , the fault timer ends, followed by a 5 a discharge cycle (cool-off). the duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid fault time-out during gate ramp- up. at time point b, gate reaches its maximum voltage as determined by v in . at time point a, gate ramps past v gateh and sqtimer starts its ramp-up to 4v. pwrgd1 pulls low at time point c after one t sqt from time point a, setting off the second sqtimer ramp up. having satisfied the requirement that pwrgd1 is low for more than one t sqt , pwrgd2 pulls low after en2 pulls high above the v ih threshold at time point d. this sets off the third sqtimer ramp-up. having satisfied the requirement that pwrgd2 is low for more than one t sqt , pwrgd3 pulls low after en3 pulls high at time point e. live insertion with short pin control of uv/ov in the example shown in figure 9, power is delivered through long connector pins whereas the uv/ov divider makes contact through a short pin. this ensures the power con- nections are firmly established before the ltc4253a-adj is activated. at time point 1, the power pins make contact and v in ramps through v lko . at time point 2, the uv/ov divider makes contact and uv > v uvhi . in addition, the in- ternal logic checks for ov < v ovhi , reset < 0.8v, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl . when all conditions are met, initial timing starts and the timer capacitor is charged by a 5 a current source pull- up. at time point 3, timer reaches the v tmrh threshold and the initial timing cycle terminates. the timer capaci- tor is quickly discharged. at time point 4, the v tmrl thresh- old is reached and the conditions of gate < v gatel , sense < v cb and ss < 20 ? v os must be satisfied before the gate start-up cycle begins. ss ramps up as dictated by r ss ? c ss ; gate is held low by the analog current limit amplifier until ss crosses 20 ? v os . upon releasing gate, 50 a sources into the external mosfet gate and compen- sation network. when the gate voltage reaches the mosfets threshold, current begins flowing into the load capacitor at time point 5. at time point 6, load current reaches ss control level and the analog current limit loop activates. between time points 6 and 8, the gate voltage is servoed and the sense voltage is regulated at v acl (t) and soft-start limits the slew rate of the load current. if the sense voltage (v sense C v ee ) reaches the v cb threshold at time point 7, the circuit breaker timer activates. the timer capacitor, c t is charged by a (200 a+8?i drn ) current pull-up. as the load capacitor nears full charge, load current begins to decline. at point 8, the load current falls and the sense voltage drops below v acl (t). the analog current limit loop shuts off and the gate pin ramps fur- ther. at time point 9, the sense voltage drops below v cb and the fault timer ends, followed by a 5 a discharge current source (cool-off). when gate ramps past v gateh threshold at time point a, sqtimer starts its ramp-up. pwrgd1 pulls low at time point c after one t sqt from time
ltc4253a-adj 24 4253a-adjf applicatio s i for atio wu u u point a, setting off the second sqtimer ramp-up. pwrgd2 pulls low at time point d when en2 is high and pwrgd1 is low for more than one t sqt . pwrgd3 pulls low at time point e when en2 and en3 is high and pwrgd2 is low for more than one t sqt . at time point b, gate reaches its maxi- mum voltage as determined by v in . undervoltage timing in figure 10 when the uvl pin drops below v uvlo (time point 1), the ltc4253a-adj shuts down with timer, ss and gate pulled low. if current has been flowing, the sense pin voltage decreases to zero as gate collapses. when uv recovers and clears v uvhi (time point 2), an initial time cycle begins followed by a start-up cycle. figure 9. power-up timing with a short pin (all waveforms are referenced to v ee ) gate start-up initial timing v ovhi v lko v gatel v sqtmrl gnd C v ee or (C48rtn) C (C48v) ovl ov v in timer gate sense uv clears v uvhi , check ov < v ovhi , reset < 0.8v, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl v out 12 3456 78 9 timer clears v tmrl , check gate < v gatel , sense < v cb and ss < 20 ? v os ss drain pwrgd1 a b v uvhi pwrgd2 pwrgd3 sqtimer en2 en3 c d e 5 a 5 a v sqtmrh 4253a f09 v tmrh v acl v cb v tmrl 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 5 a 5 a 50 a 50 a 50 a v drncl v drnl v in C v gateh 200 a + 8 ? i drn uvl uv
ltc4253a-adj 25 4253a-adjf applicatio s i for atio wu u u v in undervoltage lockout timing v in undervoltage lockout comparator, uvlo has a similar timing behavior as the uv pin timing except it looks at v in < (v lko Cv lkh ) to shut down and v in > v lko to start. in an undervoltage lockout condition, both uv and ov com- parators are held off. when v in exits undervotlage lockout, the uv and ov comparators are enabled. figure 10. undervoltage timing (all waveforms are referenced to v ee ) 50 a uv clears v uvhi , check ov condition, reset < 0.8v, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl timer clears v tmrl , check gate < v gatel , sense < v cb and ss < 20 ? v os uvl uv timer gate sense ss drain pwrgd1 pwrgd2 pwrgd3 sqtimer en2 en3 12 3456789abcd 4253 f10 initial timing gate start-up 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 5 a uvl drops below v uvlo . gate, ss and timer are pulled down, pwrgd releases e v uvlo v gatel v uvhi v acl v sqtmrl v cb 5 a 5 a 50 a v sqtmrh v drncl v drnl v in C v gateh 50 a 200 a + 8 ? i drn v tmrh v tmrl 5 a overvoltage timing during normal operation, if the ov pin exceeds v ovhi as shown at time point 1 of figure 11, the timer and pwrgd status are unaffected; ss and gate pull down; load disconnects. at time point 2, ovl recovers and drops below the v ovlo threshold; gate start-up begins. if the overvoltage glitch is long enough to deplete the load capacitor, time points 4 through 7 may occur.
ltc4253a-adj 26 4253a-adjf applicatio s i for atio wu u u figure 11. overvoltage timing (all waveforms are referenced to v ee ) circuit breaker timing in figure 12a, the timer capacitor charges at 200 a if the sense pin exceeds v cb but v drn is less than 5v. if the sense pin returns below v cb before timer reaches the v tmrh threshold, timer is discharged by 5 a. in figure 12b, when timer exceeds v tmrh , gate pulls down immediately and the chip shuts down. in figure 12c, multiple momentary faults cause the timer capacitor to integrate and reach v tmrh followed by gate pull down and the chip shuts down. during chip shutdown, ltc4253a-adj latches timer high with a 5 a pull-up current source. resetting a fault latch a latched circuit breaker fault of the ltc4253a-adj has the benefit of a long cooling time. the latched fault can be reset by pulsing the reset pin high for >20 s to over- come the internal glitch filter as shown in figure 13b. after the reset pulse, ss and gate ramp up without an initial timing cycle provided the interlock conditions are satisfied. v acl v cb v in C v gateh ovl ov timer gate sense ss 123456789 gate start-up 4253a f11 ovl drops below v ovlo , check gate < v gatel , sense < v cb and ss < 20 ? v os ov overshoots v ovhi . gate and ss are pulled down, pwrgd signals and timer are unaffected v ovhi v ovlo v tmrh v gatel 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 50 a 50 a 5 a 200 a + 8 ? i drn alternative methods of reset include using an external switch to pulse the uvl/uv pin below v uvlo or the v in pin below (v lko C v lkh ). pulling the timer pin below v tmrl and the ss pin to 0v then simultaneously releasing them also achieves a reset. an initial timing cycle is generated for reset by pulsing the uvl/uv pin or v in pin, while no initial timing cycle is generated for reset by pulsing of the timer and ss pins. using reset as an on/off switch the asynchronous reset pin can be used as an on/off function to cut off supply to the external power modules or loads controlled by the chip. pulling reset high will pull gate, ss, timer and sqtimer low and the pwrgd signal high. the supply is fully cut off if the reset pulse is maintained wide enough to overcome the internal 20 s glitch filter. as long as reset is high, gate, ss, timer and sqtimer are strapped to v ee and the supply is cut off. when reset is released, the chip waits for the interlock conditions before recovering as described in the opera- tion, interlock conditions section and figure 13c.
ltc4253a-adj 27 4253a-adjf applicatio s i for atio wu u u figure 12. circuit breaker timing behavior (all waveforms are referenced to v ee ) (12a) momentary circuit breaker fault (12b) circuit breaker time-out (12c) multiple circuit breaker fault analog current limit and fast current limit in figure 14a, when sense exceeds v acl , gate is regu- lated by the analog current limit amplifier loop. when sense drops below v acl , gate is allowed to pull up. in figure 14b, when a severe fault occurs, sense exceeds v fcl and gate immediately pulls down until the analog current amplifier establishes control. if the severe fault causes v out to exceed v drncl , the drain pin is clamped at v drncl . i drn flows into the drain pin and is multiplied by 8. this extra current is added to the timer pull-up current of 200 a. this accelerated timer current of (200 a+8?i drn ) produces a shorter circuit breaker fault delay. careful selection of c t , r d and mosfet helps prevent soa damage in a low impedance fault condition. soft-start if sel is floated high and the ss pin is not connected, this pin defaults to a linear voltage ramp, from 0v to 1.4v in about 200 s at gate start-up, as shown in figure 15a. if a soft-start capacitor, c ss , is connected to this ss pin, the soft-start response is modified from a linear ramp to an rc response (equation 8), as shown in figure 15b. this feature allows load current to slowly ramp-up at gate start-up. soft-start is initiated at time point 3 by a timer transition from v tmrh to v tmrl (time points 1 and 2), by the ovl pin falling below the v ovlo threshold after an ov condition, or by the reset pin falling < 0.8v after a reset condition. when the ss pin is below 0.2v, the analog current limit amplifier keeps gate low. above 0.2v, gate is released and 50 a ramps up the compensation net- work and gate capacitance at time point 4. meanwhile, the ss pin voltage continues to ramp up. when gate reaches the mosfets threshold, the mosfet begins to conduct. due to the mosfets high g m , the mosfet current quickly reaches the soft-start control value of v acl (t) (equation 7). at time point 6, the gate voltage is controlled by the current limit amplifier. the soft-start control voltage reaches the circuit breaker voltage, v cb at time point 7 and the circuit breaker timer activates. as the load capacitor nears full charge, load current begins cb fault cb fault cb fault cb fault 12 1 2 12 34 timer gate sense v out ss drain pwrgd1 timer gate sense v out ss drain pwrgd1 timer gate sense v out ss drain pwrgd1 4253a f12 cb times-out cb times-out v tmrh v acl v cb v acl v cb 5 a 5 a v drncl 200 a + 8 ? i drn 200 a + 8 ? i drn v tmrh v acl v cb v drncl 200 a + 8 ? i drn v tmrh
ltc4253a-adj 28 4253a-adjf figure 13. reset functions (all waveforms are referenced to v ee ) applicatio s i for atio wu u u reset pulse width must be >20 s to overcome internal glitch filter reset pulse width must be >20 s to overcome internal glitch filter 123456789 latched timer reset by reset pulling high reset < v il , check uvlo, uv, ov condition, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl reset < v il , check uvlo, uv, ov condition, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl timer gate sense reset ss drain pwrgd1 v tmrh 20 s v ih v il v acl v cb v tmrl v gatel v lko v uvhi 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 5 a 50 a 50 a 5 a 50 a v drncl v drnl v in C v gateh 200 a + 8 ? i drn 123456789 4253a f13 timer gate sense reset ss drain pwrgd1 v ih v il v acl v cb v tmrl v gatel v lko v uvhi 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 50 a 50 a 5 a 50 a v drncl v drnl v in C v gateh 200 a + 8 ? i drn 123 4 567 8 reset < v il , check uvlo, uv, ov condition, gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl timer gate sense reset ss drain pwrgd1 v in v in v in uvl uv uvl uv v il v acl v cb v tmrl v gatel v lko 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 50 a 50 a 5 a 50 a v drncl t sqt v drnl v in C v gateh 200 a + 8 ? i drn v uvhi uvl uv t sqt t sqt 20 s (13a) reset forcing start-up without initial timer cycle (13b) reset of ltc4253-adj? latched fault (13c) reset as an on/off switch
ltc4253a-adj 29 4253a-adjf figure 15. soft-start timing (all waveforms are referenced to v ee ) (15a) without external c ss (15b) with external c ss figure 14. current limit behavior (all waveforms are referenced to v ee ) (14a) analog current limit fault (14b) fast current limit fault (15c) with sel = low and external c ss applicatio s i for atio wu u u to decline below v acl (t). the current limit loop shuts off and gate releases at time point 8. at time point 9, sense voltage falls below v cb and timer deactivates. a third soft-start mode is shown in figure 15c. the sel pin is tied low and a soft-start capacitor, c ss , is connected to the ss pin. the behavior is similar to figure 15b until time point 4 when gate is released and starts to ramp up. instead of continuing its ramp-up as in mode two, the ss pin voltage is servoed at a voltage that is just above 0.2v (20 ? v os ) to keep the current limit amplifier off and the gate ramping up freely. at time point 5, gate ramps past the external mosfets threshold and inrush current starts to flow. at time point 6, v sense goes above v acl (t) and the servo on ss is released while the gate voltage is con- trolled by the current limit amplifier with v acl (t) ramping up from near zero. the result is a current profile (as 12 12 34 timer gate sense v out ss drain pwrgd1 timer gate sense v out drain pwrgd1 4253a f14 cb times-out v tmrh v acl v cb v acl v fcl v cb 5 a 200 a + 8 ? i drn 200 a + 8 ? i drn v drncl v tmrh 12 34 5 6 7 7a 8 9 10 11 end of initial timing cycle 12 3 4 56 7 8 9 10 11 end of initial timing cycle 4253a f15 timer gate sense ss drain v tmrh v acl v cb v tmrl v tmrh v tmrl v gs(th) v gs(th) 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 50 a 50 a v drncl v drnl v in C v gateh 200 a + 8 ? i drn timer gate sense ss drain v acl v cb 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 50 a 50 a v drncl v drnl v in C v gateh 200 a + 8 ? i drn 12 3 4 56 7 8 9 10 11 end of initial timing cycle v tmrh v tmrl v gs(th) timer gate sense ss drain v acl v cb 20 ? (v acl + v os ) 20 ? (v cb + v os ) 20 ? v os 5 a 50 a 50 a v drncl v drnl v in C v gateh 200 a + 8 ? i drn
ltc4253a-adj 30 4253a-adjf reflected in v sense ) that ramps up smoothly from near zero. v sense does not show a large kink as in figure 15b when v acl (t) already has a substantial offset from zero at time point 6. sel tied low chooses this ss servo mode during soft-start while sel set high allows the ss pin to do an open-loop ramp-up as in figures 15a and 15b. the stability of the ss servo loop requires a c ss > 5nf. large values of c ss can cause premature circuit breaker time-out as v acl (t) may marginally exceed the v cb poten- tial during the circuit breaker delay. the load capacitor is unable to achieve full charge in one gate start-up cycle. a more serious side effect of a large c ss value is that soa duration may be exceeded during soft-start into a low impedance load. a soft-start voltage below v cb will not activate the circuit breaker timer. power limit circuit breaker figure 16 shows the ltc4253a-adj in a power limit circuit breaking application. the sense pin is modulated by board voltage v supply . the zener voltage, v z of d1, is set to be the same as the lowest operating voltage, v supply(min) = 43v. if the goal is to have the high supply operating voltage, v supply(max) = 71v give the same power as available at v supply(min) , then resistors r4 and figure 16. power limit circuit breaker application r5 are selected by: r r v v cb supply max 5 4 = () (17) if r5 is 22 ? , then r4 is 31.6k. the peak circuit breaker power limit is: power max vv vv power at v power at v supply min supply max supply min supply max supply min supply min () ?? ? .? () ( ) () ( ) () () = + () = 2 4 1 064 (18) when v supply = 0.5 ? (v supply(min) + v supply(max) ) = 57v the peak power at the fault current limit occurs at the supply overvoltage threshold. the fault current limited power is: power fault v r vv v r r supply s acl supply z () ?( )? = () ?? ? ? ? ? ? ? 5 4 (19) applicatio s i for atio wu u u r6 2.2k r4 31.6k r9 22k d1 bzv85c43 r7 2.2k q2 fzt857 r8 2.2k ? pwrgd1 v in reset v in1 v ee sel ltc4253a-adj power module 1 pwrgd2 pwrgd3 ov ovl drain ss gate sqtimer sense timer en power module 2 en load 3 en r in 10k 20k(1/4w)/2 uv uvl en3 en2 4253a f16 r c 10 ? r5 22 ? r d 1m r s 0.02 ? v in1 v in1 en2 en3 power module 1 output power module 2 output q1 irf530s c c 10nf c t 0.68 f c1 10nf c in 1 f c sq 0.1 f c ss 33nf + c2 100 f c3 0.1 f C 48v rtn (short pin) C 48v rtn (long pin) C 48v (long pin) reset (long pin) r2 2.05k 1% 2k 1% r1 20k 1% 255k 1% ? moc207 ? ? ? ? r3
ltc4253a-adj 31 4253a-adjf package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 20-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) uf package 20-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1710) .337 C .344* (8.560 C 8.738) gn20 (ssop) 0204 12 3 4 5 6 7 8910 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 17 18 19 20 15 14 13 12 11 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .0075 C .0098 (0.19 C 0.25) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .058 (1.473) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4.00 0.10 (4 sides) note: 1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-1)to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.38 0.10 20 19 1 2 bottom viewexposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf20) qfn 10-04 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.30 typ
ltc4253a-adj 32 4253a-adjf ? linear technology corporation 2005 related parts part number description comments lt1640ah/lt1640al negative high voltage hot swap controllers in so-8 negative high voltage supplies from -10v to -80v lt1641-1/lt1641-2 positive high voltage hot swap controllers in so-8 supplies from 9v to 80v, autoretry/latched off ltc1642 fault protected hot swap controller 3v to 16.5v, overvoltage protection up to 33v lt4250 C 48v hot swap controller active current limiting, supplies from C 20v to C 80v ltc4251/ltc4251-1 C 48v hot swap controllers in sot-23 fast active current limiting, supplies from C 15v ltc4251-2 ltc4252-1/ltc4252-2 C 48v hot swap controllers in ms8/ms10 fast active current limiting, supplies from C 15v, ltc4252a-1/ltc4252a-2 drain accelerated response, 1% accurate uv/ov thresholds ltc4260 positive voltage hot swap controller with i 2 c onboard adc for current and voltage monitoring, compatible monitoring 8.5v to 80v operation figure 17. ?8v/2.5a application with foldback current limiting and transistor enabled sequencing without feedback applicatio s i for atio wu u u circuit breaker with foldback current limit figure 17 shows the ltc4253a-adj in a foldback current limit application. when v out is shorted to the C 48v rtn supply, current flows through resistors r4 and r5. this results in a voltage drop across r5 and a corresponding reduction in voltage drop across the sense resistor, r s , as the acl amplifier servos the sense voltage between the sense and v ee pins to about 60mv. the short-circuit current through r s reduces as the v out voltage increases during an output short-circuit condition. without foldback current limiting resistor r5, the current is limited to 3a during analog current limit. with r5, the short-circuit current is limited to 0.5a when v out is shorted to 71v. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com lt/tp 0805 500 ? printed in usa r7 100k r6 100k r8 100k r9 100k r10 3k pwrgd1 v in en2 en3 v in v ee ltc4253a-adj power module 2 pwrgd2 pwrgd3 uvl uv ovl ov reset drain ss gate sqtimer sense timer en power module 1 en power module 3 en power module 4 en r in 10k 20k(1/4w)/2 4253 f17 sel r c 10 ? r4 38.3k r d 3.3m r s 0.02 ? q1 irf530s v out c c 10nf r5 22 ? c t 1 f c1 10nf r11 47k c sq 0.1 f c ss 33nf + c3 0.1 f c2 100 f c in 1 f r2 2.05k 1% r1 20k 1% 255k 1% 2k 1% r3 ? fmmt493 ? ? ? reset (long pin) C 48v rtn (short pin) C 48v rtn (long pin) C 48v (long pin)

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