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[AK7754] ms1138-e-01-pb - 1 - 2012/03 general description the AK7754 is a highly integrated audio digital signal pr ocessor (dsp) with two audio i/f?s, microphone and headphone amplifier. the audio dsp has 1536step/fs (at 48khz sampling) parallel processing power, and akm?s original hands-free technology provides hi gh performance noise and echo cancelling. the 96k-bit delay memory allows surround processing, acoustic ef fect and parametric equaliz ers. as the AK7754 is a ram based dsp, it is programmable for user requir ements. the internal src has various sampling rate converting modes, corresponds many sampling ra tes without changing the dsp operating sampling frequency. the AK7754 is available in a space saving small 48pin qfn package. features dsp block - word length: 24bit (coefficient ram & data ram: f24 floating point) - processing speed: 13.6 ns (1536step/fs fs=48khz; 9216step/fs fs=8khz) - multiplication: 20 x 16 36-bit double precision arithmetic available - divider 20 / 20 20bit - alu: 40bit arithmetic operation (overflow margin 4bit) 24bit floating point arithmetic and logic operation - program ram: 2048 x 36bit - coefficient ram: 2048 x 16bit (f24 floating point) - data ram: 512 x 24-bit (f24 floating point) - offset register: 32 x 12bit - delay ram1: 3072 x 24bit - delay ram2: 2048 x 12bit - sampling rate: fs= 8.0k ~ 48khz - master/slave operation - master clock: 1536fs (generated from 32fs, 48fs, 64fs, 128f s, 256fs, 384fs by internal pll) two digital interfaces (i/f 1, i/f 2) - digital signal input port (4ch) msb just ified 24bit/lsb justified 24/20/16bit and i 2 s - digital signal input port (6ch) msb justified 24bit/ lsb justified 20/16bit and i 2 s - short / long frame -24 bit linear, 8 bit a-law, 8 bit -law stereo 24bit adc block - sampling rate: 8 ~ 48khz - adc characteristics s/(n+d): 82db ,dr, s/n: 89db - three analog input selectors (differential, single-ended inputs) - channel independent mic, analog line gain amp (0db, 9db~27db, 3dbstep) - channel independent digital volume (24db ~ -103db, 0.5db step, mute) - integrated dc offset can celing high pass filter digital microphone i/f audio dsp with stereo codec + mic/hp-amp AK7754
[AK7754] ms1138-e-01-pb - 2 - 2012/03 stereo 24bit dac - sampling rate: 8 ~ 48khz - digital volume (12db~-115db, 0.5db step, mute) - digital de-emphasis filter (tc=50/15 s, fs=32khz, 44.1khz, 48khz) line outputs - single-ended or differential outputs - s/(n+d): 91db ,dr, s/n: 96db - stereo analog volume (+0 ~ -28db, 2.0db step, mute) stereo headphone amplifier with a volume control - rated output power: 27mw/ch @16 ? - s/(n+d): 70db , s/n: 89db - stereo analog volume (+0 ~ -50db,1.0/2.0/4.0db step, mute) - click noise free at power on/off src block - 2ch x 1 system - input sampling frequency: 8khz ~ 96khz - output sampling frequency: 8khz ~ 48khz analog bypass mode - bypass amplifier (0db~-21db, 3db step) output mixer p interface: i 2 c bus (400khz fast-mode) power supply analog avdd: 3.0v ~ 3.6v (typ.3.3v) digital1 dvdd: 3.0v ~ 3.6v (typ.3.3v) digital2 dvdd18: 1.7v ~ 1.9v (typ.1.8v) hp-amp hvdd: 3.0v ~ 3.6v (typ.3.3v) operating temperature range: -20 c ~ 85 c package: 48pin qfn (0.5mm pitch)
[AK7754] ms1138-e-01-pb - 3 - 2012/03 block diagram figure 1. block diagram initrstn rdy/sdoutm sdin2/jx2 test1 vcom lflt bick1/jx1 lrck1/jx0 bick2/jx1 lrck2/jx0 srclflt clko outl/outp scl cad0 cad1 pull down vref clkgen & cont sdin1/jx2 sda test2 micif 2 3 dvdd dvdd18 open drain a dc sdoutad src wdt wdten sto locke srci srco 1 0 din2 srcbicko srclrcko din3 dout2 sdout2 dsp out2e seldi2 mbitclk0 mlrclk0 mdspclk0 mclk 0 1 0 2 3 dout3 1 0 2 3 gp1 gp0 dac hpl vss hvdd in1l/in1p in2l/in1n in3r/dmdat a in r dmdat mpwr mic power hvcom seldo2[1:0] seldom[1:0] seldai[1:0] din1 dout1 1 0 2 3 out1e sdout1 irpt 1 0 2 3 seldo1[1:0] hpr a vdd unlock xti clkoe so/rdy digmic if 1 0 so rdy 0 1 selson selmn outme hp hp dmclk xt o line line pmlol pmhp l pmadl/ r pmdal/r pmhpr pmmp pmlor pmsrc pmdsp bicko lrcko bickoe lrckoe dar dal outr/outn in1l/in1 p in2 l in1n pmmicl micl in3l/dmclk pmlinl linl in1r/in2p in2r/in2n in1r/in2p in2r in2n pmmicr micr pmlinr linr a inl 1 0 0 1 in3r in3l pmps l pmps r 0 1 1 0 bps l bps r mprf 1 0 seljx2 jx2e jx1e jx0e jx2 jx1 jx0 1 0 1 0 seljx
[AK7754] ms1138-e-01-pb - 4 - 2012/03 dsp block diagram cp0,cp1 cram 2048w x 16-bit dp0,dp1 dram 512w x 24-bit mpx16 mpx20 ofreg 32w x 12-bit x y multiply 16 x 20 serial i/f cbus(16-bit) dbus(24-bit) 36-bit 24-bit 40-bit 40-bit 40-bit dlram 3072w x 24-bit ptmp(lifo) 6 x 24-bit dlp0,dlp1 2 x 24,20,16-bit 2 x 24,20,16-bit din1 di n2 (src) 2 x 24,20,16-bit 2 x 24,20,16-bit 40-bit dout1 tmp 12 x 24-bit 2 x 24,20,16-bit 2 x 24,16-bit din3 (adc) dout2 dout3 (dac) 512w x 24-bit 2048w x 12-bit
[AK7754] ms1138-e-01-pb 5 2012/03 ordering guide AK7754en -20 +85 c 48pin qfn (0.5mm pitch) akd7754 evaluation board for AK7754 pin layout (tbd) AK7754en top view lflt test1 xto xt i dvdd vss1 dvdd1 8 1 2 3 4 5 8 bick1/jx1 10 bick o 7 11 6 12 9 outr/outn hpl hpr hvdd hvcom vss3 srcl flt dvdd test2 36 35 34 33 32 29 27 30 26 31 25 28 vss2 init rstn sto sda scl cad0 cad1 lrc k2/jx0 bick2/jx1 rdy/sdoutm rdy sdin2/jx2 sdout2 sdout1 clko 24 23 22 21 2 0 19 18 17 16 1 5 14 1 3 37 38 39 4 0 41 42 43 44 45 46 47 48 vss4 vcom mprf mpwr in1r/in2p in1l/in1p outl/outp a vdd in2r/in2n in2l/in 1n in3r/dmdat in3l/dmclk sd in1/jx2 lrc k1/jx 0 lrcko
[AK7754] ms1138-e-01-pb 6 2012/03 no. name i/o function classification 1 lflt o pll rc component connect pin connect a capacitor and resistor b etween this pin and vss4. this pin outputs ?l? during initial reset. analog output 2 test1 i test1 pin (internal pull-down) this pin must be connected to vss1. test 3 xto o crystal oscillator output pin when a crystal oscillator is used, co nnect it between xti and xto. when an external clock is used, leave this pin open. during initial reset, the output of this pin is hi-z. 4 xti i crystal oscillator input pin/ master clock input connect a crystal oscillator between this pin and the xto pin, or input an external clock to the xti pin. when ckm[2:0] bits= 0h, 1h, 2h, input ?l? to this pin. system clcok 5 dvdd - power supply for digital section 3.0v ~ 3.6v 6 vss1 - ground pin 0v 7 dvdd18 - digital power supply pin 1.7v~1.9v digital power supply jx2 i conditional jump pin2 (jx2e bit = ?1?) conditional input 8 sdin1 i serial data input pin1 data i/f jx1 i conditional jump pin1 (jx2e bit = ?1?) conditional input 9 bick1 i serial bit clock input pin1 data i/f jx0 conditional jump pin0 (jx2e bit = ?1?) conditional input 10 lrck1 i lr channel select clock pin1 data i/f 11 bicko o serial bit clock output pin (bickoe bit = ?1?) outputs ?l? during initial reset in master mode. system clock output 12 lrcko o lr channel select clock pin (lrckoe bit = ?1?) outputs ?l? during initial reset in master mode. system clock output 13 clko o clock output pin (clkoe bit = ?1?) outputs ?l? during initial reset in master mode. system 14 sdout1 o serial data output pin1 outputs ?l? during initial reset in master mode. data i/f 15 sdout2 o serial data output pin2 outputs ?l? during initial reset in master mode. data i/f jx2 i conditional jump pin2 (jx2e bit = ?1?) conditional input 16 sdin2 i serial data input pin2 data i/f jx1 i conditional jump pin1 (jx2e bit = ?1?) conditional input 17 bick2 i serial bit clock input pin2 (for src) data i/f pin function
[AK7754] ms1138-e-01-pb 7 2012/03 no. name i/o function classification jx0 i conditional jump pin0 (jx0e bit = ?1?) a conditional jump pin (jx0) is availa ble by setting control register (jx0e) to ?1? when scksek bit = ?1?. conditional input 18 lrck2 i lr channel select clock pin2 (for src) data i/f 19 cad1 i i 2 c bus address pin1 20 cad0 i i 2 c bus address pin0 21 scl i i 2 c bus interface 22 sda i/o i 2 c bus clock outputs ?hi-z? during initial reset. i2c 23 rdy o data write ready output pin for microprocessor interface microprocessor i/f rdy o data write ready output pin for microprocessor interface (selm bit= ?0?) 24 sdoutm o serial data monitering selector output pin (selm bit= ?0?) outputs ?l? during initial reset. microprocessor i/f 25 sto o status output pin outputs ?h? during initial reset. status 26 initrstn i initial reset pin use to initialize the AK7754. this pin must be ?l? when power up the AK7754. reset 27 test2 i test2 pin this pin must be connected to dvdd. test 28 dvdd - power supply for digital section 3.0v ~ 3.6v digital power supply 29 vss2 - ground pin 0v digital power supply 30 srclflt o src, pll rc component connect pin connect a 1 f capacitor between this pin and vss2. this pin outputs ?l? during initial reset. analog output 31 vss3 - ground pin 0v analog power supply 32 hvcom o headphone common voltage output pin connect a of 1 f cap to vss3. do not use for an outside circuits. outputs ?l? during initial reset. headphone 33 hvdd - headphone power supply pin 3.0v~3.6v analog power supply 34 hpr o headphone rch output pin outputs ?l? during initial reset analog output 35 hpl o headphone lch output pin outputs ?l? during initial reset analog output outr o dac rch output pin (lodif bit= ?0?) outputs ?l? during initial reset 36 outn o inverted line output pin (lodif bit= ?1?) outputs ?l? during initial reset analog output outl o dac lch output pin (lodif bit= ?0?) outputs ?l? during initial reset 37 outp o dac non-inverted differential analog output pin (lodif bit= ?1?) outputs ?l? during initial reset analog output 38 avdd - analog power supply pin 3.0v~3.6v analog power supply
[AK7754] ms1138-e-01-pb 8 2012/03 no. name i/o function classification 39 vss4 - ground pin 0v analog power supply 40 vcom o analog common voltage connect 0.1 f and 2.2 f capacitors in parallel to vss4. never to use for an external circuit. outputs ?l? during initial reset analog output 41 mprf o ripple filter pin for microphone power supply connect a 1uf capacitor betw een this pin and vss4. analog output 42 mpwr o power supply pin for microphone outputs ?hi-z? during initial reset analog output in1r i rch single-end input pin1 (mdifr bit = ?0?) 43 in2p i mic differential non-inverted input pin2 (mdifr bit = ?1?) analog input in1l i lch single-end input pin1 (mdifl bit = ?0?) 44 in1p i mic differential non-in verted input pin1 (mdifl bit = ?1?) analog input in2r i rch single-end input pin2 (mdifr bit = ?0?) 45 in2n i mic differential inverted input pin2 (mdifr bit = ?1?) analog input in2l i lch single-end input pin2 (mdifl bit = ?0?) 46 in1n i mic differential inverted input pin1 (mdifl bit = ?1?) analog input in3r i rch single-end input pin3 (dmic bit = ?0?) analog input 47 dmdat i digital microphone data input pin (dmic bit = ?1?) digital microphone in3l i lch single-end input pin3 (dmic bit = ?0?) analog input 48 dmclk o digital microphone clock pin (dmic bit = ?1?) digital microphone note: do not leave digital input pins open. handling of unused pin the following table illustrates recommended states for open pins: classification pin name setting analog in1l/in1p,in1r/in2p,in2l/in1n,in2r/in2n,in3l,in3r leave open clko, bicko, lrcko, sdout1-2, sdoutm, sto, soutm/rdy,xto leave open digital sdin1, sdin2, bick1, bick2, lr ck1, lrck2, xti connect to vss1
[AK7754] ms1138-e-01-pb 9 2012/03 (vss1=vss2=vss3=vss4= 0v: note 1 ) parameter symbol min max unit power supply voltage (avdd=dvdd) analog analog digital digital difference(vss1~4) avdd hvdd dvdd dvdd18 gnd -0.3 -0.3 -0.3 -0.3 -0.3 4.3 4.3 4.3 2.5 0.3 v v v v v input current (except for power supply pin) iin ? 10 ma analog input voltage ( note 2 ) vina -0.3 (avdd+0.3) or 4.3 v digital input voltage ( note 3 ) vind1 -0.3 (dvdd+0.3) or 4.3 v operating ambient temperature ta -20 85 oc storage temperature tstg -65 150 oc note 1. all indicated voltages are with respect to ground. note 2. vss1-5 must be connected to the same ground plane. note 3. the maximum digital input voltage is smaller value between (dvdd+0.3)v and 4.3v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. (vss1=vss2=vss3=vss4=0v: note 1 ) parameter symbol min typ max unit power supply voltage analog analog digital digital avdd hvdd dvdd dvdd18 3.0 3.0 3.0 1.7 3.3 3.3 3.3 1.8 3.6 3.6 3.6 1.9 v v v v hvdd-avdd hvdd-dvdd avdd-dvdd vdd1 vdd2 vdd3 -0.3 -0.3 -0.3 0 0 0 +0.3 +0.3 +0.3 v v v note 4. the power supply sequence for avdd, hvdd, dvdd and dvdd18 is not critical but all power supplies must be on before start operating the AK7754. note 5. do not turn off the power supply of the AK7754 with the power supply of the surrounding device turned on. dvdd must not exceed the pull-up of sda and scl of i2 c bus. (the diode exists for dvdd in the sda and scl pins.) warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet. absolute maximum ratings recommended operating conditions
[AK7754] ms1138-e-01-pb 10 2012/03 analog characteristics (codec) adc characteristics (ta=25oc; avdd=dvdd=hvdd=3.3v, dvdd18=1.8v; vss1=vss2=vss3=vss4=0v; bick1=64fs; signal frequency 1khz; measurement frequency =20hz~20khz, fs=48khz, pmsrc=pmhpl=pmhpr bits=?0?, ckm mode 6 (ckm[2:0]=6h) unless otherwise specified.) parameter min typ max unit mic/linein amplifier: in1l,in1r,in2l,in2r,in3l,in3r pins input resistance 22.5 30 37.5 k gain max (mgnl/r2-0, linl/r2-0 bits = ?0h?) - 0 - db min (mgnl/r2-0, linl/r2-0 bits = ?7h?) - +27 - db bypass amplifier: in1l,in1r,in2l,in2r,in3l,in3r pins (mgnl/r2-0 = 0h, linl/r2-0 = 0h) gain max (bpgl/r2-0 bit = ?0h?) - 0 - db min (bpgl/r2-0 bit = ?7h?) - -21 - db mic power supply: mpwr pin output voltage ( note 6 ) 2.18 2.3 2.4 v output current - - 4 ma resolution 24 bits dynamic characteristics in1l/in1r, in2l/in2r, in3l/in3r pins stereo adc sdout1/2/m (voladl/r=30h(0db) ( note 12 ) 70 77 db s/(n+d) (-1dbfs) ( note 13 ) 74 82 db ( note 12 ) 74 82 db dynamic range (a-weight) ( note 13 ) 81 89 db ( note 12 ) 74 82 db s/n (a-weight) ( note 13 ) 81 89 db inter-channel isolation (fin=1khz) ( note 7 ) ( note 13 ) 90 105 db dc accuracy channel gain mismatch 0.0 0.3 db analog input ( note 12 ) 0.098 vpp input voltage differential ( note 8 , note 10 ) ( note 13 ) 1.0 1.1 1.2 ( note 12 ) 0.196 vpp stereo adc input voltage single-ended ( note 9 , note 11 ) ( note 13 ) 2.0 2.2 2.4 note 6. the output voltage is proportional to avdd. vout=0.76 x avdd (typ.) note 7. inter-channel isolation between in1-3l and in1-3r pins when ?1db fs signal is input. note 8. the input voltage is proportional to avdd. vin=0.030 x avdd ( typ.)@mgnl2-0=mgnr2-0 bits = ?5h?(+21db), vin=0.33 x avdd (typ.) @mgnl2-0=mgnr2-0 bits = ?0h?(+0db) note 9. the input voltage is proportional to avdd. vin=0.059 x avdd ( typ.)@mgnl2-0=mgnr2-0 bits = ?5h?(+21db), vin=0.67 x avdd (typ.) @mgnl2-0=mgnr2-0 bits = ?0h?(+0db) note 10. in1p, in1n, in2p and in2n pins note 11. in1l, in1r, in2l, in2r, in3l and in3r pins note 12. mgnl2-0=mgnr2-0 bits = ?5h? (+21db) note 13. mgnl2-0=mgnr2-0 bits = ?0h? (+0db)
[AK7754] ms1138-e-01-pb 11 2012/03 dac characteristics (ta=25oc; avdd=dvdd=hvdd=3.3v, dvdd18=1.8v; vss1=vss2=vss3=vss4=0v; bick1=64fs; signal frequency 1khz; measurement frequency=20hz~20khz, fs =48khz, pmsrc=pmhpl=pmhpr bits = ?0?, ckm mode 6 (ckm[2:0]=6h, unless otherwise specified.) parameter min typ max unit resolution 24 bits dynamic characteristics; stereo dac outl/r pins voldal/r=18h(0db) lodif=?0? s/(n+d) (0dbfs) 80 91 db dynamic range (a-weight) 88 96 db s/n (a-weight) 88 96 db inter-channel isolation (fin=1khz) ( note 14 ) 90 110 db dc accuracy channel gain mismatch 0.0 0.5 db analog volume characteristics min 0.0 db gain amount max 28.0 db step width 2.0 db analog output single-end 2.06 2.17 2.28 vpp output voltage ( note 15 ) differential 2.06 2.17 2.28 vpp load resistance 10 k ? stereo dac load capacitance 30 pf note 14. inter-channel isolation between lch and rch of the dac. note 15. full scale output voltage. the output voltage is proportional to avdd. vout=0.67 x avdd (typ.)
[AK7754] ms1138-e-01-pb 12 2012/03 analog characteristics (hp-amp) (ta=25oc; avdd=hvdd=dvdd=3.3v; dvdd18=1.8v; vss1=vss2=vss3=vss4=0v; signal frequency 1khz; measurement frequency=20hz~20kh z@48khz; pmsrc bit=?0?), r l =16 ; circuit external capacitance: c1=c2=open. ckm mode6, unless otherwise specified.) parameter min typ max unit analog volume characteristics max (hpgl,hpgr[4:0] bits= ?1fh?) - +0 - db gain min (hpgl,hpgr[4:0] bits= ?01h?) - -50 - db step width 0.1 1 - db 0.1 2 - db +0db -16db -16db -38db -38db -50db - 4 - db headphone-amp characteristics: dac hpl/hpr pins, rl=16 ( note 16 ) output voltage 1.68 1.87 2.06 vpp s/(n+d) (-3dbfs) 60 70 - db s/n (a-weighted) 83 89 - db inter channel isolation 60 75 - db inter channel gain mismatch - 0.0 1.0 db load resistance (rl, figure 2 ) 16 - - load capacitance (c1, figure 2 ) - - 30 pf load capacitance (c2, figure 2 ) - - 300 pf note 16. because of an asynchronous ci rcuit operation, the charact eristic may deteriorate when src is in operation. figure 2. headphone amp output circuit ? + + c1 c2 rl 10 ? 0.22 f 47 f hpl pin hpr pin hp-amp measurement point
[AK7754] ms1138-e-01-pb 13 2012/03 (ta=25 c; avdd=hvdd=dvdd=3.3v; dvdd18=1.8v; vss1=v ss2=vss3=vss4=0v; signal frequency 1khz; measurement frequency= 20hz~fso/2) parameter symbol min typ max unit resolution 24 bits input sample rate fsi 8 96 khz output sample rate fso 8 48 khz thd+n (input= 1khz, 0dbfs) fso/fsi=44.1khz/48khz fso/fsi=44.1khz/96khz fso/fsi=48khz/44.1khz fso/fsi=48khz/96khz fso/fsi=48khz/8khz fso/fsi=16khz/48khz fso/fsi=16khz/44.1khz fso/fsi=8khz/48khz fso/fsi=8khz/44.1khz -111 -104 -111 -111 -111 -111 -104 -111 -78 -103 db db db db db db db db db dynamic range (input= 1khz, -60dbfs) fso/fsi=44.1khz/48khz fso/fsi=44.1khz/96khz fso/fsi=48khz/44.1khz fso/fsi=48khz/96khz fso/fsi=48khz/8khz fso/fsi=16khz/48khz fso/fsi=16khz/44.1khz fso/fsi=8khz/48khz fso/fsi=8khz/44.1khz dynamic range (input= 1khz, -60dbfs, a-weighted) fso/fsi=44.1khz/48khz 108 112 112 112 112 112 112 112 112 112 115 db db db db db db db db db db ratio between input and output sample rate fso/fsi 0.167 6 - src characteristics
[AK7754] ms1138-e-01-pb 14 2012/03 (ta=-20oc~85oc; avdd= hvdd= 3.0v~3.6v; dvdd18=1.8v; vss1=vss2=vss3=vss4=0v) parameter symbol min typ max unit high level input voltage ( note 17 ) vih 80%dvdd v low level input voltage ( note 17 ) vil 20%dvdd v scl, sda high level input voltage vih 70%dvdd v scl, sda low level input voltage vil 30%dvdd v dmdat high level input voltage vih 65%dvdd v dmdat low level input voltage vil 35%dvdd v high level output voltage: iout=-100 a ( note 18 ) voh dvdd-0.4 v low level output voltage: iout=100 a ( note 18 ) vol 0.4 v sda low level output voltage iout=3ma vol 0.4 v input leak current ( note 19 ) input leak current test1/2 pin ( note 20 ) input leak current xti pin iin iid iix 22 26 10 a a a note 17. except for the scl, sda pin. note 18. except for the sda pi n. the dmclk pin is included. note 19. except for the test2 pin, test1 pin and xti pin. note 20. the test1 pin has an internal pull-down device, nominally 150k ? . (ta=-20oc ~ 85oc; avdd=hvdd=dvdd=3.3v; dvdd18=1.8v; vss1=vss2=vss3=vss4=0v, fin=1 khz, 24 bit, fs=48khz, bick1=64fs (ckm mode=4, bitfs mode=0), codec (full-duplex mode, no output loads) and dsp running with programmed that connects dsp din3 with dout1 and din1 with dout3. parameter min typ max unit power supplies: ( note 21 ) power-up (irstn pin = ?h?) codec + dsp + lineout + hp all circuit power-up avdd+dvdd 21 - ma hvdd 4.8 ma dvdd18 avdd=dvdd=hvdd=3.3v, dvdd18=1.8v 29 - ma power consumption 137 mw avdd+dvdd 22 38 ma hvdd 5.0 7.5 ma dvdd18 avdd=dvdd=hvdd=3.6v, dvdd18=1.9v 31 70 ma reset (irstn pin = ?l?), reset condition ( note 22 ) avdd+dvdd+hvdd - 1 10 a dvdd18 3 200 a note 21. the actual power consumption of dvdd18 depends on the master clock frequency and the step size of the dsp program. (bitfs bit = ?2h? and dsps bit = ?0?) note 22. all digital input pins must be fixed to logic high /low. dc characteristics power consumption
[AK7754] ms1138-e-01-pb 15 2012/03 adc block 1. fs=8khz (ta=-20oc~85oc, avdd= hvdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v, vss1=vss2=vss3=vss4=0v; fs=8 khz; note 23 ) parameter symbol min typ max unit passband (0.1db) ( note 24 ) (-1.0db) (-3.0db) pb 0 3.63 3.83 3.15 khz khz khz stopband sb 4.66 khz passband ripple ( note 24 ) pr 0.1 db stopband attenuation ( note 25 , note 26 ) sa 68 db group delay distortion gd 0 s group deley (ts=1/fs) gd 16 ts note 23. frequencies of each amplitude ch aracteristics are in proportion to fs (sam pling rate). the characteristic of the high pass filter is not included. note 24. the passband is from dc to 3.15khz when fs=8khz. note 25. the stopband is 4.66khz to 507.34khz when fs=8khz. note 26. when fs = 8khz, the analog modulator samples the input signal at 512khz. 2. fs=48khz (ta=-20oc~85oc, avdd=hvdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v, vss1=vss2=vss3=vss4=0v; fs=48 khz; note 27 ) parameter symbol min typ max unit passband (0.1db) ( note 28 ) (-0.2db) (-3.0db) pb 0 20.0 23.0 18.9 khz khz khz stopband sb 28.0 khz passband ripple ( note 28 ) pr 0.04 db stopband attenuation ( note 29 , note 30 ) sa 68 db group delay distortion gd 0 s group delay (ts=1/fs) gd 16 ts note 27. frequencies of each amplitude characteris tics are in proportion to fs (sampling rate). note 28. the passband is from dc to 18.9khz when fs=48khz. note 29. the stopband is 28khz to 3.044mhz when fs=48khz. note 30. when fs = 48khz, the analog modulat or samples the input signal at 3.07mhz. digital filter characteristics
[AK7754] ms1138-e-01-pb 16 2012/03 dac block 1. fs=8khz (ta=-20oc ~ 85oc, avdd=hvdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v; vss1=vss2 = vss3=vss4=0v; fs=48khz; dem1-0 bits= ?0?, fs=8khz; note 27 ) parameter symbol min typ max unit passband (0.05db) ( note 31 ) (-6.0db) pb 0 4 3.62 khz khz stopband ( note 31) sb 4.37 khz passband ripple pr 0.01 db stopband attenuation (ts=1/fs) ( note 32) sa 64 db group delay gd 24 ts digital filter + analog filter amplitude characteristic 20hz~3.5khz 0.5 db 2. fs=48khz (ta=-20oc ~ 85oc, avdd=hvdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v; vss1=vss2=vss3=vss4=0v; fs=48khz; dem1-0 bits= ?0?, fs=48khz; note 27 ) parameter symbol min typ max unit digital filter passband (0.05db) ( note 31 ) (-6.0db) pb 0 - 24.0 21.7 - khz khz stopband ( note 31 ) sb 26.2 khz passband ripple pr 0.01 db stopband attenuation sa 64 db group delay (ts=1/fs) ( note 32 ) gd - 24 ts digital filter + analog filter amplitude characteristic 0~20.0khz 0.5 db note 31. pass band and stop band parameter is related to sampling frequency(fs). pb=0.4535fs (at-0.05db), sb=0.5465fs. note 32. the digital filter?s delay is calculated as the time from setting 24-bit data into the input register until an analog signal is output.
[AK7754] ms1138-e-01-pb 17 2012/03 system clock (ta= -20oc ~ 85oc, avdd=hvdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v, vss1=vss2=vss3=vss4=0v, cl=20pf) parameter symbol min typ max unit xti ckm[2:0]bits=4h-7h a) with a crystal oscillator: ckm[2:0]bits=6h fxti 11.2896 12.288 mhz ckm[2:0]bits=7h fxti 16.9344 18.432 mhz b) with an external clock duty cycle 40 50 60 % ckm[2:0]bits=4h,6h fxti 11.0 11.2896 12.288 12.4 mhz ckm[2:0]bits=5h,7h fxti 16.5 16.9344 18.432 18.6 mhz lrck1 frequency @scksel bit=0 ( note 33 ) fs 8 48 khz bick1 frequency @scksel bit=0 ( note 34 ) high level width low level width tbclkh tbclkl 64 64 ns ns frequency fbclk 0.23 3.072 3.1 mhz lrck2 frequency @scksel bit=1 ( note 35 ) fs 8 48 khz bick2 frequency @scksel bit=1 ( note 36 ) high level width low level width tbclkh tbclkl 64 64 ns ns frequency fbclk 0.23 3.072 3.1 mhz note 33. input lrck1 frequency is the same as sampling rate (fs). note 34. when biclk1 is used as a master clock refe rence clock, it should be synchronized with lrck1. note 35. input lrck2 frequency is the same as sampling rate (fs). note 36. when biclk2 is used as a master clock refe rence clock, it should be synchronized with lrck2. src input clock (ta= -20oc ~ 85oc, avdd=hvdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v, vss1=vss2=vss3=vss4=0v, @scksel bit =?0?) parameter symbol min typ max unit lrclki2 frequency fs 8 96 khz bitclki2 frequency frequency fbclk 0.23 3.072 6.2 mhz high level width tbclkh 32 ns low level width tbclkl 32 ns switching characteristics
[AK7754] ms1138-e-01-pb 18 2012/03 reset (ta= -20 oc ~ 85 oc, avdd=hvdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1=vss2=vss3=vss4=0v) parameter symbol min typ max unit initrstn ( note 37 ) trst 600 ns note 37. the initrstn pin should be ?l? when power up the AK7754. audio interface 1) sdin1/2, sdout1/2/m (ta= -20oc ~ 85oc, avdd=hvdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v, vss1=vss2=vss3=vss4=0v, cl=20pf) parameter symbol min typ max unit dsp section input sdin1/2 delay time from biclk1 ? ? to lrclk1 scksel bit= ?0? ( note 38 ) tblrd 20 ns delay time from lrclk1 to bitclk1 ? ? scksel bit= ?0? ( note 39 ) tlrbd 20 ns delay time from biclk2 ? ? to lrclk2 scksel bit= ?1? ( note 38 ) tblrd 20 ns delay time from lrclk2 to bitclk2 ? ? scksel bit= ?1? ( note 39 ) tlrbd 20 ns serial data input latch setup time tbsids 80 ns serial data input latch hold time tbsidh 80 ns src section input sdin2 (scksel bit= ?1?) delay time from biclk2 ? ? to lrclk2 ( note 39 ) tblrd 20 ns delay time from lrclk2 to bitclk2 ? ? ( note 39 ) tlrbd 20 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns output sdout1, sdout2, sdoutm delay time from lrclk1 to serial data output ( note 40 ) tlrd 80 ns delay time from bick1 ? ? to serial data output ( note 41 ) tbsod 80 ns delay time from lrcko to serial data output ( note 40 ) tlrd 80 ns delay time from bicko to serial data output ( note 42 ) tbsod 80 ns sdin1/2 sdout1/2 ( note 43 ) delay time from sdin1/2 to sdout1/2 output tiod 60 ns note 38. bitclki1 edge must not occur at the same time as lrclki1 edge. note 39. bitclki2 edge must not occur at the same time as lrclki2 edge. note 40. except i 2 s. note 41. when bick1 polarity is reversed, delay time is from bick1 ? ?. note 42. when bick2 polarity is reversed, delay time is from bick2 ? ?. note 43. sdin1 sdout1: seldo1[1:0] bits= ?1h?, out1e bit= ?1? sdin2 sdout2: seldo2[1:0] bits= ?1h?, out2e bit= ?1?
[AK7754] ms1138-e-01-pb 19 2012/03 digital microphone (dmic) switching characteristics (ta= -20 ? c ~85 ? c; avdd=hvdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v, vss1= vss2= vss3= vss4= 0v, cl=100pf) parameter symbol min typ max unit dmdat dmdat setup time tdmds 50 ns dmdat hold time tdmdh 0 ns dmclk frequency fdmck 0.5 64fs 3.1 mhz duty cycle ddmck 40 50 60 % rise time tdmckr 10 ns fall time tdmckf 10 ns note 44. clock frequency is depend on the sampling rate (fs) which is set by ckm[1:0] or dfs[1:0] bits. i 2 c bus interface (ta= -20oc ~ 85oc; avdd=hvdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v, vss1=vss2=vss3=vss4=0v; cl=20pf) parameter symbol min typ max unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated start condition tsu:sta 0.6 s sda hold time from scl falling thd:dat 0 0.9 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 45. i 2 c-bus is a trademark of nxp b.v.
[AK7754] ms1138-e-01-pb 20 2012/03 timing diagram 1/fxti 1/fxti vih1 vil1 xti 1/fs 1/fs vih1 vil1 lrck1 tbclkl tbclkh 1/fbclk 1/fbclk vih1 vil1 bick1 tbclk=1/fbclk txti=1/fxti ts =1 / f s lrck2 bick2 figure 3. system clock figure 4. reset note 46. the initrstn pin must be ?l? when power-up/power-down the AK7754. vil1 trst initrstn
[AK7754] ms1138-e-01-pb 21 2012/03 audio interface tbsids tblrd t lrbd vih1 lrck1/2 bick1/2 vil1 vih1 vil1 vih1 vil1 tbsidh sdin1/2 figure 5. audio interface (dsp section slave mode input) tbsids tblrd t lrbd vih1 lrck2 bick2 vil1 vih1 vil1 vih1 vil1 tbsidh sdin2 figure 6. audio interface (src section input) tlrd vih1 lrck1/2 bick1/2 vil1 vih1 vil1 sdout1/2/m tbso d tlrd tbsod 50%dvdd figure 7. audio interface (slave mode output)
[AK7754] ms1138-e-01-pb 22 2012/03 figure 8. audio interface (master mode input) figure 9. audio interface (master mode output) tbsids tmbl tmbl 50%dvdd lrcko bicko vih1 vil1 tbsidh 50%dvdd tlrd 50%dvdd lrcko bicko sdout1/2/m 50%dvdd tbsod tlrd tbsod 50%dvdd
[AK7754] ms1138-e-01-pb - 23 - 2012/03 digital microphone interface input interface tdmck 65%dvdd dmclk 35%dvdd td mck l 50%dvdd fdmck = 1/tdmck ddmck = 100 x tdmkl / tdmck tdmckr tsfall figure 10. dmclk clock timing dmclk 50%dvdd dmdat tdmds vih3 vil3 tdmdh figure 11. audio interface timing, dclkp bit = ?1?) dmclk 50%dvdd dmdat tdmds vih3 vil3 td mdh figure 12. audio interface timing, dclkp bit = ?0?) i 2 c bus interface figure 13. i 2 c bus interface thigh scl sda vih tlow tbuf thd:sta t r tf thd:da t tsu:da t tsu:sta sto p start start sto p tsu:sto vil vih vil tsp
[AK7754] ms1138-e-01-pb - 24 - 2012/03 package 48pin qfn (unit: mm) c0.60max c b 0.08 c a 0.400.10 +0.07 -0.05 0.20 0.02 +0.03 -0.02 7.000.10 6.750.10 7.000.10 6.750.10 0.23 m 0.10 a b 5.1 5.1 0.50 0.85 +0.15 -0.05 note: the exposed pad on the bottom surface of the package must be open or connected to the ground. materials and lead specification package: epoxy, halogen (bromine and chlorine) free lead frame: copper lead-finish: soldering (pb free) plate
[AK7754] ms1138-e-01-pb - 25 - 2012/03 marking a km AK7754en xxxxxxx 1 48 xxxxxxx: date code identifier (7 digits) date (y/m/d) revision reason page contents 10/06/01 00 first edition 12/03/23 01 error correction 8 pin function in2p (no. 43): mic differential inverted input pin2 mic differential non-inverted input pin2 in2n (no. 45): mic differential non-inverted input pin2 mic differential inverted input pin2 revision history
[AK7754] ms1138-e-01-pb - 26 - 2012/03 important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, appli cation circuits, software and other related information contained in this document are provided only to illustrate the operation and application exam ples of the semiconductor produc ts. you are fully responsible for the incorporation of these external circuits, application ci rcuits, software and other rela ted information in the design of your equipments. akm assumes no responsibility for any losses in curred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor authorized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to func tion or perform may reasonably be expected to r esult, whether directly or indirectly, in the loss of th e safety or effectiveness of the device or system conta ining it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designe d or intended for life support or maintenance of safety or for applications in medici ne, aerospace, nuclear energy, or other fields, in which its failure to fun ction or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm pr oducts, who distributes, dispos es of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility an d liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. thank you for your access to akm products information. more detail product inform ation is available, pl ease contact our sales office or authorized distributors.

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