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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9283 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 8-bit, 50 msps/80 msps/100 msps 3 v a/d converter functional block diagram ref timing v d pwrdwn v dd a in gnd ref out ref in adc output staging encode ad9283 8 d7?0 t/h a in features 8-bit, 50, 80, and 100 msps adc low power: 90 mw at 100 msps on-chip reference and track/hold 475 mhz analog bandwidth snr = 46.5 db @ 41 mhz at 100 msps 1 v p-p analog input range single 3.0 v supply operation (2.7 vC3.6 v) power-down mode: 4.2 mw applications battery powered instruments hand-held scopemeters low cost digital oscilloscopes general description the ad9283 is an 8-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is opti- mized for low cost, low power, small size and ease of use. the product operates at a 100 msps conversion rate, with outstand- ing dynamic performance over its full operating range. the adc requires only a single 3.0 v (2.7 v to 3.6 v) power supply and an encode clock for full performance operation. no external reference or driver components are required for many applications. the digital outputs are ttl/cmos compatible and a separate output power supply pin supports interfacing with 3.3 v or 2.5 v logic. the encoder input is ttl/cmos compatible. a power-down function may be exercised to bring total consumption to 4.2 mw. in power-down mode, the digital outputs are driven to a high impedance state. fabricated on an advanced cmos process, the ad9283 is available in a 20-lead surface mount plastic package (ssop) specif ied o ver the industrial temperature range (?0 c to +85 c).
C2C rev. c ad9283?pecifications (v dd = 3.0 v, v d = 3.0 v; single-ended input; ext ernal reference, unless o therwise noted) test ad9283brs-100 ad9283brs-80 ad9283brs-50 parameter temp level min typ max min typ max min typ max unit resolution 8 8 8 bits dc accuracy differential nonlinearity 25 ci 0.5 +1.25 0.5 +1.25 0.5 +1.25 lsb full vi +1.50 +1.50 +1.50 lsb integral nonlinearity 25 c i ?.25 0.75 +1.25 ?.25 0.75 +1.25 ?.25 0.75 +1.25 lsb full vi +2.25 +1.50 +1.50 lsb no missing codes full vi guaranteed guaranteed guaranteed gain error 1 25 ci 6 2.5 +6 6 2.5 +6 6 2.5 +6 % fs full vi ? +8 ? +8 ? +8 % fs gain tempco 1 full vi 80 80 80 ppm/ c analog input input voltage range (with respect to a in ) full v 512 512 512 mv p-p common-mode voltage full v 200 200 200 mv input offset voltage 25 c i ?5 10 +35 ?5 10 +35 ?5 10 +35 mv full vi 40 40 40 mv reference voltage full vi 1.2 1.25 1.3 1.2 1.25 1.3 1.2 1.25 1.3 v reference tempco full vi 130 130 130 ppm/ c input resistance 25 c i 7 10 13 7 10 13 7 10 13 k ? full vi 5 16 5 16 5 16 k ? input capacitance 25 cv 2 2 2 pf full vi a analog bandwidth, full power 25 c v 475 475 475 mhz switching performance maximum conversion rate full vi 100 80 50 msps minimum conversion rate 25 civ111msps encode pulsewidth high (t eh )25 c iv 4.3 1000 5.0 1000 8.0 1000 ns encode pulsewidth low (t el )25 c iv 4.3 1000 5.0 1000 8.0 1000 ns aperture delay (t a )25 cv 0 0 0 ns aperture uncertainty (jitter) 25 c v 5 5 5 ps rms output valid time (t v ) 2 full vi 2.0 3.0 2.0 3.0 2.0 3.0 ns output propagation delay (t pd ) 2 full vi 4.5 7.0 4.5 7.0 4.5 7.0 ns digital inputs logic ??voltage full vi 2.0 2.0 2.0 v logic ??voltage full vi 0.8 0.8 0.8 v logic ??current full vi 1 1 1 a logic ??current full vi 1 1 1 a input capacitance 25 c v 2.0 2.0 2.0 pf digital outputs logic ??voltage full vi 2.95 2.95 2.95 v logic ??voltage full vi 0.05 0.05 0.05 v output coding offset binary code offset binary code offset binary code power supply power dissipation 3, 4 full vi 90 120 90 115 80 100 mw power-down dissipation full vi 4.2 7 4.2 7 4.2 7 mw power supply rejection ratio (psrr) 25 c i 18 18 18 mv/v
C3C rev. c ad9283 test ad9283brs-100 ad9283brs-80 ad9283brs-50 parameter temp level min typ max min typ max min typ max unit dynamic performance 5 transient response 25 cv 2 2 2 ns overvoltage recovery time 25 cv 2 2 2 ns signal-to-noise ratio (snr) (without harmonics) f in = 10.3 mhz 25 c i 46.5 47 44 47 db f in = 27 mhz 25 c i 46.5 44 47 47 db f in = 41 mhz 25 c i 43.5 46.5 47 db f in = 76 mhz 25 c v 46.0 db signal-to-noise ratio (sinad) (with harmonics) f in = 10.3 mhz 25 c i 45 47 43.5 46.5 db f in = 27 mhz 25 c i 45.5 43.5 46.5 46 db f in = 41 mhz 25 c i 42.5 45 42 db f in = 76 mhz 25 c v 42.5 db effective number of bits f in = 10.3 mhz 25 c i 7.3 7.5 7.6 bits f in = 27 mhz 25 c i 7.4 7.5 7.5 bits f in = 41 mhz 25 c i 7.3 7.5 bits f in = 76 mhz 25 c v 6.9 bits 2nd harmonic distortion f in = 10.3 mhz 25 c i 57 60 55 60 dbc f in = 27 mhz 25 c i 60 55 60 56 dbc f in = 41 mhz 25 c i 50 58 55 dbc f in = 76 mhz 25 cv 46 dbc 3rd harmonic distortion f in = 10.3 mhz 25 c i 54.5 70 55 70 dbc f in = 27 mhz 25 c i 55 55 62.5 60 dbc f in = 41 mhz 25 c i 47 52.5 60 dbc f in = 76 mhz 25 cv 53 dbc two-tone intermod distortion (imd) f in = 10.3 mhz 25 c v 52 52 52 dbc notes 1 gain error and gain temperature coefficient are based on the adc only (with a fixed 1.25 v external reference). 2 t v and t pd are measured from the 1.5 v level of the encode input to the 50%/50% levels of the digital outputs swing. the digital output l oad during test is not to exceed an ac load of 10 pf or a dc current of 40 a. 3 power dissipation measured with encode at rated speed and a dc analog input. 4 typical thermal impedance for the rs style (ssop) 20-lead package: jc = 46 c/w, ca = 80 c/w, ja = 126 c/w. 5 snr/harmonics based on an analog input voltage of ?.7 dbfs referenced to a 1.024 v full-scale input range. specifications subject to change without notice. absolute maximum ratings * v d , v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v analog inputs . . . . . . . . . . . . . . . . . . . . ?.5 v to v d + 0.5 v digital inputs . . . . . . . . . . . . . . . . . . . ?.5 v to v dd + 0.5 v vref in . . . . . . . . . . . . . . . . . . . . . . . . ?.5 v to v d + 0.5 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . ?5 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c maximum case temperature . . . . . . . . . . . . . . . . . . . 150 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9283 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package package model ranges descriptions options ad9283brs -50, -80, -100 ?0 c to +85 c 20-lead ssop rs-20 ad9283/pcb 25 c evaluation board * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. warning! esd sensitive device
ad9283 C4C rev. c explanation of test levels test level i 100% production tested. ii 100% production tested at 25 c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characteriza- tion testing. v parameter is a typical value only. vi 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for mili- tary devices. pin configuration top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad9283 encode gnd v d vref out vref in gnd a in v d d7 (msb) d6 d5 d1 d2 d3 d4 v dd gnd pwrdwn d0 (lsb) a in pin function descriptions pin number mnemonic function 1 pwrdwn power-down function select; logic high for power-down mode (digital outputs go to high impedance state) 2 vref out internal reference output (1.25 v typ); bypass with 0.1 f to ground 3 vref in reference input for adc (1.25 v typ) 4, 9, 16 gnd ground 5, 8 v d analog 3 v power supply 6a in analog input for adc (can be left open if operating in single-ended mode, but rec- ommend connection to a 0.1 f capacitor and a 25 ? resistor in series to ground for better input matching) 7a in analog input for adc 10 encode encode clock for adc (adc samples on rising edge of encode) 11?4, 17?0 d7?4, d3?0 digital outputs of adc 15 v dd digital output power supply. nominally 2.5 v to 3.6 v table i. output coding (vref = 1.25 v) step a in ? in digital output 255 0.512 1111 1111 ? ? 128 0.002 1000 0000 127 ?.002 0111 1111 ? ? 0 ?.512 0000 0000
ad9283 C5C rev. c a in v dd a in 33.3k 14.3k 33.3k 14.3k figure 2. equivalent analog input circuit v d v bias ref in figure 3. equivalent reference input circuit encode v d figure 4. equivalent encode input circuit out v dd figure 5. equivalent digital output circuit out v d (
+ )
*
a in encode t a sample n sample n+1 sample n+2 sample n+3 sample n+4 sample n+5 1/ fs t el t eh d7 d0 data n 4 data n 3 data n 2 data n 1 data n data n+1 t pd t v figure 1. timing diagram
ad9283 C6C rev. c frequency 0 ?0 ?0 db ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 encode = 100msps a in = 10.3mhz snr = 46.5db sinad = 45db 2nd = 57dbc 3rd = 54.5dbc tpc 1. spectrum: f s = 100 msps, f in = 10.3 mhz frequency 0 10 90 db 50 60 70 80 30 40 20 encode = 100msps a in = 41mhz snr = 46.5db sinad = 45db 2nd = 58dbc 3rd = 52.5dbc tpc 2. spectrum: f s = 100 msps, f in = 40 mhz frequency 0 90 db encode = 100msps a in = 76mhz snr = 46db sinad = 42.5db 2nd = 46dbc 3rd = 53dbc 80 70 60 50 40 30 20 10 tpc 3. spectrum: f s = 100 msps, f in = 76 mhz frequency a in 10 20 30 40 50 60 80 100 70 65 db 45 40 30 55 50 60 2nd 3rd 35 encode = 100msps tpc 4. harmonic distortion vs. a in frequency frequency 0 10 90 db 50 60 70 80 30 40 20 encode = 100msps a in 1 = 9mhz a in 2 = 10mhz imd = 52dbc tpc 5. two-tone intermodulation distortion frequency 10 20 30 40 50 60 80 90 55 db 45 40 35 30 50 100 snr sinad encode = 100msps tpc 6. sinad/snr vs. a in frequency ?typical performance characteristics
ad9283 C7C rev. c encode rate 10 100 49 48 db 44 43 46 45 47 sinad a in = 10.3mhz snr 20 30 40 50 60 70 80 90 tpc 7. sinad/snr vs. encode rate encode pulsewidth high ?ns 6.5 6.0 4.5 4.0 60 50 db 10 0 30 20 40 encode = 100msps a in = 10.3mhz snr sinad 7.0 5.5 5.0 3.5 3.0 tpc 8. sinad/snr vs. encode pulsewidth high bandwidth mhz 0.5 1.0 5.5 0 600 db 100 200 300 400 500 0.0 0.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 tpc 9. adc frequency response: f s = 100 msps encode rate 10 20 30 40 50 60 70 80 120 power mw 40 20 0 80 60 100 90 100 a in = 10.3mhz
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$' temperature c 40 200 20406080 49 48 db 44 46 45 47 60 100 sinad snr tpc 11. sinad/snr vs. temperature code 1.00 0.75 lsb 0.25 0.50 0.75 1.00 0.25 0.00 0.50
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ad9283 C8C rev. c code 2.0 lsb 0.5 1.0 1.5 2.0 0.5 0.0 1.0 1.5 tpc 13. integral nonlinearity applications theory of operation the analog signal is applied differentially or single-endedly to the inputs of the ad9283. the signal is buffered and fed for- ward to an on-chip sample-and-hold circuit. the adc core architecture is a bit-per-stage pipeline type converter utilizing switch capacitor techniques. the bit-per-stage blocks determine the 5 msbs and drive a flash converter to encode the 3 lsbs. each of the 5 msb stages provides sufficient overlap and error correction to allow optimization of performance with respect to comparator accuracy. the output staging block aligns the data, carries out the error correction and feeds the data to the eight output buffers. the ad9283 includes an on-chip reference (nominally 1.25 v) and generates all clocking signals from one externally applied encode command. this makes the adc easy to interface with and requires very few external components for operation. encode input the encode input is fully ttl/cmos compatible with a nominal threshold of 1.5 v. care was taken on the chip to match clock line delays and maintain sharp clock logic transi- tions. any high speed a/d converter is extremely sensitive to the quality of the sampling clock provided by the user. this adc uses an on-chip sample-and-hold circuit which is essen- tially a mixer. any timing jitter on the encode will be com- bined with the desired signal and degrade the high frequency performance of the adc. the user is advised to give commen- surate thought to the clock source. analog input the analog input to the adc is fully differential and both inputs are internally biased. this allows the most flexible use of ac or dc and differential or single-ended input modes. for peak perform ance the inputs are biased at 0.3 v d . see the specification table for allowable common-mode range when dc coupling the input. the inputs are also buffered to reduce the load the user needs to drive. for best dynamic performance, the impedances at a in and a in should be matched. the importance of this increases with sampling rate and analog input frequency. the nominal input range is 1.024 v p-p. digital outputs the digital outputs are ttl/cmos compatible. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing to ease interfacing with 2.5 v or 3.3 v logic. the ad9283 goes into a low power state within two clock cycles following the assertion of the pwrdwn input. pwrdwn is asserted with a logic high. during power-down the outputs transition to a high impedance state. the time it takes to achieve optimal performance after disabling the power- down mode is approximately 15 clock cycles. care should be taken when loading the digital outputs of any high speed adc. large output loads create current transients on the chip that can degrade the converter? performance. voltage reference a stable and accurate 1.25 v voltage reference is built into the ad9283 (vref out). in normal operation, the internal refer- ence is used by strapping pins 2 and 3 of the ad9283 together. the input range can be adjusted by varying the reference volt- age applied to the ad9283. no degradation in performance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage changes linearly. whether used or not, the internal reference (pin 2) should be bypassed with a 0.1 f capacitor to ground. timing the ad9283 provides latched data outputs with four pipeline delays. data outputs are available one propagation delay (t pd ) after the rising edge of the encode command (figure 1. timing diagram). the minimum guaranteed conversion rate to the adc is 1 msps. the dynamic performance of the converter will degrade at encode rates below this sample rate. evaluation board the ad9283 evaluation board offers an easy way to test the ad9283. it only requires a 3 v supply, an analog input and encode clock to test the ad9283. the board is shipped with the 100 msps grade adc. the analog input to the board accepts a 1 v p-p signal centered at ground. j1 should be used (jump e3?4, e18?19) to drive the adc through transformer t1. j2 should be used for single- ended input drive (jump e19?21). both j1 and j2 are terminated to 50 ? on the pcb. each analog path is ac-coupled to an on-chip resistor divider which provides the required dc bias. a (ttl/cmos level) sample clock is applied to connector j3 which is terminated through 50 ? on the pcb. this clock is buffered by u5 which also provides the clocks for the 574 latches, dac, and the off-card latch clock clkcon. (timing can be modified at e17.) there is a reconstruction dac (ad9760) on the pcb. the dac is on the board to assist in debug only?he outputs should not be used to measure performance of the adc.
ad9283 C9C rev. c figure 7. printed circuit board top side silkscreen figure 8. printed circuit board bottom side silkscreen figure 9. printed circuit board top side copper figure 10. printed circuit board split power layer
ad9283 C10C rev. c figure 11. printed circuit board ground layer evaluation board bill of materials ?gs01717 # qty refdes device package value 1 15 c1, c4?17 ceramic cap 0603 0.1 f 2 4 c18?21 tantalum cap bcaptajd 10 f 3 24 e1?6, e8?10, e12?19, e21, e34?39 w-hole 4 4 j1, j2, j3, j5 connector smb 5 1 p1 5-pin connector wieland connector (p/n #25.602.2553.0 top p/n #z5.530.0525.0 bottom) 6 1 p2 37-pin connector amp-747462-2 7 5 r4, r9, r10, r21, r22 resistor 1206 50 ? 8 1 r7 resistor 1206 25 ? 9 1 r23 resistor 1206 2 k ? 10 1 t1 transformer mini-circuits t1-1t-kk81 11 1 u1 ad9283 ssop-20 12 1 u3 ad9760 soic-28 13 1 u4 74acq574 soic-20 14 1 u5 sn74lvc86 so14 figure 12. printed circuit board bottom side copper
ad9283 C11C rev. c 14 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 vcc q0 q1 q2 q3 q4 q5 q6 q7 clock out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd p1 12345 vdl c16 0.1 f da0 da1 da2 da3 da4 da5 da6 da7 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 clklat u4 74acq574 d0 d1 d2 d3 gnd vdd d4 d5 d6 d7 pwdn refout refin gnd va ain va1 gnd u1 ad9283 c9 0.1 f 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vd pwdn e8 e9 e10 va e1 e2 e5 e6 c5 0.1 f c1 0.1 f va c4 0.1 f e3 e4 j1 r4 50 4 5 6 3 2 1 r7 25 c8 0.1 f c7 0.1 f r9 50 j2 e18 e19 e21 c17 0.1 f e34 e35 e36 e37 e38 e39 e16 2 1 3 4 5 6 7 1b 1a 1y 2a 2b 2y gnd 4b vcc 4a 4y 3b 3a 3y 13 14 12 11 10 9 8 e17 e15 vdl u5 sn74lvc86 c13 0.1 f clklat e12 e14 e13 clkdac vdl j3 r10 50 1 2 3 4 5 6 7 8 9 15 28 27 26 25 24 23 22 21 20 19 18 17 16 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 nc1 nc2 nc3 nc4 clk dvdd dcom nc5 avdd comp2 iouta ioutb acom comp1 fsadj refio reflo sleep da7 da6 da5 da4 da3 da2 da1 da0 clkdac c15 0.1 f c10 0.1 f vdac vdac j5 r21 50 r22 50 c14 0.1 f vdac r23 2k c12 0.1 f c18 10 f va c19 10 f vd c20 10 f vdl c21 10 f vdac p2 c37drpf u3 ad9760 c11 0.1 f vdl t1 clkcon enc enc clkcon va c6 0.1 f va vd gnd vdl vdac ain figure 13. printed circuit board s chematic
ad9283 C12C rev. c c00584bC0C10/01(c) printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 20-lead shrink small outline package (ssop) (rs-20) 20 11 10 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 revision history location page data sheet changed from rev. b to rev. c. edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

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