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1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a 512kx32 5v flash module preliminary* features n access times of 60, 90ns n based on amd: am29f040b-xxec n packaging ? 68 lead, plastic plcc, 24.94 mm (0.982 inch) square n minimum 100,000 write/erase cycles n sector architecture ? 8 equal size sectors of 64kbytes each ? any combination of sectors can be concurrently erased. also supports full chip erase n organized as 512kx32 n commercial and industrial temperature ranges n 5 volt programming. 5v 10% supply n low power cmos, 500 m a standby n embedded erase and program algorithms n ttl compatible inputs and cmos outputs n page program operation and internal program control time n built-in decoupling caps for low noise operation * this data sheet describes a product under development, not fully characterized, and is subject to change without notice. fig. 1 pin configuration for wed7f325zxe5sj-c/a pin description dq 0-31 data inputs/outputs a 0-18 address inputs w write enable e 0-3 chip selects g output enable v cc power supply v ss ground nc not connected top view block diagram october 1999 rev. eco# 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dq 17 dq 18 dq 19 v ss dq 20 dq 21 dq 22 dq 23 v cc dq 24 dq 25 dq 26 dq 27 v ss dq 28 dq 29 dq 30 dq 31 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc a 13 a 12 a 11 a 10 a 9 a 8 a 7 dq 0 dq 14 dq 13 dq 12 v ss dq 11 dq 10 dq 9 dq 8 v cc dq 7 dq 6 dq 5 dq 4 v ss dq 3 dq 2 dq 1 dq 16 a 18 a 17 e 3 e 2 e 1 e 0 nc v cc nc nc g w a 16 a 15 a 14 dq 15 512k x 8 8 dq 0-7 e 0 512k x 8 8 dq 8-15 e 1 512k x 8 8 dq 16-23 e 2 512k x 8 8 dq 24-31 e 3 a 0-18 g w
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a parameter symbol conditions unit min max input leakage current i li v cc = 5.5, v in = v ss or v cc 10 m a output leakage current i lox32 v cc = 5.5, v in = v ss or v cc 10 m a v cc active current for read (1) i cc1 cs = v il , oe = v ih , f = 5mhz 170 ma v cc active current for program or erase (2) i cc2 cs = v il , oe = v ih 240 ma v cc standby current i cc4 v cc = 5.5, cs = v ih , f = 5mhz 500 m a output low voltage v o l i ol = 12.0 ma, v cc = 4.5 0.45 v output high voltage v oh1 i oh = -2.5 ma, v cc = 4.5 0.85 x v v cc low v cc lock-out voltage v lko 3.2 4.2 v dc characteristics - cmos compatible (v cc = 5.0v, v ss = 0v, t a = -40 c to +85 c) notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (@ 5 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. dc test conditions: v il = 0.3v, v ih = v cc - 0.3v recommended operating conditions parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.0 v cc + 0.5 v input low voltage v il -0.5 +0.8 v operating temp. (com) t a 0 +70 c operating temp. (ind) t a -40 +85 c a 9 voltage for sector protect v id 11.5 12.5 v capacitance (t a = +25 c) parameter symbol conditions max unit g capacitance c oe v in = 0 v, f = 1.0 mhz 35 pf w capacitance c we v in = 0 v, f = 1.0 mhz 35 pf e 0-3 capacitance c cs v in = 0 v, f = 1.0 mhz 12 pf data i/o capacitance c i/o v i/o = 0 v, f = 1.0 mhz 15 pf address input capacitance c ad v in = 0 v, f = 1.0 mhz 35 pf this parameter is guaranteed by design but not tested. absolute maximum ratings notes: 1. stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. 2. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, inputs may overshoot v ss to -2.0 v for periods of up to 20ns. maximum dc voltage on output and i/o pins is v cc + 0.5v. during voltage transitions, outputs may overshoot to vcc + 2.0 v for periods of up to 20ns. 3. minimum dc input voltage on a 9 pin is -0.5v. during voltage transitions, a 9 may overshoot vss to -2v for periods of up to 20ns. maximum dc input voltage on a 9 is +13.5v which may overshoot to 14.0 v for periods up to 20ns. 4. recommended soldering temperature not to exceed 215 c for 20 seconds. parameter unit operating temperature (com) 0 to +70 c operating temperature (ind.) -40 to +85 c supply voltage range (v cc ) -2.0 to +7.0 v signal voltage range (any pin except a9) (2) -2.0 to +7.0 v storage temperature range -55 to +125 c data retention 10 years endurance (write/erase cycles) 100,000 cycles min. a 9 voltage for sector protect (v id ) (3) -2.0 to +14.0 v
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a ac characteristics C write/erase/program operations,e controlled (v cc = 5.0v, v ss = 0v, t a = -40 c to +85 c) parameter symbol -60 -70 -90 -100 unit min max min max min max min max write cycle time t avav t wc 60 70 90 100 ns write enable setup time t wlel t ws 0000ns chip select pulse width t eleh t cp 30 35 45 50 ns address setup time t avel t as 0000ns data setup time t dveh t ds 25 30 45 45 ns data hold time t ehdx t dh 0000ns address hold time t elax t ah 40 40 45 45 ns chip select pulse width high t ehel t cph 20 20 20 20 ns duration of byte programming operation t whwh1 11 11ms sector erase time t whwh2 30 30 30 30 sec read recovery time t ghel 0000 m s chip programming time 25 25 25 25 sec chip erase time t whwh2 120 120 120 120 sec
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a ac characteristics C write/erase/program operations, we controlled (v cc = 5.0v, t a = -40 c to +85 c) ac characteristics C read only operations (v cc = 5.0v, t a = -40 c to +85 c) parameter symbol -60 -70 -90 -100 unit min max min max min max min max read cycle time t avav t rc 60 70 90 100 ns address access time t avqv t acc 60 70 90 100 ns chip select access time t elqv t ce 60 70 90 100 ns output enable to output valid t glqv t oe 25 30 35 40 ns chip select to output high z (1) t ehqz t df 18 18 20 20 ns output enable high to output high z (1) t ghqz t df 18 18 20 20 ns output hold from address, e or g change, t axqx t oh 0000ns whichever is first 1. guaranteed by design, but not tested. parameter symbol -60 -70 -90 -100 unit min max min max min max min max write cycle time t avav t wc 60 70 90 100 ns chip select setup time t elwl t cs 0000ns write enable pulse width t wlwh t wp 30 35 45 50 ns address setup time t avwh t as 0000ns data setup time t dvwh t ds 25 30 45 45 ns data hold time t whdx t dh 0000ns address hold time t whax t ah 40 40 45 45 ns write enable pulse width high t whwl t wph 20 20 20 20 ns duration of byte programming operation t whwh1 11 11ms sector erase t whwh2 30 30 30 30 sec read recovery time before write t ghwl 0000 m s v cc set-up time t vcs 50 60 80 90 m s chip programming time 50 60 80 90 sec output enable setup time t oes 0000ns output enable hold time (1) t oeh 10 10 10 10 ns chip erase time t whwh2 120 120 120 120 sec 1. for toggle and data polling.
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a fig. 2 ac waveforms for read operations addresses cs oe we outputs high z addresses stable t oe t rc output valid t ce t acc t oh high z t df e g w
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. fig. 3 write/erase/program operation, w controlled addresses cs oe we data 5.0 v 5555h pa pa t wc t cs pd d 7 d out t ah t wph t dh t ds data polling t as t rc t wp a0h t oe t df t oh t ce t ghwl t whwh1 e g w
7 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a fig. 4 ac waveforms chip/sector erase operations note: 1. sa is the sector address for sector erase. addresses cs oe we data v cc 5555h 2aaah 2aaah sa 5555h 5555h t wp t cs t vcs 10h/30h 55h 80h 55h aah aah t ah t as t ghwl t wph t dh t ds e g w
8 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a fig. 5 ac waveforms for data polling during embedded algorithm operations cs oe we t oe t ce t ch t oh d7 d7 = valid data high z d0-d6 = invalid d0-d7 valid data t df d7 d0-d6 t oeh t whwh 1 or 2 t oe data e g w
9 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a notes: 1. pa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. d 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. addresses we oe cs data 5.0 v 5555h pa pa t wc t ws pd d 7 d out t ah t cph t cp t dh t ds data polling t as t ghel a0h t whwh1 fig. 6 alternate e controlled programming operation timings w g e
10 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a package dimension: 68 lead plastic plcc 5.08 (0.200) max 1.27 (0.050) typ 23.93 (0.942) 0.25 (0.010) 25.40 (1.000) max 20.32 (0.800) max all linear dimensions are millimeters and parenthetically in inches
11 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed7f325zxe5sj-c/a operational range c = commercial 0 to +70 c a = industrial / aramid -40 to +85 c access speed 60 = 60ns 90 = 90ns package type j = surface mount 68 lead flash ram architecture s = symetrical component / voltage option 5 = amd; 5v base component width e = x8 option features x = none address density 5z = 512k data bus width 32 = x32 number of memory banks blank = single plating finish f = tin/lead flash white electronic designs corp. ordering information wed 7 f 32 5z x e 5 s j - c/a

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