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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. mos integrated circuit pd45d128442, 45d128842, 45d128164 128 m-bit synchronous dram with double data rate (4-bank, sstl_2) data sheet document no. e0030n10 (1st edition) (previous no. m13852ej3v0ds00) date published january 2001 cp (k) printed in japan elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. description the pd45d128442, 45d128842, 45d128164 are high-speed 134,217,728 bits synchronous dynamic random- access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively. the synchronous drams use double data rate (ddr) where data bandwidth is twice of regular synchronous dram. the synchronous dram is compatible with sstl_2 (stub series terminated logic for 2.5 v). the synchronous dram is packaged in 66-pin plastic tsop (ii). features ? fully synchronous dynamic ram with all input signals except dm, dqs and dq referenced to a positive clock edge ? double data rate interface differential clk (/clk) input data inputs and dm are synchronized with both edges of dqs data outputs and dqs are synchronized with a cross point of clk and /clk ? quad internal banks operation ? possible to assert random column address in every clock cycle ? programmable mode register set /cas latency (2, 2.5) burst length (2, 4, 8) wrap sequence (sequential / interleave) ? automatic precharge and controlled precharge ? cbr (auto) refresh and self refresh ? x4, x8, x16 organization ? byte write control (x4, x8) by dm ? byte write control (x16) by ldm and udm ? 2.5 v 0.2 v power supply for v dd ? 2.5 v 0.2 v power supply for v dd q ? maximum clock frequency up to 133 mhz ? sstl_2 compatible with all signals ? 4,096 refresh cycles/64 ms ? 66-pin plastic tsop (ii) (10.16 mm (400)) ? burst termination by precharge command and burst stop command
data sheet e0030n10 2 pd45d128442, 45d128842, 45d128164 ordering information part number organization (word x bit x bank) clock frequency mhz (max.) package pd45d128442g5-c75-9lg 8m x 4 x 4 133 66-pin plastic tsop (ii) pd45d128442g5-c80-9lg 125 (10.16 mm (400)) pd45d128842g5-c75-9lg 4m x 8 x 4 133 pd45d128842g5-c80-9lg 125 pd45d128164g5-c75-9lg 2m x 16 x 4 133 pd45d128164g5-c80-9lg 125
data sheet e0030n10 3 pd45d128442, 45d128842, 45d128164 part number nec memory capacity 128: 128m bits organization 4: x4 8: x8 interface 2: sstl_2 package g5: tsop (ii) v dd c: 2.5 v minimum cycle time 75: 7.5 ns (133mhz) 80: 8 ns (125mhz) data rate d: double synchrounous dram number of banks 4: 4bank [x4, x8] [x16] 164 organization 16: x16 number of banks and interface 4: 4bank, sstl_2 pd45d128 842 g5 - c80
data sheet e0030n10 4 pd45d128442, 45d128842, 45d128164 pin configurations /xxx indicates active low signal. [ pd45d128442] 66-pin plastic tsop (ii) (10.16 mm (400)) 8m word x 4 bit x 4 bank v dd nc v dd q nc dq0 v ss q nc nc v dd q nc dq1 v ss q nc nc v dd q nc nc v dd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss nc v ss q nc dq3 v dd q nc nc v ss q nc dq2 v dd q nc nc v ss q dqs nc v ref v ss dm /clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a11 : address inputs a0 - a11 : row address inputs a0 - a9, a11 : column address inputs ba0, ba1 : bank select dq0 - dq3 : data inputs/outputs dqs : data strobe clk, /clk : system clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dm : dq write mask enable v dd : supply voltage v ss : ground v dd q : supply voltage for dq and dqs v ss q : ground for dq and dqs v ref : input reference nc : no connection
data sheet e0030n10 5 pd45d128442, 45d128842, 45d128164 [ pd45d128842] 66-pin plastic tsop (ii) (10.16 mm (400)) 4m word x 8 bit x 4 bank v dd dq0 v dd q nc dq1 v ss q nc dq2 v dd q nc dq3 v ss q nc nc v dd q nc nc v dd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq7 v ss q nc dq6 v dd q nc dq5 v ss q nc dq4 v dd q nc nc v ss q dqs nc v ref v ss dm /clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a11 : address inputs a0 - a11 : row address inputs a0 - a9 : column address inputs ba0, ba1 : bank select dq0 - dq7 : data inputs/outputs dqs : data strobe clk, /clk : system clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dm : dq write mask enable v dd : supply voltage v ss : ground v dd q : supply voltage for dq and dqs v ss q : ground for dq and dqs v ref : input reference nc : no connection
data sheet e0030n10 6 pd45d128442, 45d128842, 45d128164 [ pd45d128164] 66-pin plastic tsop (ii) (10.16 mm (400)) 2m word x 16bit x 4 bank v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v dd q ldqs nc v dd nc ldm /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ss q udqs nc v ref v ss udm /clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a11 : address inputs a0 - a11 : row address inputs a0 - a8 : column address inputs ba0, ba1 : bank select dq0 - dq15 : data inputs/outputs ldqs, udqs : data strobe clk, /clk : system clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable ldm, udm : dq write mask enable v dd : supply voltage v ss : ground v dd q : supply voltage for dq, ldqs and udqs v ss q : ground for dq, ldqs and udqs v ref : input reference nc : no connection
data sheet e0030n10 7 pd45d128442, 45d128842, 45d128164 block diagram a0 - a11, ba0, ba1 /cs /ras /cas /we column decoder input & output buffer latch circuit data control circuit column decoder row decoder memory cell array bank a sense amp. bank b bank c bank d control logic column address buffer and burst counter row address buffer and refresh counter mode register clock generator dq clk /clk cke dqs dm dll clk, /clk
data sheet e0030n10 8 pd45d128442, 45d128842, 45d128164 contents 1. input/output pin function 10 2. commands 11 3. simplified state diagram 15 4. truth table 16 4.1 command truth table 16 4.2 dm truth table 16 4.3 cke truth table 16 4.4 operative command table 17 4.5 command truth table for cke 20 5. initialization 21 6. programming the mode register 22 7. mode register 23 7.1 burst length and sequence 24 8. address bits of bank-select and precharge 25 9. precharge 26 9.1 read to precharge command interval 26 9.2 write to precharge command interval 27 10. auto precharge 28 10.1 read with auto precharge 28 10.2 write with auto precharge 29 11. read/write command interval 30 11.1 read to read command interval 30 11.2 write to write command interval 31 11.3 write to read command interval 32 11.4 read to write command interval 33
data sheet e0030n10 9 pd45d128442, 45d128842, 45d128164 12. burst termination 34 12.1 burst stop command in read cycle 34 12.2 precharge termination in read cycle 35 12.3 precharge termination in write cycle 36 13. electrical specifications 37 13.1 absolute maximum ratings 37 13.2 recommended operating conditions 37 13.3 pin capacitance (ta = 25 c, f = 1 mhz) 37 13.4 dc characteristics 1 (recommended operating conditions unless otherwise noted) 38 13.5 dc characteristics 2 (recommended operating conditions unless otherwise noted) 38 13.6 ac characteristics (recommended operating conditions unless otherwise noted) 39 13.6.1 test conditions 39 13.6.2 timing diagram 40 13.6.3 synchronous characteristics 41 13.6.4 synchronous characteristics example 42 13.6.5 asynchronous characteristics 42 14. package drawing 74 15. recommended soldering conditions 75 16. revision history 76
data sheet e0030n10 10 pd45d128442, 45d128842, 45d128164 1. input/output pin function pin name input/output function clk, /clk input clk and /clk are the master clock inputs. the timing reference point for the differential clock is when clk and /clk cross. all control and address inputs except for dq and dm are latched by a rising edge of clk. by both of rising and falling edges of clk, output dq and dqs are validated. cke input cke controls power down mode. when the pd45d128xxx is not in burst mode and cke is negated, the device enters power down mode and deactivates internal clock signals, input buffers and output drivers. during power down mode, cke must remain low. /cs input /cs low starts a command input cycle. when /cs is high, commands are ignored but the current operations will be continued. /ras, /cas, /we input as well as regular sdrams, each combination of /ras, /cas, and /we input in conjunction with /cs input at a rising edge of clk determines sdram operation. refer to the command table. a0 C a11 input row address is determined by a0 - a11 at the rising edge of clk in active command cycle. it does not depend on the bit organization. column address is determined by a0 - a9, a11 at the rising edge of clk in read or write command cycle. it depends on the bit organization: a0 - a9, a11 for x4 device, a0 - a9 for x8 device, a0 - a8 for x16 device. a10 defines precharge mode. when a10 is high in precharge command cycle, all banks are precharged; when a10 is low, only the bank selected by ba0 and ba1 is precharged. when a10 is high in read or write command cycle, precharge starts automatically after the burst access. ba0, ba1 input ba0, ba1 are bank select signals. in command cycle, ba0 and ba1 low select bank a, ba0 high and ba1 low select bank b, ba0 low and ba1 high select bank c and then ba0 and ba1 high select bank d. dq0 C dq15 input/output dq pins have the same function as i/o pins on conventional drams. dqs, ldqs, udqs input/output active on the both edges for data input and output. dm, ldm, udm input dm's are latched by both of rising and falling edges of the dqs. in write mode, dm's control byte mask. unlike regular sdrams, dm's do not control read operation. v ref input v ref is reference voltage for sstl input buffers. v dd , v dd q, v ss , v ss q (power supply) v dd and v ss are power supply pins for internal circuits. v dd q and v ss q are power supply pins for the output buffers.
data sheet e0030n10 11 pd45d128442, 45d128842, 45d128164 2. commands extended mode register set command (/cs, /ras, /cas, /we low) the pd45d128xxx has an extended mode register that defines enabling or disabling dll. in this command, a0 through a11, ba0 and ba1 are the data input pins. after power on, the extended mode register set command must be executed to enabling or disabling dll. the extended mode register can be set only when all banks are in idle state. during t mrd , the pd45d128xxx can not accept any other commands. fig.1 extended mode register set command /we /cas /ras /cs cke clk h add a10 ba1 ba0 mode register set command (/cs, /ras, /cas, /we low) the pd45d128xxx has a mode register that defines how the device operates. in this command, a0 through a11, ba0 and ba1 are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when all banks are in idle state. during t mrd , the pd45d128xxx can not accept any other commands. fig.2 mode register set command /we /cas /ras /cs cke clk h add a10 ba0,ba1 bank activate command (/cs, /ras = low, /cas, /we = high) the pd45d128xxx has four banks, each with 4,096 rows. this command activates the bank and the row address selected by ba0 and ba1, and by a0 through a11 respectively. this command corresponds to a conventional dram's /ras falling. fig.3 bank activate command /we /cas /ras /cs cke clk h add a10 ba0,ba1 row row
data sheet e0030n10 12 pd45d128442, 45d128842, 45d128164 precharge command (/cs, /ras, /we= low, /cas = high) this command begins precharge operation of the bank selected by ba0, ba1 and a10. when a10 is high, all banks are precharged, regardless of ba0 and ba1. when a10 is low, only the bank selected by ba0 and ba1 is precharged. after this command, the pd45d128xxx can't accept the activate command to the precharging bank during t rp (precharge to activate command period). this command can terminate the current burst operation. this command corresponds to a conventional dram's /ras rising. fig.4 precharge command /we /cas /ras /cs cke clk h add (precharge select) a10 ba0, ba1 read command (/cs, /cas = low, /ras, /we = high) this command begins the burst read operation. the bank and the burst start column address are selected by ba0 and ba1 and by a0 through a11 respectively. read data is available after /cas latency requirements which have been met. and it is synchronized with dqs. fig.5 read command /we /cas /ras /cs cke clk h add (auto precharge select) col. a10 ba0, ba1 write command (/cs, /cas, /we = low, /ras = high) this command begins burst write operation. the bank and the burst start column address are selected by ba0 and ba1 and by a0 through a11 respectively. write data must be input by dq0 through dq15. byte mask data must be input by dm, ldm, and udm. both data must be synchronized with dqs that is inputted after this command. fig.6 write command /we /cas /ras /cs cke clk h add (auto precharge select) col. a10 ba0, ba1
data sheet e0030n10 13 pd45d128442, 45d128842, 45d128164 cbr (auto) refresh command (/cs, /ras, /cas = low, /we, cke = high) this command is a request to begin the cbr (auto) refresh operation. the refresh address is generated internally. before executing cbr (auto) refresh, all banks must be precharged. after this cycle, all banks will be in the idle (precharged) state and ready for a bank activate command. during t rfc (refresh command to refresh or activate command period), the pd45d128xxx cannot accept any other command. fig.7 cbr (auto) refresh command /we /cas /ras /cs cke clk h add a10 ba0, ba1 self refresh entry command (/cs, /ras, /cas, cke = low, /we = high) after the command execution, self refresh operation continues while cke remains low. when cke goes high, the pd45d128xxx will exit the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. before executing self refresh, all banks must be precharged. fig.8 self refresh entry command /we /cas /ras /cs cke clk add a10 ba0, ba1 burst stop command (/cs, /we = low, /ras, /cas = high) this command can stop the current read burst operation. fig.9 burst stop command /we /cas /ras /cs cke clk h add a10 ba0, ba1
data sheet e0030n10 14 pd45d128442, 45d128842, 45d128164 no operation (/cs = low, /ras, /cas, /we = high) this command is not an execution command. this command doesn't begin or terminate any operation. fig.10 no operation /we /cas /ras /cs cke clk h add a10 ba0, ba1
data sheet e0030n10 15 pd45d128442, 45d128842, 45d128164 3. simplified state diagram writa pre/pall pre/pall reada read bst pre (precharge termination) pre (precharge termination) act mrs, emrs ref pwdn pdex self idle mode register set cbr (auto) refresh bank active self refresh power down precharge read reada power on writ read automatic sequence manual input read self refresh recovery bank activating srex reada reada (t rp ) (burst end) (t wr/ t dal ) (t wr ) (burst end) (t mrd ) (t rfc ) writa writ pwdn pdex
data sheet e0030n10 16 pd45d128442, 45d128842, 45d128164 4. truth table 4.1 command truth table function symbol cke /cs /ras /cas /we address n-1 n ba0 ba1 a10 a0-9,a11 device deselect desl h x h x x x x x x no operation nop h x l h h h x x x burst stop bst h x l h h l x x x read read h x l h l h v l v read with auto precharge reada h write writ h x l h l l v l v write with auto precharge writa h bank active act h x l l h h v prechrage select bank pre h x l l h l v l x precharge all banks pall x h x mode register set mrs h x l l l l l l l v extended mode register set emrs h l l v 4.2 dm truth table cke dm function symbol n-1 n u l data write enable enb h x l data mask mask h x h upper byte write enable enbu h x l x lower byte write enable enbl h x x l upper byte write inhibit masku h x h x lower byte write inhibit maskl h x x h 4.3 cke truth table current state function symbol cke /cs /ras /cas /we address n-1 n idle cbr (auto) refresh command ref h h l l l h x idle self refresh entry self h l self refresh self refresh exit srex l h h x x x x l h h x x idle power down entry pwdn h l h x x x x l h h x x bank(s) active power down entry pwdn h l h x x x x l h h x x power down power down exit pdex l h h x x x x l h h x x remark h = high level, l = low level, v = valid, x = high or low level (don't care)
data sheet e0030n10 17 pd45d128442, 45d128842, 45d128164 4.4 operative command table note1 (1/3) current state /cs /ras /cas /we address command action notes idle h x x x x desl nop or power down l h h h x nop nop or power down l h h l x bst illegal 2 l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/writa illegal 2 l l h h ba, ra act bank activating l l h l ba, a10 pre/pall nop 3 l l l h x ref/self cbr (auto) refresh or self refresh 4 l l l l op-code mrs mode register set 4 l l l l op-code emrs extended mode register set 4 row active h x x x x desl nop l h h h x nop nop l h h l x bst illegal 2 l h l h ba, ca, a10 read/reada begin read/read with ap l h l l ba, ca, a10 writ/writa begin write/write with ap l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall precharge/precharge all banks 5 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal read h x x x x desl nop (row active after burst end) l h h h x nop nop (row active after burst end) l h h l x bst terminate burst, row active 6 l h l h ba, ca, a10 read/reada terminate burst, begin new read/ read with ap 6 l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall terminate burst, precharge/precharge all banks 6 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal write h x x x x desl nop (row active after t wr ) l h h h x nop nop (row active after t wr ) l h h l x bst illegal l h l h ba, ca, a10 read/reada terminate burst, begin read/read with ap 6 l h l l ba, ca, a10 writ/writa terminate burst, begin new write/ write with ap 6 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall terminate burst, precharge/precharge all banks 6 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal
data sheet e0030n10 18 pd45d128442, 45d128842, 45d128164 (2/3) current state /cs /ras /cas /we address command action notes read with auto h x x x x desl nop (precharge after burst end) precharge l h h h x nop nop (precharge after burst end) l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal write with h x x x x desl nop (idle after t dal ) auto precharge l h h h x nop nop (idle after t dal ) l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal precharge h x x x x desl nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l x bst illegal 2 l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/writa illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall nop (idle after t rp ) 3 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal row activating h x x x x desl nop (row active after t rcd ) l h h h x nop nop (row active after t rcd ) l h h l x bst illegal 2 l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/writa illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal
data sheet e0030n10 19 pd45d128442, 45d128842, 45d128164 (3/3) current state /cs /ras /cas /we address command action notes write recovering h x x x x desl nop (row active after t wr ) l h h h x nop nop (row active after t wr ) l h h l x bst nop (row active after t wr ) l h l h ba, ca, a10 read/reada begin read/read with ap l h l l ba, ca, a10 writ/writa begin new write/write with ap l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal write recovering h x x x x desl nop (idle after t dal ) with auto precharge l h h h x nop nop (idle after t dal ) l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h x ref/self illegal l l l l op-code mrs illegal l l l l op-code emrs illegal refresh h x x x x desl nop (idle after t rfc ) l h h h x nop nop (idle after t rfc ) l h h l x bst nop (idle after t rfc ) 2 l h l x x read/writ illegal 2 l l h x x act/pre/pall illegal 3 l l l x x ref/self/mrs/e mrs illegal mode register h x x x x desl nop (idle after t mrd ) accessing l h h h x nop nop (idle after t mrd ) l h h l x bst illegal 2 l h x x x read/writ illegal 2 l l x x x act/pre/pall/r ef/self/mrs/em rs illegal 2 remark h = high level, l = low level, x = high or low level (don't care), ba = bank address, ra = row address, ca = column address, a10 = precharge control address, op-code = operand code, nop = no operation, ap = auto precharge, illegal = device operation and/or data-integrity are not guaranteed notes 1. all entries assume that cke was active (high level) during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified states; function may be legal in the bank indicated by ba0, ba1 depending on the state of that bank. 3. nop to bank precharging or in idle state. may precharge bank indicated by ba0, ba1. 4. illegal if any bank is not idle. 5. illegal if t ras is not satisfied. 6. must satisfy command interval and/or burst terminate condition.
data sheet e0030n10 20 pd45d128442, 45d128842, 45d128164 4.5 command truth table for cke current state cke /cs /ras /cas /we add command action notes n-1 n self refresh h x x x x x x illegal(impossible) l h h x x x x srex exit s.r, self refresh recovery 2 l h h x x l l x x x x x maintain self refresh self refresh recovery h h h x x x x desl nop (idle after t rc ) h h l h h h x nop nop (idle after t rc ) h l x x x x x illegal l x x x x x x illegal (impossible) power down h x x x x x x illegal (impossible) l h h x x x x pdex exit power down, idle l h h x x l l x x x x x maintain power down all banks idle h h v v v v x refer to operative command table h l h x x x x pwdn power down entry 1 h l l h h h x pwdn power down entry 1 h l l x x l x illegal h l l h l x x illegal h l l l h x x illegal h l l l l h x self self refresh entry 1 l x x x x x x power down row active h x x x x x x refer to operative command table l x x x x x x power down 1 any state except h h v v v v v refer to operative command table listed above h l x x x x x illegal l x x x x x x illegal (impossible) remark h = high level, l = low level, x = high or low level (don't care), v = valid, add = address (a0 - a11, ba0, ba1), illegal = device operation and/or data-integrity are not guaranteed notes 1. self refresh can be entered only from all banks idle state. power down can be entered only from all banks idle or row active state. 2. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit.
data sheet e0030n10 21 pd45d128442, 45d128842, 45d128164 5. initialization the pd45d128xxx is initialized in the power-on sequence according to the following. (1) power must first be applied to v dd , then v dd q, and finally to v ref . v tt must be applied. (2) maintaining an lvcmos low level on cke during power-up is required to guarantee that the dq and dqs output will be in hi-z state. (3) to stabilize internal circuits, when power is applied a 100 s or longer pause must precede any signal toggling. (4) after the pause, all banks must be precharged using precharge command. the precharge all banks command is convenient. (5) emrs command must be performed to enable or disable dll. then mrs command must be applied to reset dll. after this mrs command additional 200 cycles are required before read command. (6) all banks must be precharged using precharge command again. then two or more cbr (auto) refresh command must be performed. (7) after the refresh the mode register can be programmed by mrs command. case 1: mrs after the ref clk command ref mrs t rp t mrd t rfc t rfc pall ref any command t mrd dll enable / disable dll reset cke min. 200 cycles before read command t mrd mrs emrs pall minimum of 2 times ref command must be performed. remark two refresh commands may be follow the first mrs command.
data sheet e0030n10 22 pd45d128442, 45d128842, 45d128164 6. programming the mode register the mode register is programmed by the mode register set command using address bits ba0, ba1, a11 through a0 as data inputs. the register retains data until it is reprogrammed or the device loses power. the mode register has five fields; option : a11 through a9, a7 dll reset : a8 /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued during t mrd . /cas latency /cas latency is the mode critical of the parameters being set. it tells the device how many clocks must elapse before the data will be available. the value is determined by the frequency of the clock and the speed grade of the device. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become hi-z. the burst length is programmable as 2, 4 and 8. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either sequential or interleave. the method chosen will depend on the type of cpu in the system. some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing. 7.1 burst length and sequence shows the addressing sequence for each burst length using them. both sequences support bursts of 2, 4 and 8. the extended mode register has two fields; option : a11 through a1 dll enable : a0
data sheet e0030n10 23 pd45d128442, 45d128842, 45d128164 7. mode register ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 vender specific x x x x x 0 1 v v v v v v v ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 0 0 0 0 0 0 0 0 0 0 dll extended mode register set ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register set 0 0 0 0 0 dll 0 ltmode wt bl remark v = valid, x = don't care /we /cas /ras /cs cke clk a0 - a11, ba0, ba1 mode register set timming bit 8 dll 0 normal 1 reset bit 0 dll 0 enable 1 disable bit 2 - bit 0 wt = 0 wt = 1 000 r r 001 2 2 burst 010 4 4 length 011 8 8 100 r r 101 r r 110 r r 111 r r wrap bit 3 mode type 0 sequential 1 interleave bit 6 - bit 4 /cas latency 000 r 001 r latency 010 2 mode 011 r 100 r 101 r 110 2.5 111 r remark r: reserved
data sheet e0030n10 24 pd45d128442, 45d128842, 45d128164 7.1 burst length and sequence [burst length = two] starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [burst length = four] starting address (column address a1 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [burst length = eight] starting address (column address a2 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
data sheet e0030n10 25 pd45d128442, 45d128842, 45d128164 8. address bits of bank-select and precharge [activate command] ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row address ba1 ba0 result 0 0 select bank a, ''activate'' command 0 1 select bank b, ''activate'' command 1 0 select bank c, ''activate'' command 1 1 select bank d, ''activate'' command [precharge command] ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row address ba1 ba0 a10 result 0 0 0 precharge bank a 0 1 0 precharge bank b 1 0 0 precharge bank c 1 1 0 precharge bank d x x 1 precharge all banks remark x = don't care [read/write command] ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 column address a10 result 0 disables auto-precharge 1 enables auto-precharge ba1 ba0 result 0 0 enables read/write commands for bank a 0 1 enables read/write commands for bank b 1 0 enables read/write commands for bank c 1 1 enables read/write commands for bank d
data sheet e0030n10 26 pd45d128442, 45d128842, 45d128164 9. precharge 9.1 read to precharge command interval the precharge command can be issued anytime after t ras (min.) is satisfied. soon after the precharge command is issued, precharge operation performed and the ddr sdram enters the idle state after t rp is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. /cas latency = 2 : (burst length/2) clocks after the read command is issued. /cas latency = 2.5 : (burst length/2) clocks after the read command is issued. clk t0 t2 t1 t3 t4 t5 burst length = 4 q1 q2 q3 read dq command q4 q1 q2 dq command q3 q4 /cas latency = 2 /cas latency = 2.5 /clk cke read (must satisfy t ras ) pre pre hi-z hi-z dqs dqs hi-z hi-z
data sheet e0030n10 27 pd45d128442, 45d128842, 45d128164 9.2 write to precharge command interval in order to write all burst data to the memory cell correctly, the asynchronous parameter t wr must be satisfied. the t wr specification defines the earliest time that a precharge command can be issued. clk burst length = 4 q1 q2 q3 write dq command q4 /cas latency = 2, 2.5 /clk dm (must satisfy t ras ) pre hi-z dqs preamble postamble t wr t0 t2 t1 t3 t4 t5
data sheet e0030n10 28 pd45d128442, 45d128842, 45d128164 10. auto precharge during a read or write command cycle, a10 controls whether auto precharge is selected. a10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begin automatically. the t ras must be satisfied with a read with auto precharge or a write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. in read cycle, once auto precharge has started, an activate command to the bank can be issued after t rp has been satisfied. in write cycle, the t dal must be satisfied to issue the next activate command to the bank being precharged. 10.1 read with auto precharge when a read with auto precharge command is issued, the auto precharge begins (burst length / 2) clocks later from a read with auto precharge command. clk burst length = 4 q1 q2 q3 reada dq command q4 q1 q2 dq command q3 q4 /cas latency = 2 /cas latency = 2.5 /clk cke reada burst length / 2 cycle (when t ras is satisfied) act act hi-z hi-z t rp auto precharge starts auto precharge starts t0 t2 t1 t3 t4 t5 remark reada means read with auto precharge command
data sheet e0030n10 29 pd45d128442, 45d128842, 45d128164 10.2 write with auto precharge when a write with auto precharge command is issued, the auto precharge begins after t wr is satisfied. clk burst length = 2 writea dq command dqs /cas latency = 2, 2.5 /clk cke act t wr (when t ras is satisfied) d2 t rp auto precharge starts t dal = t wr + t rp t0 t2 t1 t3 t4 t5 d1 remark writea means write with auto precharge command
data sheet e0030n10 30 pd45d128442, 45d128842, 45d128164 11. read/write command interval 11.1 read to read command interval during a read cycle, when new read command is issued, it will be effective after /cas latency, even if the previous read operation does not completed. read will be interrupted by another read. the interval between commands is minimum 1 cycle. each read command can be issued in every clock without any restriction. clk burst length = 4 qb1 qb2 qb3 read a dq command qb4 dq command /cas latency = 2 /cas latency = 2.5 /clk cke read a 1 cycle read b read b hi-z hi-z qa1 qa2 qb1 qb2 qb3 qa1 qa2 t0 t2 t1 t3 t4 t5
data sheet e0030n10 31 pd45d128442, 45d128842, 45d128164 11.2 write to write command interval during a write cycle, when new write command is issued, the previous burst will terminate and the new burst will begin with new write command. write will be interrupted by another write. the interval between commands is minimum 1 cycle. each write command can be issued in every clock without any restriction. clk burst length = 4 write a dqs command /cas latency = 2, 2.5 /clk cke 1 cycle da1 dq da2 db1 db2 db3 db4 write b t0 t2 t1 t3 t4 t5
data sheet e0030n10 32 pd45d128442, 45d128842, 45d128164 11.3 write to read command interval the burst write operation can be interrupted by read command of any bank. the data bus must be high impedance at least 1 cycle prior to the first output data. the minimum time interval between the rising clock edge after the last input data and the read command is t wr . when the read command is issued, the invalid data from the burst write cycle must be masked by dm. clk write a dqs command /cas latency = 2 /clk cke read b dq da1 dm qb1 qb2 qb3 qb4 write a dqs command read b dq da1 da2 dm qb1 qb2 /cas latency = 2.5 dq and dqs : input dq and dqs : output da2 t wr qb3 t0 t2 t1 t3 t4 t5 t6 hi-z hi-z hi-z hi-z
data sheet e0030n10 33 pd45d128442, 45d128842, 45d128164 11.4 read to write command interval to interrupt the burst read operation using the write command, the burst stop command must be issued to avoid data conflict. the data bus must be high impedance at least 1 cycle before the write command is issued. when the write command is issued, any residual data from the burst read cycle must be terminated by the burst stop command. when /cas latency is 2, 2.5, the burst stop command must be issued at least 2 cycles prior to the write command. clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 8 t9 read a dqs command /cas latency = 2 /clk cke t10 t11 write b dq qa1 qa2 t12 t13 t14 db1 db2 read a dqs command write b dq qa1 qa4 /cas latency = 2.5 dq and dqs : output dq and dqs : input bst bst db1 db2 qa3 qa4 hi-z hi-z qa2 qa3 db db t0 t2 t1 t3 t4 t5 t6 hi-z hi-z
data sheet e0030n10 34 pd45d128442, 45d128842, 45d128164 12. burst termination 12.1 burst stop command in read cycle during a burst read cycle, when the burst stop command is issued at the rising edge of the clock (clk), the burst read data are terminated and the data bus goes to high impedance after the /cas latency from the burst stop command. clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 8 t9 q1 q2 q3 read dq command q4 q1 q2 dq command q3 q4 /cas latency = 2 /cas latency = 2.5 /clk cke t10 t11 read (when t ras is satisfied) bst bst hi-z hi-z t0 t2 t1 t3 t4 t5 remark bst means burst stop command
data sheet e0030n10 35 pd45d128442, 45d128842, 45d128164 12.2 precharge termination in read cycle during a burst read cycle without auto precharge, the burst read operation is terminated by a precharge command of the same banks. when the precharge command is issued at the rising edge of the clock (clk), the burst read operation is terminated and the data bus goes to high impedance after the /cas latency from the precharge command. the precharge command can be issued after t ras (min.) is satisfied. clk burst length = full page q1 q2 q3 read dq command q4 q1 q2 dq command q3 q4 /cas latency = 2 /cas latency = 2.5 /clk cke read (when t ras is satisfied) pre pre hi-z hi-z t0 t2 t1 t3 t4 t5
data sheet e0030n10 36 pd45d128442, 45d128842, 45d128164 12.3 precharge termination in write cycle during a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same banks. in order to write the last input data to the memory cell correctly, t wr (min.) must be satisfied. when the precharge command is issued at the rising edge of the clock (clk), the invalid data from the burst write cycle must be masked dm. clk burst length = 8 write dqs command /cas latency = 2, 2.5 /clk cke t wr pre dq d1 d2 dm t0 t2 t1 t3 t4 t5
data sheet e0030n10 37 pd45d128442, 45d128842, 45d128164 13. electrical specifications ? all voltages are referenced to v ss (gnd). ? after power up, wait more than 100 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. 13.1 absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to v ss v dd , v dd q ? 0.5 to +3.6 v voltage on any pin relative to v ss v t ? 0.5 to +3.6 v short circuit output current i o 50 ma power dissipation p d 1 w storage temperature t stg ? 55 to + 125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 13.2 recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v dd 2.3 2.5 2.7 v supply voltage for dq, dqs v dd q 2.3 2.5 2.7 v input reference voltage v ref 0.49 v dd q 0.51 v dd q v termination voltage v tt v ref ? 0.04 v ref v ref + 0.04 v high level dc input voltage v ih (dc) v ref + 0.15 v dd + 0.3 v low level dc input voltage v il (dc) ? 0.3 v ref ? 0.15 v input differential voltage (clk and /clk) v id (dc) 0.36 v dd q + 0.6 v input crossing point voltage (clk and /clk) v ix 0.5 v dd qC0.2 0.5 v dd q+0.2 v operating ambient temperature t a 0 70 c 13.3 pin capacitance (t a = 25 c, f = 100 mhz) parameter symbol condition min. typ. max. unit input capacitance c i1 a0 - a11, ba0, ba1 2.5 3.5 pf c i2 clk, /clk, cke, /cs, /ras, /cas, /we 2.5 3.5 pf data input/output capacitance c io1 dqs, ldqs, udqs 4 5.5 pf c io2 dq0 - dq15, dm, ldm, udm 4 5.5 pf
data sheet e0030n10 38 pd45d128442, 45d128842, 45d128164 13.4 dc characteristics 1 (recommended operating conditions unless otherwise noted) maximum parameter symbol test condition /cas latency grade x4 x8 x16 unit notes -c75 160 ma 1 operating current (act-pre) i dd0 t rc = t rc(min.) , t ck = t ck (min.) , one bank, active-precharge, dq, dm and dqs inputs changing twice per clock cycle, address and control inputs changing once per clock cycle -c80 140 cl = 2 -c75 165 170 175 ma -c80 150 155 160 cl = 2.5 -c75 175 180 185 operating current (act-read-pre) i dd1 t rc = t rc(min.) , t ck = t ck (min.) , one bank, active-read-precharge, i o = 0 ma, burst length = 2, address and control inputs changing once per clock cycle -c80 160 165 170 precharge power down standby current i dd2p cke v il(max.) , t ck = t ck(min.) , all banks idle, power down mode 5 ma idle standby current i dd2n cke v ih(min.) , t ck = t ck(min.) , /cs v ih(min.) , all banks idle, address and other control inputs changing once per clock cycle 50 ma active power down standby current i dd3p cke v il(max.) , t ck = t ck(min.) , one bank active, power down mode 50 ma active standby current i dd3n /cs v ih(min.) , cke v ih(min.) , t ck = t ck(min.) , t rc = t ras(max.) , one bank, active-precharge, dq, dm and dqs inputs changing twice per clock cycle, address and other control inputs changing once per clock cycle 70 ma cl = 2 -c75 170 180 200 ma 2 -c80 170 180 200 cl = 2.5 -c75 230 240 265 operating current (burst read) i dd4r t ck = t ck(min.) , continuous burst read, burst length = 2, i o = 0ma, one bank active, address and control inputs changing once per clock cycle -c80 215 225 250 cl = 2 -c75 160 170 190 ma 2 -c80 160 170 190 cl = 2.5 -c75 220 230 255 operating current (burst write) i dd4w t ck = t ck(min.) , continuous burst write, burst length = 2, one bank active, address and control inputs changing once per clock cycle -c80 205 215 240 cbr (auto) refresh current i dd5 t rfc = t rfc(min.) -c75 270 ma -c80 250 self refresh current i dd6 cke 0.2 v 2 ma notes 1. i dd1 depends on output loading and cycle rates. specified values are obtained with the output open. 2. i dd4r and i dd4w depend on output loading and cycle rates. specified values are obtained with the output open. 13.5 dc characteristics 2 (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit notes input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v ? 2 2 a output leakage current i o(l) d out is disabled, v o = 0 to v dd q + 0.3 v ? 5 5 a output high current i oh v out = v dd q ? 0.43 v C16.8 ma output low current i ol v out = 0.35 v 16.8 ma
data sheet e0030n10 39 pd45d128442, 45d128842, 45d128164 13.6 ac characteristics (recommended operating conditions unless otherwise noted) 13.6.1 test conditions parameter symbol value unit notes input reference voltage (input timing measurement reference level) v ref v dd q x 0.5 v termination voltage (output timing measurement reference level) v tt v ref v 1 high level ac input voltage v ih (ac) v ref + 0.31 v low level ac input voltage v il (ac) v ref ? 0.31 v input differential voltage (clk and /clk) v id (ac) 0.7 v input signal slew rate slew 1 v/ns 2 notes 1. output waveform timing is measured where the output signal crosses through the v tt level. 2. slew rate is to be maintained in the v il (ac) to v ih (ac) range of the input signal swing. slew = (v ih (ac)-v il (ac))/ ? t output r t = 50 ? c load = 30 pf v tt
data sheet e0030n10 40 pd45d128442, 45d128842, 45d128164 13.6.2 timing diagram t ck t dqsck t dqsck t ch t cl t is t ih t is t ih t is t ih t is t ih valid valid t rpre valid t ac t ac t qh t qh t dqsq t rpst t dqsck valid valid valid valid t dqsck valid t dqsq t dh t ds t dh t ds t wpst t dqsl t dqsh t dsh valid valid t rpst t ac t ac t dqsq t dqsq t qh t qh t wpres t wpre t dqss clk dqs (output) (cl = 2.5) dq (output) (cl = 2.5) /clk command (input) address (input) dqs (output) (cl = 2) dq (output) (cl = 2) dqs (input) t dqss (min.) dq and dm (input) v id (ac) v tt v tt v tt v tt v ref + 0.31 v v ref - 0.31 v v ref + 0.31 v v ref - 0.31 v v ref + 0.31 v v ref - 0.31 v v ref + 0.31 v v ref - 0.31 v v ref v ref t dh t ds t dh t ds t wpst t dqsl t dqsh t dqss valid valid t wpres t wpre t dqss dqs (input) t dqss (max.) dq and dm (input) v ref + 0.31 v v ref - 0.31 v v ref + 0.31 v v ref - 0.31 v v ref v ref t rpre
data sheet e0030n10 41 pd45d128442, 45d128842, 45d128164 13.6.3 synchronous characteristics parameter symbol -c75 (pc266b) -c80 (pc200) unit note min. max. min. max. clock cycle time cl = 2.5 t ck 7.5 15 8 15 ns cl = 2 10 15 10 15 clk high-level width t ch 0.45 0.55 0.45 0.55 t ck clk low-level width t cl 0.45 0.55 0.45 0.55 t ck dq output access time from clk, /clk t ac C0.75 0.75 C0.8 0.8 ns dqs output access time from clk, /clk t dqsck C0.75 0.75 C0.8 0.8 ns dqs-dq skew (for dqs and associated dq signals) t dqsq C0.5 0.5 C0.6 0.6 ns dqs-dq skew (for dqs and all dq signals) t dqsqa C0.5 0.5 C0.6 0.6 ns data out low-impedance time from clk, /clk t lz C0.75 0.75 C0.8 0.8 ns data out high-impedance time from clk, /clk t hz C0.75 0.75 C0.8 0.8 ns half clock period t hp t ch , t cl t ch , t cl ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp C 0.75 t hp C 1 ns dq and dm input setup time t ds 0.5 0.6 ns dq and dm input hold time t dh 0.5 0.6 ns dq and dm input pulse width (for each input) t dipw 1.75 2 ns dqs write preamble setup time t wpres 0 0 ns dqs write preamble t wpre 0.25 0.25 t ck write postamble t wpst 0.4 0.6 0.4 0.6 t ck write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs falling edge to clk setup time t dss 0.2 0.2 t ck dqs falling edge hold time from clk t dsh 0.2 0.2 t ck address and control input setup time t is 0.9 1.1 ns address and control input hold time t ih 0.9 1.1 ns address and control input pulse width t ipw 2.2 2.5 ns internal write to read command delay t wtr 1 1 t ck
data sheet e0030n10 42 pd45d128442, 45d128842, 45d128164 13.6.4 synchronous characteristics example symbol t ck =7.5 ns t ck =8 ns t ck =10 ns unit min. max. min. max. min. max. t ch 3.375 4.125 3.6 4.4 4.5 5.5 ns t cl 3.375 4.125 3.6 4.4 4.5 5.5 ns t rpre 6.75 8.25 7.2 8.8 9 11 ns t rpst 3 4.5 3.2 4.8 4 6 ns t wpre 1.875 2 2.5 ns t wpst 3 4.5 3.2 4.8 4 6 ns t dqss 5.625 9.375 6 10 7.5 12.5 ns t dqsh 2.625 2.8 3.5 ns t dqsl 2.625 2.8 3.5 ns t dss 1.5 1.6 2 ns t dsh 1.5 1.6 2 ns t wtr 7.5 8 10 ns 13.6.5 asynchronous characteristics parameter symbol -c75(pc266b) -c80(pc200) unit min. max. min. max. act to ref/act command period (operation) t rc 65 70 ns ref to ref/act command period (refresh) t rfc 75 80 ns act to pre command period t ras 45 120,000 50 120,000 ns pre to act command period t rp 20 20 ns act to read/write delay t rcd 20 20 ns act(one) to act(another) command period t rrd 15 15 ns write recovery time t wr 15 15 ns auto precharge write recovery time + precharge time t dal 35 35 ns mode register set command cycle time t mrd 15 15 ns exit self refresh to command t xsnr 75 80 ns refresh time (4,096 refresh cycles) t ref 64 64 ms
data sheet e0030n10 43 pd45d128442, 45d128842, 45d128164 ac parameters for read timing 1 (manual precharge, burst length = 4, /cas latency = 2.5) t ras t rc ba0 t ih t rp t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dm t rcd t is t ch t cl t ck t is t ih l activate command for bank a precharge command for bank a read command for bank a activate command for bank a t ck t cl t ch /clk t is t ih dqs dq t ac t dqsq t dqsq t dqsq t dqsq t ac t ac t ac t qh t qh t qh t qh t dqsck t dqsck t dqsck t dqsck t rpre t rpst hi-z v tt hi-z v tt
data sheet e0030n10 44 pd45d128442, 45d128842, 45d128164 ac parameters for read timing 2 (auto precharge, burst length = 4, /cas latency = 2.5) t ras t rrd t rc ba0 t ih t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dm t rcd t is t ch t cl t ck t is t ih t is t ih activate command for bank c activate command for bank d bank c read command with auto precharge activate command for bank c dqs dq hi-z v tt t ac t dqsq t dqsq t dqsq t dqsq t ac t ac t ac t qh t qh t qh t qh t dqsck t dqsck t dqsck t dqsck t rpre t rpst t ck t cl t ch /clk auto precharge start for bank c hi-z v tt
data sheet e0030n10 45 pd45d128442, 45d128842, 45d128164 relationship between frequency and latency speed version -c75 -c 80 clock cycle time [ns] 7.5 10 8 10 frequency [mhz] 133 100 125 100 /cas latency 2.5 2 2.5 2 [t rcd ] 3 2 3 2 /ras latency (/cas latency + [t rcd ]) 5.5 4 5.5 4 [t rc ] 9 7 9 7 [t rfc ] 10 8 10 8 [t ras ] 6 5 7 5 [t rrd ] 2 2 2 2 [t rp ] 3 2 3 2 [t wr ] 2 2 2 2 [t dal ] 5 4 5 4 [t mrd ] 2 2 2 2 [t xsnr ] 10 8 10 8
data sheet e0030n10 46 pd45d128442, 45d128842, 45d128164 ac parameters for write timing (burst length = 8, /cas latency = 2.5) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke ba0 a10 add dm dq hi-z t is t ih t rcd t rc t rrd t rcd t ras t rc t wr t rp t ih t is t ih t is /cs /ras /cas /we ba1 auto precharge start for bank c activate command for bank c activate command for bank b bank b write command without auto precharge activate command for bank b bank c write command with auto precharge precharge command for bank b activate command for bank c /clk t ds t dh dqs t dqss t wpst hi-z v tt v tt t wpres t wpre t dal
data sheet e0030n10 47 pd45d128442, 45d128842, 45d128164 mode register set (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dm dq ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 v tt t mrd address key t rp all banks precharge command mode register set command activate command is valid h v tt dqs /clk hi-z hi-z
data sheet e0030n10 48 pd45d128442, 45d128842, 45d128164 power on sequence and cbr (auto) refresh clk cke /cs /ras /cas /we ba1 a10 add dm dq t2 t3 t4 t5 t0 t1 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 hi-z low level is necessary 2 refresh cycles are necessary t rp t rfc all banks precharge command is necessary all banks precharge command is necessary mode register set command is necessary refresh command is necessary activate command refresh command is necessary ba0 dqs hi-z /clk more than 200 cycles are necessary before read command t mrd v tt v tt t rfc address key address key address key extended mode register set command (dll enable / disable) is necessary mode register set command (dll reset) is necessary t mrd t mrd
data sheet e0030n10 49 pd45d128442, 45d128842, 45d128164 /cs function (at 100 mhz, burst length = 4, /cas latency = 2.5) only /cs signal needs to be issued at minimum rate clk cke /cs /ras /cas /we ba1 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h l hi-z l ba0 l raa qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab3 dab4 activate command for bank a read command for bank a write command for bank a precharge command for bank a raa caa cab /clk dqs hi-z v tt v tt
data sheet e0030n10 50 pd45d128442, 45d128842, 45d128164 power down m ode (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa3 caa hi-z raa ba0 t is qaa1 qaa2 activate command for bank a power down mode entry read command for bank a precharge command for bank a precharge standby power down mode exit qaa4 /clk dqs hi-z v tt v tt raa
data sheet e0030n10 51 pd45d128442, 45d128842, 45d128164 cbr (auto) refresh clk cke /cs /ras /cas /we ba1 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ba0 v tt t rp h t rfc t rfc q1 precharge command is necessary cbr (auto) refresh cbr (auto) refresh activate command read command /clk q2 v tt dqs hi-z hi-z
data sheet e0030n10 52 pd45d128442, 45d128842, 45d128164 self refresh (entry and exit) clk cke /cs /ras /cas /we ba1 a10 add dm dq t0 t1 t2 t3 t4 tn tn+1 tn+2 tm tm+1 tm+2 tk tj tj+1 tj+2 t rp t xsnr t xsnr ba0 hi-z precharge command is necessary self refresh entry self refresh exit next clock enable self refresh entry (or activate command) activate command self refresh exit next clock enable /clk dqs hi-z v tt v tt
data sheet e0030n10 53 pd45d128442, 45d128842, 45d128164 random column read (page with same bank) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 v tt qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 h rad raa cad cac caa rad cab ba0 raa precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a qad1 qad2 qad3 qad4 dqs v tt /clk hi-z hi-z
data sheet e0030n10 54 pd45d128442, 45d128842, 45d128164 random column read (page with same bank) (2/2) (burst length = 4, /cas latency = 2.5) clk cke /cs /ras /cas /we ba1 a10 add t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h raa raa caa cac caa raa cab ba0 raa /clk dm dq v tt qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a qad1 qad2 qad3 qad4 dqs v tt hi-z hi-z
data sheet e0030n10 55 pd45d128442, 45d128842, 45d128164 random column write (page with same bank) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we a10 add dm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h rdd rda cdd cdc cda rdd cdb rda activate command for bank d write command for bank d write command for bank d write command for bank d precharge command for bank d activate command for bank d write command for bank d hi-z dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 /clk dq dqs v tt ddd1 ddd2 ddd3 ddd4 v tt hi-z ba0 ba1
data sheet e0030n10 56 pd45d128442, 45d128842, 45d128164 random column write (page with same bank) (2/2) (burst length = 4, /cas latency = 2.5) clk cke /cs /ras /cas /we a10 add t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 h rdd rda cdd cdc cda rdd cdb rda activate command for bank d write command for bank d write command for bank d write command for bank d precharge command for bank d activate command for bank d write command for bank d /clk ba0 dm dq ba1 dqs v tt ddd1 ddd2 ddd3 ddd4 v tt hi-z
data sheet e0030n10 57 pd45d128442, 45d128842, 45d128164 random row read (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z qda1 qda2 qda3 qda4 qda5 qda6 qda7 qda8 qba1 qba2 qba3 qba4 qba5 h rdb rda cdb cba cda rdb rba rda ba0 rba qba6 qba7 qba8 activate command for bank d read command for bank d activate command for bank b read command for bank b precharge command for bank d activate command for bank d read command for bank d qdb1 qdb2 qdb3 qdb4 qdb5 qdb6 qdb7 qdb8 dqs hi-z v tt v tt /clk
data sheet e0030n10 58 pd45d128442, 45d128842, 45d128164 random row read (ping-pong banks) (2/2) (burst length = 8, /cas latency = 2.5) clk cke /cs /ras /cas /we ba0 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z h rbb rba cbb caa cba rbb raa rba raa ba1 activate command for bank b read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b precharge command for bank a qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 qaa8 qbb1 qbb2 qbb3 qbb4 qbb5 qbb6 /clk dqs v tt v tt hi-z qbb7
data sheet e0030n10 59 pd45d128442, 45d128842, 45d128164 random row w rite (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l daa5 daa6 daa7 daa8 dda1 dda2 dda3 dda4 dda5 dda6 dda7 dda8 h raa cab cda caa rda raa rda rab rab daa1 daa2 daa3 daa4 activate command for bank a write command for bank a write command for bank d activate command for bank d precharge command for bank a activate command for bank a write command for bank a precharge command for bank d ba0 hi-z ba1 /clk dqs hi-z v tt v tt dab1 dab2 dab3 dab4 dab5 dab6 dab7 dab8
data sheet e0030n10 60 pd45d128442, 45d128842, 45d128164 random row w rite (ping-pong banks) (2/2) (burst length = 8, /cas latency = 2.5) clk cke /cs /ras /cas /we t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h raa cab cda rda raa rda rab caa rab activate command for bank a write command for bank a write command for bank d activate command for bank d precharge command for bank a activate command for bank a precharge command for bank d write command for bank a a10 add dm dq ba0 hi-z ba1 /clk dqs hi-z v tt v tt daa5 daa6 daa7 daa8 dda1 dda2 dda3 dda4 dda5 dda6 dda7 dda8 daa1 daa2 daa3 daa4 dab1 dab2 dab3 dab4 dab5 dab6 dab7 dab8 hi-z
data sheet e0030n10 61 pd45d128442, 45d128842, 45d128164 read and w rite (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dm dq activate command for bank a read command for bank a write command for bank a 0-clock latency read command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z at the end of wrap function h raa cac cab ba0 caa raa word masking /clk qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 qaa8 dab1 dab3 dab4 dab5 dab6 dab7 dab8 qac1 qac2 qac3 qac4 qac5 qac6 qac7 qac8 dqs hi-z v tt v tt hi-z
data sheet e0030n10 62 pd45d128442, 45d128842, 45d128164 read and w rite (2/2) (burst length = 8, /cas latency = 2.5) clk cke /cs /ras /cas /we ba1 a10 add t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h raa cac cab caa raa ba0 activate command for bank a read command for bank a write command for bank a 0-clock latency read command for bank a /clk dm dq word masking qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 qaa8 dab1 dab3 dab4 dab5 dab6 dab7 dab8 qac1 qac2 qac3 dqs hi-z v tt v tt hi-z qac1 qac2 qac3
data sheet e0030n10 63 pd45d128442, 45d128842, 45d128164 interleaved column read cycle (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h raa rda ba0 raa rda caa cda cdb cdc cab cdd activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a read command for bank d precharge command for bank a precharge command for bank d read command for bank a dq v tt dqs v tt dc4 dc1 dc2 dc3 db4 aa1 aa2 aa3 aa4 aa5 aa6 aa7 aa8 da1 da2 da3 da4 db1 db2 db3 ab4 ab1 ab2 ab3 dd1 dd2 dd3 dd4 dd5 dd6 dd7 dd8 /clk hi-z hi-z
data sheet e0030n10 64 pd45d128442, 45d128842, 45d128164 interleaved colum n read cycle (2/2) (burst length = 8, /cas latency = 2.5) clk cke /cs /ras /cas /we ba1 a10 add dqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h raa rda ba0 raa cab cdc rda cda caa activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a precharge command for bank d precharge command for bank a read command for bank a cdb dq v tt dqs v tt dc4 dc1 dc2 dc3 db4 aa1 aa2 aa3 aa4 aa5 aa6 aa7 aa8 da1 da2 da3 da4 db1 db2 db3 ab4 ab1 ab2 ab3 ab5 ab6 ab7 ab8 /clk hi-z hi-z
data sheet e0030n10 65 pd45d128442, 45d128842, 45d128164 interleaved column w rite cycle (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z h raa rba raa rba caa cba cbb cbc cab cbd ba1 activate command for bank a write command for bank a activate command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b write command for bank b write command for bank b write command for bank b /clk aa1 aa2 aa3 aa4 ba1 ba2 bc1 bc2 bd1 bd2 bd3 bd4 ab1 ab2 bb1 bb2 aa5 aa6 aa7 aa8 ba3 ba4 bc3 bc4 bd5 bd6 bd7 bd8 ab3 ab4 bb3 bb4 dqs hi-z v tt v tt
data sheet e0030n10 66 pd45d128442, 45d128842, 45d128164 interleaved colum n w rite cycle (2/2) (burst length = 8, /cas latency = 2.5) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 hi-z h raa rba raa cab cbc rba cba cbb caa cbd activate command for bank a write command for bank a activate command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b write command for bank b write command for bank b write command for bank b ba1 aa1 aa2 aa3 aa4 ba1 ba2 bc1 bc2 bd1 bd2 bd3 bd4 ab1 ab2 bb1 bb2 aa5 aa6 aa7 aa8 ba3 ba4 bc3 bc4 bd5 bd6 bd7 bd8 ab3 ab4 bb3 bb4 dqs /clk hi-z v tt v tt
data sheet e0030n10 67 pd45d128442, 45d128842, 45d128164 auto precharge after read burst (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h ba1 rdb rac rda raa raa cab caa rdb cda rda cac cdb rac activate command for bank a activate command for bank d bank a read command without auto precharge bank d read command with auto precharge activate command for bank d bank a read command with auto precharge auto precharge start for bank d bank d read command with auto precharge auto precharge start for bank a auto precharge start for bank d activate command for bank a bank a read command with auto precharge v tt dqs v tt /clk hi-z hi-z
data sheet e0030n10 68 pd45d128442, 45d128842, 45d128164 auto precharge after read burst (2/2) (burst length = 8, /cas latency = 2.5) clk cke /cs /ras /cas /we ba0 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h rdb raa raa cab caa rdb cda rda cdb ba1 rda activate command for bank a activate command for bank d bank a read command without auto precharge bank d read command with auto precharge activate command for bank d bank a read command with auto precharge auto precharge start for bank a bank d read command with auto precharge auto precharge start for bank d v tt dqs v tt /clk hi-z hi-z
data sheet e0030n10 69 pd45d128442, 45d128842, 45d128164 auto precharge after write burst (1/2) (burst length = 8, /cas latency = 2) activate command for bank a bank a write command without auto precharge activate command for bank d activate command for bank d bank d write command with auto precharge bank d write command with auto precharge bank a write command with auto precharge auto precharge start for bank d auto precharge start for bank a activate command for bank a bank a write command with auto precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb rac rda raa raa cab caa rdb cda rda cac cdb rac clk cke /cs /ras /cas /we ba0 a10 add dm dq hi-z ba1 /clk dqs hi-z v tt v tt
data sheet e0030n10 70 pd45d128442, 45d128842, 45d128164 auto precharge after write burst (2/2) (burst length = 8, /cas latency = 2.5) clk cke /cs /ras /cas /we a10 add t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h rdb raa raa cab caa rdb cda rda cdb rda activate command for bank a bank a write command without auto precharge activate command for bank d bank d write command with auto precharge bank a write command with auto precharge auto precharge start for bank d auto precharge start for bank a activate command for bank d bank d write command with auto precharge ba0 dm dq hi-z ba1 /clk dqs hi-z v tt v tt
data sheet e0030n10 71 pd45d128442, 45d128842, 45d128164 byte write operation (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add ldm upper dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h hi-z hi-z ba1 udm lower dq activate command read command lower byte not write upper byte not write /clk udqs ldqs v tt v tt v tt v tt hi-z hi-z read command lower byte not write
data sheet e0030n10 72 pd45d128442, 45d128842, 45d128164 pre (precharge) termination of burst (1/2) (burst length = 8, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h raa rab caa raa rab cab t rp t rp t ras activate command for bank a activate command for bank a write command for bank a pre command termination pre command termination precharge command for bank a activate command for bank a read command for bank a precharge command for bank a t ras rac rac clk cke /cs /ras /cas /we ba0 a10 add dm dq ba1 dqs /clk hi-z write mask daa1 daa2 daa3 daa4 qab1 qab2 qab3 qab4 qab5 qab6 hi-z v tt v tt
data sheet e0030n10 73 pd45d128442, 45d128842, 45d128164 pre (precharge) termination of burst (2/2) (burst length = 8, /cas latency = 2.5) clk cke /cs /ras /cas /we ba0 a10 add dm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z h ba1 raa rab caa raa rab cab t rp t rp t ras activate command for bank a activate command for bank a write command for bank a pre command termination precharge command for bank a precharge command for bank a activate command for bank a read command for bank a pre command termination t ras write mask rac rac daa1 daa2 daa3 daa4 qab1 qab2 qab3 qab4 qab5 qab6 dqs /clk hi-z v tt v tt
data sheet e0030n10 74 pd45d128442, 45d128842, 45d128164 14. package drawing m 66 34 133 p a cn b m d l k j h i g f detail of lead end notes 1. each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. 2. dimension "a" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. s s e r l s item b c i 66-pin plastic tsop ( ii ) (10.16 mm (400)) a d e f g h j k l millimeters 0.65 (t.p.) 0.865 max. 10.16 0.10 22.22 0.05 0.10 0.05 0.24 1.1 0.1 11.76 0.20 1.00 + 0.08 ? 0.07 0.80 0.2 0.145 + 0.025 ? 0.015 0.50 0.12 m p r 3 + 5 ? 3 0.25 0.60 0.15 s 0.10 n s66g5-65-9lg-1
data sheet e0030n10 75 pd45d128442, 45d128842, 45d128164 15. recommended soldering conditions please consult with our sales offices for soldering conditions of the pd45d128xxx. type of surface mount device pd45d128xxxg5: 66-pin plastic tsop (ii) (10.16 mm (400))
data sheet e0030n10 76 pd45d128442, 45d128842, 45d128164 16. revision history (1/2) edition / page description date this edition previous edition type of revision location nec corporation (m13852e) 2nd edition / throughout throughout modification v cc v dd , v cc q v dd q, i cc i dd jun. 1999 p.1 p.1 modification power supply for v dd , v dd q p.2 p.2 modification ordering information (part number, clock frequency) p.3 p.3 modification part number (minimum cycle time) p.10 p.10 modification function (clk, /clk, cke, ba0, ba1)) p.11 p.11 modification extended mode register set command, mode register set command p.13 p.13 modification cbr (auto) refresh command p.15 p.15 modification 3. simplified state diagram p.16 p.16 modification 4.1 command truth table (a0-7 a0-9) 4.3 cke truth table (srex, pwdn, pwdn, pdex) p.17 p.17 modification row active(ref/self), write(desl, nop, ref/self) p.18 p.18 deletion row activating (srs) p.19 p.19 modification write recovering (desl, nop, bst), refresh (desl, nop, bst), mode register accessing (desl, nop) p.20 p.20 modification self refresh (srex), power down (pdex), all banks idle (power down) p.21 p.21 modification 5. initialization p.22 p.22 modification mode register fields addition extended mode register fields p.23 p.23 deletion jedec standard test set modification vender specific (a8) p.27, 29 p.27, 29 modification t dpl t wr p.32 p.32 modification 1 cycle t wr p.36 p.36 modification t dpl t wr p.37 p.37 modification 13.2 recommended operating conditions (v dd , v dd q, v ref ) addition 13.2 recommended operating conditions (v id(dc) , v ix ) p.38 p.38 modification 13.4 dc characteristics 1 deletion 13.5 dc characteristics 2 (v oh , v ol ) addition 13.5 dc characteristics 2 (i oh , i ol ) p.39 p.39 addition 13.6.1 test conditions (v id(ac) ) p.40 p.40 modification 13.6.2 timing diagram p.41 p.41 modification 13.6.3 synchronous characteristics p.42 p.42 modification 13.6.4 synchronous characteristics example 13.6.5 asynchronous characteristics p.43, 44 p.43, 44 modification ba1 ba0, ba0 ba1, t dqsv t dv p.45 p.45 modification relationship between frequency and latency p.46-73 p.46-73 modification ba1 ba0, ba0 ba1 p.46 p.46 modification t dqss , t dpl t wr p.47 p.47 modification t rsc t mrd p.48 p.48 modification power on sequence and cbr (auto) refresh (timing chart) p.51 p.51 modification t rc t rfc p.52 p.52 addition t xsnr deletion 200 cycles p.54 p.54 modification dqs, dq (t16-t19) p.57 p.57 modification dqs (t17-t21) p.61 p.61 modification read command for bank a (t14-t15), dqs, dq (t16-t21) p.62 p.62 modification burst length = 4 burst length = 8 p.66 p.66 modification precharge command for bank b (t19-t22)
data sheet e0030n10 77 pd45d128442, 45d128842, 45d128164 (2/2) edition / page description date this edition previous edition type of revision location nec corporation (m13852e) 2nd edition / p.71 p.71 modification read command (t13-t14) jun. 1999 3rd edition / p.15 p.15 modification 3. simplified state diagram april 2000 p.33 p.33 modification 11.4 read to write command interval p.37 p.37 modification 13.2 recommended operating conditions (v ref (min.,max.), v ih (dc)( min.), v il (dc)(max.)) modification 13.3 pin capacitance modification 13.3 pin capacitance (c i2 , c io2 (condition)) p.38 p.38 modification 13.4 dc characteristics 1 (i dd2p (maximum), i dd3p , i dd3n , i dd4r , i dd4w (test condition)) modification 13.5 dc characteristics 2 (i i(l) (min.,max.), i oh , i ol (min.)) p.39 p.39 modification 13.6.1 test conditions (v ih(ac) , v il(ac) (value)) modification 13.6.1 test conditions (figure) p.40 p.40 modification 13.6.2 timing diagram p.41 p.41 addition 13.6.3 synchronous characteristics (t hp , t qh , t dqsh , t dqsl , t dss , t dsh , t ipw ) deletion 13.6.3 synchronous characteristics (t dv , t dsl,h , t td , t t ) modification 13.6.3 synchronous characteristics (t wpre ) p.42 p.42 addition 13.6.4 synchronous characteristics example (t dqsh , t dqsl , t dss , t dsh ) deletion 13.6.4 synchronous characteristics example (t dv , t dsl,h ) modification 13.6.4 synchronous characteristics example (t wpre ) p.43 p.43 modification ac parameters for read timing 1 p.44 p.44 modification ac parameters for read timing 2 p.46 p.46 modification ac parameters for write timing p.54 p.54 modification random column read (page with same bank) (2/2) p.74 p.74 modification package drawing elpida memory, inc. (e0030n) 1st edition / jan. 2001 ? ? ? republished by elpida memory, inc.
data sheet e0030n10 78 pd45d128442, 45d128842, 45d128164 [memo]
data sheet e0030n10 79 pd45d128442, 45d128842, 45d128164 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd45d128442, 45d128842, 45d128164 m8e 00. 4 the information in this document is current as of aplil, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of elpida's data sheets or data books, etc., for the most up-to-date specifications of elpida semiconductor products. not all products and/or types are available in every country. please check with an elpida memory, inc. for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of elpida. elpida assumes no responsibility for any errors that may appear in this document. elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of elpida semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while elpida endeavours to enhance the quality, reliability and safety of elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. elpida semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product be fore using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of elpida semiconductor products is "standard" unless otherwise expressly specified in elpida's data sheets or data books, etc. if customers wish to use elpida semiconductor products in applications not intended by elpida, they must contact an elpida memory, inc. in advance to determine elpida's willingness to support a given application. (note) (1) "elpida" as used in this statement means elpida memory, inc. and also includes its majority-owned subsidiaries. (2) "elpida semiconductor products" means any semiconductor product developed or manufactured by or for elpida (as defined above). ? ? ? ? ? ?

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