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cy14b101k 1 mbit (128k x 8) nvsram with real time clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06401 rev. *l revised april 5, 2010 features 25 ns [1] , 35 ns, and 45 ns access times pin compatible with stk17ta8 data integrity of cypress nvsr am combined with full featured real time clock (rtc) ? low power, 350 na rtc current ? capacitor or battery backup for rtc watchdog timer clock alarm with programmable interrupts hands off automatic store on power down with only a small capacitor store to quantumtrap? initiated by software, device pin, or on power down recall to sram initiated by software or on power up infinite read, write, and recall cycles high reliability ? endurance to 200k cycles ? data retention: 20 years at 55 c single 3v operation with tolerance of +20%, ?10% commercial and industrial temperature 48-pin ssop package (rohs compliant) functional description the cypress cy14b101k combines a 1 mbit nonvolatile static ram with a full featured real time clock in a monolithic integrated circuit. the embedded nonvolatile elements incorporate quantumtrap technology producin g the world?s most reliable nonvolatile memory. the sram is read and written an infinite number of times, while independent, nonvolatile data resides in the nonvolatile elements. the real time clock function pr ovides an accurate clock with leap year tracking and a programmable high accuracy oscillator. the alarm function is programmable for one time alarm or periodic seconds, minutes, hours, or days. there is also a programmable watchdog timer for process control. store/ recall control power control software detect static ram array 1024 x 1024 quantumtrap 1024 x 1024 store recall column io column dec row decoder input buffers oe ce we hsb v cc v cap a 15 - a 0 a 0 a 1 a 2 a 3 a 4 a 10 a 11 a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 rtc mux a 16 - a 0 x 1 x 2 int v rtcbat v rtccap logic block diagram note 1. 25 ns speed in industrial temperature range is over the operating voltage range of 3.3v+ 0.3v only. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 2 of 29 contents features .............................................................................. 1 functional description ....................................................... 1 logic block diagram .......................................................... 1 contents .............................................................................. 2 pin configurations ............................................................. 3 device operation ................................................................ 4 sram read ................................................................. 4 sram write ............................................................... 4 autostore? operation ................................................... 4 hardware store (hsb) operat ion .............................. 4 hardware recall (power up) . .................................... 5 software store ........................................................... 5 software recall ......................................................... 5 data protection ............................................................. 5 noise considerations .................................................... 5 low average active power ........................................... 6 best practices ............................................................... 6 real time clock operation ................................................ 8 nvtime operation ......................................................... 8 clock operations ........................................................... 8 reading the clock ......................................................... 8 setting the clock ........................................................... 8 backup power ............................................................... 8 stopping and starting the oscillator .............................. 8 calibrating the clock ..................................................... 9 alarm ............................................................................. 9 watchdog timer ............................................................ 9 power monitor ............................................................. 10 interrupts ..................................................................... 10 interrupt register ........................................................ 10 flags register ............................................................. 10 maximum ratings ............................................................. 16 operating range .............................................................. 16 dc electrical characteristics .......................................... 16 data retention and endurance ....................................... 17 capacitance ...................................................................... 17 thermal resistance ......................................................... 17 ac test conditions .......................................................... 17 ac switching characteristics ......................................... 18 ac switching characteristics (continued) ..................... 19 autostore or power up recall .................................... 20 software controlled store/recall cycles ................ 21 hardware store cycle ................................................... 22 soft sequence commands .............................................. 22 rtc characteristics ......................................................... 23 truth table for sram operations ................................. 23 part numbering nomenclature .. ..................................... 24 ordering information ....................................................... 25 package diagrams ........................................................... 26 document history page ................................................... 27 sales, solutions, and legal information ........................ 29 worldwide sales and design support ......... ........... ..... 29 products ...................................................................... 29 [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 3 of 29 pin configurations figure 1. 48-pin ssop table 1. pin definitions pin name alt i/o type description a 0 ? a 16 input address inputs. used to select one of the 131,072 bytes of the nvsram. dq0 ? dq7 input output bidirectional data i/o lines. used as input or output lines depending on operation nc no connect no connects . this pin is not connected to the die we w input write enable input, active low . when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce e input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tri-state. x 1 output crystal connection drives crystal on start up. x 2 input crystal connection for 32.768 khz crystal. v rtccap power supply capacitor supplied backup rtc supply voltage . (left unconnected if v rtcbat is used) v rtcbat power supply battery supplied backup rtc supply voltage . (left unconnected if v rtccap is used) int output interrupt output . program to respond to the clock alarm, the watchdog timer, and the power monitor. programmable to either active hi gh (push or pull) or low (open drain). v ss ground ground for the device . must be connected to ground of the system. v cc power supply power supply inputs to the device . hsb input output hardware store busy . when low this output indicates a hardware store is in progress. when pulled low external to the chip it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore? capacitor. supplies power to nvsram during power loss to store data from sram to nonvolatile elements. v cap a 16 a 14 a 12 a 7 a 6 a 5 a 4 v cc a 15 hsb we a 13 a 8 a 9 a 11 oe a 10 dq dq7 6 dq5 ce dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 int nc nc nc v ss nc dq0 a 3 a 2 a 1 a 0 dq1 dq2 nc nc nc nc v ss nc v cc 48-ssop top view (not to scale) v rtcbat x 1 x 2 v rtccap [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 4 of 29 device operation the cy14b101k nvsram consis ts of two functional compo- nents paired in the same physical cell. the components are sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14b101k supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 200k store operations. see the ?truth table for sram operations? on page 23 for a complete description of read and write modes. sram read the cy14b101k performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0-16 determines which of the 131,072 data bytes are accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (see figure 8 on page 18). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (see figure 9 on page 18). the data outputs repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs mu st be stable before entering the write cycle and must remain stable until either ce or we go high at the end of the cycle. the data on the common i/o pins dq 0?7 is written into the memory if the data is valid t sd before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore ? operation the cy14b101k stores data to nvsram using one of three storage operations: 1. hardware store activated by hsb 2. software store activated by an address sequence 3. autostore on device power down autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14b101k. during normal operations, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 2 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 16 for the size of the v cap . the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull up should be placed on we to hold it inactive during power up. this pull up is only effective if the we signal is tri-state during power up. many mpus tri-state their controls on power up. verify this when using the pull up. when the nvsram comes out of power-on-recall, the mpu must be active or the we held inactive until the mpu comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation takes place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation took place. monitor the hsb signal by the system to dete ct if an autostore cycle is in progress. hardware store (hsb ) operation the cy14b101k provides the hsb pin for controlling and acknowledging the store operations. use the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14b101k conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is inter- nally driven low to indicate a busy condition while the store (initiated by any means) is in progress. this pin is externally pulled up if it is used to drive other inputs. figure 2. autostore mode v cc v cc v cap v cap we 10k ohm 0.1 f u [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 5 of 29 sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14b101k continues sram operations for t delay . during t delay , multiple sram read operations take place. if a write is in progress when hsb is pulled low, it is allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. during any store operation, regardless of how it is initiated, the cy14b101k continues to drive the hsb pin low, releasing it only when the store is co mplete. after completing the store operation, the cy14b101k remains disabled until the hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power up) during power up or after any low power condition (v cc cy14b101k document number: 001-06401 rev. *l page 6 of 29 low average active power cmos technology provides the cy14b101k the benefit of drawing significantly le ss current when it is cycled at times longer than 50 ns. figure 3 shows the relationship between i cc and read/write cycle time. the worst case current consumption is shown for commercial temperature range, v cc = 3.6v, and chip enable at maximum frequency. only standby current is drawn when the chip is disabled. the overall average current drawn by the cy14b101k depends on the following items: the duty cycle of chip enable the overall cycle rate for accesses the ratio of reads to writes the operating temperature the v cc level i/o loading best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of the product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites sometimes reprograms these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. the end product?s firmware should not assume that an nv array is in a set programmed state. routines that check memory content values to de termine first time syst em configuration and cold or warm boot status, must always program a unique nv pattern (for example, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufac- turing test to ensure these syst em routines work consistently. the oscen bit in the calibration register at 0x1fff8 should be set to 1 to preserve battery lif e when the system is in storage (see stopping and starting the oscillator on page 8). the vcap value specified in this data sheet includes a minimum and a maximum value size. the best practice is to meet this requirement and not exceed the maximum vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor. customers who want to use a larger vcap value to make sure there is extra store charge should discuss their vcap size selection with cypress. figure 3. current versus cycle time [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 7 of 29 table 2. mode selection ce we oe a15 ? a0 mode i/o power h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [2, 3, 4] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [2, 3, 4] notes 2. the six consecutive address locations are in the order listed. we is high during all six cycles to enable a nonvolatile cycle. 3. while there are 17 address lines on the cy14b101k, only the lower 16 lines are used to control software modes. 4. o state depends on the state of oe . the i/o table shown is based on oe low. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 8 of 29 real time clock operation nvtime operation the cy14b101k offers internal registers that contain clock, alarm, watchdog, interrupt, and co ntrol functions. rtc registers use the last 16 address locations of the sram. internal double buffering of the clock and the clock or timer information registers prevents accessing transitional internal clock data during a read or write operation. double buffering also circumvents disrupting normal timing counts or clock accuracy of the internal clock while accessing clock data. clock and alarm registers store data in bcd format. the rtc register addresses for cy14b101k range from 0x1fff0 to 0x1ffff. refer to rtc register map[6, 7] on page 12 and register map detail on page 13 for detailed description. clock operations the clock registers maintain ti me up to 9,999 years in one second increments. the user sets the time to any calendar time and the clock automatically keep s track of days of the week, month, leap years, and cent ury transitions. there are eight registers dedicated to the clock functions that are used to set time with a write cycle and to read time during a read cycle. these registers contain the time of day in bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. reading the clock the double buffered rtc register structure reduces the chance of reading incorrect data from the clock. the user should stop internal updates to the cy14b101k time keeping registers before reading clock data, to prevent reading of data in transition. stopping the internal register updates does not affect clock accuracy. the updating process is stopped by writing a ?1? to the read bit ?r? (in the flags register at 0x1f ff0), and does not restart until a ?0? is written to the read bit. the rtc registers are then read while the internal clock continues to run. after a ?0? is written to the read bit (?r?), all cy14b101k registers are simultaneously updated within 20 ms. setting the clock setting the write bit ?w? (in the flags register at 0x1fff0) to a ?1? stops updates to the time keeping registers and enables the time to be set. the correct day, date, and time are then written into the registers in 24 hour bcd forma t. the time written is referred to as the ?base time?. this value is stored in nonvolatile registers and used in calculation of the current time. resetting the write bit to ?0? transfers those values to the actual clock counters, after which the clock resumes normal operation. backup power the rtc in the cy14b101k is intended for permanently powered operations. either the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when the primary power, v cc , fails and drops below v switch , the device switches to the backup power supply. the clock oscillator uses very little current to maximize the backup time available from t he backup source. regardless of clock operation with the primary source removed, the data stored in nvsram is secure, as it is stored in the nonvolatile elements when power was lost. during backup operation, the cy14b101k consumes a maximum of 300 na at 2v. the user should choose capacitor or battery values according to the application. backup time values, based on maximum current specifications, are shown in the following table. nominal times are approxi- mately three times longer. using a capacitor has the obvious advantage of recharging the backup source each time the syst em is powered up. if a battery is used, use a 3v lithium; t he cy14b101k only sources current from the battery when the primary power is removed. however, the battery is not recharged at any time by the cy14b101k. the battery capacity is chosen for total anticipated cumulative downtime required over the life of the system. stopping and starting the oscillator the oscen bit in the calibratio n register at 0x1fff8 controls the enable and disable of the osci llator. this active low bit is nonvolatile and is shipped to customers in the ?enabled? (set to 0) state. to preserve the batte ry life when the system is in storage, oscen bit must be set to ?1?. this turns off the oscillator circuit, extending the battery life. if the oscen bit goes from disabled to enabled, it takes approximately 5 seconds (10 seconds maximum) for th e oscillator to start. while system power is off, if the voltage on the backup supply (v rtccap or v rtcbat ) falls below their res pective minimum level, the oscillator may fail.the cy14b 101k has the ability to detect oscillator failure when system power is restor ed. this is recorded in the oscf (oscillator failed bi t) of the flags register at address 0x1fff0. when the device is powered on (v cc goes above v switch ), the oscen bit is checked for ?enabled? status. if the oscen bit is enabled and the oscillator is not active within the first 5 ms, the oscf bit is se t to ?1?. the syst em must check for this condition and then write ?0 ? to clear the flag. note that in addition to setting the oscf flag bit, the time registers are reset to the ?base time? (see ?setting the clock? on page 8), which is the value last written to the time keeping registers. the control or calibration registers and t he oscen bit are not affected by the ?oscillator failed? condition. the value of oscf must be reset to ?0? when the time registers are written for the first time. this initializes the state of this bit which may have become set when the system was first powered on. to reset oscf, set the write bi t ?w? (in the flags register at 0x1fff0) to ?1? to enable writes to the flag register. write a ?0? to the oscf bit and then reset the write bit to ?0? to disable writes. table 3. rtc backup time capacitor value backup time 0.1f 72 hours 0.47f 14 days 1.0f 30 days [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 9 of 29 calibrating the clock the rtc is driven by a quartz controlled oscillator with a nominal frequency of 32.768 khz. clock accuracy depends on the quality of the crystal and calibration. the crystal oscillators typically have an error of + 20ppm to + 35ppm. however, cy14b101k employs a calibration circuit that improves the accuracy to +1/?2 ppm at 25c. this implies an error of +2.5 seconds to -5 seconds per month. the calibration circuit adds or subtra cts counts from the oscillator divider circuit to achieve this accuracy. the number of pulses that are suppressed (subtracted, negati ve calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibration register at 0x1fff8. the calibration bits occupy the five lower order bits in the calibration register. these bits are set to represent any value between ?0? and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. adding counts speeds the clock up and subtracting counts slows the clock down. if a binary ?1? is loaded into the register, it corre- sponds to an adjustment of 4.0 68 or ?2.034 ppm offset in oscil- lator error, depending on the sign. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per mi nute, have one se cond shortened by 128 or lengt hened by 256 osc illator cycles. if a binary ?1? is loaded into the register, only the first two minutes of the 64 minute cycle is modified. if a bina ry 6 is loaded, the first 12 are affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is, 4.068 or ?2.034 ppm of adjustment per calibration st ep in the calibration register. to determine the required calibration, the cal bit in the flags register (0x1fff0) must be set to ?1?. this causes the int pin to toggle at a nominal frequency of 512 hz. any deviation measured from the 512 hz indicates the degree and direction of the required correction. for exam ple, a reading of 512.01024 hz indicates a +20 ppm error. hence, a decimal value of ?10 (001010b) must be loaded into the calibration register to offset this error. note setting or changing the calibr ation register does not affect the test output frequency. to set or clear cal, set the writ e bit ?w? (in the flags register at 0x1fff0) to ?1? to enable writes to the flag register. write a value to cal, and then reset the wr ite bit to ?0? to disable writes. alarm the alarm function compares user programmed values of alarm time and date (stored in the re gisters 0x1fff1-5) with the corre- sponding time of day and date values. when a match occurs, the alarm internal flag (af) is set and an interrupt is generated on int pin if alarm interrupt enable (aie) bit is set. there are four alarm match fields - date, hours, minutes, and seconds. each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field is used in the match process. depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. selecting all match bits (all 0s) causes an exact time and date match. there are two ways to detect an alarm event: by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x1fff0 indicates that a date or time match has occurred. the af bit is set to ?1? when a match occurs. reading the flags or control register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. note cy14b101k requires the alarm match bit for seconds (0x1fff2 - d7) to be set to ?0? for proper operation of alarm flag and interrupt. alarm registers are not nonvolatile and, therefore, need to be reinitialized by software on power up. to set, clear or enable an alarm, set the ?w? bit (in flags register - 0x1fff0) to ?1? to enable writes to alarm registers. after writing the alarm value, clear the ?w? bit back to ?0? for the changes to take effect. watchdog timer the watchdog timer is a free running down counter that uses the 32 hz clock (31.25 ms) derived from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the timer consists of a loadable register and a free running counter. on power up, the watchdog time out value in register 0x1fff7 is loaded into the counter load register. counting begins on power up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to ?1?. the counter is compared to the terminal value of ?0?. if the counter reaches this value, it causes an internal flag and an optional interrupt output. you can prevent the time out interrupt by setting wds bit to ?1? prior to the counter reaching ?0 ?. this causes the counter to reload with the watchdog time out value and to be restarted. as long as the user sets the wds bit prior to the counter reaching the terminal value, the interrupt and wdt flag never occur. new time out values are written by setting the watchdog write bit to ?0?. when the wdw is ?0?, ne w writes to the watchdog time out value bits d5-d0 are enabled to modify the time out value. when wdw is ?1?, writes to bits d5 -d0 are ignored. the wdw function enables a user to set the wds bit without concern that the watchdog timer value is modified. a logical diagram of the watchdog timer is shown in figure 4 . note that setting the watchdog time out value to ?0? disables the watchdog function. the output of the watchdog timer is the flag bit wdf that is set if the watchdog is allowed to time out. the flag is set upon a watchdog time out and cleared when the user reads the flags or control registers. if the watchdog time out occurs, the user also enables an optional interrupt source to drive the int pin. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 10 of 29 power monitor the cy14b101k provides a power management scheme with power fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low v cc access. the power monitor is based on an internal band gap reference circuit that compares the v cc voltage to v switch threshold. as described in the ?autostore? operation? on page 4, when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source, read and write opera- tions to nvsram are inhibited and the clock functions are not available to the user. the clock continues to operate in the background. the updated clock data is available to the user t hrecall delay after v cc is restored to the device (see ?autostore or power up recall? on page 20). interrupts the cy14b101k has a flags register, interrupt register and interrupt logic that can signal interrupt to the microcontroller. there are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. each of these can be individually enabled to drive the int pin by app ropriate setting in the interrupt register (0x1fff6). in addition, each has an associated flag bit in the flags register (0x1fff0) that the host processor uses to determine the cause of the interrupt. the int pin driver has two bits that specify its behavior when an interrupt occurs. an interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in interrupts register is enabled (set to ?1?). af ter an interrupt source is active, two programmable bits, h/l and p/l, determine the behavior of the output pin driver on int pin. these two bits are located in the interrupt register and can be used to drive level or pulse mode output from the int pin. in pulse mode, the pulse width is internally fixed at approximately 200 ms. this mode is intended to reset a host microcontroller. in the level mode, the pin goes to its active polarity until the flags r egister is read by the user. this mode is used as an interrupt to a host microcontroller. the control bits are summarized in the following section. interrupt register watchdog interrup t enable - wie . when set to ?1?, the watchdog timer drives the int pin and an internal flag when a watchdog time out occurs. when wie is set to ?0?, the watchdog timer only affects the wdf flag in flags register. alarm interrupt enable - aie . when set to ?1?, the alarm match drives the int pin and an internal flag. when aie is set to ?0?, the alarm match only affects the af flag in flags register. power fail interrupt enable - pfe . when set to ?1?, the power fail monitor drives the pin and an internal flag. when pfe is set to ?0?, the power fail monitor only affects the pf flag in flags register. high/low - h/l . when set to a ?1?, the int pin is active high and the driver mode is push pull. the int pin drives high only when v cc is greater than v switch . when set to a ?0?, the int pin is active low and the drive mode is open drain. active low (open drain) is operational even in battery backup mode. pulse/level - p/l . when set to a ?1? and an interrupt occurs, the int pin is driven for approximatel y 200 ms. when p/l is set to a ?0?, the int pin is driven high or low (determined by h/l) until the flags or control register is read. when an enabled interrupt source activates the int pin, an external host reads the flags re gisters to determine the cause. remember that all flags are clear ed when the register is read. if the int pin is programmed for level mode, then the condition clears and the int pin returns to its inactive state. if the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. the pulse does not complete its specified duration if the flags register is read. if the int pin is used as a host reset, then the flags or control register is not read during a reset. flags register the flag register has three flag bits: wdf, af, and pf, which can be used to generate an interrupt. these flags are set by the watchdog timeout, alarm match, or power fail monitor respec- tively. the processor can either poll this register or enable inter- rupts to be informed when a flag is set. these flags are automat- ically reset once the register is read. the flags register is automatically loaded with the value 00h on power up (except for the oscf bit. see ?stopping and starting the oscillator? on page 8.) figure 4. watchdog timer block diagram 1 hz oscillator clock divider counter zero compare wdf wds load register wdw d q q watchdog register write to watchdog register 32 hz 32,768 khz [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 11 of 29 figure 5. interrupt block diagram figure 6. rtc recommende d component configuration wdf - watchdog timer flag wie - watchdog interrupt pf - power fail flag pfe - power fail enable af - alarm flag aie - alarm interrupt enable p/l - pulse level h/l - high/low enable watchdog timer power monitor clock alarm vint wdf wie pf pfe af aie p/l pin driver h/l int v cc v ss c 1 c 2 rf y 1 x 1 x 2 a 0 a 1 a 2 a 3 dq 0 recommended values y1 = 32.768 khz rf = 10 m c1 = 0 (install cap footpr int, but leave unloaded) c2 = 56 pf + 10% (do not vary from this value) note 5. schottky diodes, (v f < 0.4v at i f =100 ma) are recommended at pins a 0 - a 3 and dq 0 in applications where undershoot exceeds -0.5v. please see application note an49947 for further details. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 12 of 29 table 4. rtc register map [6, 7] register bcd format data [6] function/range d7 d6 d5 d4 d3 d2 d1 d0 0x1ffff 10s years years years: 00?99 0x1fffe 0 0 0 10s months months months: 01?12 0x1fffd 0 0 10s day of month day of month day of month: 01?31 0x1fffc 0 0 0 0 0 day of week day of week: 01?07 0x1fffb 0 0 10s hours hours hours: 00?23 0x1fffa 0 10s minutes minutes minutes: 00?59 0x1fff9 0 10s seconds seconds seconds: 00?59 0x1fff8 oscen (0) 0 cal sign (0) calibration (00000) calibration values [8] 0x1fff7 wds (0) wdw (0) wdt (000000) watchdog [8] 0x1fff6 wie (0) aie (0) pfe (0 ) 0 h/l (1) p/l (0) 0 0 interrupts [8] 0x1fff5 m (1) 0 10s alarm date alarm day alarm, day of month: 01?31 0x1fff4 m (1) 0 10s alarm hours alarm hours alarm, hours: 00?23 0x1fff3 m (1) 10 alarm minutes alarm minutes alarm, minutes: 00?59 0x1fff2 m (1) 10 alarm seconds alarm, seconds alarm, seconds: 00?59 0x1fff1 10s centuries centuries centuries: 00?99 0x1fff0 wdf af pf oscf 0 cal (0) w (0) r (0) flags [8] notes 6. ( ) designates values shipped from the factory. 7. the unused bits of rtc registers are reserved for future use and should be set to ?0?. 8. is a binary value, not a bcd value. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 13 of 29 table 5. register map detail 0x1ffff time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0?99. 0x1fffe time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibble (four bi ts) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operate s from 0 to 1. the range for the register is 1?12. 0x1fffd time keeping - date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower nibb le (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operat es from 0 to 3. the range fo r the register is 1?31. leap years are automatically adjusted for. 0x1fffc time keeping - day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble (three bits) contains a value that correlates to da y of the week. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, because the day is not integrated with the date. 0x1fffb time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibb le (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the r ange for the register is 0?23. 0x1fffa time keepin g - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and oper ates from 0 to 5. the range for the register is 0?59. 0x1fff9 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble (four bits ) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operat es from 0 to 5. the range for the register is 0?59. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 14 of 29 0x1fff8 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to 1, the oscillator is stopped. when set to 0, the oscillator runs. disabling the oscillator saves battery or capacitor power during storage. calibration sign determines if the calibration adjustment is applied as an a ddition (1) to or as a subtraction (0) from the time-base. calibration these five bits control the calibration of the clock. 0x1fff7 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to 1 reloads and restarts the watchdog timer. setting the bit to 0 has no effect. the bit is cleared automatically after the watchdog timer is reset. the wds bit is write only. reading it always returns a 0. wdw watchdog write enable. setting this bit to 1 disables any write to the watchdog timeout value (d5?d0). this allows the user to set the watchdog strobe bit without disturbing the ti meout value. setting this bit to 0 allows bits d5?d0 to be written to the watchdog register when the next write cycle is complete. this function is explained in detail in the ?watchdog timer? on page 9. wdt watchdog timeout selection. the watchdog timer interval is se lected by the 6-bit value in this register. it represents a multiplier of the 32 hz count (31.25 ms). the range of timeout va lue is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 fh). setting the watchdog timer register to 0 disables the timer. these bits can be written only if the wdw bit was set to 0 on a previous cycle. 0x1fff6 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfie 0 h/l p/l 0 0 wie watchdog interrupt enable. when set to 1 and a watchdog timeout occurs, the watchdog timer drives the int pin and the wdf flag. when set to 0, the watchdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to 1, the alarm match dr ives the int pin and the af flag. when set to 0, the alarm match only affects the af flag. pfie power fail enable. when set to 1, the alarm match drives the int pin and the pf flag. when set to 0, the power fail monitor affects only the pf flag. 0 reserved for future use h/l high/low. when set to 1, the int pin is driven active hi gh. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to 1, the int pin is driven active (d etermined by h/l) by an inte rrupt source fo r approximately 200 ms. when set to 0, the int pin is driven to an active level (as set by h/l) until the flags register is read. 0x1fff5 alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date value. m match. when this bit is set to 0, the date value is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the date value. table 5. register map detail (continued) [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 15 of 29 0x1fff4 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. when this bit is set to 0, the hours value is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the hours value. 0x1fff3 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the ma sk bit to select or deselect the minutes value. m match. when this bit is set to 0, the minutes value is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the minutes value. 0x1fff2 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the ma sk bit to select or deselect the seconds? value. m match. when this bit is set to 0, the seconds value is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the seconds value. 0x1fff1 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 10s centuries centuries contains the bcd value of centur ies. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. the range for the register is 0-99 centuries. 0x1fff0 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf 0 cal w r wdf watchdog timer flag. this read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags register is read or on power-up. af alarm flag. this read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. it is cleared when the flags register is read or on power-up. pf power fail flag. this read only bit is set to 1 when power falls below the power fail threshold v switch . it is cleared to 0 when the flags register is read or on power-up. oscf oscillator fail flag. set to 1 on power up if the oscillator is enabled and not running in t he first 5 ms of operation. thi s indicates that rtc backup power failed and clock value is no longer valid. the user must reset this bit to 0 to clear this condition (flag). the chip does not clear this flag. this bit survives power cycles. cal calibration mode. when set to 1, a 512 hz square wave is ou tput on the int pin. when set to 0, the int pin resumes normal operation. this bit defaults to 0 (disabled) on power up. w write enable: setting the w bit to 1 freezes updates of the rtc registers. the user can then write to rtc registers, alarm registers, calibration register, interrupt register and flags register. setting the w bit to 0 causes the contents of the rtc registers to be transferred to the time keeping counters if the time has been changed (a new base time is loaded). this bit defaults to 0 on power up. r read enable: setting r bit to 1, stops clock updates to us er rtc registers so that cl ock updates are not seen during the reading process. set r bit to 0 to resume clock updates to the holding register. setting this bit does not require w bit to be set to 1. this bit defaults to 0 on power up. table 5. register map detail (continued) [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 16 of 29 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +125 c supply voltage on v cc relative to gnd ... .......?0.5v to 4.1v voltage applied to outputs in high z state ....................................... ?0.5v to v cc + 0.5v input voltage...........................................?0.5v to vcc + 0.5v transient voltage (<20 ns) on any pin to ground potential .............. .... ?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount pb soldering temperature (3 seconds).......................................... +260 c dc output current (1 output at a time, 1s duration) ... 15 ma static discharge voltage.......................................... > 2001v (mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c dc electrical characteristics over the operating range (vcc = 2.7v to 3.6v) [9, 10] parameter description test conditions min max unit i cc1 average v cc current t rc = 25 ns t rc = 35 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. commercial 65 55 50 ma ma industrial 70 60 55 ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store 6ma i cc3 average v cc current at t avav = 200 ns, 3v, 25c typical we > (v cc ? 0.2v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 10 ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store 3ma i sb v cc standby current we > (v cc ? 0.2v). all others v in < 0.2v or > (v cc ?0.2v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz 3ma i ix input leakage current v cc = max, v ss < v in < v cc ?1 +1 a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih ?1 +1 a v ih [11] input high voltage 2.0 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 17 120 f notes 9. the hsb pin has i out = ?10 a for v oh of 2.4 v, this parameter is characterized but not tested. 10. the int pin is open drain and does not source or sink current when interrupt register bit d3 is low. 11. v ih changes by 100 mv when v cc > 3.5v. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 17 of 29 data retention and endurance parameter description min unit data r data retention 20 years nv c nonvolatile store operations 200 k capacitance these parameters are guaranteed but not tested. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0 v 7 pf c out output capacitance 7pf thermal resistance these parameters are guaranteed but not tested. parameter description test conditions 48-ssop unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 34.85 c/w jc thermal resistance (junction to case) 16.35 c/w figure 7. ac test loads ac test conditions 3.0v output 5 pf r1 577 r2 789 3.0v output 30 pf r1 577 r2 789 for tri-state specs input pulse levels ..................................................0 v to 3 v input rise and fall times (10% - 90%)........................ < 5 ns input and output timing referenc e levels ......... .......... 1.5 v [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 18 of 29 ac switching ch aracteristics parameter description 25 ns [1] 35 ns 45 ns unit min max min max min max cypress parameter alt. parameter sram read cycle t ace t elqv chip enable access time 25 35 45 ns t rc [12] t avav, t eleh read cycle time 25 35 45 ns t aa [13] t avqv address access time 25 35 45 ns t doe t glqv output enable to data valid 12 15 20 ns t oha [13] t axqx output hold after address change 3 3 3 ns t lzce [14] t elqx chip enable to output active 3 3 3 ns t hzce [14] t ehqz chip disable to output inactive 10 13 15 ns t lzoe [14] t glqx output enable to output active 0 0 0 ns t hzoe [14] t ghqz output disable to output inactive 10 13 15 ns t pu [15] t elicch chip enable to power active 0 0 0 ns t pd [15] t ehiccl chip disable to power standby 25 35 45 ns figure 8. sram read cycle 1: address controlled [12, 13, 16] figure 9. sram read cycle 2: ce and oe controlled [12, 16] w 5& w $$ w 2+$ $''5(66 '4'$7$287 '$7$9$/,' $''5(66 w 5& &( w $&( w /=&( w 3' w +=&( 2( w '2( w /=2( w +=2( '$7$9$/,' $&7,9( 67$1'%< w 38 '4'$7$287 ,&& notes 12. we is high during sram read cycles. 13. device is continuously selected with ce and oe both low. 14. measured 200 mv from steady state output voltage. 15. these parameters are guaranteed by design and are not tested. 16. hsb must remain high during read and write cycles. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 19 of 29 ac switching ch aracteristics (continued) parameter description 25 ns [1] 35 ns 45 ns unit min max min max min max cypress parameter alt. parameter sram write cycle t wc t avav write cycle time 25 35 45 ns t pwe t wlwh, t wleh write pulse width 20 25 30 ns t sce t elwh, t eleh chip enable to end of write 20 25 30 ns t sd t dvwh, t dveh data setup to end of write 10 12 15 ns t hd t whdx, t ehdx data hold after end of write 0 0 0 ns t aw t avwh, t aveh address setup to end of write 20 25 30 ns t sa t avwl, t avel address setup to start of write 0 0 0 ns t ha t whax, t ehax address hold after end of write 0 0 0 ns t hzwe [14, 17] t wlqz write enable to output disable 10 13 15 ns t lzwe [14] t whqx output active after end of write 3 3 3 ns figure 10. sram write cycle 1: we controlled [16, 18] figure 11. sram write cycle 2: ce controlled t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 17. if we is low when ce goes low, the outputs remain in the high impedance state. 18. ce or we are greater than v ih during address transitions. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 20 of 29 autostore or power up recall parameter description cy14b101k unit min max t hrecall [19] power up recall duration 40 ms t store [20, 21] store cycle duration commercial 12.5 ms industrial 15 ms v switch low voltage trigger level 2.65 v t vccrise vcc rise time 150 s figure 12. autostore/power up recall v cc v switch t store t store t hrecall t hrecall autostore power-up recall read & write inhibited store occurs only if a sram write has happened no store occurs without atleast one sram write t vccrise notes 19. t hrecall starts from the time v cc rises above v switch . 20. if an sram write does not taken place since t he last nonvolatile cycle, no store takes place. 21. industrial grade devices require 15 ms max. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 21 of 29 software controlled store/recall cycles [22, 23] parameter alt. parameter description 25 ns [1] 35 ns 45 ns unit min max min max min max t rc t avav store/recall initiation cycle time 25 35 45 ns t sa t avel address setup time 0 0 0 ns t cw t eleh clock pulse width 20 25 30 ns t ha t ehax address hold time 1 1 1 ns t recall recall duration 170 170 170 s figure 13. ce controlled software store/recall cycle [23] figure 14. oe controlled software store/recall cycle [23] t rc t rc t sa t sce t ha t store / t recall data valid data valid 6#sserdda 1#sserdda high impedance address ce oe dq (data) t rc t rc 6#sserdda 1#sserdda address t sa t sce t ha t store / t recall data valid data valid high impedance ce oe dq (data) notes 22. the software sequence is clocked with ce controlled or oe controlled reads. 23. the six consecutive addresses are read in the order listed in the table 2 on page 7. we is high during all six consecutive cycles. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 22 of 29 hardware store cycle parameter alt. parameter description cy14b101k unit min max t delay [26] time allowed to comp lete sram cycle 1 70 s t phsb t hlhx hardware store pulse width 15 ns figure 15. hardware store cycle soft sequence commands parameter description cy14b101k unit min max t ss [23, 25] soft sequence processing time 70 s figure 16. soft sequence processing [23, 25] w +/+; w 6725( w +/%/ w '(/$< '$7$9$/,' '$7$9$/,' +,*+,03('$1&( +,*+,03('$1&( +6%,1 '4'$7$287 +6%287 w 3+6% $gguhvv $gguhvv $gguhvv $gguhvv 6riw6htxhqfh &rppdqg w 66 w 66 &( $gguhvv 9 && w 6$ w &: 6riw6htxhqfh &rppdqg w &: notes 24. this is the amount of time it takes to take action on a soft sequence command. vcc power must re main high to effectively reg ister command. 25. commands such as store and recall lock out i/o until operation is complete which further increas es this time. see specific c ommand. 26. read and writ e cycles in progress before hsb are given this amount of time to complete. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 23 of 29 rtc characteristics parameter description test conditions min max unit i bak [27] rtc backup current commercial 300 na industrial 350 na v rtcbat [28] rtc battery pin voltage 1.8 3.3 v v rtccap [29] rtc capacitor pin voltage 1.2 2.7 v tocs rtc oscillator time to start at min temperature from power up or enable 10 sec at 25 c temperature from power up or enable 5 sec truth table for sram operations hsb should remain high for sram operations. ce we oe inputs and outputs mode power h x x high z deselect/power down standby l h l data out (dq 0 ?dq 7 ); read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ); write active notes 27. from either v rtccap or v rtcbat. 28. typical = 3.0v during normal operation. 29. typical = 2.4v during normal operation. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 24 of 29 part numbering nomenclature option: t - tape and reel blank - std. speed: 25 - 25 ns data bus: k - x8 + rtc density: 101 - 1 mb voltage: b - 3.0v cypress nvsram 14 - autostore + software store + hardware store package: sp - 48 ssop 35 - 35 ns temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) pb-free cy 14 b 101 k - sp 25 x c t 45 - 45 ns [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 25 of 29 ordering information these parts are not recommended for new designs. speed (ns) ordering code package diagram operating voltage range package type operating range 25 cy14b101k-sp25xc 51-85061 2.7v to 3.6v 48-pin ssop commercial cy14b101k-sp25xct cy14b101k-sp25xi 51-85061 3.0v to 3.6v 48-pin ssop industrial cy14b101k-sp25xit 35 cy14b101k-sp35xc 51-85061 2.7v to 3.6v 48-pin ssop commercial cy14b101k-sp35xct cy14b101k-sp35xi 51-85061 2.7v to 3.6v 48-pin ssop industrial CY14B101K-SP35XIT 45 cy14b101k-sp45xc 51-85061 2.7v to 3.6v 48-pin ssop commercial cy14b101k-sp45xct cy14b101k-sp45xi 51-85061 2.7v to 3.6v 48-pin ssop industrial cy14b101k-sp45xit all these parts are pb-free. contact your local cypress sales represen tative for availability of these parts. [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 26 of 29 package diagrams figure 17. 48-pin shrunk small outline package (51-85061) 51-85061 *d [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 27 of 29 document history page document title: cy14b101k 1 mbit (128 k x 8) nvsram with real time clock document number: 001-06401 rev. ecn no. orig. of change submission date description of change ** 425138 tup see ecn new data sheet *a 437321 tup see ecn show data sheet on external web *b 471966 tup see ecn changed i cc3 from 5 ma to 10 ma changed isb from 2 ma to 3 ma changed v ih(min) from 2.2v to 2.0v changed t recall from 40 ms to 100 ms changed endurance from 1 million cycles to 500k cycles changed data retention from 100 years to 20 years added soft sequence processing time waveform updated part numbering nomenclature and ordering infor- mation added rtc characteristics table added rtc recommended component configuration *c 503272 pci see ecn changed from advance to preliminary changed the term ?unlimited? to ?infinite? changed endurance from 500k cycles to 200k cycles added temperature spec. to data retention - 20 years at 55c removed icc 1 values from the dc table for 25 ns and 35 ns industrial grade changed icc 2 value from 3 ma to 6 ma in the dc table added a footnote on v ih added footnote 18 related to using the software command changed v switch(min) from 2.55v to 2.45v updated part nomenclature table and ordering information table *d 597002 tup see ecn removed v switch(min) specification from the autostore/power up recall table changed t glax specification from 20 ns to 1 ns added t delay(max) specification of 70 ms in the hardware store cycle table removed t hlbl specification changed t ss specification form 70 ms (min) to 70 ms (max) changed v cap(max) from 57 mf to 120 mf *e 688776 vkn see ecn added footnote 7 related to hsb added footnote 8 related to int pin changed t glax to t ghax removed abe bit from interrupt register *f 1349963 uha/sfv see ecn changed from preliminary to final added note 5 regarding the w bit in the flag register updated ordering information table *g 1739984 vsutmp8/aesa see ecn added pinout diagram and pin definition table *h 2427986 gvch/pyrs 04/23/08 move to external web [+] feedback not recommended for new designs
cy14b101k document number: 001-06401 rev. *l page 28 of 29 *i 2663934 gvch/pyrs 02/24/09 updated features updated pin definition of we removed autostore enable/disable section added best practices updated ?reading the clock?, ?backup power?, ?stopping and starting the oscillator? and ?alarm? descriptions under rtc operation modified ?figure 4. rtc recommended component configu- ration? added footnotes 4, 5 and 6 added default values to rtc register map? table updated flag register description in register map detail? table added industrial specs for 25ns and 35ns speed changed v ih from vcc+0.3 to vcc+0.5 added ?data retention and endurance? table on page 15 added thermal resistance values added alternate parameters in t he ac switching characteristics table renamed t oh to t oha changed t hrecall from 20 to 40ms changed t recall spec from 100 s to 170 s (including t ss of 70us) renamed t as to t sa renamed t ghax to t ha updated figure 13, 14, 15 and 16 renamed t hlhx to t phsb added truth table for sram operations *j 2815609 gvch 11/26/09 added note in the ordering information table and watermark to state that the parts in this data sheet are not recommended for new designs. added the contents page. *k 2895330 gvch 03/18/10 added foot note 1 for 25ns access speed. updated package diagram. added operating voltage range column to ordering information *l 2902517 gvch 03/31/2010 added watermark "not recommended for new designs" in pdf version. move to external web. document title: cy14b101k 1 mbit (128 k x 8) nvsram with real time clock document number: 001-06401 rev. ecn no. orig. of change submission date description of change [+] feedback not recommended for new designs
document number: 001-06401 rev. *l revised april 5, 2010 page 29 of 29 autostore and quantumtrap are registered trademarks of cypress semiconductor corporation. all products and company names mentio ned in this document are the trademarks of their respective holders. cy14b101k ? cypress semiconductor corporation, 2006-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representative s, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback not recommended for new designs

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