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HM62G18256 series 4m synchronous fast static ram (256k-words x 18-bits) ade-203-1007(z) preliminary, rev. 0.0 feb. 5, 1999 features 3.3v+10%, C5% operation 4m bit density 200mhz - 250mhz frequency synchronous operation internal self-timed late write byte write control (2byte write selects, one for each 9 bits) optional x 36 configuration hstl compatible i/o programmable impedance output drivers user selective input trip - point differential , hstl clock inputs asynchronous g output control asynchronous sleep mode bga 119pin package limited set of boundary scan jtag ieee 1149.1 compatible protocol : single clock register-register mode ordering information type number access time cycle time package HM62G18256bp-5 HM62G18256bp-4 2.5 ns 2.2 ns 5.0 ns 4.0 ns 119 bump 1. 27 mm 14 mm x 22 mm bga (bp-119a)
HM62G18256 series 2 pin arrangement 1234567 a b c d e f g h j k l m n p r t u vddq sa0 sa6 nc sa4 sa2 vddq nc nc sa7 nc sa8 nc nc nc sa13 sa3 vdd sa5 sa1 nc dqb0 nc vss zq vss dqa4 nc nc dqb1 vss ss vss nc dqa5 vddq nc vss g vss dqa6 vddq nc dqb2 sweb nc nc dqa7 dqb3 nc vss nc vss dqa8 nc vddq vdd vref vdd vref vdd vddq nc dqb8 vss k vss nc dqa3 dqb7 nc k swea dqa2 nc vddq dqb6 vss swe vss nc vddq dqb5 nc vss sa16 vss dqa1 nc nc dqb4 vss sa14 vss nc dqa0 nc sa9 m1 vdd m2 sa10 nc nc sa17 sa11 nc sa12 sa15 zz vddq tms tdi tck tdo nc vddq (top view) vss vss
HM62G18256 series 3 block diagram a0- a17 jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag tap controller r-add register1 ss register swe register swex register w-add register ss swe swex g zz vref zq tdi tck tms tdo dqa0-8 dqb0-8 k k mux row decoder multiplex 18 2 18 2 18 18 1 wrc doc d-out register ob d-in register wa sa match column decoder memory cell array (256kx18) clk ctrl impedance contorol logic
HM62G18256 series 4 pin descriptions name i/o type descriptions note v dd supply core power supply v ss supply ground v ddq supply output power supply v ref supply input reference : provides input reference voltage k input clock input. active high. k input clock input. active low. ss input synchronous chip select swe input synchronous write enable san input synchronous address input n=0,1,2...17 swex input synchronous byte write enables x = a, b g input asynchronous output enable zz input power down mode select zq input output impedance control 1 dqxn i/o synchronous data input / output x = a, b n=0,1,2...8 m1, m2 input output protocol mode select tms input boundary scan test mode select tck input boundary scan test clock tdi input boundary scan test data input tdo output boundary scan test data output nc no connection m1 m2 protocol v ss v dd synchronous register to register operation 2 notes: 1. zq is to be connected to vss via a resistance rq where 150 w rq 350 w , if zq=v ddq or open, output buffer impedance will be maximum. a case of minimum impedance, it needs to connect over 120 w between zq and vss. 2. there is 1 protocol with mode pin. mode control pins( m1 , m2 ) are to be tied either v dd or vss. the state of the mode control inputs must be set before power-up and must not change during device operation. mode control inputs are not standard inputs and may not meet vih or vil specification.
HM62G18256 series 5 truth table zz ss g swe swea sweb k k operation dq(n) dq(n+1) h x x x x x x x sleep mode high-z high-z l h x x x x l-h h-l dead (not selected) x high-z l x h x x x x x dead (dummy read) high-z high-z l l l h x x l-h h-l read x dout(a,b) 0-8 l l x l l l l-h h-l write a, b byte high-z din(a,b)0- 8 l l x l l h l-h h-l write a byte high-z din(a)0-8 l l x l h l l-h h-l write b byte high-z din(b)0-8 notes: 1. x means dont care for synchronous inputs, and h or l for asynchronous inputs. 2. swe , ss , swea to sweb , sa are sampled at the rising edge of k clock. 3. although differential clock operation is implied, this sram will operate properly with one clock phase (either k or k )tied to vref. under such single-ended clock operation, all parameters specification within this document will be met.
HM62G18256 series 6 absolute maximum ratings parameter symbol rating unit note input voltage on any pin v in -0.5 to v ddq +0.5 v 1, 4 core supply voltage v dd -0.5 to 3.9 v 1 output supply voltage v ddq -0.5 to 2.2 v 1, 4 operating temperature t opr 0 to 70 c storage temperature t stg -55 to 125 c output shortCcircuit current i out 25 ma latch up current i li 200 ma package junction to case thermal resistance q jc 2 c/w 5,7 package junction to ball thermal resistance q jb 5 c/w 6,7 notes: 1. all voltage are referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then vin. remember, according to the absolute maximum ratings table, v ddq is not to exceed 3.9v, whatever the instantaneous value of v ddq . 5. q jc is measured at the center of mold surface in fluorocarbon.(see fig1.) 6. q jb is measured on the center ball pad after removing the ball in fluorocarbon. (see fig1.) 7. these thermal resistance value have error of +/- 5 c/w. fig.1 definition of measurement q jc q jb t.c. fluorocarbon t.c. fluorocarbon
HM62G18256 series 7 recommended dc operating conditions (ta = 0 to 70 c [tj max = 110 c]) parameter symbol min typ max unit notes power supply voltage -- core v dd 3.135 3.30 3.63 v power supply voltage -- i/o v ddq 1.4 1.5 1.6 v input reference voltage -- i/o v ref 0.65 0.75 0.90 v 1 input high voltage v ih v ref +0.1 v ddq +0.3 v input low voltage v il C0.5 v ref C0.1 v clock differential voltage v dif 0.1 v ddq +0.3 v 2, 3 clock common mode voltage v cm 0.55 0.90 v 3 notes : 1. peak to peak ac component superimposed on v ref may not exceed 5% of v ref . 2. minimum differential input voltage required for differential input clock operation. 3. see figure 1. vddq vss v dif v cm figure 1. diffrential voltage / common mode voltage
HM62G18256 series 8 dc characteristics (ta = 0 to 70 c, [tjmax=110?c], v dd = 3.3v+10%, C5%) parameter symbol min max unit note input leakage current i li 2 m a1 output leakage current i lo 5 m a2 standby current i sbzz 100 ma 3 vdd operating current, excluding output drivers. 4ns cycle i dd4 500 ma 4 5ns cycle i dd5 500 ma 4 quiescent active power supply current. i dd2 180 ma 5 parameter symbol min typ max unit note output low voltage v ol v ss v ss +0.4 v 6 output high voltage v oh v ddq C0.4 v ddq v6 zq pin connect resistance rq 150 250 350 w output low current i ol (v ddq /2)/[(rq/5)C15%] (v ddq /2)/[(rq/5)+15%] ma 7,9 output high current i oh (v ddq /2)/[(rq/5)+15%] (v ddq /2)/[(rq/5)C15%] ma 8,9 note: 1. 0 vin v ddq for all input pins( except v ref ,zq,m1,m2 pin) 2. 0 vout v ddq , dq in highCz 3. all inputs (except clock) are held at either vih or vil,zz is held at vih,iout=0 ma 4. iout = 0 ma, read 50% / write 50%, v dd = v dd max , frequency =min.cycle 5. iout = 0 ma, read 50% / write 50%, v dd = v dd max , frequency = 3 mhz 6. minimum impedance push pull output buffer mode, i oh =C6ma, i ol =6ma 7. measured at v ol =1/2 v ddq 8. measured at v oh =1/2 v ddq 9. output buffer impedance can be programmed by terminating the zq pin to vss through a precision resister(rq). the value of rq is five times the output impedance desired. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 150 w and 350 w . if the status of zq pin is open , output impedance is maximum. maximum impedance occurs with zq connected to vddq. the impedance update of the output driver occurs when the sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high-z, therefore triggering an update. the user may choose to invoke asynchronous g updates by providing a g setup and hold about the k clock to guarantee the proper update. at power up, the output impedance default to minimum impedance. it will take 1024 cycles for the impedance to be completely updated if the programmed impedance is much higher than minimum impedance.
HM62G18256 series 9 ac characteristics (0?c ta 70?c [tj max = 110 c], v dd = 3.3v+10%, C5%) single differential clock register-register mode (m1 = v ss , m2 = v dd ) C 4 C 5 parameter symbol min max min max unit notes ck clock cycle time t khkh 4.0 5.0 ns ck clock high width t khkl 1.5 1.5 ns ck clock low width t klkh 1.5 1.5 ns address setup time t avkh 0.5 0.5 ns data setup time t dvkh 0.5 0.5 ns address hold time t khax 0.75 1) 1.0 ns data hold time t khdx 0.75 1) 1.0 ns clock high to output valid t khqv 2.2 2.5 ns 2 clock high to output hold t khqx 0.5 0.5 ns 2 clock high to output valid(/ss ctrl.) t khqx2 2.2 2.5 ns 2,5 clock high to output high-z t khqz 2.5 3.0 ns 2,3 output enable low to output low-z t glqx 0.5 0.5 ns 2,5 output enable low to output valid t glqv 2.5 2.5 ns 2,3 output enable low to output high-z t ghqz 2.5 2.5 ns 2,3 sleep mode recovery time t zzr 10.0 10.0 ns sleep mode enable time t zze 10.0 10.0 ns 2,3 notes: 1. guaranteed by design. 2. see ac test loading figure. 3. transitions are measured at start point of output high impedance from output low impedance. 4. output driver impedance update specifications for g induced updates. write and deselected cycles will also induce output driver updates during high-z. 5. transitions are measured 50mv from steady state voltage.
HM62G18256 series 10 read cycle 1 k k sa a1 a2 a3 a4 ss swe swex dq do 1 do 0 do 2 t khkh t avkh t khax t avkh t khax t avkh t khax t khqx t khqv t khkl t klkh read cycle 2 ( ss controlled) k k sa ss swe swex dq do 1 do 3 t khkh t klkh t avkh t avkh t khax t khax t avkh t khax t klqx2 t khkl a1 a3 a4 t khqz do 0 notes:g,zz=vil,x=a,b
HM62G18256 series 11 read cycle 3 (/g controlled) k k sa a1 a2 a3 a4 ss swe swex g dq do 3 t khkh t avkh t khax t avkh t khax t ghqz t glqv t glqx t avkh t khax t klkh t khkl do 1 do 0 write cycle k k sa ss swe swex dq di 0 di 1 di 2 di 3 g t khkh t avkh t khax t avkh t khax t avkh t khax t avkh t khax t dvkh t khdx t klkh t khkl a1 a2 a3 a4 notes:zz=vil,x=a,b
HM62G18256 series 12 read-write cycle read t khkh write t khkl t klkh read (g control) (ss control) read dead write a7 a6 a4 a3 a1 t avkh t avkh t khax t avkh t khax t glqx t ghqz t khqz t dvkh t khdx t glqv t khqv t khqx do 0 do 1 do 4 di 3 di 6 t avkh t khax t khax k k sa ss swe swex g dq zz control t khkl t klkh t khkh sleep active sleep active sleep off a1 t avkh t khax t zze t zzr do1 t avkh t khax k k sa ss swe swex zz dq notes: g,zz=vil,x=a,b
HM62G18256 series 13 input capacitance (ta = 25 c, f = 1 mhz) parameter symbol min max unit pin name input capacitance c in 4 pf san, ss , swe , swex clock input capacitance c clk 7 pf k, k , g i/o capacitance c io 5 pf dqxn note : this parameter is sampled and not 100% tested. ac test conditions parameter symbol conditions unit note input and output timing reference levels v ref 0.75 v input signal amplitude v il , v ih 0.25 to 1.25 v input rise / fall time tr, tf 0.5 (10% to 90%) ns clock input timing reference level differential cross point v dif to clock 0.75 v v cm to clock 0.75 v output loading conditions see figures note : measurement condition is the minimum impedance push pull output buffer mode, i oh =-6ma,i ol =6ma 50 w 16.7 w 16.7 w 50 w 5pf dq 0.75v 50 w 16.7 w 50 w 5pf 0.75v 0.75v
HM62G18256 series 14 boundary scan test access port operations overview in order to perform the interconnect testing of the modules that include this sram, the serial boundary scan test access port (tap) is designed to operate in a manner consistent with ieee standard 1149.1 - 1990. but does not implement all of the functions required for 1149.1 compliance the hm62g series contains a tap controller. instruction register, boundary scan register, bypass register and id register. test access port pins symbol i/o name tck test clock tms test mode select tdi test data in tdo test data out notes: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. to disable the tap, tck must be connected to vss. tdo should be left unconnected. to test boundary scan, zz pin need to be kept below vref C0.4v. tap dc operating characteristics (ta = 0?c to 70?c [tj max = 110 c]) parameter symbol min max note boundary scan input high voltage v ih 2.0 v v dd + 0.3 v boundary scan input low voltage v il C0.5 v 0.8 v boundary scan input leakage current i li C2 m a+2 m a1 boundary scan output low voltage v ol 0.4 v 2 boundary scan output high voltage v oh 2.4 v 3 notes: 1. 0 vin v dd for all logic input pin 2. i ol = C8 ma 3. i oh = 8 ma
HM62G18256 series 15 tap ac operating characteristics (ta = 0?c to 70?c [tj max = 110 c]) parameter symbol min max unit note test clock cycle time t thth 67 ns test clock high pulse width t thtl 30 ns test clock low pulse width t tlth 30 ns test mode select setup t mvth 10 ns test mode select hold t thmx 10 ns capture setup t cs 10 ns 1 capture hold t ch 10 ns 1 tdi valid to tck high t dvth 10 ns tck high to tdi dont care t thdx 10 ns tck low to tdo unknown t tlqx 0ns tck low to tdo valid t tlqv 20ns note: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture.
HM62G18256 series 16 tap ac test conditions temperature 0 c ta 70 c [tj max = 110 c] input timing measurement reference level 1.5 v input pulse levels 0 to 3.0 v input rise/fall time 2.0 ns typical (10% to 90%) output timing measurement reference level 1.5 v test load termination supply voltage (v t ) 1.5 v output load see figures v t 50 w z 0 = 50 w dut tdo boundary scan ac test load
HM62G18256 series 17 tap controller timing diagram tap controller timing diagram tck tms tdi tdo ram address t thth t thtl t tlth t mvth t thmx t thdx t dvth t tlqv t tlqx t cs t ch test access port registers register name length symbol note instruction register 3 bits ir [0;2] bypass register 1 bits bp id register 32 bits id [0;31] boundary scan register 51 bits bs [1;51] HM62G18256 series
HM62G18256 series 18 tap controller instruction set ir2 ir1 ir0 instruction operation 0 0 0 sample-z tristate all data drivers and capture the pad value 0 0 1 idcode 0 1 0 sample-z tristate all data drivers and capture the pad value 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note: this device does not perform extest, intest or the preload portion of the preload command in ieee 1149.1.
HM62G18256 series 19 boundary scan order bit # bump id signal name bit # bump id signal name 15rm2 363g sweb 2 6t sa15 37 4d zq 3 4p sa14 38 4e ss 4 6r sa10 39 4g nc 5 5t sa12 40 4h nc 67tzz 414m swe 7 7p dqa0 42 2k dqb8 8 6n dqa1 43 1l dqb7 9 6l dqa2 44 2m dqb6 10 7k dqa3 45 1n dqb5 11 5l swea 46 2p dqb4 12 4l k 47 3t sa11 13 4k k 48 2r sa9 14 4f g 49 4n sa16 15 6h dqa8 50 2t sa17 16 7g dqa7 51 3r m1 17 6f dqa6 18 7e dqa5 19 6d dqa4 20 6a sa2 21 6c sa1 22 5c sa5 23 5a sa4 24 6b nc 25 5b sa8 26 3b sa7 27 2b nc 28 3a sa6 29 3c sa3 30 2c sa13 31 2a sa0 32 1d dqb0 33 2e dqb1 34 2g dqb2 35 1h dqb3 notes: 1. bit#1 is the first scan bit to exit the chip.
HM62G18256 series 20 2. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a place holder. place holder registers are internally connected to vss. 3. in boundary scan mode, differential input k and k are referenced to each other and must be at opposite logic levels for reliable operation. 4. zz must remain at v il during boundary scan. 5. in boundary scan mode, zq must be driven to vddq or vss supply rail to ensure consistent results. 6. m1 and m2 must be driven to vdd or vss supply rail to ensure consistent results. id register bit# value vendor revision no. depth width use in the future vendor id no. fix 31 x 30 x 29 x 28 1 27 0 26 0 25 1 24 1 23 0 22 0 21 0 20 0 19 1 18 1 17 0 16 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 1 0 1
HM62G18256 series 21 tap controller state diagram 1 0 test-logic- reset run-test/ idle select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select- ir-scan 1 1 1 1 0 0 0 0 00 0 0 00 1 1 1 1 1 1 1 0 00 0 1 1 1 1 0 note: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck.
HM62G18256 series 22 package outline (bp-119a) (unit : mm) -a- -b- -c- 14.00 22.00 0.35 0.15 4xc1.2 pin 1 index c f 0.30 hitaci code jedec code eiaj code weight bp-119a conforms 1.2g c f 0.15 ab 13.0 0.10 0.60 0.10 2.10 0.25 c c 0.20 6 x 1.27 16 x 1.27 21.0 0.10 a 4x 119x f0.75 0.15 details of the part a m m
HM62G18256 series 23 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products.
HM62G18256 series 24 hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: revision record rev. date contents of modification drawn by approved by 0.0 feb. 05,1999 initial release m. ikeda s.nakazato

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