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december 2009 ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays click to see this datasheet in simplified chinese! fin324c 24-bit ultra-low power serializer / deserializer supporting single and dual displays features ultra-low operating power: ~4ma at 5.44mhz supports dual-display impl ementations with rgb or microcontroller interface no external timing reference needed spi mode support single device operates as a serializer or deserializer direct support for motorola ? -style r/w microcontroller interface direct support for intel ? -style /we, /re microcontroller interface 15mhz maximum strobe frequency utilizes fairchild?s proprietary ctl serial i/o technology available in bga and mlp packages wide parallel supply voltage range: 1.60 to 3.0v low power core operation: v dds/a =2.5 to 3.0v voltage translation capability across pair with no external components high esd protection: >15kv iec 61000 power-saving burst-mode operation applications single or dual 16/18-bit rgb cell phone displays ? single or dual 16/18-bit cell phone displays with microcontroller interface ? single or dual mobile display at qvga or hvga resolution description the fin324c is a 24-bit serializer / deserializer with dual strobe inputs. the device can be configured as a master or slave device thr ough the master/slave select pin (m/s). this allows for the same device to be used as either a serializer or deser ializer, minimizing component types in the system. the dual strobe inputs allow implementation of dual-display systems with a single pair of serdes. the fin324c can accommodate rgb, microcontroller, or spi mode interfaces. read and write transactions are supported when operating with a microcontroller interface for one or both displays. unlike other serdes solutions, no external timing reference is required for operation. the fin324c is designed for ultra-low power operation. reset (/res) and standby (/stby) signals put the device in an ultra-low power state. in standby mode, the outputs of the slave device maintain state, allowing the system to resume operation from the last-known state. the device utilizes fairchild?s proprietary ultra-low power, low-emi current transfer logic? (ctl) technology. the serial interface disables between transactions to minimize emi at the serial interface and to conserve power. cmos parallel output buffers have been implemented with slew rate control to adjust for capacitive loading and to minimize emi. related application notes for additional information, please visit: http://www.fairchildsemi.com/userdes. ? an-5058 serdes? frequently asked questions ? an-5061 serdes? layout guidelines ? an-6047 fin324c reset and standby
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 2 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays ordering information order number operating temperature range package description eco status packing method fin324cmlx -30 to 85c 40-terminal molded leadless package (mlp), quad, jedec mo-220, 6mm square green tape & reel FIN324CGFX -30 to 85c 42-ball, ultra small scale ball grid array (uss-bga), jedec mo-195, 3.5 x 4.5mm wide, 0.5mm ball pitch rohs tape & reel for fairchild?s definition of ?green? eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . typical application diagram baseband / microprocessor fin324 2 we/pclk data/control 24 fin324 cks ds lcd ?a? lcd ?b? we / pclk we / pclk data / control 24 supports optional secondary display figure 1. typical application diagram
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 3 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays pin definitions pin i/o type # pins description of signals m/s cmos in 1 master/slave control input: the master is tied to the processor. the slave is tied to the display(s). m/s=1 master, m/s=0 slave /res cmos in 1 reset and power-down signal /res=0: resets and powers down all circuitry /res=1: device enabled /stby cmos in 1 master standby signal /stby=0: device powered down /stby=1: device enabled slew cmos in 1 slave output slew rate control slew=1: fast edge rate slew=0: slow edge rate par/spi cmos in 1 parallel / spi display interface select par/spi=1: parallel interface par/spi=0: spi interface using strb0 and wclk0 cksel cmos in 1 master clock source select input. cksel=1: strb1 and wclk1 active cksel=0: strb0 and wclk0 active dp[17:0] cmos i/o 18 parallel data i/o. i/o direction controlled by m/s pin and r/w internal state. dp[6] spi mode sclk signal pin when par/spi=0 (slave only) dp[7] spi mode sdat signal pin when par/spi=0(slave only) cntl[5:0] cmos i/o 6 parallel data i/o. i/o direction controlled by m/s pin m/s=1: inputs m/s=0: outputs r/w cmos i/o 1 read / write input control or output signal. m/s=1: input m/s=0: output functional operation: r/w=1: read r/w=0: write strb0 strb1 cmos in 2 word latch or pixel clock input. wclk0 wclk1 cmos out 2 word latch or pixel clock output. sclk sdat /cs cmos i/o 2 spi mode signal pins. the master sclk input is shared with cntl[5] when m/s=1 and pari/spi=0. the master sdat input is shared with cntl[4] when m/s=1 and pari/spi=0. the master /cs input is shared with strb0 when m/s=1 and par/spi=0. the slave sclk output is shared with dp[6] and cntl[5] when m/s=0 and par/spi=0. the slave sdat output is shared with dp[7] and cntl[4] when m/s=0 and par/spi=0. the slave /cs output is shared with wclk0 when m/s=0 and par/spi=0. cks+ cks- differential serial i/o 2 serial clock differential signal (1) ds+ ds- differential serial i/o 2 serial data differential signal (1) vddp supply 1 power supply for parallel i/o and internal circuitry. vdds supply 1 power supply for serial i/o. vdda supply 1 power supply for internal bit clock generator. gnd supply 1-3 ground pins: bga - c1 and d2; e3 is for supplier use only and must be tied to ground. mlp - center pad; pin 12 is for supplier use only and must be tied to ground. note: 1. serial i/o signals are swapped on the slave so system traces do not have to cross between master and slave.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 4 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays pin assignments 1 2 3 4 5 6 7 8 9 10 cksel cks+ cks- vdds vdda ds- ds+ /res par/spi m/s 30 29 28 27 26 25 24 23 22 21 dp[16] dp[15] dp[14] dp[13] dp[12] vddp dp[11] dp[10] dp[9] dp[8] 11 12 13 14 15 16 17 18 19 20 /stby gnd dp[0] dp[1] dp[2] dp[3] dp[4] dp[5] dp[6] dp[7] 40 39 38 37 36 35 34 33 32 31 r/w cntl[5] or sclk cntl[4] or sdat cntl[3] cntl[2] cntl[1] cntl[0] strb0 strb1 dp[17] ground pad 1 2 3 4 5 6 7 8 9 10 vddp ds+ ds- vdds vdda cks- cks+ /res par/spi m/s 30 29 28 27 26 25 24 23 22 21 dp[16] dp[15] dp[14] dp[13] dp[12] vddp dp[11] dp[10] dp[9] dp[8] 11 12 13 14 15 16 17 18 19 20 slew gnd dp[0] dp[1] dp[2] dp[3] dp[4] dp[5] sclk or dp[6] sdat or dp[7] 40 39 38 37 36 35 34 33 32 31 r/w cntl[5] or sclk cntl[4] or sdat cntl[3] cntl[2] cntl[1] cntl[0] wclk0 wclk1 dp[17] ground pad master slave m/s=1 m/s=0 figure 2. mlp pin assignments (40 pins, 6x6mm, .5mm pitch, top view) 42 f bg a pa c ka g e 3.5mm x 4.5mm (.5mm pitch) (top view) 123456 a b c d e f g master (m/s=1) slave (m/s=0) 1 2 3 4 5 6 1 2 3 4 5 6 a r/w cntl[4] or sdat cntl[2] strob0 dp[ 17] dp[16] a r/w cntl[4] or sdat cntl[2] wclk0 dp[17] dp[16] b cksel cntl[5] or sclk cntl[3] strob1 dp[15] dp[14] b vddp cntl[5] or sclk cntl[3] wclk1 dp[15] dp[14] c gnd vddp cntl[1] cntl[ 0] dp[13] dp[12] c gnd vddp cntl[1] cnt l[0] dp[13] dp[12] d cks+ gnd m/s dp[11] dp[9] dp[10] d ds+ gnd m/s dp[ 11] dp[9] dp[10] e cks- vdds gnd dp [2] dp[7] dp[8] e ds- vdds gnd dp[2] dp[7] or sdat dp[8] f ds- vdda par/spi dp[0] dp[4] dp[6] f cks- vdda par/spi dp[0] dp[4] dp[6] or sclk g ds+ /res /stby dp[1] dp[3] dp[5] g cks+ /res slew dp[1] dp[3] dp[5] figure 3. bga pin assignments
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 5 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays system control pins (m/s) master / slave selection: a given device can be configured as a master or slave device based on the state of the m/s pin. table 1. master/slave m/s configuration 0 slave mode 1 master mode (par/spi) spi mode selection: the par/spi signal configures strb0(wclk0) for spi mode write operation. strb1(wclk1) always operates in parallel mode. control signals cntl[5:0] all pass in spi mode. in spi mode, the sclk signal is used to strobe the serializer. spi mode supports spi writes only. table 2. channel 0 par/spi configuration par /spi m/s=1 master m/s=0 slave 0 spi mode sdat=cntl[4] sclk=cntl[5] /cs=strb0 spi mode sdat=dp[7] & cntl[4] sclk=dp[6] & cntl[5] /cs=wclk0 1 parallel mode parallel mode (cksel) strobe selection signal: the cksel signal exists only on the master device and determines which strobe signal is active. the active strobe signal is selected by cksel and par/spi inputs. table 3. par/spi par /spi cksel master strobe source slave strobe source 0 0 cntl[5] dp[6] & cntl[5] 0 1 strb1 wclk1 1 0 strb0 wclk0 1 1 strb1 wclk1 (/res, /stby) reset and standby mode functionality: reset and standby mode functionality is determined by the state of the /res and /stby signals for the master device and the /res and internal standby-detect signal for the slave device. the /res control signal has a filter that rejects spurious pulses on /res. table 4. reset and standby modes /res /stby (2) master slave 0 x reset mode reset mode 1 0 standby mode standby mode (2) 1 1 operating mode operating mode note: 2. the slave device is put into standby mode through control signals sent from the master device. table 5. reset and standby mode states pin master reset / standby slave reset slave standby dp[17:0] disabled low last data cntl[5:0] disabled low last data strb[0:1] (wclk[0:1]) disabled high high (slew) slew control: the slew control operates only when in slave mode. this signal changes the edge rate of the dp[17:0], cntl[5:0], r/w, wclk1, and wclk0 signals to optimize edge rate for the load being driven. master read mode outputs have ?slow? edge rates. see the ac deserializer specifications table for ?slow? and ?fast? edge rates. table 6. slew rate control /stby (slew) slave m/s=0 0 ?slow? 1 ?fast? cmos i/o signals system control signals the system control signals consist of m/s, /res, /stby(slew), par/spi, and cksel. for connectivity flexibility, these signals are over-voltage tolerant to the maximum supply voltage connected to the device. this allows these signals to be tied high to either a v dds or v ddp supply without static current consumption. these signals are all cmos inputs and should never be allowed to float. parallel i/o signals the parallel data port signals consist of the dp[17:0], cntl[5:0], r/w, and strb1(0)(wclk1(0)) signals. these signals have built-in voltage translation, allowing the signals of the master and slave to be connected to different v ddp supply voltages.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 6 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays serial i/o signals ctl i/o technology the serial i/o is implemented using fairchild?s proprietary differential ctl i/o technology. during data transfers, the serial i/o are powered up to a normal operating mode around .5v. upon completion of a data transfer, the serial i/o goes to a lower power mode around v dds . serial i/o orientation logic the serial i/o signal traces should not cross between the master and the slave. the pin locations have been designed to eliminate the need to cross traces. see table 7, figure 4, and figure 5. table 7. serial pin orientation master (m/s=1) (pad/pin #) slave (m/s=0) (pad/pin #) package cks+ cks- ds- ds+ cks+ cks- ds- ds+ mlp 2 3 6 7 7 6 3 2 bga d1 e1 f1 g1 g1 f1 e1 d1 bga slave a b c d e f g 1 23456

bga master g f e d c b a ds- cks- cks+ 654321 ds+ 21 22 23 24 25 26 27 28 29 30 10 9 8 7 6 5 4 3 2 1 31 32 33 34 35 36 37 38 39 40 20 19 18 17 16 15 14 13 12 11 2 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 mlp master m/s par/spi /res ds+ ds- vdda vdds cks- cks+ cksel(h) mlp slave cksel(h) (ds+) (ds-) vdds vdda (cks-) (cks+) /res par/spi m/s figure 4. bga pair figure 5. mlp pair
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 7 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays master/slave read transactions read transactions have two phases: the read-control phase, where cntl[5:0], r/w, cksel are transmitted to the deserializer; and the read-data phase, where the dp[17:0] signals of the slave are read and transmitted back to the master device. the slave device generates its own strobe signal for latching in the data. slave data must be valid prior to the wclkn signal going high. master serializer operation (read control phase) when the r/w signal is asserted high and the strobe signal transitions low, the read-control phase of the read cycle is initiated. the r/w signal must not transition until the read cycle completes. for a read transaction, only eight control signals are captured. the 18 dp bits are ignored during the read operation. the following sequence must occur for data to be serialized properly: 1. cpu selects input strobe source (cksel=0 or 1). 2. cpu sends signals (r/w=1, cksel, cntl[5:0]). 3. cpu sends low strobe signal. slave deserializer operation (read-control phase) 1. captures data from serial transfer. 2. internally decodes that this is a read transaction. 3. outputs control signals and prepares dp pins to accept data. 4. outputs falling edge of wclk pulse. slave serializer read operation (read-data phase) the slave serializer is enabled on the tail end of the read-control phase of operation. the operation of the serializer is identical to the master serialization except that the strobe signal is generated internally and only the data bits dp[17:0] are captured. 1. display device outputs data onto dp bus on falling edge of wclk. 2. captures parallel data on generated rising edge of wclk signal. 3. serializes data stream. master deserializer read operation (read-data phase): 1. receives valid serial stream. 2. outputs data dp[17:0]. 3. cpu asserts rising edge of strobe signal to capture data. spi write transaction spi mode is activated by asserting the par/spi signal low on both the master and slave device. a spi write is only performed when cksel=0. during a spi transaction, sclk must be connected to cntl[5] and is the strobe source for serialization. sdat is on cntl[4] and all of the remaining control signals and strb0 are serialized. strb0 should be connected to the spi mode chip select. on the rising edge of sclk, all eight control signals (cntl[5:0], r/w, cksel) are captured and serialized. the data signals are not sent. the deserializer captures the serial stream and outputs it to the parallel port. as shown in table 2, sdat and sclk are output on multiple pins. the dp[7] and dp[6] connections can be used for displays with dual-mode operation and the data pins are multiplexed with the spi signals. cntl[5] and cntl[4] signals can be used when the signals are not multiplexed.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 8 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays applications diagrams vddp a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 nc a1 nc d3 f3 g3 g2 b1 vddp1 notes: 1. write-only interface. 2. unused slave output pin must be nc (no connection). 3. /cs used to strobe sub-display data. 4. 5. pclk used for rgb mode pin numbers for bga package. . /cs pclk gpio /stby /res cksel main display pclk r,g,b [5:0] hsync vsync sd oe sub- display d ata [7 : 0] d/c /cs reset p/s 2 edge rate control option slew must be connected to vddp or gnd for low power. vddp vdds/a strb0 strb1 cntl[5] r/w m/s par/spi /stby /res cksel r,g,b[5:0] dp[17:0] hsync_d/c cntl[0] vsync cntl[1] oe cntl[3] sd cntl[2] reset cntl[4] vddp vdds/a wclk0 wclk1 dp[17:0] cntl[0] cntl[1] cntl[2] cntl[3] cntl[4] cntl[5] r/w m/s par/spi slew /res vddp vddp1 vdds/a vddp2 vdds/a cks+ cks- ds+ ds- cks+ cks- ds+ ds- d1 e1 g1 f1 g1 f1 d1 e1 a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 a1 d3 f3 g3 g2 b1 e3 d2 c1 e3 d2 c1 c2 e2 f2 c2 e2 f2 baseband processor master slave gnd gnd gnd gnd gnd gnd figure 6. dual display with parallel rgb main display and 6800-style microcontroller sub-display a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 a1 nc d3 f3 g3 g2 b1 notes: 1. write-only interface. 2. unused slave output pin must be nc (no connection). 3. /we used to strobe sub-display data. 4. 5. pclk used for rgb mode pin numbers for bga package. . /we pclk gpio /stby /res cksel main display pclk r,g,b [5:0] hsync vsync sd oe sub- display d ata [ 7 : 0 ] addr /we reset p/s /cs vddp2 edge rate control option slew must be connected to vddp or gnd for low power. vddp vdds/a strb0 strb1 cntl[5] r/w m/s par/spi /stby /res cksel r,g,b[5:0] dp[17:0] hsync_addr cntl[0] vsync cntl[1] oe cntl[3] sd cntl[2] reset cntl[4] vddp vdds/a wclk0 wclk1 dp[17:0] cntl[0] cntl[1] cntl[2] cntl[3] cntl[4] cntl[5] r/w m/s par/spi slew /res vddp vddp1 vddp1 vdds/a vddp2 vdds/a cks+ cks- ds+ ds- cks+ cks- ds+ ds- d1 e1 g1 f1 g1 f1 d1 e1 a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 a1 d3 f3 g3 g2 b1 e3 d2 c1 e3 d2 c1 c2 e2 f2 c2 e2 f2 /cs baseband processor master slave gnd gnd gnd gnd gnd gnd figure 7. dual display with parallel rgb main display and x86-style microcontroller sub-display
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 9 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays application diagrams (continued) vddp1 a4 b4 d4:g6 c4 c3 a3 b3 a2 nc b2 nc a1 nc d3 f3 g3 g2 b1 notes: 1. write-only interface (r/w hardwired low). 2. spi sub-display interface par/spi=low for both master and slave. . 3. sclk connected to cntl[5]; sdat connected to cntl[4]. 4. 5. 6. shared data pin sdat; sclk connections on sub-display. unused slave output pin must be nc (no connection). pin numbers for bga package. /cs pclk gpio /stby /res cksel main display pclk r,g,b [5:0] hsync vsync sd sub- display sclk sdat /cs d/c reset p/s vddp2 edge rate control option slew must be connected to vddp or gnd for low power. vddp vdds/a strb0 strb1 cntl[5] r/w m/s par/spi /stby /res cksel r,g,b[5:0] dp[17:0] hsync cntl[0] vsync cntl[1] d/c cntl[3] sd cntl[2] sdat cntl[4] vddp vdds/a wclk0 wclk1 dp[17:0] cntl[0] cntl[1] cntl[2] cntl[3] cntl[4] cntl[5] r/w m/s par/spi slew /res vddp vddp1 vdds/a vddp2 vdds/a cks+ cks- ds+ ds- cks+ cks- ds+ ds- d1 e1 g1 f1 e3 d2 c1 g1 f1 d1 e1 e3 d2 c1 a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 a1 d3 f3 g3 g2 b1 gnd gnd gnd c2 e2 f2 c2 e2 f2 sclk module 1 f6 sclk dp[6] e5 sdat dp[7] baseband processor master slave gnd gnd gnd figure 8. dual display with rgb main display and spi sub-display interface vddp1 a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 a1 d3 f3 g3 g2 b1 notes: 1. r/w interface. r/w signal connected to baseband microprocessor. . 2. 3. 4. unused slave output pin must be nc (no connection). par/spi connected high to indicate parallel operation. pin numbers for bga package. . /cs0 /cs1 gpio /stby /res cksel main display /cs1 data[17:0] d/c reset 1 r/w sub- display data [17:0] d/c /cs0 reset 0 p/s vddp2 edge rate control option slew must be connected to vddp or gnd for low power. vddp vdds/a strb0 strb1 cntl[5] r/w m/s par/spi /stby /res cksel data[17:0] dp[17:0] cntl[0] cntl[1] d/c reset 0 reset 1 cntl[3] cntl[2] cntl[4] vddp vdds/a wclk0 wclk1 dp[17:0] cntl[0] cntl[1] cntl[2] cntl[3] cntl[4] cntl[5] r/w m/s par/spi slew /res vddp vddp1 vdds/a vddp2 vdds/a cks+ cks- ds+ ds- cks+ cks- ds+ ds- d1 e1 g1 f1 g1 f1 d1 e1 a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 a1 d3 f3 g3 g2 b1 e3 d2 c1 e3 d2 c1 c2 e2 f2 c2 e2 f2 module 1 r/w nc nc nc baseband processor master slave gnd gnd gnd gnd gnd gnd figure 9. r/w dual display with parallel mi crocontroller main display and sub-display
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 10 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays application diagrams (continued) vddp1 a4 b4 d4:g6 c4 c3 a3 b3 a2 nc b2 nc a1 d3 f3 g3 g2 b1 notes: 1. dual display r/w intel? interface. 2. 3. 4. 5. unused slave output pin must be nc (no connection). gpio signal used to select read or write functionality. connected to cksel and r/w. displays selected via the chip selects. pin numbers for bga package. . /re /we gpio /stby /res cksel0 cksel1 main display /re /we data[17:0] addr /cs1 sub- display /re /we data[7:0] addr /cs0 edge rate control option slew must be connected to vddp or gnd for low power. vddp vdds/a strb0 strb1 cntl[5] r/w m/s par/spi /stby /res cksel data[17:0] dp[17:0] cntl[0] cntl[1] addr /cs0 /cs1 cntl[3] cntl[2] cntl[4] vddp vdds/a wclk0 wclk1 dp[17:0] cntl[0] cntl[1] cntl[2] cntl[3] cntl[4] cntl[5] r/w m/s par/spi slew /res vddp vddp1 vdds/a vddp2 vdds/a cks+ cks- ds+ ds- cks+ cks- ds+ ds- d1 e1 g1 f1 e3 d2 c1 g1 f1 d1 e1 e3 d2 c1 a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 a1 d3 f3 g3 g2 b1 c2 e2 f2 c2 e2 f2 module 1 vddp2 baseband processor master slave gnd gnd gnd gnd gnd gnd figure 10. dual r/w x86-style microcontroller display interface additional application information flex cabling: the serial i/o information is transmitted at a high serial rate. care must be taken implementing this serial i/o flex cable. the following best practices shoul d be used when developing the flex cabling or flex pcb. keep all four differential serial wires the same length. do not allow noisy signals over or near differential serial wires. example: no cmos traces over differential serial wires. use only one ground plane or wire over the differential se rial wires. do not run ground over top and bottom. design goal of 100-ohms differential characteristic impedance. do not place test points on differential serial wires. use differential serial wires a minimum of 2cm away from the antenna. visit fairchild?s website at http://www.fairchildsemi.com/pr oducts/interface/userdes.html , contact your sales rep, or contact fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 11 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd supply voltage -0.5 +3.6 v all input/output voltage -0.5 v ddp +0.5 v t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 4 seconds) +260 c esd iec 61000 board level 15 kv human body model, jesd22-a114 all pins 7.5 kv serial i/0, /res, par/spi to gnd 14.0 recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dda , v dds (3) supply voltage 2.5 3.0 v v ddp supply voltage 1.6 v dda/s v t a operating temperature -30 +85 c note : 3. v dda and v dds supplies must be hardwired together to the same power supply. v ddp must be less than or equal to v dda /v dds .
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 12 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays electrical specifications values valid for over supply voltage and operating temperature ranges unless otherwise specified. symbol parameter test conditions min. typ. max. unit dc parallel i/o and serial characteristics v ih input high voltage 0.7 x v ddp v ddp v v il input low voltage gnd 0.3 x v ddp v v oh output high voltage slew=0 i oh =-250a 0.8 x v ddp v slew=1 i oh =-1ma v ol output low voltage slew=0 i ol =250a 0.2 x v ddp v slew=1 i ol =1ma i in input current -5 5 a v go serial input voltage ground offset slave relative to master 0 v z serial transmission line impedance 70 100 120 power characteristics i dyn_ser dynamic current of master device v dda/s =2.75v, m/s=1, v ddp =1.8v, /stby=1, /res=1 5.44mhz 4 ma 12.00mhz 7 15.00mhz 8 i dyn_des dynamic current of slave device v dda/s =2.75v m/s=0 v ddp =1.8v, /stby=1, /res=1, c l =0pf 5.44mhz 5 ma 12.00mhz 8 15.00mhz 10 i brst_m burst standby current of master v dda/s =2.75v, v ddp =1.8v, m/s=1, /stby=1, /rst=1, no strobe signal, c l =0pf 1.3 ma i brst_s burst standby current of slave v dda/s =2.75v, v ddp =1.8v, m/s=0, /stby=1, /rst=1, no strobe signal, c l =0pf 1.8 ma i stby standby current serializer or deserializer v dds/a =v ddp =3.0v, /stby=0, /rst=1 10 a i res reset current serializer or deserializer v dds/a =v ddp =3.0v, /rst=0 10 a ac operating characteristics f wstrb0 write strobe frequency cksel=0 strb0 0 8 mhz f wstrb1 write strobe frequency cksel=1 strb1 0 15 mhz f rstrb read strobe frequency 0 2 mhz t r , t f input edge rates (5) 40 ns t s1 write mode setup time dp before strbn , figure 11 5 ns t h1 write mode hold time dp after strbn , figure 11 15 ns t s2 read mode setup time r/w, cntl before strbn figure 12 0 ns t h2 read mode hold time r/w, cntl after strbn figure 12 16 ns t s-strb cksel to strbn setup time cksel before active edge strbn (4) , cksel before spi /cs, spi /cs before cksel figure 13, figure 14 50 ns
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 13 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays symbol parameter test conditions min. typ. max. unit ac deserializer specifications t r0 , t f0 output edge rates of wclk0,wclk1 slew=0, cl=5pf 20% to 80% (5) 8 17 ns slew=1, c l =5pf 20% to 80% (5) 10 t r1 , t f1 output edge rates of r/w, dp[17:0] cntl[5:0] slew=0, c l =5pf 20% to 80% (5) 8 22 ns slew=1, c l =5pf 20% to 80% (5) 17 t cs cntl[5:0],r/w to falling edge of wclkn m/s=0 (5) , c l =5pf 50% to 50% (5) figure 15 0 4 ns t pdv-wr0 dp, cntl to wclk0 par/spi=1 (5) , figure 15 50 60 ns t pdv-wr1 dp, cntl to wclk1 par/spi=1 (5) , figure 15 18 24 ns t pdv-rd cntl to wclkn par/spi=1 (5) , figure 17 200 224 ns t pdv-spi data, cntl to sclk par/spi=0 (5) , figure 16 40 60 ns t pwl-wr0 wclk0 pulse width low; write mode m/s=0, r/w=0, par/spi=1 (5,7) figure 15 50 56 ns t pwl-wr1 wclk1 pulse width low; write mode m/s=0, r/w=0, par/spi=1 (5,7) figure 15 18 20 ns t pwl-rd pulse width low of wclk; read mode m/s=0, r/w=1, par/spi=1 (5,7) figure 17 200 220 ns t pwl-spi pulse width low of wclk; spi mode m/s=0, r/w=0, par/spi=0 (5,7) figure 16 40 56 ns ac data latencies t pd-wr0 write latency write mode, cksel=0 (8,9,10) figure 15 147 ns t pd-wr1 write latency write mode, cksel=1 (8,9,10) figure 15 111 ns t pd-rd total read latency read mode (8,10,11) figure 17 340 480 ns t pd-rdc read control latency read mode (8,10,12) figure 17 276 ns t pd-rdd read data latency read mode (8,10,13) figure 17 84 ns t pd-spi spi write latency spi-write mode (8,10,14) figure 16 115 ns ac oscillator specifications f osc serial operating frequency 240 275 310 mhz t osc-stby oscillator stabilization time after standby v dda =v dds =2.75v /res=1, /stby transition 15 30 s t osc-res oscillator stabilization time after reset v dda =v dds =2.75v /stby=1, /res transition 30 50 s ac reset and standby timing t vdd-off power down relative to /res (15) figure 19 20 s t strb-res /res after last strbn m/s=1, /stby=1, r/w=0 (16) figure 19 0 ns t strb-stby standby time after last strobe m/s=1, /stby=1 (17) figure 19 200 ns t res-off master/slave reset disable time m/s=1 /stby=1, /res= figure 19 15 20 s
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 14 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays symbol parameter test conditions min. typ. max. unit t vdd-skew allowed skew between v ddp and v dda/s (18) figure 18 - + ms t vdd-res minimum reset low time after v dd stable m/s=0, /res= (19) figure 18 20 s t res-stby /stby wait time after /res m/s=1 /res=1, /stby= figure 18 20 s t dvalid /stby to active edge of strobe m/s=0 /res=1 (20) figure 18 30 s notes: 4. active edge of strobe is the rising edge for a writ e transaction and the falling edge for a read transaction. 5. characterized, but not production tested. 6. indirectly tested through serial clock frequency and serial data bit tests. 7. pulse width low wclkn measur ements are measured at 30% of v ddp . measurements apply when slew=0 or slew=1. 8. minimum times occur with maximum oscillator frequency. maximum times occur with minimum oscillator frequency. 9. write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and i/o propagation delays. 10. assumes propagation delay across the flex cable and through the i/os of 20ns. 11. total read latency t pd-rd is the sum of the read-control phase latency (t pd-rdc ) and the read-data phase latency (t pd-rdd ). t pd-rd =t pd-rdc + t pd-rdd . 12. read-control latency is the sum of the delay through the master serializer and slave deserializer, plus flex cable flight times and i/o propagation delays. 13. read data latency is the sum of the delay through the slave serializer and master deserializer, plus flex cable flight times and i/o propagation delays. 14. spi-write latency is the sum of the delay through the mast er serializer and slave deserializer, plus the flight time across the flex cable and i/o propagation delays. 15. timing allows the device to completely reset prior to powering down. 16. internal reset filter allows assertion prio r to completion of read or write date transfer. 17. timing ensures that last write transaction is complete prior to going into standby. 18. v dda/s must power up together. v ddp may power-up relative to v dda/s in any order without static power being consumed. guaranteed by characterization. 19. /res signal should be held low for minimum time s pecified after supplies go high. it is recommended that /res be held low during the power supply ramp. 20. strbn must be held off until internal oscillator has stabilized.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 15 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays typical performance characteristics strobe dp,cntl data t s1 t h1 strobe dp,cntl data setup time h old t ime setup: cksel=0 or 1, r/w=0 strbn cntl,r/w control t s2 setup time t h2 strbn cntl,r/w control hold time setup: cksel=0 or 1, r / w=1 figure 11. master write setup and hold time figure 12. master read setup and hold time strb1 dp,cntl data setup: cksel=0 or 1, r/w=0 strb0 cksel t s-strb t s-strb spi /cs t s-strb strb1 cntl data setup: cksel=0 or 1, r/w=1 strb0 cksel t s-strb t s-strb figure 13. cksel write setup time figure 14. cksel read setup time setup: cksel=0 or 1, r/w=0, par/spi=1 cks strbn ds dp cntl wclkn t pd-wr t pwln t cs t pdv setup: cksel=0, r/w=0, par/spi=0, /cs=0 cks master sclk ds slave sdat, cntl, /cs slave sclk t pd-spi t pwl-spi t cs t pdv-spi figure 15. slave write mode timing figure 16. slave spi mode timing
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 16 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays typical performance characteristics (continued) setup: cksel=0 or 1, r/w=1, par/spi=1 cks strbn ds cntl slv wclkn] dp slv dp mstr t pd-rd c t pd-rd d t pd-rd t pwl-rd n t csn t pdv-rd n figure 17. slave read mode timing vddp vdds/a /res /stby dp[23:0],r/w strbn cks ds off on t vdd-skew dynamic mode standby mode valid data t vdd-res t dvalid t res-stby deserializer figure 18. power-up timing vddp vdds/a /res /stby strobe deserializer off on dynamic mode t vddoff t strb-stby t strb-res t res-off standby mode figure 19. power-down timing
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 17 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays physical dimensions notes: a. conforms to jedec registration mo-220, variation wjjd-2 with exception that this is a sawn version.. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m-1994. d. land pattern per ipc sm-782. e. width reduced to avoid solder bridging. f. dimensions are not inclusive of burrs, mold flash, or tie bar protrusions. g. drawing filename: mkt-mlp40arev3. 6.00 6.00 0.80 max 0.10 c seating plane 0.08 c 0.05 0.00 (0.20) c 0.15 c 0.15 c pin #1 ident 0.50 4.20 4.00 0.50 0.30 4.20 4.00 0.50 0.10 cab 0.05 c 0.18-0.30 a b 6.38min 0.20min 4.77min 4.37max 0.28 max 0.50typ (0.80) x4 x40 e (datum a) (datum b) pin #1 id figure 20. 40-lead, molded leadless package (mlp) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 18 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays physical dimensions (continued) figure 21. 42-ball, ball grid array (bga) package package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin324c rev. 1.1.4 19 serdes? fin324c ? 24-bit ultra-low power serializer / deserializer supporting single and dual displays

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