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1/29 september 2004 m69aw024b 16 mbit (1m x16) 3v asynchronous psram features summary supply voltage: 2.7 to 3.3v access time: 60ns, 70ns low standby current: 70a deep power down current: 10a low v cc data retention: 2.3v compatible with standard lpsram figure 1. package bga tfbga48 (zb) 6x8 mm
m69aw024b 2/29 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 address inputs (a0-a19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data inputs/outputs (dq8-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chip enable (e1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 chip enable (e2 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 upper byte enable (ub ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 lower byte enable (lb ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 vss gr ound. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 deep power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. read and standby modes ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. output enable controlled, read mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. chip enable controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. address access after g control, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . 16
3/29 m69aw024b figure 10.address access after e1 control, read mode ac waveforms . . . . . . . . . . . . . . . . . . . 16 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11.e1 controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12.w controlled, single write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13.w controlled, continuous write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14.e1 controlled, read/write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15.e1 controlled, read/write ac waveforms 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16.g controlled read, w controlled write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17.g controlled read, w controlled write ac waveforms 2 . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. power down and power-up ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18.standby mode entry ac waveforms, after read or write . . . . . . . . . . . . . . . . . . . . . . . 23 figure 19.power-down ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 20.power-up mode ac waveforms - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21.power-up mode ac waveforms - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 22.power-up mode ac waveforms - 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. low v cc data retention characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 23.low v cc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 24.tfbga48 6x8mm - 6x8 ball array, 0.75mm pitch, package outline, bottom view . . . . 26 table 11. tfbga48 6x8mm - 6x8 ball array, 0.75mm pitch, package mechanical data. . . . . . . . 26 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
m69aw024b 4/29 summary description the m69aw024b is a 16 mbit (16,777,216 bit) cmos memory, organized as 1,048,576 words by 16 bits, and is supplied by a single 2.7v to 3.3v supply voltage range. m69aw024b is a member of stmicroelectronics psram memory family, based on the one-transis- tor per-cell architecture. these devices are manu- factured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. however, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard asynchronous sram interface. the internal control logic of the m69aw024b han- dles the periodic refresh cycle, automatically, and without user involvement. write cycles can be performed on a single byte by using upper byte enable (ub ) and lower byte en- able (lb ). the device can be put into standby mode using chip enable (e1 ) or in deep power down mode by using chip enable (e2). power-down mode achieves a very low current consumption by halting all the internal activities. since the refresh circuitry is halted, the duration of the power-down should be less than the maximum period for refresh, if the user has not finished with the data contents of the memory. figure 2. logic diagram table 1. signal names ai07406 20 a0-a19 w dq0-dq15 v cc m69aw024b g 16 e1 ub lb v ss e2 a0-a19 address input dq0-dq15 data input/output e1 , e2 chip enable, power down g output enable w write enable ub upper byte enable lb lower byte enable v cc supply voltage v ss ground nc not connected (no internal connection)
5/29 m69aw024b figure 3. tfbga connections (top view through package) ai07409 a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 nc a11 a8 a18 dq0 a3 a6 a5 a4 e1 a10 a9 a13 a7 a2 e2 c dq4 d dq5 a14 a15 g h dq11 a19 ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc nc v ss dq6 a16
m69aw024b 6/29 signal descriptions see figure 2., logic diagram , and table 1., signal names , for a brief overview of the sig- nals connected to this device. address inputs (a0-a19). the address inputs select the cells in the memory array to access dur- ing read and write operations. data inputs/outputs (dq8-dq15). the upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a write or read operation, when upper byte enable (ub ) is driven low. data inputs/outputs (dq0-dq7). the lower byte data inputs/outputs carry the data to or from the lower part of the selected address during a write or read operation, when lower byte enable (lb ) is driven low. chip enable (e1 ). when asserted (low), the chip enable, e1 , activates the memory state ma- chine, address buffers and decoders, allowing read and write operations to be performed. when de-asserted (high), all other pins are ignored, and the device is put, automatically, in low-power standby mode. chip enable (e2). the chip enable, e2, puts the device in deep power-down mode when it is driven low. this is the lowest power mode. output enable (g ). the output enable, g , pro- vides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. write enable (w ). the write enable, w , controls the bus write operation of the memory. upper byte enable (ub ). the upper byte en- able, ub , gates the data on the upper byte data inputs/outputs (dq8-dq15) to or from the upper part of the selected address during a write or read operation. lower byte enable (lb ). the lower byte en- able, lb , gates the data on the lower byte data inputs/outputs (dq0-dq7) to or from the lower part of the selected address during a write or read operation. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read or write) and for driving the refresh logic, even when the device is not being accessed. v ss ground. the v ss ground is the reference for all voltage measurements.
7/29 m69aw024b figure 4. block diagram ai07410 dynamic memory array row decoder column decoder control logic e1 refresh controller arbitration logic internal clock generator input/output buffer address ub e2 g w lb power controller v cc v ss address v cc dq0-dq7 dq8-dq15
m69aw024b 8/29 table 2. operating modes note: 1. x = v ih or v il . 2. output disable mode should not be kept longer than 1s. 3. power-down mode can be entered from stand-by state, and all dq pins are in hi-z state. 4. can be either vil or vih but must be valid before read or write. 5. byte read is not supported. 6. either or both lb and ub must be low, v il , for read operations. operation e2 e1 w g lb ub a0-a19 dq0-dq7 dq8- dq15 i cc data re- tention standby (deselect) v ih v ih x (1) x (1) x (1) x (1) x (1) hi-z hi-z i sb ye s output disabled (2) v ih v il v ih v ih x (1) x (1) note (4) hi-z hi-z i cc ye s output disabled (no read) v ih v il v ih v il v ih v ih valid hi-z hi-z i cc ye s word read(5) v ih v il v ih v il v il(6) valid output valid i cc ye s word read v ih v il v ih v il v il v il valid output valid i cc ye s upper byte write v ih v il v il v ih v ih v il valid invalid input valid i cc ye s lower byte write v ih v il v il v ih v il v ih valid input valid invalid i cc ye s word write v ih v il v il v ih v il v il valid input valid input valid i cc ye s power-down (3) v il x (1) x (1) x (1) x (1) x (1) x (1) hi-z hi-z i pd no
9/29 m69aw024b operation operational modes are determined by device con- trol inputs w , e1 , e2, lb and ub as summarized in the operating modes table (see table 2. ). power on sequence because the internal control logic of the m69aw024b needs to be initialized, the following power-on procedure must be followed before the memory is used: ? apply power and wait for v cc to stabilize ? wait 400s while driving both chip enable signals (e1 and e2) high ? activate the memory by driving chip enable (e1 ) low. read mode the device is in read mode when: ? write enable (w ) is high and ? output enable (g ) low and ? the two chip enable signals are asserted (e1 is low, and e2 is high). the time taken to enter read mode (t elqv , t glqv or t blqv ) depends on which of the above signals was the last to reach the appropriate level. data out (dq15-dq0) may be indeterminate during t elqx , t glqx and t blqx , but data will always be valid during t avqv . write mode the device is in write mode when ? write enable (w ) is low and ? chip enable (e1 ) is low and ? the two chip enable signals are asserted (e1 is low, and e2 is high) ? one of upper byte enable (ub ) or lower byte enable (lb ) is low, while the other is high. the write cycle begins just after the event (the fall- ing edge) that causes the last of these conditions to become true (t avwl or t avel or t avbl ). the write cycle is terminated by the earlier of a ris- ing edge on write enable (w ) or chip enable (e1 ). if the device is in write mode (chip enable (e1 ) is low, output enable (g ) is low, upper byte en- able (ub ) or lower byte enable (lb ) is low), then write enable (w ) will return the outputs to high im- pedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of op- eration. data input must be valid for t dvwh before the rising edge of write enable (w ), or for t dveh before the rising edge of chip enable (e1 ), which- ever occurs first, and remain valid for t whdx , t ehdx standby mode the device is in standby mode when: ? chip enable (e1 ) is high and ? chip enable (e2) is high. the input/output buffers and the decoding/control logic are switched off, but the dynamic array con- tinues to be refreshed. in this mode, the memory current consumption, i sb , is reduced, and the data remains valid. deep power-down mode the device is in deep power-down mode when: ? chip enable (e2 is low).
m69aw024b 10/29 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. table 3. absolute maximum ratings symbol parameter min max unit i o output current ?50 50 ma t a ambient operating temperature ?30 85 c t stg storage temperature ?55 125 c v cc core supply voltage ?0.5 3.6 v v io input or output voltage ?0.5 3.6 v
11/29 m69aw024b dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 4. operating and ac measurement conditions note: 1. all voltages are referenced to v ss . 2. the input transition time used in ac measurements is 5ns. for other input transition times, see table 9. figure 5. ac measurement load circuit figure 6. ac measurement i/o waveform parameter m69aw024b unit ?60, ?70 min max v cc supply voltage 1 2.7 3.3 v ambient operating temperature ?30 85 c load capacitance (c l ) 50 pf output circuit protection resistance (r 1 ) 50 ? input rise and fall times 4 ns input pulse voltages 0 to v cc v input and output timing ref. voltages v cc /2 v output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc v input transition time 2 (t ) between v il and v ih 5ns ai07222c v cc /2 out c l includes jig capacitance device under test c l r 1 ai07753 v cc i/o timing reference voltage 0v v cc /2 v cc output timing reference voltage 0v 0.7v cc 0.3v cc
m69aw024b 12/29 table 5. capacitance note: 1. outputs deselected. table 6. dc characteristics note: 1. average ac current, outputs open, cycling at t avax (min). 2. maximum dc voltage on input and i/o pins is v cc +0.3v. during voltage transitions, input may positive overshoot to v cc + 1.0v for a period of up to 5ns. 3. minimum dc voltage on input or i/o pins is ?0.3v. during voltage transitions, input may positive overshoot to v ss + 1.0v for a period of up to 5ns. symbol parameter test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 5pf c out (1) output capacitance v out = 0v 8pf symbol parameter test condition min max unit i cc1 (1) operating supply current v cc = 3.3v, v in = v ih or v il , e1 = v il , e2 = v ih , i out = 0ma t rc /t wc = min 20 ma t rc /t wc = 1s 3.0 ma i li input leakage current 0v v in v cc ?1 1 a i lo output leakage current 0v v out v cc ?1 1 a i pd deep power down current v cc = 3.3v, v in = v ih or v il , e2 0.2v 10 a i sb standby supply current cmos 3.1v v cc 3.3v, v in = v ih or v il , e1 = v ih and e2 = v ih , i out = 0ma 1.5 ma 2.7v v cc 3.1v, v in = v ih or v il , e1 = v ih and e2 = v ih , i out = 0ma 1ma 3.1v v cc 3.3v, v in 0.2v or v cc ?0.2v, e1 v cc ?0.2v and e2 v cc ?0.2v), i out = 0ma 100 a 2.7v v cc 3.1v, v in 0.2v or v cc ?0.2v, e1 v cc ?0.2v and e2 v cc ?0.2v), i out = 0ma 70 a v ih (2) input high voltage 3.1v v cc 3.3v 2.6 v cc + 0.3 v 2.7v v cc 3.1v 2.2 v cc + 0.3 v v il (3) input low voltage 3.1v v cc 3.3v ?0.3 0.6 v 2.7v v cc 3.1v ?0.3 0.5 v v oh output high voltage 3.1v v cc 3.3v, i oh = ?0.5ma 2.5 v 2.7v v cc 3.1v, i oh = ?0.5ma 2.2 v v ol output low voltage v cc = 3v, i ol = 1ma 0.4 v
13/29 m69aw024b table 7. read and standby modes ac characteristics symbol alt. parameter m69aw024b unit ?60 ?70 min max min max t avax t rc read cycle time 80 90 ns t ave h t rc address valid to chip enable high (read cycle time) 80 90 ns t avel (5) t asc address set-up time to chip enable low ?5 ?5 ns t avgh t rc address valid to output enable high (read cycle time) 80 90 ns t avgl1 (3,6) t aso address valid to output enable low 25 30 ns t avgl 2 (7) t aso (abs) address valid to output enable low (absolute) 5 5 ns t av qv (1,4) t aa address access time 60 70 ns t axav (4,8) t ax address invalid time 5 5 ns t axqx (1) t oh output hold time after address transition 5 5 ns t blel (5) t bsc lb , ub set-up time to chip enable low ?5 ?5 ns t blgl t bso lb , ub set-up time to output enable low 0 0 ns t ehax t chah chip enable high to address hold time ?5 ?5 ns t ehbh t chbh chip enable high to lb , ub high ?5 ?5 ns t ehel t cp chip enable high pulse width 10 12 ns t ehqx (1) t oh output hold time after chip enable low 5 5 ns t ehqz (2) t chz chip enable high to output hi-z 20 25 ns t elax (4) t clah chip enable low to address hold time 80 90 ns t eleh t rc chip enable low to chip enable high (read cycle time) 80 90 ns t elgh t rc chip enable low to output enable high (read cycle time) 80 90 ns t elgl (3,6,9,10) t clol chip enable low to output enable low delay time 25 1000 30 1000 ns t elqv (1,3) t ce chip enable access time 60 70 ns t elqx (2) t clz chip enable low to output lo-z 5 5 ns t ghax t ohah output enable high to address hold time ?5 ?5 ns t ghbh t ohbh output enable high to lb , ub high ?5 ?5 ns t ghgl1 (6,9,10) t op output enable high pulse width 25 1000 30 1000 ns t ghgl2 (7) t op (abs) output enable high pulse width (absolute) 10 10 ns t ghqx (1) t oh output hold time after output enable low 5 5 ns t ghqz (2) t ohz output enable high to output hi-z 20 25 ns t glax (4,9) t olah output enable low to address hold time 45 50 ns t gleh (9) t olch output enable low to chip enable high delay time 45 50 ns
m69aw024b 14/29 note: 1. c l = 50pf with 1 ttl and r1=50 ? . 2. c l = 5pf 3. t elqv is applicable if g is brought to low before e1 goes low and if actual value of either t avgl1 or t elgl , or both, is shorter than the specified value. 4. only applicable to a0, a1 and a2 when both and g and e1 are kept low for address access. 5. applicable if g is brought to low before e1 goes low. 6. t avgl1 , t elgl (min) and t ghgl1 (min) are reference values when the access time is determined by t glqv . if the actual value of each parameter is lower than the specified minimum values, t glqv is increased by the difference between the actual value and the spec- ified minimum value. 7. t avgl2 and t ghgl2 correspond to absolute minimum values during g controlled access. 8. t axav is applicable when two or more addresses from a0 to a2 are switched from the previous state. 9. if the actual value of t elgl or t ghgl1 is lower than the specified minimum value, t glax and t gleh will be equal to t avax (min) ? t elgl (actual) and t avax (min) ? t ghgl1 (actual), respectively. 10. the maximum value is applicable if e1 is kept low. t glqv (1) t oe output enable access time 35 40 ns t glqx (2) t olz output enable low to output lo-z 0 0 ns symbol alt. parameter m69aw024b unit ?60 ?70 min max min max
15/29 m69aw024b figure 7. output enable controlled, read mode ac waveforms note: 1. e2 = high and w = high. 2. either or both lb and ub must be low when both e1 and g are low. figure 8. chip enable controlled, read mode ac waveforms note: 1. e2 = high and w = high. 2. either or both lb and ub must be low when both e1 and g are low. ai07743 telgh tghax telgl telqv tglqv tavgl1 tgleh valid a0-a19 e1 g dq0-dq15 address valid address valid valid tavgh tghax tavgl2 tglqv tglqx tghqz tghqx tghqx tglqx tghqz tghgl1 lb, ub tblgl tghbh tblgl tghbh ai07744 teleh tehax telqv valid a0-a19 e1 g dq0-dq15 address valid address valid valid teleh tehax tavel telqx tehqz tehqx tehqx telqx tehqz tavel telqv tehel lb, ub tblel tblel tehbh tehbh
m69aw024b 16/29 figure 9. address access after g control, read mode ac waveforms note: 1. e2 = high and w = high. 2. either or both lb and ub must be low when both e1 and g are low. figure 10. address access after e1 control, read mode ac waveforms note: 1. e2 = high and w = high. 2. either or both lb and ub must be low when both e1 and g are low. ai07745 tavax tghax data valid a3-a19 g dq0-dq15 address valid address valid data valid tavgh tglax taxav tglqv tglqx taxqx tghqx tghqz tavgl1 a0-a2 tavqv address valid address valid (no change) lb, ub e1 tblgl tghbh ai07746 tehax data valid a3-a19 e1 g dq0-dq15 address valid address valid data valid taveh telax taxav telqv telqx taxqx tehqx tehqz tavel a0-a2 tavqv lb, ub tehbh tblel
17/29 m69aw024b table 8. write mode ac characteristics symbol alt. parameter m69aw024b unit ?60 ?70 min max min max t ave l (2) t as address set-up time to chip enable low 0 0 ns t avwl t as address set-up time to write enable low 0 0 ns t axgl1 (3,4) t oeh address invalid to output enable low 25 1000 35 1000 ns t axgl2 (5) t oeh (abs) address invalid to output enable low (absolute) 12 15 ns t blel t bs lb , ub set-up time to chip enable low ?5 ?5 ns t blwl t bs lb , ub set-up time to write enable low ?5 ?5 ns t dveh t ds data set-up time to chip enable high 15 20 ns t dvwh t ds data set-up time to write enable high 15 20 ns t ehbh t bh lb , ub hold time from chip enable high ?5 ?5 ns t ehdx t dh input data hold time from chip enable high 0 0 ns t ehel1 (9,10) t wrc chip enable high pulse width to chip enable low 20 20 ns t ehel2 (10) t cp chip enable high pulse width to chip enable low 10 12 ns t ehwh t wh write enable low hold time 0 0 ns t ehwl t wh write enable high hold time 0 0 ns t elax (2) t ah address hold time from chip enable low 35 40 ns t eleh1 (1,8) t cw chip enable write pulse width 45 50 ns t eleh2 (1,9,10) t wrc chip enable write recovery time 20 20 ns t elel t wc chip enable write cycle time 80 90 ns t elwl t cs chip enable write set-up time 0 1000 0 1000 ns t ghax (7) t ohah address hold time from output enable high ?5 ?5 ns t ghbh t bh lb , ub hold time from output enable high ?5 ?5 ns t ghel (6) t ohcl output enable high to chip enable low set-up time ?5 ?5 ns t ghwl (3) t oes output enable set-up time 0 1000 0 1000 ns t whav (1,3,9,10) t wr write enable high to address valid 20 1000 20 1000 ns t whbh t bh lb , ub hold time from write enable high ?5 ?5 ns t whdx t dh input data hold time from write enable high 0 0 ns t wheh t ch chip enable write hold time 0 1000 0 1000 ns t whel t ws write enable high set-up time 0 0 ns t whwl (1,3,9,10) t wr write enable write recovery time to write enable low 20 1000 20 1000 ns t wlav t wc write enable low to address valid write cycle time 80 90 ns t wlax (2) t ah address hold time from write enable low 35 40 ns
m69aw024b 18/29 note: 1. the minimum value must be equal to or greater than the sum of actual t eleh (or t wlwh ). 2. the new write address is valid from either e1 high or w high. 3. t axgl1 is specified from end of t avax (min) and is a reference value when access time is determined by t axgl1 . if actual value is lower than specified minimum value, t axgl1 is increased by the difference between the actual value and the specified minimum value. 4. t axgl1 maximum is applicable if e1 is kept low and both w and g are kept high. 5. t axgl2 is the absolute minimum value if the write cycle terminates with w and e1 low. 6. t ghel (min) must be kept if the read cycle is not performed prior to the write cycle. in case g is disabled after a time t ghel (min), w must go low t eleh2 (min) after e1 goes low. in other words, the read cycle is initiated if t ghel (min) is not kept. 7. applicable if e1 stays low after the read cycle. 8. t eleh or t wlwh is applicable if the write operation is initiated by e1 or w , respectively. 9. if the write operation is terminated by w followed by e1 high, the sum of actual t elwl and t wlwh and the sum of actual t avwl and t wlwh must be equal or greater than 60ns. 10. t ehel1 or t whwl is applicable if the write operation is terminated by e1 or w , respectively. if e1 goes high before t whwl (min), then t ehel1 (min) must apply. 11. t ehel1 and t ehel2 is applicable if write operation is terminated by e1 and w , respectively. in case e1 is brought to high before sat- isfaction of t ehel2 (min), the t ehel1 (min) is also applied. 12. for other timings please refer to table 7., read and standby modes ac characteristics . t wlel t ws write enable low set-up time 0 0 ns t wlwh (1,8) t wp write enable write pulse width 45 50 ns t wlwl t wc write enable write cycle time 80 90 ns symbol alt. parameter m69aw024b unit ?60 ?70 min max min max
19/29 m69aw024b figure 11. e1 controlled, write ac waveforms note: 1. e2 must be high during the write cycle. figure 12. w controlled, single write ac waveforms note: 1. e2 must be high during the write cycle. ai07411c valid data input a0-a19 e1 g dq0-dq15 address valid address valid tdveh tehdx tghel tblel twlel teleh1 tehel1 telel tehbh tblel tehwh twlel tavel telax w ub, lb tavel ai07412c valid data input a0-a19 e1 g dq0-dq15 address valid address valid tdvwh twhdx tghwl tblwl tehel2 twlwl twlwh twhwl tghax tavwl w ub, lb tavwl address valid twlax twheh tghel telwl twhbh tghqz tghbh
m69aw024b 20/29 figure 13. w controlled, continuous write ac waveforms note: 1. e2 must be high during the write cycle. figure 14. e1 controlled, read/write ac waveforms note: 1. write address is valid from the falling edge of either e1 or w , whichever occurs later. ai07413c valid data input a0-a19 e1 g dq0-dq15 address valid address valid tdvwh twhdx tghwl twlwl twlwh twhwl tghax tavwl w ub, lb tavwl address valid twlax tghel telwl twhbh tghqz tblwl tblwl tghbh ai07414c write data input a0-a19 e1 g dq0-dq15 address valid address valid tdveh tehdx tghel twhel telel teleh1 tehel1 tehax tavel w ub, lb tavel address valid telax tehel1 tehqz twlel tehwh tehwl tglqx tehqx read data output tehbh tblgl tblel tehbh elgl
21/29 m69aw024b figure 15. e1 controlled, read/write ac waveforms 2 figure 16. g controlled read, w controlled write ac waveforms note: 1. e1 can be tied to low for w and g controlled operation. when e1 is tied to low, output is exclusively controlled by g . ai07415c write data input a0-a19 e1 g dq0-dq15 read address tehqx twlel teleh tehel1 tavel w ub, lb tehax tehwh twhel tehwl tehqz tghel tehdx read data output write address tehel1 tavel tblel telqx telgl tblel tehbh tehel1(min) telqv tehbh ai07416c write data input a0-a19 e1 g dq0-dq15 write address read address tdvwh twhdx tghwl twlav twlwh twhav tghax tavwl w ub, lb tavgl1 address valid twlax tghqz tglqx tghqx read data output low tblgl tblwl tghbh twhbh
m69aw024b 22/29 figure 17. g controlled read, w controlled write ac waveforms 2 note: 1. e1 can be tied to low for w and g controlled operation. when e1 is tied to low, output is exclusively controlled by g . ai07417c write data input a0-a19 e1 g dq0-dq15 read address tghqx tavgh w ub, lb tghax twhav tghqz tghwl twhdx read data output write address tavwl tblwl tglqx tavgl1 tglqv low twhbh tblgl tghbh
23/29 m69aw024b table 9. power down and power-up ac parameters note: 1. some data may be written to any address location if t ehwh is less than the minimum required time. 2. the device has to enter and exit power down mode after t chcl . 3. the input transition time used in ac measurements is 5ns. figure 18. standby mode entry ac waveforms, after read or write note: both t ehgh and t ehwh define the earliest entry timing for stand-by mode. if either of timing is not satisfied, it takes the t avax (min) period from either the last address transition of a0, a1 and a2, or e1 rising edge. symbol alt. parameter m69aw024b unit ?60 ?70 min max min max t clel t csp e2 low setup time for power down entry 10 10 ns t elch t c2lp e2 low hold time after power down entry 80 90 ns t chel t chh e1 high hold time following e2 high after power- down exit (sleep mode only) 350 350 s t ehel t chhp e1 high hold time following e2 high after power- down exit (not in sleep mode) 400 400 s t ehch1 t chs e1 high setup time following e2 high after power- down exit 10 10 ns t ehch2 t c2lh power-up time 1 50 50 s t chcl1 2 t chcl2 2 t c2hl power-up time 2 50 50 s t ehgh t chox e1 high to g invalid time for standby entry 10 10 ns t ehwh t chwx e1 high to w invalid time for standby entry 10 10 ns t t t t input transition time 1 25 1 25 ns ai07741 e1 g w tehgh tehwh active (write) standby active (read) standby e1 g w
m69aw024b 24/29 figure 19. power-down ac waveforms note: this power down mode can be also be used in ?power-up mode ac waveforms - 2?. figure 20. power-up mode ac waveforms - 1 note: t vhch starts from v cc reaching v cc (min). figure 21. power-up mode ac waveforms - 2 note: t vhcl starts from v cc reaching v cc (min). e1 must be taken high prior to, or together with, the rising edge on e2. telch ai07739 e1 tehch1 tchel tclel e2 dq power down entry power down mode power down exit hi-z ai07740 v cc v cc min e2 e1 tchel tehch2 tehch1 0v ai07742 v cc v cc min e2 e1 tchel tchcl2 tclel tehch1 telch 0v tchcl1
25/29 m69aw024b figure 22. power-up mode ac waveforms - 3 note: both e1 and e2 must go high as v cc reaches v cc (min). if not, the timings provided in power-up mode ac waveforms 1 ( figure 20. ) or power-up mode ac waveforms 2 ( figure 21. ) should be used to ensure proper operation. table 10. low v cc data retention characteristics note: 1. t a = ?30 to 85c 2. all other inputs at v ih v cc ?0.2v or v il 0.2v. 3. see figure 23. for measurement points. figure 23. low v cc data retention ac waveforms symbol parameter test condition 1 min max unit v dr (2) supply voltage (data retention) e1 = e2 v cc ?0.2v, or e1 = v ih and e2 = v ih 2.3 3.5 v i ccdr supply current (data retention) v cc = v dr , v in 0.2v or v cc ?0.2v, e1 = v cc ?0.2v and e2 v cc ?0.2v, i out = 0ma 70 a t cdr (2,3) chip deselected to data retention time v cc = 2.7v 0ns t r (3) operation recovery time v cc = 2.7v 100 ns ? v/ ? t (3) vcc voltage transition time 0.2 v/s ai08054c v cc v cc min e2 e1 0v tehel ai07408 data retention mode ? v/ ? t 3.5v tcdr 2.7v 2.3v e1 e1 and e2 v dd ? 0.2v or v ih (min) v cc e2 0.4v v ss tr ? v/ ? t data bus must be hi-z
m69aw024b 26/29 package mechanical figure 24. tfbga48 6x8mm - 6x8 ball array, 0.75mm pitch, package outline, bottom view note: drawing is not to scale. table 11. tfbga48 6x8mm - 6x8 ball array, 0.75mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 3.750 ? ? 0.1476 ? ? ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.250 ? ? 0.2067 ? ? e 0.750 ? ? 0.0295 ? ? fd 1.125 ? ? 0.0443 ? ? fe 1.375 ? ? 0.0541 ? ? sd 0.375 ? ? 0.0148 ? ? se 0.375 ? ? 0.0148 ? ? e1 e d1 d eb a2 a1 a bga-z26 ddd fd fe sd se e ball "a1"
27/29 m69aw024b part numbering table 12. ordering information scheme the notation used for the device number is as shown in table 12. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest stmi- croelectronics sales office. example: m69aw024 b l 70 zb 8 t device type m69 = 1t/1c memory cell architecture mode a = asynchronous operating voltage w = 2.7 to 3.3v array organization 024 = 16 mbit (1m x16) option 1 b = 2 chip enable; no write and standby from ub and lb option 2 l = low leakage speed class 60 = 60ns 70 = 70ns package zb = tfbga48 6x8mm - 6x8 ball array, 0.75mm pitch temperature range 8 = ?30 to 85c shipping method t = tape & reel packing
m69aw024b 28/29 revision history table 13. document revision history date rev. revision details 01-jun-2002 1.0 first issue 04-feb-2003 2.0 document completely revised 14-mar-2003 2.1 ac testing load circuit revised; 60ns access time device added 29-apr-2003 2.2 timing parameter names changed in tables and illustrations 25-jul-2003 2.3 chip enable signals e1 and e2 must change together during power-on sequence 07-may-2004 3.0 datasheet title updated. table 2., operating modes updated for read operations. 29-sep-2004 4.0 minor modification in first paragraph of summary description.
29/29 m69aw024b information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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