data brief for further information contact your local stmicroelectronics sales office. february 2012 doc id 022766 rev 1 1/10 10 EVAL6474H stepper motor driver mounting the l6474 features voltage range from 8 v to 45 v phase current up to 3 a rms spi with daisy chain feature socket for external resonator or crystal flag led indicator suitable for use in combination with the steval-pcc009v2 description the EVAL6474H demonstration board is a microstepping motor driver. in combination with the steval-pcc009v2 communication board and the easyspin evaluation software, the board allows the user to investigate all the features of the l6474 device. the EVAL6474H supports the daisy chain configuration making it suitable for the evaluation of the l6474 in multi-motor applications. EVAL6474H www.st.com
board description EVAL6474H 2/10 doc id 022766 rev 1 1 board description figure 1. jumper and connector location table 1. EVAL6474H specifications parameter value supply voltage (vs) 8 to 45 v maximum output current (each phase) 3 a rms logic supply voltage (vreg) externally supplied: 3.3 v internally supplied: 3 v typical logic interface voltage (vdd) externally supplied: 3.3 v or 5 v internally supplied: vreg low level logic input voltage 0 v high level logic input voltage vdd (1) 1. all logic inputs are 5 v tolerant. operating temperature -25 to +125 c l6474h thermal resistance junction-to-ambient 21 c/w typical phase a connector power supply connector (8 v - 45 v) master spi connector sync output flag led (red) adcin input regulation jp1: vdd supply from master spi connector jp2: jp4: stck to slave spi connector jp5: dir to slave spi connector vdd to vreg connection oscin/oscout connector jp3: daisy chain termination phase b connector slave spi connector application reference area am10269v1
EVAL6474H board description doc id 022766 rev 1 3/10 table 2. jumpers and connectors description name type function j1 power supply motor supply voltage j5 power output bridge a outputs j6 power output bridge b outputs j2 spi connector master spi j3 spi connector slave spi j4 nm connector oscin and oscout pins j7 nm connector sync output tp1 (vs) test point motor supply voltage test point tp4 (vdd) test point logic interface supply voltage test point tp5 (vreg) test point logic supply voltage/l6474 internal regulator test point tp6 (gnd) test point ground test point tp2 (stck) test point step clock input test point tp8 (dir) test point dir output test point tp3 (stby/res) test point stby/res input test point tp7 (flag) test point flag output test point table 3. slave spi connector pinout (j11) pin number type description 1 digital input l6474 direction input 2 open drain output l6474 flag output 3 ground ground 4 supply ext_vdd (can be used as external logic power supply) 5 digital output spi master in slave out signal (connected to the l6474 sdo output through daisy chain termination jumper jp2) 6 digital input spi serial clock signal (connected to l6474 ck input) 7 digital input spi master out slave in signal (connected to the l6474 sdi input) 8 digital input spi slave select signal (connected to the l6474 cs input) 9 digital input l6474 step-clock input 10 digital input l6474 standby/reset input
board description EVAL6474H 4/10 doc id 022766 rev 1 figure 2. EVAL6474H schematic vdd vreg vs spi_out gnd application reference flag dir stby/res stck 1a 2a 1b 2b vs gnd sync option stck dir ncs ck sdi sdo adcin dir flag ck ncs stby_reset stck miso sdi flag stby_reset sdo miso ck flag stby_reset ncs sdo miso stck dir vs vreg vdd vreg vdd vdd vreg ext_vdd vs ext_vdd vreg vdd ext_vdd vdd vdd vs tp8 1 j1 morsv-508-2p 1 2 + c9 100uf/63v jp3 + c2 47uf/6.3v u1 l6474 vdd 17 vreg 6 oscin 7 oscout 8 cp 10 vboot 11 adcin 5 vsa 2 vsa 26 vsb 12 vsb 16 pgnd 13 pgnd 27 out1a 1 out2a 28 out1b 14 out2b 15 agnd 9 dir 4 dgnd 21 sync 22 flag 24 sdo 18 sdi 20 ck 19 cs 23 stby_res 3 stck 25 epad 29 jp5 j3 con-flat-5x2-180m 1 2 3 4 5 6 7 8 9 10 tp1 1 j7 n.m. 1 j5 morsv-508-2p 1 2 r6 39k c11 10nf/50v c5 100nf/4v c14 1nf/4v c1 220nf/16v j6 morsv-508-2p 1 2 j4 n.m. 1 2 c13 3.3nf/4v tp6 1 c8 100nf/50v dl1 red 2 1 jp4 tp2 1 r1 39k c10 100nf/50v tp4 1 tp7 1 + c4 10uf/4v c7 100nf/50v r3 39k tp5 1 tp3 1 jp1 + c9a 100uf/63v r5 470 d1 bav99 1 2 3 c15 1nf/4v c6 100nf/50v r4 39k c3 100nf/6.3v jp2 r2 50k 1 3 2 c16 1nf/4v j2 spi_in 1 2 3 4 5 6 7 8 9 10 am10276v1
EVAL6474H board description doc id 022766 rev 1 5/10 table 4. bill of material item quantity reference value package 1 1 c1 220 nf/16 v capc-0603 2 1 c2 47 f/6.3 v capc-3216 3 1 c3 100 nf/6.3 v capc-0603 4 1 c4 10 f/4 v capc-3216 5 1 c5 100 nf/4 v capc-0603 6 4 c6,c7,c8,c10 100 nf/50 v capc-0603 7 1 c9a 100 f/63 v cape-r8h12-p35 8 1 c9 100 f/63 v capes-r10hxx 9 1 c11 10 nf/50 v capc-0603 10 1 c13 3.3 nf/4 v capc-0603 11 3 c14,c15,c16 1 nf/4 v capc-0603 12 1 dl1 led diode (red) ledc-0805 13 1 d1 bav99 sot-23 14 1 jp1 jumper - open jp2so 15 4 jp2,jp3,jp4,jp5 jumper - closed jp2so 16 3 j1,j5,j6 screw connector 2 poles morsv-508-2p 17 2 j2, j3 pol. idc male header vertical 10 poles con-flat-5x2-180m 18 1 j4 n.m. strip254p-m-2 19 1 j7 n.m. tpth-44sq70 20 4 r1,r3,r4,r6 39 k resc-0603 21 1 r2 50 k trimm-100x50x110-64w 22 1 r5 470 resc-0603 23 8 tp1,tp2,tp3,tp4,t p5,tp6,tp7,tp8 test point th 24 1 u1 l6474h htssop28
board description EVAL6474H 6/10 doc id 022766 rev 1 figure 3. EVAL6474H - layout (silk screen) figure 4. EVAL6474H - layout (top layer) am10270v1 am10271v1
EVAL6474H board description doc id 022766 rev 1 7/10 figure 5. EVAL6474H - layout (inner layer 2) figure 6. EVAL6474H - layout (inner layer 3) am10272v1 am1027 3 v1
board description EVAL6474H 8/10 doc id 022766 rev 1 figure 7. EVAL6474H - layout (bottom layer) 1.1 thermal data figure 8. thermal impedance graph am10274v1 110 100 1000 0 5 10 15 20 25 time ( s ) zth (c/w) am10275v1
EVAL6474H revision history doc id 022766 rev 1 9/10 2 revision history table 5. document revision history date revision changes 02-feb-2012 1 initial release.
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