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rev. 1.1 8/11 copyright ? 2011 by sili con laboratories si8410/20/21 / si8422/23 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) l ow -p ower , s ingle and d ual -c hannel d igital i solators features applications safety regulatory approvals description silicon lab's family of ultra-low-power di gital isolators are cmos devices offering substantial data rate, propagation delay, power, size, reliability, and external bom advantages when compared to legacy isolation technologies. the operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. all device versions have schmitt trigger inputs for high noise immunity and only require v dd bypass capacitors. data rates up to 150 mbps are supported, and all devices achieve worst-case propagation delays of less than 10 ns. ordering options include a choice of isolation ratings (up to 5 kv) and a selectable fail-safe operating mode to control the default output state during power loss. all products are safety certified by ul, csa, and vde, and products in wide-body packages support reinforced insulation withstanding up to 5 kv rms . ? high-speed operation ?? dc to 150 mbps ? no start-up initialization required ? wide operating supply voltage: 2.6?5.5 v ? up to 5000 v rms isolation ? high electromagnetic immunity ? ultra low power (typical) 5 v operation: ?? < 2.6 ma/channel at 1 mbps ?? < 6.8 ma/channel at 100 mbps 2.70 v operation: ?? < 2.3 ma/channel at 1 mbps ?? < 4.6 ma/channel at 100 mbps ? schmitt trigger inputs ? selectable fail-safe mode ?? default high or low output ? precise timing (typical) ?? 11 ns propagation delay max ?? 1.5 ns pulse width distortion ?? 0.5 ns channel-channel skew ?? 2 ns propagation delay skew ?? 5 ns minimum pulse width ? transient immunity 45 kv/s ? wide temperature range ?? ?40 to 125 c at 150 mbps ? rohs compliant packages ?? soic-16 wide body ?? soic-8 narrow body ? industrial auto mation systems ? medical electronics ? hybrid electric vehicles ? isolated switch mode supplies ? isolated adc, dac ? motor control ? power inverters ? communication systems ? ul 1577 recognized ?? up to 5000 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation ) ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) ?? en60950-1 (reinforced insulation) ordering information: see page 29.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 2 rev. 1.1
rev. 1.1 3 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 3. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2. under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4. fail-safe operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5. typical performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. pin descriptions (wide-body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5. pin descriptions (narrow-b ody soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7. package outline: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8. land pattern: 16-pin wide-b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9. package outline: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 10. land pattern: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11. top marking: 16-pin wide b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 12. top marking: 8-pin narrow -body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 4 rev. 1.1 1. electrical specifications table 1. electrical characteristics (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 2.15 2.3 2.5 v vdd negative-going lockout hysteresis vdd hys 45 75 95 mv positive-going input threshold vt+ all inputs rising 1.6 ? 1.9 v negative-going input threshol d vt? all inputs falling 1.1 ? 1.4 v input hysteresis v hys 0.40 0.45 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?5 0? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.0 3.0 1.0 1.5 1.5 4.5 1.5 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.7 5.8 1.7 2.0 2.6 8.7 2.6 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.7 1.7 3.7 3.7 2.6 2.6 5.6 5.6 ma si8422ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 3.7 3.7 1.7 1.7 5.6 5.6 2.6 2.6 ma si8423ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 5.4 1.7 1.3 1.7 8.1 2.6 2.0 2.6 ma notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.1 5 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 1 mbps supply current (all inputs = 500 khz square wave, c l = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 2.0 1.1 3.0 1.7 ma si8420ax, bx v dd1 v dd2 ? ? 3.5 1.9 5.3 2.9 ma si8421ax, bx v dd1 v dd2 ? ? 2.8 2.8 4.2 4.2 ma si8422ax, bx v dd1 v dd2 ? ? 2.8 2.8 4.2 4.2 ma si8423ax, bx v dd1 v dd2 ? ? 3.4 1.9 5.1 2.9 ma 10 mbps supply current (all inputs = 5 mhz square wave, c l = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 2.1 1.5 3.1 2.1 ma si8420bx v dd1 v dd2 ? ? 3.6 2.6 5.4 3.6 ma si8421bx v dd1 v dd2 ? ? 3.2 3.2 4.5 4.5 ma si8422bx v dd1 v dd2 ? ? 3.2 3.2 4.5 4.5 ma si8423bx v dd1 v dd2 ? ? 3.4 2.5 5.1 3.5 ma table 1. electrical characteristics (continued) (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 6 rev. 1.1 100 mbps supply current (all inputs = 50 mhz square wave, c l = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 2.1 5.0 3.1 6.3 ma si8420bx v dd1 v dd2 ? ? 3.7 9.8 5.4 12.3 ma si8421bx v dd1 v dd2 ? ? 6.8 6.8 8.5 8.5 ma si8422bx v dd1 v dd2 ? ? 6.8 6.8 8.5 8.5 ma si8423bx v dd1 v dd2 ? ? 3.4 9.2 5.1 11.5 ma timing characteristics si8422ax, si8423ax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns si8422bx, si8423bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 1 4.0 8.0 11 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? 1.5 3.0 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 5n s all models output rise time t r c l = 15 pf ? 2.0 4.0 ns output fall time t f c l = 15 pf ? 2.0 4.0 ns peak eye diagram jitter t jit(pk) see figure 6 ? 350 ? ps common mode transient immunity cmti v i =v dd or 0 v 20 45 ? kv/s start-up time 3 t su ?1 54 0 s table 1. electrical characteristics (continued) (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.1 7 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) figure 1. propagation delay timing typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 8 rev. 1.1 table 2. electrical characteristics (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 2.15 2.3 2.5 v vdd negative-going lockout hysteresis vdd hys 45 75 95 mv positive-going input threshold vt+ all inputs rising 1.6 ? 1.9 v negative-going input threshol d vt? all inputs falling 1.1 ? 1.4 v input hysteresis v hys 0.40 0.45 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance (si8410/20) 1 z o ?5 0? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.0 3.0 1.0 1.5 1.5 4.5 1.5 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.7 5.8 1.7 2.0 2.6 8.7 2.6 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.7 1.7 3.7 3.7 2.6 2.6 5.6 5.6 ma si8422ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 3.7 3.7 1.7 1.7 5.6 5.6 2.6 2.6 ma si8423ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 5.4 1.7 1.3 1.7 8.1 2.6 2.0 2.6 ma notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
rev. 1.1 9 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 1 mbps supply current (all inputs = 500 khz square wave, c l = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 2.0 1.1 3.0 1.7 ma si8420ax, bx v dd1 v dd2 ? ? 3.5 1.9 5.3 2.9 ma si8421ax, bx v dd1 v dd2 ? ? 2.8 2.8 4.2 4.2 ma si8422ax, bx v dd1 v dd2 ? ? 2.8 2.8 4.2 4.2 ma si8423ax, bx v dd1 v dd2 ? ? 3.4 1.9 5.1 2.9 ma 10 mbps supply current (all inputs = 5 mhz square wave, c l = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 2.0 1.3 3.0 1.8 ma si8420bx v dd1 v dd2 ? ? 3.5 2.3 5.3 3.2 ma si8421bx v dd1 v dd2 ? ? 3.0 3.0 4.4 4.4 ma si8422bx v dd1 v dd2 ? ? 3.0 3.0 4.4 4.4 ma si8423bx v dd1 v dd2 ? ? 3.4 2.2 5.1 3.1 ma table 2. electrical characteristics (continued) (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 10 rev. 1.1 100 mbps supply current (all inputs = 50 mhz square wave, c l = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 2.0 3.6 3.0 4.5 ma si8420bx v dd1 v dd2 ? ? 4.5 7.0 5.3 8.8 ma si8421bx v dd1 v dd2 ? ? 5.3 5.3 6.6 6.6 ma si8422bx v dd1 v dd2 ? ? 5.3 5.3 6.6 6.6 ma si8423bx v dd1 v dd2 ? ? 3.4 6.6 5.1 8.3 ma timing characteristics si8422ax, si8423ax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh ? t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns si8422bx, si8423bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 1 4.0 8.0 11 ns pulse width distortion |t plh ? t phl | pwd see figure 1 ? 1.5 3.0 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 5n s table 2. electrical characteristics (continued) (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
rev. 1.1 11 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) all models output rise time t r c l = 15 pf ? 2.0 4.0 ns output fall time t f c l = 15 pf ? 2.0 4.0 ns peak eye diagram jitter t jit(pk) see figure 6 ? 350 ? ps common mode transient immunity cmti v i =v dd or 0 v 20 45 ? kv/s start-up time 3 t su ?1 54 0 s table 2. electrical characteristics (continued) (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 12 rev. 1.1 table 3. electrical characteristics 1 (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 2.15 2.3 2.5 v vdd negative-going lockout hysteresis vdd hys 45 75 95 mv positive-going input threshold vt+ all inputs rising 1.6 ? 1.9 v negative-going input threshol d vt? all inputs falling 1.1 ? 1.4 v input hysteresis v hys 0.40 0.45 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0. 4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 2 z o ?5 0? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.0 3.0 1.0 1.5 1.5 4.5 1.5 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.7 5.8 1.7 2.0 2.6 8.7 2.6 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.7 1.7 3.7 3.7 2.6 2.6 5.6 5.6 ma si8422ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 3.7 3.7 1.7 1.7 5.6 5.6 2.6 2.6 ma si8423ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 5.4 1.7 1.3 1.7 8.1 2.6 2.0 2.6 ma notes: 1. specifications in this table are al so valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 4. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.1 13 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 1 mbps supply current (all inputs = 500 khz square wave, c l = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 2.0 1.1 3.0 1.7 ma si8420ax, bx v dd1 v dd2 ? ? 3.5 1.9 5.3 2.9 ma si8421ax, bx v dd1 v dd2 ? ? 2.8 2.8 4.2 4.2 ma si8422ax, bx v dd1 v dd2 ? ? 2.8 2.8 4.2 4.2 ma si8423ax, bx v dd1 v dd2 ? ? 3.3 1.8 5.0 2.8 ma 10 mbps supply current (all inputs = 5 mhz square wave, c l = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 2.0 1.1 3.0 1.7 ma si8420bx v dd1 v dd2 ? ? 3.5 2.1 5.3 3.0 ma si8421bx v dd1 v dd2 ? ? 2.9 2.9 4.3 4.3 ma si8422bx v dd1 v dd2 ? ? 2.9 2.9 4.3 4.3 ma si8423bx v dd1 v dd2 ? ? 3.4 2.0 5.1 2.9 ma table 3. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. specifications in this table are al so valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 4. start-up time is the time period from the applic ation of power to valid data at the output.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 14 rev. 1.1 100 mbps supply current (all inputs = 50 mhz square wa ve, cl = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 2.0 2.0 3.0 3.0 ma si8420bx v dd1 v dd2 ? ? 3.5 5.5 5.3 6.9 ma si8421bx v dd1 v dd2 ? ? 4.6 4.6 5.8 5.8 ma si8422bx v dd1 v dd2 ? ? 4.6 4.6 5.8 5.8 ma si8423bx v dd1 v dd2 ? ? 3.4 5.2 5.1 6.5 ma timing characteristics si8422ax, si8423ax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 3 t psk(p-p) ??4 0n s channel-channel skew t psk ??3 5n s si8422bx, si8423bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 1 4.0 8.0 11 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? 1.5 3.0 ns propagation delay skew 3 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 5n s table 3. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. specifications in this table are al so valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 4. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.1 15 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) all models output rise time t r c l = 15 pf ? 2.0 4.0 ns output fall time t f c l = 15 pf ? 2.0 4.0 ns peak eye diagram jitter t jit(pk) see figure 6 ? 350 ? ps common mode transient immunity cmti v i =v dd or 0 v 20 45 ? kv/s start-up time 4 t su ?1 54 0 s table 4. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg ?65 ? 150 c operating temperature t a ?40 ? 125 c supply voltage v dd1 , v dd2 ?0.5 ? 6.0 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive channel i o ??10ma lead solder temperature (10 s) ? ? 260 c maximum isolation voltage (1 s) nb soic-8 ? ? 4500 v rms maximum isolation voltage (1 s) wb soic-16 ? ? 6500 v rms notes: 1. permanent device damage may occur if the above absolut e maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temper ature from ?40 to 150 c. table 3. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. specifications in this table are al so valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 4. start-up time is the time period from the applic ation of power to valid data at the output.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 16 rev. 1.1 table 5. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a 150 mbps, 15 pf, 5 v ?40 25 125 c supply voltage v dd1 2.70 ? 5.5 v v dd2 2.70 ? 5.5 v *note: the maximum ambient temperature is dependent upon data frequency, output loading, the number of operating channels, and supply voltage. table 6. regulatory information* csa the si84xx is certified under csa component acceptan ce notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. 60601-1: up to 125 v rms reinforced insulation working voltage; up to 380 v rms basic insulation working voltage. vde the si84xx is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 891 v peak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. ul the si84xx is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic insulation. *note: regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "6. ordering guide" on page 29.
rev. 1.1 17 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) table 7. insulation and safety-related specifications parameter symbol test condition value unit wb soic-16 nb soic-8 nominal air gap (clearance) 1 l(io1) 8.0 min 4.9 min mm nominal external tracking (creepage) 1 l(io2) 8.0 min 4.01 min mm minimum internal gap (internal clearance) 0.014 0.008 mm tracking resistance (proof tracking index) pti iec60112 600 600 v rms erosion depth ed 0.019 0.040 mm resistance (input-output) 2 r io 10 1,2 10 1,2 ? capacitance (input-output) 2 c io f = 1 mhz 2.0 1.0 pf input capacitance 3 c i 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in ?7. package outline: 16-pin wide body soic?, ?9. package ou tline: 8-pin narrow body soic?. vde certifies the clearance and creepage limits as 8.5 mm minimum for the wb soic-16 package and 4.7 mm minimum for the nb soic-8 package. ul does not impose a clearance and creepage minimum for componen t level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic-8 and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si84xx is conver ted into a 2-terminal device. pins 1?8 (1?4, nb soic-8) are shorted together to fo rm the first terminal and pins 9?16 (5?8, nb so ic-8) are shorted togethe r to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 8. iec 60664-1 (vde 0844 part 2) ratings parameter test conditions specification nb soic8 wb soic 16 basic isolation group material group i i installation classification rated mains voltages < 150 v rms i-iv i-iv rated mains voltages < 300 v rms i-iii i-iv rated mains voltages < 400 v rms i-ii i-iii rated mains voltages < 600 v rms i-ii i-iii
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 18 rev. 1.1 table 9. iec 60747-5-2 insulation characteristics for si84xxxx* parameter symbol test condition characteristic unit wb soic-16 nb soic-8 maximum working insulation voltage v iorm 891 560 vpeak input to output test voltage method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1671 1050 transient overvoltage v iotm t = 60 sec 6000 4000 vpeak pollution degree (din vde 0110, table 1) 22 insulation resistance at t s , v io =500v r s >10 9 >10 9 ? *note: maintenance of the safety data is ensu red by protective circuits. the si84xx provides a climate classification of 40/125/21. table 10. iec safety limiting values 1 parameter symbol test condition min typ max unit wb soic-16 nb soic-8 case temperature t s ? ? 150 150 c safety input, output, or supply current i s ? ja = 140 c/w (nb soic-8), 100 c (wb soic-16), v i =5.5v, t j =150c, t a =25c ? ? 220 160 ma device power dissipation 2 p d ? ? 150 150 mw notes: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figures 2 and 3. 2. the si84xx is tested with vdd1 = vdd2 = 5.5 v, t j =150oc, c l = 15 pf, input a 150 mbps 50% duty cycle square wave.
rev. 1.1 19 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) figure 2. (wb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 3. (nb soic-8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 11. thermal characteristics parameter symbol wb so ic-16 nb soic-8 unit ic junction-to-air thermal resistance ? ja 100 140 oc/w 0 200 150 100 50 500 250 125 0 case temperature (oc) safety-limiting values (ma) 460 375 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.3 v v dd1 , v dd2 = 5.5 v 360 220 0 200 150 100 50 400 200 100 0 case temperature (oc) safety-limiting values (ma) 320 300 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.3 v v dd1 , v dd2 = 5.5 v 270 160
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 20 rev. 1.1 2. functional description 2.1. theory of operation the operation of an si84xx channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initializat ion at start-up. a simplified block diagra m for a single si84xx channel is shown in figure 4. figure 4. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 5 for more details. figure 5. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
rev. 1.1 21 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 2.2. eye diagram figure 6 illustrates an eye-diagram take n on an si8422. for the data source, the test used an anritsu (mp1763c) pulse pattern generator set to 1000 ns/div. the output of the generator's clock and data from an si8422 were captured on an oscillosc ope. the results illustra te that data integrity was mainta ined even at the high data rate of 150 mbps. the results also show that 2 ns pulse wid th distortion and 250 ps peak jitter were exhibited. figure 6. eye diagram
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 22 rev. 1.1 3. device operation device behavior during start-up, normal operation, an d shutdown is shown in figu re 7, where uvlo+ and uvlo- are the positive-going and negative-going thresholds resp ectively. refer to table 12 to determine outputs when power supply ( v dd ) is not present. table 12. si84xx logic operation table v i input 1,4 vddi state 1,2,3 vddo state 1,2,3 v o output 1,4 comments hp p h normal operation. lp p l x 5 up p h 6 (si8422/23) l 6 (si8410/20/21) upon transition of vddi from unpowered to powered, v o returns to the same state as v i in less than 1 s. x 5 p up undetermined upon transition of vddo from unpowered to powered, v o returns to the same state as v i within 1 s. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. 2. powered (p) state is defined as 2.70 v < vdd < 5.5 v. 3. unpowered (up) state is defined as vdd = 0 v. 4. x = not applicable; h = logic high; l = logic low. 5. note that an i/o can power the die for a given side through an internal diode if its source has adequate current. 6. see "6. ordering guide" on page 29 for details. this is the se lectable fail-safe operating mode (ordering option). some devices have default output state = h, and some have default output state = l, depending on the ordering part number (opn).
rev. 1.1 23 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 3.1. device startup outputs are held low during powerup until v dd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs. 3.2. under voltage lockout under voltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when v dd is below its specified operating circuits range. both side a and side b each have their own undervoltage lockout monitors. each side can enter or exit uvlo in dependently. for example, side a unconditionally enters uvlo when v dd1 falls below v dd1(uvlo?) and exits uvlo when v dd1 rises above v dd1(uvlo+) . side b operates the same as side a with respect to its v dd2 supply. figure 7. device behavior during normal operation input v dd1 uvlo- v dd2 uvlo+ uvlo- uvlo+ output tstart tstart tstart tphl tplh tsd
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 24 rev. 1.1 3.3. layout recommendations to ensure safety in the end us er application, high voltage circ uits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, su ch as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). table 6 on page 16 and table 7 on page 17 detail the working voltage and creepage/clearan ce capabilities of the si84xx. thes e tables also detail the component standards (ul1577, iec60747, csa 5a), which are readily accepted by certif ication bodies to provide proof for end-system specifications requirements. refer to the en d-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1. supply bypass the si841x/2x family requires a 0.1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, it is further recommended that the user also add 1 f bypass capacitors and include 100 ? resistors in series with the inputs and outputs if the system is excessively noisy. 3.3.2. pin connections no connect pins are not internally connecte d. they can be left floating, tied to v dd , or tied to gnd. 3.3.3. output pin termination the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces. 3.4. fail-saf e operating mode si84xx devices feature a selectable (by ordering option ) mode whereby the default ou tput state (when the input supply is unpowered) can either be a logic high or logi c low when the output supply is powered. see table 12 on page 22 and "6. ordering guide" on page 29 for more information.
rev. 1.1 25 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 3.5. typical perfor mance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 1, 2, and 3 for actual specification limits. figure 8. si8410 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 9. si8420 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 10. si8421 typical v dd1 or v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 11. si8410 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 12. si8420 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 13. si8422 typical v dd1 or v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 102030405060708090100110120130140150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 2.70v 3.3v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v
26 rev. 1.1 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) figure 14. si8423 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 15. si8423 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 16. propagation delay vs. temperature 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 2.70v 3.3v 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 temperature (degrees c) delay (ns) rising edge falling edge
rev. 1.1 27 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 4. pin descriptions (wide-body soic) name soic-16 pin# si8410 soic-16 pin# si842x type description gnd1 1 1 ground side 1 ground. nc* 2, 5, 6, 8,10, 11, 12, 15 2, 6, 8,10, 11, 15 no connect nc v dd1 3 3 supply side 1 power supply. a1 4 4 digital i/o side 1 digital input or output. a2 nc 5 digital i/o side 1 digital input or output. gnd1 7 7 ground side 1 ground. gnd2 9 9 ground side 2 ground. b2 nc 12 digital i/o side 2 digital input or output. b1 13 13 digital i/o side 2 digital input or output. v dd2 14 14 supply side 2 power supply. gnd2 16 16 ground side 2 ground. *note: no connect. these pins are not internally connected. they can be left floating, tied to v dd or tied to gnd. gnd1 nc a1 v dd1 gnd2 b1 nc gnd2 i s o l a t i o n rf xmitr rf rcvr nc gnd1 nc nc v dd2 nc si8410 wb soic-16 nc nc gnd1 a2 nc a1 v dd1 gnd2 b1 nc b2 gnd2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr nc gnd1 nc nc v dd2 nc si8420/23 wb soic-16 gnd1 a2 nc a1 v dd1 gnd2 b1 nc b2 gnd2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr nc gnd1 nc nc v dd2 nc si8421 wb soic-16 gnd1 a2 nc a1 v dd1 gnd2 b1 nc b2 gnd2 i s o l a t i o n rf xmitr nc gnd1 nc nc v dd2 nc si8422 wb soic-16 rf rcvr rf xmitr rf xmitr rf rcvr
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 28 rev. 1.1 5. pin descriptions (narrow-body soic) name soic-8 pin# si842x type description v dd1 1 supply side 1 power supply. gnd1 4 ground side 1 ground. a1 2 digital i/o side 1 digital input or output. a2 3 digital i/o side 1 digital input or output. b1 7 digital i/o side 2 digital input or output. b2 6 digital i/o side 2 digital input or output. v dd2 8 supply side 2 power supply. gnd2 5 ground side 2 ground. i s o l a t i o n v dd1 v dd2 a1 b1 a2 b2 rf xmitr rf rcvr gnd1 gnd2 si8422 nb soic-8 rf rcvr rf xmitr rf rcvr rf xmitr i s o l a t i o n v dd1 v dd2 a1 b1 rf xmitr rf rcvr a2 b2 rf xmitr rf rcvr gnd1 gnd2 si8423 nb soic-8
rev. 1.1 29 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 6. ordering guide table 13. ordering guide 1 ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side maximum data rate (mbps) default output state isolation rating temp range package type si8422ab-b-is 1 1 1 high 2.5 kvrms ?40 to 125 c nb soic-8 si8422bb-b-is 1 1 150 high si8423ab-b-is 2 0 1 high si8423bb-b-is 2 0 150 high si8410ad-a-is 2 1 0 1 low 5.0 kvrms ?40 to 125 c wb soic-16 si8410bd-a-is 2 1 0 150 low si8420ad-a-is 2 2 0 1 low si8420bd-a-is 2 2 0 150 low si8421ad-b-is 2 1 1 1 low si8421bd-b-is 2 1 1 150 low SI8422AD-B-IS 1 1 1 high si8422bd-b-is 1 1 150 high si8423ad-b-is 2 0 1 high si8423bd-b-is 2 0 150 high notes: 1. all packages are rohs-compliant with pea k reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. moisture sensitivity level is msl2a for wide-body soic-16 packages. moisture sensitivity level is msl2a for narrow-body soic-8 packages. 2. refer to si8410/20/21 data sheet for information regarding 2.5 kv rated versions of these products.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 30 rev. 1.1 7. package outline: 16-pin wide body soic figure 17 illustrates the package details for the si84xx digital isolator. table 1 4 lists the values for the dimensions shown in the illustration. figure 17. 16-pin wide body soic table 14. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b 0.31 0.51 c 0.20 0.33 e 1.27 bsc h 0.25 0.75 l 0.4 1.27 ? 0 7
rev. 1.1 31 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 8. land pattern: 16-pin wide-body soic figure 18 illustrates the reco mmended land pattern details for the si84 xx in a 16-pin wide-body soic. table 15 lists the values for the dimens ions shown in the illustration. figure 18. 16-pin soic land pattern table 15. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 32 rev. 1.1 9. package outline: 8-pin narrow body soic figure 19 illustrates the packa ge details for the si84xx. table 16 lists the values for the dimens ions shown in the illustration. figure 19. 8-pin small outline integrated circuit (soic) package table 16. package diagram dimensions symbol millimeters min max a 1.35 1.75 a1 0.10 0.25 a2 1.40 ref 1.55 ref b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 bsc h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 ? 0 ? 8 ? ?
rev. 1.1 33 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 10. land pattern: 8-pin narrow body soic figure 20 illustrates the recommended land pattern details for the si84xx in an 8-pin narrow-body soic. table 17 lists the values for the dimens ions shown in the illustration. figure 20. pcb land pattern: 8-pin narrow body soic table 17. pcm land pattern dimensions (8-pin narrow body soic) dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 34 rev. 1.1 11. top marking: 16-pin wide body soic figure 21. isolator top marking table 18. top marking explanation line 1 marking: base part number ordering options (see ordering guide for more information). si84 = isolator product series xy = channel configuration x = # of data channels (2, 1) y = # of reverse channels (1, 0) 1,2 s = speed grade a = 1 mbps; b = 150 mbps v = insulation rating a=1kv; b=2.5kv; c=3.75kv; d=5kv line 2 marking: yy = year ww = workweek assigned by assembly subcontractor. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly house. line 3 marking: circle = 1.5 mm diameter (center-justified) ?e3? pb-free symbol. country of origin iso code abbreviation tw = taiwan. notes: 1. the si8422 has one reverse channel. 2. the si8423 has zero reverse channels. si84xysv yywwtttttt tw e3
rev. 1.1 35 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 12. top marking: 8-p in narrow-body soic figure 22. isolator top marking table 19. top marking explanations line 1 marking: base part number ordering options (see ordering guide for more information). si84 = isolator product series xy = channel configuration x = # of data channels (2, 1) y = # of reverse channels (1, 0) 1,2 s = speed grade a = 1 mbps; b = 150 mbps v = insulation rating a=1kv; b=2.5kv; c=3.75kv; d=5kv line 2 marking: yy = year ww = workweek assigned by assembly subcontractor. corresponds to the year and workweek of the mold date. r = product (opn) revision f = wafer fab line 3 marking: circle = 1.1 mm diameter left-justified ?e3? pb-free symbol. first two characters of the manufacturing code. a = assembly site i = internal code xx = serial lot number last four characters of the manufacturing code. notes: 1. the si8422 has one reverse channel. 2. the si8423 has zero reverse channels. si84xysv yywwrf aixx e3
36 rev. 1.1 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) d ocument c hange l ist revision 0.1 to revision 1.0 ? updated ? features? on page 1. ?? updated transient immunity ? removed block diagram from page 1. ? added chip graphics on page 1. ? added peak eye diagram jitter in tables 1, 2, and 3. ?? updated transient immunity ? moved table 12 to page 22. ? added "3. device operation" on page 22. ? added "3.4. fail-safe operating mode" on page 24. ? moved ?typical performance characteristics? to page 25. ? deleted rf radiated emissions section. ? deleted rf magnetic and common-mode transient immunity section. ? updated msl rating to msl2a. revision 1.0 to revision 1.1 ? numerous text edits. ? added notes to tables 18 and 19.
rev. 1.1 37 si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) n otes :
si8410/20/21 (5 kv) si8422/23 (2.5 & 5 kv) 38 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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