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92006hkim no.0459-1/17 LC72F3781 overview the LC72F3781 is a etr controller with an on-chip one-time prom for use with the lc723781n, 2n, 3n, 4 and 5 mask versions. since it has the equivalent electrical performance, pin layout and package as these mask versions, it is ideally suited for checking program operations, starting the initial shipment of finished products and reducing the switchover time frame when specifications are changed. the prom size is 128 kbytes (64k 16 bits). functions ? rom : up to 64k steps (65,535 16-bits) the subroutine area holds 4k steps (4,096 16-bits) ? ram : up to 16k 4-bits (in banks 00 through ff) ? stack : 32levels ? serial i/o : three channels. these circuits can support both 2-wire and 3-wire 8-bit communication techniques, and can be switched between msb first and lsb first operation. one of six internally generated serial transfer clock rates can be selected: 12.5khz, 37.5khz, 187.5khz, 281.25khz, 375khz, and 450khz ? external interrupts : seven interrupt inputs (pins int0 through int5, and the hold pin) these interrupts can be set to switch between rising and falling edges, although the hold pin only supports falling edge detection. ? internal interrupts : seven interrupts ; four intern al timer interrupts, and three serial i/o interrupts. ordering number : en*a0459a cmos ic electronic tuning radio for car audio etr controller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC72F3781 no.0459-2/17 ? interrupt nesting levels : 14 levels interrupts are prioritized in hardware as follows : hold pin>int0 pin>int1 pin>int2 pin>int3 pin>int4 pin>int5 pin> s-i/o0>s-i/o1>s-i/o2>internal tmr0>internal tmr1>internal tmr2> internal tmr3 ? a/d converter : 8-bit resolution and 8 inputs ? general-purpose ports : input ports : 13 output ports : 4 i/o ports : 62 (these pins can be switched between input and output in 1-bit units.) ? pll block : includes a sub-charge pump for high-speed locking. supports dead zone control. built-in unlock detection circuit twelve reference frequencies : 1khz, 3khz, 3.125khz, 5khz, 6.25khz, 9khz, 10khz, 12.5khz, 25khz, 30khz, 50khz, and 100khz ? universal counter : this 20-bit counter can be used for either frequency or period measurement and supports four measurement (calculation) periods : 1ms, 4ms, 8ms, and 32ms ? timers : two fixed timers and two programmable timers (8-bit counters) tmr0 : supports four periods : 10 s, 100 s, 1ms, and 5ms tmr1 : supports four periods : 10 s, 100 s, 1ms, and 10ms tmr2 and tmr3 : programmable 8-bit counters. input clocks with 10 s, 100 s, and 1ms one 125-ms timer flip-flop provided ? beep circuit : provides 12 fixed beep tones : 500hz, 1khz, 2khz, 2.08khz, 2.2khz, 2.5khz, 3khz, 3.125khz, 3.33khz, 3.75khz, 4.17khz, and 7.03khz programmable 8-bit beep tone generator. reference clocks with frequencies of 50khz, 15khz, and 5khz. ? reset : built-in voltage detection reset circuit external reset pin ? cycle time : 1.33 s/833ns (all instructions are one word), x?tal : 4.5mhz/7.2mhz supports software switching (initial cycle time is 1.33 s) ? halt mode : the microcontroller operating clock is stopped in halt mode. there are four conditions that can clear halt mode : interrupt requests, timer flip-flop overflows, port pa inputs, and hold pin inputs. ? operating supply voltage : 4.5 to 5.5v (microcontroller block only : 3.5 to 5.5v) ? package : qip100e ? development tools : emulator : re128v evaluation chip : lc72ev3780 evaluation board : eb-72ev3780
LC72F3781 no.0459-3/17 specifications absolute maximum ratings at ta = 25 c v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max -0.3 to +6.5 v v in 1 pc-port -0.3 to +8 v input voltage v in 2 all input pins other than v in 1 -0.3 to v dd +0.3 v v out 1 pj-port -0.3 to +14 v v out 2 pc-port -0.3 to +8 v output voltage v out 3 all input pins other than v out 1 and v out 2 -0.3 to v dd +0.3 v i out 1 pc, pj-port 0 to +5 ma output current i out 2 pb, pd, pe, pf, pg, pk, pl, pm, pn, po, pp pq, pr, ps, pt-port, eo1, eo2, subpd 0 to +3 ma allowable power dissipation pd max ta = -40 to +85 c 400 mw operating temperature topr -40 to +85 c storage temperature tstg -40 to +125 c allowable operating range at ta = -40 to +85 c, v dd = 3.5 to 5.5v ratings parameter symbol pins min typ mx uit v dd 1 cpu and pll operation 4.5 5.0 5.5 v dd 2 cpu operation 3.5 5.5 supply voltage v dd 3 memory retention 1.1 5.5 v v ih 1 pb, pc, ph, pi, pl, pm, pn, pp, po, pq, pr, ps, pt-port, hctr, lctr, ineo, subpd (with the i/o ports set to input mode) 0.7v dd v dd v v ih 2 pd, pe, pf, pg, pk-port, lctr (in period measurement mode), hold , reset 0.8v dd v dd v v ih 3 sns 2.5 v dd v input high-level voltage v ih 4 pa-port 0.6v dd v dd v v il 1 pb, pc, ph, pi, pl, pm, pn, pp, po, pq, pr, ps, pt-port, hctr, lctr, ineo, subpd (with the i/o ports set to input mode) 0 0.3v dd v v il 2 pa, pd, pe, pf, pg, pk-port, lctr (in period measurement mode), reset 0 0.2v dd v v il 3 sns 0 1.1v input low-level voltage v il 4 hold 0 0.4v dd v f in 1 xin 4.0 4.5 8.0 mhz f in 2 fmin : v in 2, v dd 1 10 150 mhz f in 3 fmin : v in 3, v dd 1 10 130 mhz f in 4 amin(h) : v in 3, v dd 1 2.0 40 mhz f in 5 amin(l) : v in 3, v dd 1 0.5 10 mhz f in 6 hctr : v in 3, v dd 1 0.4 12 mhz f in 7 lctr : v in 3, v dd 1 100 500 khz input frequency f in 8 lctr (in period measurement) : v ih 2, v il 2, v dd 1 1 20 10 3 hz v in 1 xin 0.5 1.5 vrms v in 2 fmin 0.07 1.5 vrms input amplitude v in 3 fmin, amin, hctr, lctr 0.04 1.5 vrms input voltage range v in 6 adi0 to adi7 0 v dd v
LC72F3781 no.0459-4/17 electrical characteristics in the allowable operating ranges ratings parameter symbol pins min typ max unit i ih 1 xin : v i = v dd = 5.0v 2.0 5.0 15 a i ih 2 fmin, amin, hctr, lctr : v i = v dd = 5.0v 4.0 10 30 a input high-level current i ih 3 pa, pb, pc, pd, pe, pf, pg, ph, pi, pk, pl, pm, pn, po, pp, pq, pr, ps, pt-port, sns , hold , reset , hctr, lctr, ineo, subpd : v i = v dd = 5.0v (with the ports pb, pc, pd, pe, pf, pg, pk, pl, pm, pn, pp, po, pq, pr, ps, and pt-port set to input mode) 3 a i il 1 xin : v i = v dd = v ss 2.0 5.0 15 a i il 2 fmin, amin, hctr, lctr : v i = v dd = v ss 4.0 10 30 a input low-level current i il 3 pa, pb, pc, pd, pe, pf, pg, ph, pi, pk, pl, pm, pn, po, pp, pq, pr, ps, pt-port, sns , hold , reset , hctr, lctr, ineo, subpd : v i = v ss (with the ports pb, pc, pd, pe, pf, pg, pk, pl, pm, pn, pp, po, pq, pr, ps, and pt-port set to input mode) 3 a hysteresis vh pd, pe, pf, pg, pk-port, reset , lctr (in period measurement) 0.1v dd 0.2v dd v v oh 1 pb, pd, pe, pf, pg, pk, pl , pm, pn, po, pp, pq, pr, ps, pt-port : i o = -1ma v dd -1.0 v v oh 2 eo1, eo2, subpd : i o = -500 a v dd -1.0 v output high-level voltage v oh 3 xout : i o = -200 a v dd -1.0 v v ol 1 pb, pd, pe, pf, pg, pk, pl , pm, pn, po, pp pq, pr, ps, pt-port : i o = -1ma 1.0 v v ol 2 eo1, eo2, subpd : i o = -500 a 1.0 v v ol 3 xout : i o = -200 a 1.5 v output low-level voltage v ol 4 pc, pj-port : i o = -5ma 2.0 v i off 1 pb, pd, pe, pf, pg, pk, pl , pm, pn, po, pp, pq, pr, ps, pt-port -3 +3 a i off 2 eo1, eo2, subpd -100 +100 na output off leakage current i off 3 pc, pj-port -5 +5 a a/d conversion error adi0 to adi7 -1.5 +1.5 lsb rejected pulse width prej1 sns 50 s power down detection voltage vdet 2.7 3.0 3.3 v i dd 1 v dd 1 : f in 2 = 130mhz ta = 25 c 5 10 ma i dd 2 v dd 1 : f in 2 = 130mhz ta = 25 c 5.5 11 ma i dd 3 v dd 2 : halt mode ta = 25 c, x?tal : 4.5 mhz *1 (fig. 1) 0.45 ma i dd 4 v dd 2 : halt mode ta = 25 c, x?tal : 7.2mhz 0.55 ma i dd 5 backup mode (osc stopped) v dd = 5.5v, ta = 25 c *2 (fig. 2) 5 a power supply current i dd 6 backup mode (osc stopped) v dd = 2.5v, ta = 25 c *2 (fig. 2) 1 a * 1 : twenty instruction steps are executed every millisecond. the pll, universal counter, and other functions are stopped.
LC72F3781 no.0459-5/17 test circuits figure 1. i dd 2 in halt mode figure 2. i dd 3 and i dd 4 in backup mode package dimensions unit:mm (typ) 3151a sanyo : qip100e(14x20) 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0.1 0.3 0.65 (0.58) 130 80 51 31 50 100 81 ilc05525 a 20pf 4.5mhz 20pf xout v dd v ss fmin amin hctr lctr test 1, 2 res hold pa, ph, pi ports pb through pg, and pj through pt are all left open. however, ports pb through pg, pk through pt, subpd are left open in output mode. xin sns ports pa through pt are all left open. ilc05526 a 20pf 4.5mhz 20pf xout v dd v ss fmin amin hctr lctr test 1, 2 res hold xin sns
LC72F3781 no.0459-6/17 pin assignment ilc05527 topview xout test1 eo1 eo2 v ss pll v dd pll ineo subpd(in) hold hctr(in) lctr(in) reset ph0/adi0 ph1/adi1 ph2/adi2 ph3/adi3 v ss adc fmin amin xin test2 vreg v ss cpu si0/pg3 so0/pg2 sck0/pg1 pg0 si1/pf3 so1/pf2 sck1/pf1 pf0 si2/pe3 so2/pe2 sck2/pe1 pe0 pd3 pd2 pd1/int5 pd0/int4 pc3 pc2 pc1 pc0 pb3 pb2 pb1 pb0 pa3 pa2 pi0/adi4 pi1/adi5 pi2/adi6 pi3/adi7 pj0 pj1 pj2 pj3 pk0/int0 pk1/int1 pk2/int2 pk3/int3 pl0 pl1 pl2 pl3 pm0 pm1 pm2 pm3 pn0/beep pn1 pn2 pn3 po0 po1 po2 po3 pp0 pp1 sns pa1 pa0 pt1 pt0 ps3 ps0 v ss port v dd port pr0 pr3 pr2 pq3 pq2 pq1 pq0 pp3 pp2 ps2 ps1 pr1 100 LC72F3781 (qip100e) 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o i/o i/o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 i/o i/o i/o i i/o i/o i/o i/o i/o i/o o i i i/o i/o i/o i/o i/o-port high-voltage output port (open drain) middle-voltage i/o-port (output : open drain) i/o-port i/o-port i/o-port (schmitt) (schmitt) a/d-c input-port input-port
LC72F3781 no.0459-7/17 block diagram ilc05528 hctr amin fmin xin xout lctr sns v dd v ss hold test1 test2 pa0 pa1 pa2 pa3 pb0 pb1 pb2 pb3 pc0 pc1 pc2 pc3 eo1 eo2 subpd ineo pj3 pj2 pj1 pj0 divider snsf/f sns 1/2 v-det 1/16, 1/17 system clock generator universal counter (20bits) timer prog 2 fix 2 ram 16k 4bit dtr/adr bus drive. address decoder rom 64k 16bit program counter pf mpx skip address decoder stack 32 27bits (pc, bank, cf, pf) judge a/d-c (8bits) latch a latch b bus interrupt control status write register status read register alu instruction decoder pll data latch reference divider programmble divider selector data latch bus drive. bus control bank pe0 sck2/pe1 so2/pe2 si2/pe3 pf0 sck1/pf1 so1/pf2 si1/pf3 sio 3 mpx(8ch) data latch bus drive. phase detector unlock f/f sub c.p. reset int4/pd0 int5/pd1 pd2 pd3 data latch bus drive. data latch bus drive. data latch bus drive. data latch bus drive. pg0 sck0/pg1 so0/pg2 si0/pg3 data latch bus drive. adi0/ph0 adi1/ph1 adi2/ph2 adi3/ph3 bus drive. bus drive. adi4/pi0 adi5/pi1 adi6/pi2 adi7/pi3 interrupt data latch bus drive. data latch bus drive. data latch bus drive. data latch bus drive. data latch bus drive. data latch bus drive. data latch bus drive. pk3/int3 pk2/int2 pk1/int1 pk0/int0 pl3 pl2 pl1 pl0 pm3 pn0/beep pn1 pn2 pn3 po0 po1 po2 po3 pp0 pp1 pp2 pp3 pq0 pq1 pq2 pq3 pr0 pr1 pr2 pr3 ps0 ps1 ps2 ps3 pt0 pt1 pm2 pm1 pm0 data latch data latch bus drive. data latch bus drive. data latch bus drive. beep gen (prg/fix) interrupt
LC72F3781 no.0459-8/17 pin description pin name pin no. i/o pin explanation equivalent circuit pa0 pa1 pa2 pa3 32 31 30 29 i dedicated input ports. these ports are designed with a low threshold voltage. input is disabled in backup mode. pb0 pb1 pb2 pb3 28 27 26 25 i/o general-purpose i/o ports. the mode (input or output) is se t using the ios2 instruction. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. pc0 pc1 pc2 pc3 24 23 22 21 i/o general-purpose i/o ports (middle-voltage input and output). the mode (input or output) is se t using the ios2 instruction. external pull-up resistors are required since the output circuits are open drain. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. pd0/int4 pd1/int5 pd2 pd3 20 19 18 17 i/o general-purpose i/o and external interrupt shared function ports. the input formats are schmitt inputs. the external interrupt function is enabled when the external interrupt enable flag is set. ? when used as general-purpose i/o ports : the mode (input or output) is set in 1-bit units using the ios2 instruction. ? when used as external interrupt pins : the external interrupt functions are enabled by setting the corresponding external interrupt enable flag (int4en or int5en). in this case, the pins must be set to input mode in advance. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. continued on next page. ilc05529 back up ilc05530 back up ilc05531 back up ilc05532 back up
LC72F3781 no.0459-9/17 continued from preceding page. pin name pin no. i/o pin explanation equivalent circuit pe0 pe1/sck2 pe2/so2 pe3/si2 pf0 pf1/sck1 pf2/so1 pf3/si1 pg0 pg1/sck0 pg2/so0 pg3/si0 16 15 14 13 12 11 10 9 8 7 6 5 i/o general-purpose i/o ports with shar ed functions as serial i/o ports. the input formats are schmitt i nputs. the pe1/sck2 and pe2/so2 pins can be switched to function as open drain outputs. the ios1 instruction is used to switch between the general-purpose i/o port and serial i/o port functions. ? when used as general-purpose i/o ports : the pins are set to the general-purpose i/o port function using the ios1 instruction. the mode (input or output) is set in 1-bit units using the ios1 instruction ? when used serial i/o ports : the pins are set to the serial i/o port function using the ios1 instruction. [pin states when set to the serial i/o port function] pe0, pf0, pg0 ? general-purpose i/o pe1, pf1, pg1 ? sck input or output pe2, pf2, pg2 ? so output pe3, pf3, pg3 ? si input the pe1/sck2 and pe2/so2 pins ca n be switched to function as open drain outputs with the ios2 instruction. when using this circuit type, the external pull-up resistors must be connected to the same power supply as that used by the ic. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. xin xout 1 100 i o connections for 4.5mhz/7.2mhz crystal oscillator element eo1 eo2 98 97 o main charge pump outputs. these pins output a high level when the frequency of the local oscillator divided by n is higher than that of the reference frequency, and they output a low level when that frequency is lower. they go to the high-impedance st ate when the frequencies match. these pins go to the high-impedanc e state in backup mode, after a power on reset, and in the pll stopped state. v dd port v dd pll v ss cpu v ss port v ss adc v ss pll 39 93 4 40 81 96 - power supply connections. the v dd port and v ss port pins are mainly supply power for the peripheral i/o blocks. the v dd pll and v ss pll pins are mainly for the pll circuits and the regulator. the v ss cpu pin is mainly used by the cpu block. the v ss adc pin is mainly used by the adc block. since all the v dd and v ss pins are independent, all must be connected to the same power supply. vreg 3 o internal low voltage output. connect a bypass capacitor to this pin. continued on next page. ilc05533 pe1/pe2-port open drain control back up ilc05532 back up ilc05534 xin x out ilc05535
LC72F3781 no.0459-10/17 continued from preceding page. pin name pin no. i/o pin explanation equivalent circuit fmin 95 i fm vco (local oscillator) input. this pin is selected with cw1 in the pll instruction. the signal input to this pin must be capacitor coupled. input is disabled in backup mode, after a power on reset, and in the pll stopped state. am vco (local oscillator) input. this pin is selected and the band set with cw1 (b1, b0) in the pll instruction. b1 b0 band 1 0 2 to 40mhz (sw, am upconversion) 1 1 0.5 to 10mhz (mw, lw) amin 94 i the signal input to this pin must be capacitor coupled. input is disabled in backup mode, after a power on reset, and in the pll stopped state. sub-charge pump output and general-purpose input shared function port. the ios2 instruction is used for switching between the sub-charge pump output and general-purpose input functions. ? when used as the sub-charge pump output : the sub-charge pump output function is set up with the ios2 instruction. a high-speed locking circuit can be formed by using this pin in conjunction with the main charge pump. the sub-charge pump is contro lled using the dzc instruction. b3 b2 operation 0 0 high impedance 0 1 only operates when the pll is unlocked (450khz) 1 0 only operates when the pll is unlocked (900khz) 1 1 normal operation subpd 92 i/o ? when used as a general-purpose input : the general-purpose input function is set up with the ios2 instruction. data is read from the port using the inr instruction. this pin goes to the high-impedance state in backup mode, after a power on reset, and in the pll stopped state. ineo 91 i dedicated input port. data is read from the port using the inr instruction input is disabled in backup mode. continued on next page. ilc05536 pll stop instruction ilc05537 back up ilc05538 back up
LC72F3781 no.0459-11/17 continued from preceding page. pin name pin no. i/o pin explanation equivalent circuit hctr 90 i universal counter and general-pur pose input shared function input port. the ios1 instruction is used for switching between the universal counter and general- purpose input functions. ? when used for frequency measurement : the universal counter function is se t up with the ios1 instruction. the counter is controlled us ing ucs and ucc instructions. since this pin functions as an ac amplifier in this mode, the input signal must be input with capacitor coupling. ? when used as a general-purpose input pin : the general-purpose input function is set up with the ios1 instruction. data is read from the port using the inr (b0) instruction. input is disabled in backup mode. (the input pin will be pulled down.) the universal counter function is selected after a power on reset. lctr 89 i universal counter (frequency or period measurement) and general- purpose input shared function input port. the ios1 instruction is used for switching between the universal counter and general-purpose input functions. ? when used for frequency measurement : the universal counter function is se t up with the ios1 instruction. set up lctr frequency measurement mode with the ucs instruction, and control operation with the ucc instruction. since this pin functions as an ac amplifier in this mode, the input signal must be input with capacitor coupling. ? when used for period measurement : the universal counter function is se t up with the ios1 instruction. set up lctr frequency measurement mode with the ucs instruction, and control operation with the ucc instruction. since the bias feedback resistor is disconnected in this mode, the input signal must be input with dc coupling. ? when used as a general-purpose input pin : the general-purpose input port func tion is set up with the ios1 instruction. data is read from the port using the inr (b1) instruction. input is disabled in backup mode. (the input pin will be pulled down.) the universal counter function (hctr frequency measurement mode) is selected after a power on reset. sns 88 i voltage sense and general-purpose input shared function port. this input circuit is designed wi th a low input threshold voltage. ? when used as a voltage sense input : the pin is used to test for power failures on the return from backup mode. application can test this condition using the internal sns flip-flop. the sns flip-flop can be test ed with the tst instruction. (this usage requires external components, capacitors and resistors. for the sample application circuit, see the user?s manual.) ? when used as a general-purpose input port : when used as a general-purpose input port the pin state can be tested with the tst instruction. unlike the other input ports, input to this pin is not disabled in backup mode and after a power on reset. as a result, through currents must be taken into account when designing applications that use this pin as a general-purpose input. hold 87 i power supply monitor (with interrupt function) this is designed with a high input threshold voltage. this pin is normally connected to the acc line and used for power off detection. when a power off state is detected, the holdon flag and the hold interrupt request flag will be set. to enter backup mode, execute a ckstp instruction when the hold pin is low. set this pin high to clear backup mode. continued on next page. ilc05536 pll stop instruction ilc05539 ilc05539
LC72F3781 no.0459-12/17 continued from preceding page. pin name pin no. i/o pin explanation equivalent circuit reset 86 i system reset pin. when the cpu is operating or in ha lt mode, the system is reset when this pin is held low for at least one machine cycle. execution starts with the pc pointing to location 0. at this time the sns flip-flop is set. a low level must be applied for at least 50ms when power is first applied. ph0/adi0 ph1/adi1 ph2/adi2 ph3/adi3 pi0/adi4 pi1/adi5 pi2/adi6 pi3/adi7 85 84 83 82 81 80 79 78 i general-purpose input and a/d converte r input shared function ports. the ios1 instruction is used to switch between the general-purpose input and the a/d converter input functions. ? when used as general-purpose input ports : the general-purpose input port func tion is set up with the ios1 instruction. (in bit units) ? when used as a/d converter input pins : the a/d converter input port function is set up with the ios1 instruction. (in bit units) the pin whose voltage is to be conver ted is specified with the ios1 instruction, and the conversion is started with ucc instruction. note : since input is disabled for ports specified for the adi function, executing an input instruction for such a port will always return a low level. input is disabled in backup mode. these ports are set up as general-purpose input ports after a power on reset. pj0 pj1 pj2 pj3 76 75 74 73 o general-purpose output ports (high-voltage output) since these are open-drain output circ uits, external pull-up resistors are required. the internal transistors are turned off (resulting in a high-level output) in backup mode and after a power on reset. pk0/int0 pk1/int1 pk2/int2 pk3/int3 72 71 70 69 i/o general-purpose i/o and external interrupt shared function ports. the input formats are schmitt inputs. the external interrupt function is enabled when the external interrupt enable flag is set. ? when used as general-purpose i/o ports : the mode (input or output) is set in 1-bit units using the ios1 instruction. ? when used as external interrupt pins : the external interrupt functions are enabled by setting the corresponding external interrupt enable flag (int0en through int3en). here, the pins must be set to input mode in advance. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. continued on next page. ilc05541 back up to the a/d converter input ilc05540 ilc05542 back up ilc05543 back up
LC72F3781 no.0459-13/17 continued from preceding page. pin name pin no. i/o pin explanation equivalent circuit pl0 to 3 pm0 to 3 68 to 61 i/o general-purpose i/o ports the mode is switched between input and output with the ios instruction. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. pn0/beep pn1 pn2 pn3 60 59 58 57 i/o general-purpose i/o port and beep tone output shared function ports. the ios2 instruction is used to switch between the general-purpose i/o port and the beep tone output functions. ? when used as general-purpose i/o ports : the general-purpose i/o port function is set up with the ios2 instruction. (pins pn1 through pn3 are dedicated general-purpose output pins.) ? when used as the beep tone output pin : the beep tone output function is set up with the ios2 instruction. the frequency is set up with the beep instruction. when this pin is used as the beep tone output pin, executing an output instruction for this pin only sets the internal latch and has no influence on the output. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. po0 to 3 pp0 to 3 56 to 49 i/o general-purpose i/o ports the mode is switched between input and output with the ios instruction. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. pq0 to 3 pr0 to 3 ps0 to 3 pt0 to 3 48 to 41 38 to 33 i/o general-purpose i/o ports. the mode is switched between input and output with the ios instruction, and data is input with the inr instruction and output with the outr instruction. the spb, rpb, tpt, and tpf instruction cannot be used with these ports. input is disabled and the pins go to the high-impedance state in backup mode. these ports are set up as general-purpose input ports after a power on reset. test1 test2 99 2 lsi test pins. these pins must be connected to gnd. ilc05544 back up ilc05544 back up
LC72F3781 no.0459-14/17 concerning differences from the lc7237 81n, 2n, 3n, 4 and 5 mask versions item mask version (lc723781n, 2n, 3n, 4 and 5) otp version (LC72F3781) design rule 0.35 process 0.45 process rom masked rom structur e flash rom structure write mode not available available design considerations 1) although the electrical specifications are the same for the mask and otp versio ns, differences may arise in the actual values for the threshold level of the input ports, output cu rrent of the output ports, input sensitivity, etc. variations may also be found from lot to lot. it must therefore be kept in mind that if finished products are designed using the actual values of the samples, these variations may prevent the finished products from operating. 2) the undesirable radiation level is not listed among the sp ecifications. since differences may arise between the mask and otp versions, this must be kept in mind when designing the finished products. concerning rom writing 1) the job of writing data onto the rom in-house at sanyo semiconductor is not currently supported. 2) the LC72F3781 circuit board must be requested as the data writing board. 3) the af-9706 or af-9708 made by ando or the 1890a or 1881xp made by minato is recommended as the rom writer.
LC72F3781 no.0459-15/17 example of writing data onto the on- chip flash rom of the LC72F3781 (using the af-9706 or af-9708) i. writing the data using the af-9706 or af-9708 (made by ando) prom programmer 1. romtype settings romtype select [maker] set select [sst] set select [29ee010] set 2. start/stop address settings function 1 : address setting mode * the address that corresponds to the ro m capacity provided in the table below must be set as the stop address. type no. rom capacity stop address lc723781n 40kb 9fff lc723782n 48kb bfff lc723783n 64kb ffff lc723784 96kb 17fff lc723785 128kb 1ffff 3. executing data erasure device b set : for data erasure execution. 4. executing data writing device f set : for program and verify execution. ii. writing board the writing board is shown in the figure below. the position of pin 1 must be checked before connecting to the eprom programmer. note: the writing adapter has been changed. to be used for the general-purpose eprom programmer: model LC72F3781-adp-n eprom programmer pin 1 of eprom programmer pin 1 of LC72F3781
LC72F3781 no.0459-16/17 example of writing data onto the on- chip flash rom of the LC72F3781 (using the 1890a) i. data writing method 1. romtype settings device d734 entry entry : device code [29ee010] 2. start/stop address settings edit pae : address setting mode <1> since begin add is displayed, 00000 entry <2> since end add is displayed, 1ffff entry (128kbytes = 1ffff) <3> since buf add is displayed, 00000 entry * the address that corresponds to the ro m capacity provided in the table below must be set as the stop address. type no. rom capacity stop address lc723781n 40kb 9fff lc723782n 48kb bfff lc723783n 64kb ffff lc723784 96kb 17fff lc723785 128kb 1ffff 3. executing data writing prog pae : for program and verify execution. ii. writing board the writing board is shown in the figure below. the position of pin 1 must be checked before connecting to the eprom programmer. note: the writing adapter has been changed. to be used for the general-purpose eprom programmer: model LC72F3781-adp-n eprom programmer pin 1 of eprom programmer pin 1 of LC72F3781
LC72F3781 no.0459-17/17 ps this catalog provides information as of september, 2006. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qu ality high-reliability pr oducts, however, any and all semiconductor products fail or malfunction with some proba bility. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damag e to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products descr ibed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co .,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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