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one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 a functional block diagrams rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. features 44 v supply maximum ratings v ss to v dd analog signal range low on resistance (80 w max) low power fast switching t on < 160 ns t off < 150 ns break before make switching action plug-in upgrade for dg506a/adg506a, dg507a/adg507a, dg526/adg526a ADG406/adg407 are plug-in replacements for dg406/dg407 applications audio and video routing automatic test equipment data acquisition systems battery powered systems sample hold systems communication systems avionics lc 2 mos 8-/16-channel high performance analog multiplexers ADG406/adg407/adg426 adg407 en a0 a1 a2 s1a s8a da s8b db s1b 1 of 8 decoder en a0 a1 a2 a3 rs adg426 s1 s16 d wr decoder/ latches ADG406 en a0 a1 a2 a3 s1 s16 d 1 of 16 decoder general description the ADG406, adg407 and adg426 are monolithic cmos analog multiplexers. the ADG406 and adg426 switch one of sixteen inputs to a common output as determined by the 4-bit binary address lines a0, a1, a2 and a3. the adg426 has on- chip address and control latches that facilitate microprocessor interfacing. the adg407 switches one of eight differential inputs to a common differential output as determined by the 3- bit binary address lines a0, a1 and a2. an en input on all devices is used to enable or disable the device. when disabled, all channels are switched off. the ADG406/adg407/adg426 are designed on an enhanced lc 2 mos process that provides low power dissipation yet gives high switching speed and low on resistance. these features make the parts suitable for high speed data acquisition systems and audio signal switching. low power dissipation makes the parts suitable for battery powered systems. each channel conducts equally well in both directions when on and has an input signal range which extends to the supplies. in the off condition, signal levels up to the supplies are blocked. all channels exhibit break before make switching action preventing momentary shorting when switching channels. inherent in the design is low charge injection for minimum transients when switching the digital inputs. product highlights 1. extended signal range the ADG406/adg407/adg426 are fabricated on an enhanced lc 2 mos process giving an increased signal range which extends to the supply rails 2. low power dissipation 3. low r on 4. single/dual supply operation 5. single supply operation for applications where the analog signal is unipolar, the ADG406/adg407/adg426 can be operated from a single rail power supply. the parts are fully specified with a single +12 v power supply and will remain functional with single supplies as low as +5 v.
b version t version C40 c to C55 c to parameter +25 c +85 c +25 c +125 c units test conditions/comments analog switch analog signal range v ss to v dd v ss to v dd v r on 50 50 w typ v d = 10 v, i s = C1 ma 80 125 80 125 w max v dd = +13.5 v, v ss = C13.5 v r on match 4 4 w typ v d = 0 v, i s = C1 ma leakage currents v dd = +16.5 v, v ss = C16.5 v source off leakage i s (off) 0.5 20 0.5 50 na max v d = 10 v, v s = 7 10 v, test circuit 2 drain off leakage i d (off) v d = 10 v, v s = 7 10 v; ADG406, adg426 1 20 1 200 na max test circuit 3 adg407 1 20 1 100 na max channel on leakage i d , i s (on) v s = v d = 10 v; ADG406, adg426 1 20 1 200 na max test circuit 4 adg407 1 20 1 100 na max digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 1 1 m a max v in = 0 or v dd c in , digital input capacitance 8 8 pf typ f = 1 mhz dynamic characteristics 2 t transition 120 120 ns typ r l = 300 w , c l = 35 pf; 150 250 150 250 ns max v 1 = 10 v, v 2 = 7 10 v; test circuit 5 break before make delay, t open 10 10 10 10 ns min r l = 300 w , c l = 35 pf; v s = +5 v, test circuit 6 t on (en, wr ) 120 175 120 175 ns typ r l = 300 w , c l = 35 pf; 160 225 160 225 ns max v s = +5 v, test circuit 7 t off (en, rs ) 110 130 110 130 ns typ r l = 300 w , c l = 35 pf; 150 180 150 180 ns max v s = +5 v, test circuit 7 adg426 only t w , write pulse width 100 100 ns min t s , address, enable setup time 100 100 ns min t h , address, enable hold time 10 10 ns min t rs , reset pulse width 100 100 ns min v s = +5 v charge injection 8 8 pc typ v s = 0 v, r s = 0 w , c l = 1 nf; test circuit 10 off isolation C75 C75 db typ r l = 1 k w , f = 100 khz; v en = 0 v, test circuit 11 channel-to-channel crosstalk 85 85 db typ r l = 1 k w , f = 100 khz, test circuit 12 c s (off) 5 5 pf typ f = 1 mhz c d (off) f = 1 mhz ADG406, adg426 50 50 pf typ adg407 25 25 pf typ c d , c s (on) f = 1 mhz ADG406, adg426 60 60 pf typ adg407 40 40 pf typ power requirements v dd = +16.5 v, v ss = C16.5 v i dd 11 m a typ v in = 0 v, v en = 0 v 55 m a max i ss 11 m a typ 55 m a max i dd 100 100 m a typ v in = 0 v, v en = 2.4 v 200 500 200 500 m a max i ss 11 m a typ 55 m a max n otes 1 temperature ranges are as follows: b versions: C40 c to +85 c; t versions: C55 c to +125 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. ADG406/adg407/adg426Cspecifications 1 dual supply C2C rev. 0 (v dd = +15 v 10%, v ss = C15 v 10%, gnd = 0 v, unless otherwise noted)
rev. 0 C3C ADG406/adg407/adg426 single supply (v dd = +12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted) b version t version C40 c to C55 c to parameter +25 c +85 c +25 c +125 c units test conditions/comments analog switch analog signal range 0 to v dd 0 to v dd v r on 90 90 w typ v d = +3 v, +8.5 v, i s = C1 ma; 125 200 125 200 w max v dd = +10.8 v leakage currents v dd = +13.2 v source off leakage i s (off) 0.5 20 0.5 50 na max v d = 8 v/0.1 v, v s = 0.1 v/8 v; test circuit 2 drain off leakage i d (off) v d = 8 v/0.1 v, v s = 0.1 v/8 v; ADG406, adg426 1 20 1 200 na max test circuit 3 adg407 1 20 1 100 na max channel on leakage i d , i s (on) v s = v d = 8 v/0.1 v, test circuit 4 ADG406, adg426 1 20 1 200 na max adg407 1 20 1 100 na max digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 1 1 m a max v in = 0 or v dd c in , digital input capacitance 8 8 pf typ f = 1 mhz dynamic characteristics 2 t transition 180 180 ns typ r l = 300 w , c l = 35 pf; 220 350 220 350 ns max v 1 = 8 v/0 v, v 2 = 0 v/8 v; test circuit 5 break before make delay, t open 10 10 ns typ r l = 300 w , c l = 35 pf; v s = +5 v, test circuit 6 t on (en, wr ) 180 180 ns typ r l = 300 w , c l = 35 pf; 240 350 240 350 ns max v s = +5 v, test circuit 7 t off (en, rs ) 135 135 ns typ r l = 300 w , c l = 35 pf; 180 220 180 220 ns max v s = +5 v, test circuit 7 adg426 only t w , write pulse width 100 100 ns min t s , address, enable setup time 100 100 ns min t h , address, enable hold time 10 10 ns min t rs , reset pulse width 100 100 ns min v s = +5 v charge injection 5 5 pc typ v s = 6 v, r s = 0 w , c l = 1 nf; test circuit 10 off isolation C75 C75 db typ r l = 1 k w , f = 100 khz; test circuit 11 channel-to-channel crosstalk 85 85 db typ r l = 1 k w , f = 100 khz; test circuit 12 c s (off) 8 8 pf typ f = 1 mhz c d (off) f = 1 mhz ADG406, adg426 80 80 pf typ adg407 40 40 pf typ c d , c s (on) f = 1 mhz ADG406, adg426 100 100 pf typ adg407 50 50 pf typ power requirements v dd = +13.2 v i dd 11 m a typ v in = 0 v, v en = 0 v 55 m a max i dd 100 100 m a typ v in = 0 v, v en = 2.4 v 200 500 200 500 m a max notes 1 temperature ranges are as follows: b versions: C40 c to +85 c; t versions: C55 c to +125 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice.
C4C ADG406/adg407/adg426 rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although these devices feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide model temperature range package option* ADG406bn C40 c to +85 c n-28 ADG406bp C40 c to +85 c p-28a adg407bn C40 c to +85 c n-28 adg407bp C40 c to +85 c p-28a adg426bn C40 c to +85 c n-28 adg426brs C40 c to +85 c rs-28 *n = plastic dip, p = plastic leaded chip carrier (plcc), rs = shrink small outline package (ssop). absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C25 v analog, digital inputs 2 . . . . . . . . . . . . . v ss C 2 v to v dd + 2 v or 20 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 20 ma peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . C40 c to +85 c extended (t version) . . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic package q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . +260 c plcc package q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . . 80 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c ssop package q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 122 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at a, s, d, wr or rs will be clamped by internal diodes. current should be limited to the maximum ratings given.
C5C rev. 0 ADG406/adg407/adg426 table iii. truth table (adg426) a3 a2 a1 a0 en wr rs on switch xxxxx 1 retains previous switch condition xxxxxx0 none (address and enable latches cleared) xxxx 0 0 1 none 00001011 00011012 00101013 00111014 01001015 01011016 01101017 01111018 10001019 100110110 101010111 101110112 110010113 110110114 111010115 111110116 v dd nc d v ss s15 s14 s13 s6 s5 s4 nc s16 s8 s7 s12 s3 s11 s2 s10 s1 s9 en gnd a0 nc a1 a3 a2 13 18 1 2 28 27 5 6 7 24 23 22 3 4 26 25 821 920 10 19 11 11 12 17 16 14 15 top view (not to scale) ADG406 plcc pin configurations dip v dd db da v ss s7b s6b s5b s6a s5a s4a nc s8b s8a s7a s3a s3b s2a s2b s1a s1b en gnd a0 nc a1 nc a2 13 18 1 2 28 27 5 6 7 24 23 22 3 4 26 25 821 920 10 19 11 11 12 17 16 14 15 top view (not to scale) adg407 s4b pin configuration dip/ssop nc = no connect v dd nc d v ss s15 s14 s13 s6 s5 s4 s16 s8 s7 s12 s3 s11 s2 s10 s1 s9 en gnd a0 a1 a3 a2 13 18 1 2 28 27 5 6 7 24 23 22 3 4 26 25 821 920 10 19 11 11 12 17 16 14 15 top view (not to scale) adg426 rs wr nc = no connect s7 s6 s3 s2 s1 s5 s4 s15 s14 s11 s10 s9 s13 s12 s16 nc d v ss s8 nc gnd nc a1 a0 en a3 a2 v dd 26 27 28 42 3 15 18 17 16 12 14 13 25 24 21 20 19 23 22 top view (not to scale) 1 5 6 9 10 11 7 8 ADG406 table i. truth table (ADG406) a3 a2 a1 a0 en on switch xxxx0 none 000011 000112 001013 001114 010015 010116 011017 011118 100019 1001110 1010111 1011112 1100113 1101114 1110115 1111116 nc = no connect s7a s6a s3a s2a s1a s5a s4a s7b s6b s3b s2b s1b s5b s4b s8b nc da v ss s8a db gnd nc a1 a0 en nc a2 v dd 26 27 28 42 3 15 18 17 16 12 14 13 25 24 21 20 19 23 22 top view (not to scale) 1 5 6 9 10 11 7 8 adg407 table ii. truth table (adg407) a2 a1 a0 en on switch pair xxx0 none 00011 00112 01013 01114 10015 10116 11017 11118
C6C ADG406/adg407/adg426 rev. 0 timing diagrams (adg426) figure 1. figure 1 shows the timing sequence for latching the switch address and enable inputs. the latches are level sensitive; therefore, while wr is held low, the latches are transparent and the switches respond to the address and enable inputs. this input data is latched on the rising edge of wr . figure 2. figure 2 shows the reset pulse width, t rs , and the reset turn off time, t off ( rs ). note: all digital input signals rise and fall times are measured from 10% to 90% of 3 v. t r = t f = 20 ns. terminology v dd most positive power supply potential. v ss most negative power supply potential in dual supplies. in single supply applications, it may be connected to ground. gnd ground (0 v) reference. r on ohmic resistance between d and s. r on match difference between the r on of any two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminals d, s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t open off time measured between 80% points of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off channel. charge a measure of the glitch impulse injection transferred from the digital input to the analog output during switching. i dd positive supply current. i ss negative supply current. 50% t w 50% t s 2v 0.8v t h 3v wr 0v 3v a0, a1, a2, (a3) en 0v 50% t rs 50% 0.8v 0 3v 0v v 0 0v rs t off ( rs ) switch output
C7C rev. 0 ADG406/adg407/adg426 typical performance graphs figure 6. r on as a function of v d (v s ): single supplies figure 7. r on as a function of v d (v s ) for different temperatures figure 8. leakage currents as a function of v d (v s ) v d (v s ) ?volts r on ? w 400 0 15 100 50 2.5 0 200 150 250 300 350 12.5 10 7.5 5 v dd = +15v v ss = 0v v dd = +10v v ss = 0v v dd = +12v v ss = 0v t a = +25 c v dd = +5v v ss = 0v v d (v s ) ?volts r on ? w 150 0 15 90 30 ?0 60 ?5 120 10 5 0 ? t a = +25 c v dd = +5v v ss = ?v v dd = +10v v ss = ?0v v dd = +12v v ss = ?2v v dd = +15v v ss = ?5v v d (v s ) ?volts r on ? w 100 0 15 60 20 ?0 40 ?5 80 10 5 0 ? v dd = +15v v ss = ?5v +125 c +85 c +25 c figure 3. r on as a function of v d (v s ): dual supplies figure 4. r on as a function of v d (v s ) for different temperatures figure 5. leakage currents as a function of v d (v s ) v d (v s ) ?volts 15 ?0 ?5 10 5 0 ? v dd = +15v v ss = ?5v t a = +25 c 0.10 ?.02 0.06 0.02 0.04 0.08 0.00 leakage current ?na i d (on) i d (off) i s (off) v d (v s ) ?volts r on ? w 150 0 12 90 30 2 60 0 120 10 8 6 4 v dd = +12v v ss = 0v +125 c +85 c +25 c v d (v s ) ?volts 0.02 0.00 ?.02 ?.01 0.01 12 2 0 10 8 6 4 leakage current ?na v dd = +12v v ss = 0v t a = +25 c i d (on) i d (off) i s (off)
C8C ADG406/adg407/adg426 rev. 0 v in ?v t ?ns t on 160 60 15 120 80 3 100 1 140 13 11 9 7 5 t transition t off v dd = +15v v ss = ?5v frequency ?hz i dd ?ma 100 0.1 10 2 10 7 10 1 10 3 10 6 10 5 10 4 v dd = +15v v ss = ?5v en = 2.4v en = 0v frequency ?hz i ss ?ma 10 2 10 7 10 3 10 6 10 5 10 4 en = 0v 100 0.0001 0.1 0.001 0.01 10 1 en = 2.4v v dd = +15v v ss = ?5v supply voltage ?volts t ?ns t off 300 0 21 7 100 5 200 19 15 13 11 17 9 v in = +5v t transition t on figure 12. negative supply current vs. switching frequency figure 13. switching time vs. v in (single supply) figure 14. switching time vs. single supply figure 9. positive supply current vs. switching frequency figure 10. switching time vs. v in (bipolar supply) figure 11. switching time vs. bipolar supply v in ?v 220 80 12 140 100 4 120 2 200 160 180 10 8 6 v dd = +12v v ss = 0v t ?ns t transition t on t off 500 0 15 300 100 7 200 5 400 13 11 9 v in = +5v supply voltage ?volts t ?ns t transition t on t off
C9C rev. 0 ADG406/adg407/adg426 10 2 10 3 10 4 10 5 10 6 10 7 40 60 80 100 120 140 frequency ?hz crosstalk ?db v dd = +15v v ss = ?5v 10 2 10 3 10 4 10 5 10 6 10 7 40 60 80 100 120 140 frequency ?hz off isolation ?db v dd = +15v v ss = ?5v test circuit 1. on resistance test circuit 2. i s (off) test circuit 3. i d (off) test circuit 4. i d (on) i ds sd r on = v1/i ds v s v1 test circuits figure 16. crosstalk vs. frequency figure 15. off isolation vs. frequency v s d en +0.8v s1 s2 s16 v ss v dd v d a i d (off) v ss v dd d en +0.8v s1 s2 s16 v s a v d v ss v dd i s (off) v ss v dd d en 2.4v s1 s16 v s v ss v dd v d a i d (on) v ss v dd
C10C ADG406/adg407/adg426 rev. 0 v ss v dd v s v ss v dd a3 a2 adg426* a1 s1 rs s2 thru s16 2.4v a0 *similar connection for ADG406/adg407 gnd en c l 35pf r l 300 w wr d v in 50 w v out enable drive? in 3v 50% t on (en) 50% 90% v o t off (en) 90% 0v 0v output *similar connection for ADG406/adg407 s16 gnd en 2.4v v ss v dd v s v ss v dd a3 a2 adg426* a1 s1 rs s2 thru s15 c l 35pf r l 300 w v in wr 50 w d a0 v out 0v 3v output address drive ?v in 80% 80% t open *similar connection for ADG406/adg407 s16 gnd en 2.4v v ss v dd v 1 v ss v dd a3 a2 adg426* a1 s1 rs s2 thru s15 v 2 c l 35pf r l 300 w v in wr 50 w d a0 v out 3v 50% 50% v out address drive ?v in 90% t transition t transition 90% test circuit 5. switching time of multiplexer, t transition test circuit 6. break-before-make delay, t open test circuit 7. enable delay, t on (en), t off (en)
C11C rev. 0 ADG406/adg407/adg426 test circuit 9. reset turn-off time, t off ( rs ) test circuit 10. charge injection test circuit 8. write turn-on time, t on ( wr ) en 2.4v v ss v dd v s v ss v dd a3 a2 adg426 a1 s1 rs s2 thru s16 c l 35pf r l 300 w wr d v wr v rs a0 gnd v out 0v 3v 50% 0v v 0 output wr 0.2v 0 t on (wr) 3v v out d v out q inj = c l x d v out logic input (v in ) *similar connection for ADG406/adg407 gnd en v ss v dd c l 1nf v ss v dd adg426* rs wr d v in 2.4v a2 a1 v out s v s r s a0 a3 en 2.4v v ss v dd v s v ss v dd a3 a2 adg426 a1 s1 rs s2 thru s16 c l 35pf r l 300 w d v in gnd wr a0 v out 0v 3v 50% 0v v 0 output rs 0.8v 0 t off ( rs )
C12C ADG406/adg407/adg426 rev. 0 c1905C18C4/94 v dd v ss v ss v dd a3 adg426* gnd d a2 a1 v out en s1 s16 r l 1k w a0 v in wr rs 2.4v *similar connection for ADG406/407 test circuit 11. off isolation outline dimensions dimensions shown in inches an (mm). 28-pin plcc (p-28a) 28-pin plastic (n-28) 0.048 (1.21) 0.042 (1.07) 0.456 (11.58) 0.450 (11.43) sq 0.495 (12.57) 0.485 (12.32) sq 0.048 (1.21) 0.042 (1.07) 0.050 (1.27) bsc 26 4 top view 25 19 12 11 pin 1 identifier 5 18 0.020 (0.50) r 0.056 (1.42) 0.042 (1.07) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.025 (0.63) 0.015 (0.38) 0.180 (4.57) 0.165 (4.19) 0.430 (10.92) 0.390 (9.91) 0.110 (2.79) 0.085 (2.16) 0.040 (1.01) 0.025 (0.64) pin 1 0.580 (14.73) 0.485 (12.32) 1 14 15 28 0.015 (0.381) 0.008 (0.204) 0.625 (15.87) 0.600 (15.24) 0.195 (4.95) 0.125 (3.18) 0.250 (6.35) max 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc 0.200 (5.05) 0.125 (3.18) 0.070 (1.77) max 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 1.565 (39.70) 1.380 (35.10) 28-pin ssop (rs-28) printed in u.s.a. 0.407 (10.34) 0.397 (10.08) 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 0.311 (7.9) 0.301 (7.64) 0.0256 (0.65) bsc pin 1 15 14 1 28 0.212 (5.38) 0.205 (5.207) 1. lead no. 1 identified by a dot. 2. leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements v dd v dd adg426* d v out s1 s16 s2 1k w a0 a1 a2 a3 1k w v in 2.4v v ss v ss en gnd wr rs *similar connection for ADG406/407 test circuit 12. crosstalk

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