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| IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 1 pfm mode boost led d river with the exter nal nmos general description the IS31LT3948 is a pfm step - up dc - dc converter designed for driving the white led arrays for large size lcd panel backlighting applications . it can deliver stable constant outpu t c urrent from a few milliamps up to 2 a , programmed via an external resistor. the IS31LT3948 utilizes a control scheme in which the output is automatically adjust ed to the optimum output voltage for the system, maximizing the efficiency. furthermore, the con trol scheme is inherently stable removing the need to provide additional loop compensation . the device features external pwm dimming, which allows the flexible control of the back - lighting luminance. the IS31LT3948 has a wi de input voltage range from 5 v to 100v (note ) . an i n tegrated ovp circuit protects the chip and the system even under no - load conditions . note: the IS31LT3948 has an internal 5v shunt regulator connected to the vcc pin. a dropping resistor must be connected between the vcc pin and vin t o limit current flow. vin voltages above 100v are allowed but care must be taken to ensure that the output voltage remains greater than vin, and that the nmos voltage rating is sufficiently large. features ? w ide input voltage range : 5 v - 100v ? constant cur rent output limited only by external component selection ( n ote ) ? no l oop compensation required ? i nternal over - voltage protection ? i nternal o ver - temperature protection ? operating temperature range - 40 c to 85 c ? sop - 8 package note: the maximum output current is determined by vout/vin ratio as well as the external components. if output current and vout/vin ratio is high, high current components of inductor and nmos are needed. applications ? tv monitor backlighting, ? notebook ? automotive ? street lamp ? led lighting t ypical operating cir cuit vcc toff adj gnd gate cs fb ovp led(+) led(-) vin(5~100v ) r1 r2 r3 r4 r5 c1 c2 c3 rfb l1 d1 m1 figure 1 typical operating circuit copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time w ithout notice. issi assumes no liability arising out of the application or use of any information, products or services descr ibed herein. customers are advised to obtain the latest version of this device specification before relying on any published inform ation and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fa ilure or malfunction of the product can reasonably be expected to cause failure of th e life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfacti on, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances octo ber 201 1
IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 2 pin configurations package top view sop - 8 ovp fb gate cs vcc toff adj gnd 1 2 3 4 5 6 7 8 p in descriptions pin name function 1 vcc p ositive p ower supply input pin . internally clamped at 5v (t ypical ) . 2 toff off time setting pin. an external resistor connect ed to this pin form s a n rc discharge path to generate a constant minim um off time of the n mos 3 adj enable and input peak current control pin. pull ed up to 4.5v internally to set v csth =0.24v wh en adj is floating. if v adj <0.5v, nmos will always shutdown. if 0.5 v adj 2.4v, v cs th = v adj /10. if v adj >2.4v, v cs th =0.24v 4 gnd ground 5 gate driver?s output for the gate of the external nmos 6 cs current sense input for the boost, peak current control loop 7 fb feedback voltage input pin. used to regulate the curren t of led s by keeping vfb=0.3v. 8 ovp o vervoltage protection input pin. , if the voltage of ovp exceed 1 v , gate will always shutdown ordering information order part no. package qty/ r eel is31 lt3948 - gr ls2 - tr sop - 8 , lead - free 2500 IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 3 absolute maximum rat in gs parameter value v cc to gnd - 0.3v to 6v cs, adj,gate,toff,ovp,fb - 0.3v to 6v v cc max. input current (note ) 10ma junction temperature range - 40 o c to +150 o c storage temperature range - 65 o c to +150 o c esd human model 3 5 00v notes: 1. exceeding vcc maximu m input current may cause the pin not to clamp at 5v. 2. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rati ngs only and functional operation of the device at these or any other conditi on beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabil ity. electr ical characteristics (un less otherwise specified, vin=1 0 v, rin=10k ? , adj floating, t amb =25 o c ) symbol parameter conditions spec unit min typ max v indc input v oltage supply voltage connected to v cc via a appropriate resistor (note) 5 100 v v cc v cc c lamp v oltage rin=10kohm 4.3 5 5.6 v uvlo undervoltage t hr es h old v cc rising 2.0 2.7 3.0 v uvlo undervoltage t hres h old hy s teresis 300 mv i ss quiescent supply current v cc =5v 250 400 ua quiescent supply current when v cc undervoltage v cc = 2.5 v 5 0 75 ua v csth peak c urrent s ense threshold adj=5v 215 240 265 mv t blank peak c urrent s ense bl ank interval v cs =v csth +50mv 500 ns t off fixed turn - off interval rext=250k 10 us v adj peak curren t control low threshold 0.5 v peak curren t control high threshold 2.4 v t sd thermal shutdown threshold 125 o c t sd- hys thermal shutdown hyste resis 20 o c v fb th feedback voltage thres h old 0.29 0.3 0.31 v v ovp-th overvoltage input thres h old 0. 9 1 1. 1 v note: vin is the input voltage. when vin 5v, connect input voltage directly to v cc. when vin > 5v, input voltage should be connected to v cc pin via an appropriate ly valued resistor. IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 4 300 320 340 360 380 400 10 12 14 16 18 20 22 24 26 iout(ma) vin(v) vout=40v,rfb=0.825 ? , rcs=0.12 ? l=100uh,cout=220uf(low esr) 50 60 70 80 90 100 10 12 14 16 18 20 22 24 26 efficiency(%) vin(v) vout=40v,rfb=0.825 ? , rcs=0.12 ? l=100uh,cout=220uf(low esr) 300 320 340 360 380 400 30 34 38 42 46 50 iout(ma) vout(v ) vin=12v,rfb=0.825 ? ,rcs=0.12 ? l=100uh,cout=220uf(low esr) 50 60 70 80 90 100 30 34 38 42 46 50 efficiency(%) vout(v) vin=12v,rfb=0.825 ? , rcs=0.12 ? l=100uh,cout=220uf(low esr) 650 680 710 740 770 800 20 24 28 32 36 40 iout(ma) vin(v) vout=48v,rfb=0.392 ? ,rcs=0.1 ? l=100uh,cout=220uf(low esr) vout=48v,rfb=0.392 ? ,rcs=0.1 ? l=100uh,cout=220uf(low esr) 50 60 70 80 90 100 20 24 28 32 36 40 efficiency(%) vin(v) vout=48v,rfb=0.392 ? ,rcs=0.1 ? l=100uh,cout=220uf(low esr) vout=48v,rfb=0.392 ? ,rcs=0.1 ? l=100uh,cout=220uf(low esr) typical performance characteristics figure 2 . vin & iout figure 3 . vin & efficiency figure 4 . vout & iout figure 5 . vout & efficiency figure 6 . vin & iout figure 7 . vin & efficiency IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 5 650 680 710 740 770 800 40 42 44 46 48 50 52 54 iout(ma) vout(v) vout=48v,rfb=0.392 ? ,rcs=0.1 ? l=100uh,cout=220uf(low esr) vint=24v,rfb=0.392 ? ,rcs=0.1 ? l=100uh,cout=220uf(low esr) 50 60 70 80 90 100 40 42 44 46 48 50 52 54 efficiency(%) vout(v) vout=48v,rfb=0.392 ? ,rcs=0.1 ? l=100uh,cout=220uf(low esr) vin=24v,rfb=0.392 ? ,rcs=0.1 ? l=100uh,cout=220uf(low esr) figure 8 . vout & iout figure 9 .vout & efficiency IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 6 application informat ion internal 5v regulator the IS31LT3948 includes an internal shunt regulator of 5v (typ . ) connected to the v cc pin. when the input voltage is higher than 5 v , connect v cc to vin us ing a n appropriately valued, current limiting resistor . the regulator maintains a 5 v power supply for the internal nmos switch gate driver and the internal control circuitry. in applications where the input voltage is 5 v, connect the input voltage directl y to v cc . when v cc is connected directly to vin, vin may not exceed 5v. bypass the v cc pin using a low esr capacitor (recommended 10f ceramic capacitor) to provide a high frequency path to gnd. the current required by IS31LT3948 is 0. 25ma (typical) plu s the switching current of the external switch. the switching frequency of the external nmos affects the amount of current required, as does the nmos ?s gate charge requirement (found on the nmos data sheet). s g in f q ma . i + 25 0 (1) where f s is th e switching freq uency and q g is the external nmos gate charge. under voltage lockout IS31LT3948 features an u nder v oltage l ockout threshold of 2.7v (typical) with a hysteresis of 3 00mv . the chip is disabled when v cc is lower than 2.4v and enabled when v cc exceeds 2.7v. step - up converter IS31LT3948 ?s step - up converter uses a peak current mode topology wherein the cs pin voltage determines the peak current in the inductor of the converter and hence the duty cycle of the gate switching waveform. the basic lo op uses a pulse from an inte rnal oscillator to set an rs flip - fl op and turn on the external power nmos . after the blanking time, the i nductor current is sensed during the gate on period by a sense resistor, r cs , in the source of the external power nmos . th e c urren t through the nmos and inductor increases until the voltage across the sense resistor re aches the cs threshold, at this time , the nmos is turned off. once the nmos is turned off, the inductor reverses polarity, providing the voltage boost, and the current of inductor will decrease until the fb pin voltage drops below an internal reference voltage and the nmos is then turned on again. this operation repeats in each cycle. note: in the case where the fb pin voltage does not exceed the fb reference vo ltage of 0.3v, such as at the start - up, the nmos will remain off for the programmed minimum toff time, then the nmos is switched on again. led current control IS31LT3948 regulates the led current by sensing the voltage across an external sense resistor i n series with the leds . the voltage is sensed via the fb pin where t he internal feedback reference vo ltage is 0.3 v. the led current can be set according to the following equation easily. fb out r i 3 . 0 = (2) in order t o have an accurate led curr ent, precision resistors are required (1% is recommen ded). setting the over voltage protection the open string protection is achieved through the over voltage protection ( ovp ). in some cases, an l ed string failure will set the feedback voltage to always z ero. if this happens, t he chip will keep boosting the output voltage higher and higher again . if the output voltage reaches the programm ed ovp t hreshold, the protection mechanism will be triggered and stop s the switching action . to make sure that the c ircu it functions properly, the ovp setting resistor divider must be set with a n appropriate value. the recommended ovp v point is about 1. 25 times or 5v (choose the large r one) higher than the output voltage for normal operation. 5 5 4 r r r v v th ovp ovp + = ? (3) where, v ovp-th is 1v, and v ovp is the output voltage ovp level. dimming control there are two method s for dimming. 1) external nmos pwm dimming: fb rfb led(-) sn3948 gnd m2 pwm adj figure 10 when the pwm input is high (v h >2.4v), m2 is on and is 31lt3948 operat es normally to regulate the output current. when pwm is low (v l <0.5v), m2 is off and IS31LT3948 is shutdown. using a fixed frequency pwm signal and changing the duty cycle adjusts the average output current. the recommended 5v pwm frequency is between 200hz and 1khz. m2 is recommended to use ap2306. IS31LT3948 IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 7 2) rc filter pwm dimming: fb c4 r6 r7 r8 rfb for dimming led(-) pwm sn3948 gnd figure 11 a filtered pwm signal can be used as an adjustable dc v oltage for led dimming control. the filtered pwm signal becomes dc voltage which is summed together with the fb voltage to regulate the output current. fix the frequency of the pwm signal and change the duty cycle to adjust the led current. the led current can be calculated by the following equation : rfb r r v duty v r v iout fbth pwm fbth ) 8 7 /( ) ( 6 + ? ? = (4) t he pwm duty cycle is inversely proportio nal to the led current. that is , w hen the pwm signal is 100% duty cycle, the output current is minimum, ideally zero, and when the pwm signal is 0% duty cycle, the output current is maximum. see details va lue in the example section . note: when the v out /v in ratio is less than 2, careful consideration must be given to ensure that v out remains greater than v in at the minimum dimming level. input peak current control IS31LT3948 limits the peak inductor current , and thus the peak input current t hrough the feedback of r3 connected from s ource of nmos to ground . the required average input current is based on the boost ratio, vout/vin, and the designed value for average led current. the required average input curre nt can be calculated as: = in out out in avg v i v i ) ( (5) : assumed power conversion efficiency (the recommended value is 0.9) ge nerally, setting the peak inductor current to 1. 5 times the average input current is sufficient to maintain a good regulation of the output current. cs csth in avg in peak r v i i = = ) ( ) ( 5 . 1 (6) v csth : if 0.5 IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 8 where: v in : input voltage (v) v out : output voltage (v) i ripple : current ripple in the inductor (a) l: inductor value (h) i peak(in) : input peak current (a) i avg(in) : input average current (a) r l : inductor dcr ( ? ) r ds(on) : nmos on resistance ( ? ) v d : diode forward voltage at the required l oad current (v) the recommended switching frequency: 20khz < f < 200khz ( l ower than 20khz will cause audio nois e of the inductor and too high frequency will increase the switching loss on nmos). with fixed v in , v out , i avg(in) , and i peak(in) , the switching frequency is inversely proportional to the inductor value. select an inductor with a rating current higher than the input average current and the saturation current over the calculated peak current. to calculate the worst case inductor peak current, use t he minimum input voltage, maximum output voltage, and maximum total led current. also ensure that the inductor has a low dcr (copper wire resistance) to minimize i 2 r power loss. output capacitor the output capacitor hold s the output current during nmos tu rns on . the capacitor directly impact s the line regulation and the loading regulation. low esr capacitors using at the IS31LT3948 converter output can minimize output ripple voltage and improve output current regulation . for most applications, a 22 0 f low esr capacitor will be sufficient. proportionally lower ripple can be achieved with higher capacitor values. schottky rectifier the external diode for the IS31LT3948 must be a s chottky diode with low forward voltage drop and fast switching speed. the diod e?s average current rating must exceed the application?s average output current. the diode?s maximum reverse voltage rating must exceed the over voltage protection of the application. for pwm dimming applications , be aware of the reverse leakage of the sch ottky diode. lower leakage current will drain the output capacitor less during pwm low periods, allowing for higher pwm dimming ratios. power nmos selection the power nmos selected should have a v ds rating which exceeds the maximum over voltage protecti on (ovp) level programmed for the application. the v gs(th) of nmos should be not higher than 4v. t he r ds (on) of the nmos will determine dc power loss . the dc power loss can be cal culated by: ) ( 2 ) ( 2 1 on ds in out out on ds m loss r v duty i v r i p ? ? ? ? ? ? ? ? = = (12) the recommended nmos rating cu rrent is 5 times ( or higher ) to the input peak current ( ) ( in peak i ). be aware of the power dissipation within the nmos and deciding if the thermal resistance of the nmos package causes the junction temperature to exceed maximum ratings. pcb l ayout consideration as for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. if layout is not carefully done, the regulator could show instability as well as emi problems. ? wide traces should be used for connection of the high current loop to minimize the emi and unnecessary loss . ? the external components ground should be connected to IS31LT3948 ground as short as possible . especially the r fb ground to IS31LT3948 gr ound connection should be as short and wide as possible to have an accurate led current. ? the capacitor c1, c2, c3 should be placed as close as possible to IS31LT3948 for good filtering. especially the output capacitor c3 connection should be as short and w ide as possible. ? nmos drain is a fast switching node. the inductor and schottky diode should be placed as close as possible to the drain and the connection should be kept as short and wide as possible. avoid other traces cross ing and routing too long in parallel with this node to minim ize the noise coupling into these traces. the feedback pin ( e.g. cs, fb, ovp) should be as short as possible and rout ed away from the inductor, the s chottky diode and nmos . the feedback pin and feedback network should be shi elded with a ground plane or trace to minimize noise coupling into this circuit. ? the thermal pad on the back of nmos package must be soldered to the large ground plane for ideal power dissipation. IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 9 vcc toff adj gnd gate cs fb ovp led(+) led(-) vin(5~ 100v) r1 r2 r3 r4 r5 c1 c2 c3 rfb l1 d1 m1 pwm m2 figure.12 external nmos pwm dimming vcc toff adj gnd gate cs fb ovp led(+) led(-) vin(5~100v) r1 r2 r3 r4 r5 c1 c2 c3 c4 r6 r7 r8 rfb l1 d1 m1 pwm for dimming figure.13 rc filter pwm dimming IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 10 example input: vin = 12~24v output: iout = 350ma, vout 30~40v (9~12leds, vf=3.3v ) to calculate the worst case parameter, use the minimum input voltage, the maximum output voltage , and maximum output current. i.e. vin = 12v, iout = 350ma and vout 40v (12leds, vf=3.3v) 1. r1, c 1 and c2 assume iin = 2. 5ma ? ? = k iin vcc vin r 3 1 ? choose c1 as 220 f / 35 v c2 as 10f /1 6 v 2. r2 to set minimal - toff the recommended value is 1s s r t ext off 1 10 40 12 (min) = = ? ? choose r2 = 24 k 3. rfb to set output current and c3 ? = 86 . 0 iout v rfb fbth ? choose c3 = 220 f / 63v (low esr electrolytic capacitor) 4. r6, r7, r8 and c4 r6 r7 r8 can be obtained by: rfb r r v duty v r v iout fbth pwm fbth ) 8 7 /( ) ( 6 + ? ? = put duty=100% , v pwm = 5v and iout=0 into the equation, we have : 86 . 0 ) 8 7 /( ) 3 . 0 % 100 5 ( 6 3 . 0 0 r r r + ? ? = which can be simplified to: 8 7 r6 15.66 r r + = the low pass filter formed by r 8 & c 4 must have a corner frequency much lower than the pwm frequency. as the corner frequency of the filter decreases, the response time of the led current to changes in pwm increases. choose a corner freque ncy 50 times lower than f pwm . pwm f c r 2 50 4 8 assume f pwm is 200hz (or higher), and choose c 4 = 0.1 f , we have r 8 400 k . ? choose c 4 = 0.1 f , r 8 = 400 k . choose a nominal value for r 7 , then , we calculate r 6 . ? c hoose r 7 = 10 k , then r 6 = 26. 2 k put duty=0, v pwm = 5v and iout=350ma into the equation, then we have: a rfb rfb r r v duty v r v iout fbth pwm fbth 35 . 0 ) 10 400 /( ) 3 . 0 % 0 5 ( 2 . 26 3 . 0 ) 8 7 /( ) ( 6 = + ? ? = + ? ? = so , r fb =0.91 ? ( with the rc fil ter pwm dimming, the r fb will be different from the no dimming application.) 4. r3 to set input peak current assum e : ) ( ) ( 5 . 1 in avg in peak i i = a v i v i i in out out in avg in peak 95 . 1 9 . 0 12 35 . 0 40 5 . 1 5 . 1 5 . 1 ) ( ) ( = = = : assumed power conversion efficiency (the recommended value is 0.9) ? = = 123 . 0 ) ( in peak csth cs i v r ? choose r3= 0.1 23 , ipeak=1. 95 a 5. l1 to set frequency input average current: a v i v i in out out in avg 3 . 1 ) ( = = the current ripple in the inductor: ( ) a i i i in avg in peak ripple 3 . 1 2 ) ( ) ( = ? = according to t off > (min) off t : s r i v v v l i t l in avg in d out ripple off 1 ) ( > ? ? + = this gives l>22h . assume l=22h and ? = + + 4 . 0 ) ( cs on ds l r r r . s r r r i v l i t cs on ds l in avg in ripple on 5 . 2 ) ( ) ( ) ( + + ? = then the assumed switching frequency: ( ) khz t t f off on 285 / 1 ' + = the recommended switching frequency: 20khz < f < 200khz, according to the switching frequency is inversely proportional to the inductor value, choose l=100 h . t herefore: khz f f 63 100 22 ' = the saturation current of the inductor must exceed the input peak current ( ) ( in peak i ). IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 11 6. r4, r5 to set ovp set v ovp = vout+5v = 45v 5 5 4 r r r v v th ovp ovp + = ? ? choose r5=10k , then r 4 = 470 k . 7. nmos m1 and diode d1 i1 ( nmos ) >i peak in v1 (nmos) >v ovp nmos with r ds(on) can improve the converter efficiency. the recommended nmos rating current is 5 times (or higher) to the input peak current ( ) ( in peak i ). ? choose 1 3 n 1 0 l as m1 the average and peak current of diode must exceed the output average current and input peak current. the diode?s maximum reverse voltage rating must exceed the over voltage protection of the application. ? choose ss310 as d1 IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 12 classificatio n reflow profiles profile feature pb - free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60- 120 seconds average ramp - up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60- 150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp - down rate (tp to tsmax) 6c/second max. time 25c to peak temperatur e 8 minutes max. classification p rofile IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 13 tape and reel inform ation IS31LT3948 integrated silicon solution, inc. ? www.issi.com rev. a , 8/ 31 /2011 14 package information package outline drawing #d08 4.70 5.10 1.27bsc 3.80 4.00 8 0 5.80 6.20 0.40 1.27 0.17 0.25 1.35 1.75 1.35 1.55 0.10 0.25 0.33 0.51 |
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