1 digital output, low power, red, green, and blue color light sensor isl29120 the isl29120 is a low power, high sensitivity, integrated red, green, and blue light sensor with an i 2 c (smbus compatible) interface. its state-of-the-art photodiode array provides an accurate red, green and blue spectral response. the adc is capable of rejecting 50hz and 60hz flicker caused by artificial light sources. a selectable range allows the user to optimize sensitivity suitable for the specific application. isl29120 is optimized for sensing red, green and blue light components in an non-infrared environment (fluorescent and led lighting). when operating in infrared rich environments, an external ir blocking filter should be used for accurate measurements. in normal continuous oper ation, the isl29120 power consumption is 70a, which reduces to 0.3a in power down mode. in polling mode, the auto-p ower-down function shuts down most of the device after each adc conversion. the isl29120 supports both hard ware and software interrupts. the interrupt thresholds are us er programmable. the interrupt persistency feature reduces false trigger notification. designed to operate on supplie s from 2.25v to 3.3v and i 2 c supply from 1.7v to 3.6v, the isl29120 is specified for operation over the -40c to +85c ambient temperature range. features ? 70a operating current, 0.3a shutdown current ?i 2 c (smbus compatible) output ? programmable 4, 8, 12 or 16-bits adc resolution ?programmable interrupt windows ? two optical sensitivity ranges ? 2.25 to 3.63v operating power supply ? 1.7v to 3.6v supply for i 2 c interface ? 2.0mmx2.1mmx0.7mm 6 ld odfn package applications ? smart phone, pda, gps, tablet pcs, lcd-tvs, digital picture frames, digital cameras ? dynamic display color balancing ? printer color enhancement ? industrial/commercial led lighting color management ? ambient light color detection/correction ? oled display aging compensation figure 1. typical application figure 2. relative spectral sensitivity for red, green and blue sense modes vdd_pullup smbmaster int sda scl int sda scl vdd vdd gnd rext 499k ? c1 1f r1 4 6 5 1 3 2 isl29120 pull-up resistors 2.7k ? to 10k ? r2 100 ? 300 400 500 600 700 800 900 1000 1100 0.5 0.4 0.3 0.2 0.1 0 wavelength (nm) relative sensitivity (%) red sensor green sensor blue sensor may 29, 2012 fn8314.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl29120 2 fn8314.0 may 29, 2012 pin configuration isl29120 (6 ld odfn) top view figure 3. block diagram vdd rext gnd sda scl command register integration adc data register photodiode light 3 2 5 6 1 f osc iref 4 int process array data i 2 c/smbus isl29120 red, green, blue 1 2 3 6 5 4 vdd gnd rext sda scl int *exposed pad (0) can be connected to gnd or electrically isolated pad ordering information part number (notes 1, 2, 3) temp. range (c) package tape and reel (pb-free) pkg. dwg. # ISL29120IROZ-T7 -40 to +85 6 ld odfn l6.2x2.1 isl29120iroz-evalz evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl29120 . for more information on msl please see tech brief tb477 . pin descriptions pin number pin name description 0 pad exposed thermal pad, connected to ground. 1 vdd positive power supply, 2.25v to 3.63v. 2gndground pin. 3 rext connect to ground through a 499k ? resistor. 4int interrupt output, open drain 5scli 2 c serial clock input scl and sda are open drain. pull-up to 1.7v min to 3.63v max power supply. 6sdai 2 c serial data input/output
isl29120 3 fn8314.0 may 29, 2012 absolute maximum ratings (t a = +25c) thermal information v dd , supply voltage between v dd and gnd . . . . . . . . . . . . . . . . . . . . . .4.0v i 2 c bus (scl, sda) pin voltage. . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to 4.0v i 2 c bus (scl, sda) pin current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10ma rext pin voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to v dd +0.5v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv thermal resistance (typical) ja (c/w) 6 ld odfn package (note 4) . . . . . . . . . . . . . . . . . . . . . 62 maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +90c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v dd = 3v, t a = +25c, r ext = 499k ? 1% tolerance, 16-bit adc operation, unless otherwise specified. parameter description condition min (note 5) typ max (note 5) unit v dd power supply range 2.25 3.63 v i dd supply current 70 85 a i dd1 supply current when powered down software disabled or auto power-down 0.01 0.3 a v i2c supply voltage range for i 2 c interface 1.7 3.63 v t int adc conversion time 16-bit adc data 90 ms f i2c i 2 c clock rate range 400 khz data_0 dark count range setting = 0; adc resolution 16 bits 1 5 counts data_fs full scale adc code adc resolution 16 bits 65535 counts data_red red count range = 0; = 640nm; irradiance 155 w/cm 2 15000 20000 25000 counts range = 1; = 640nm; irradiance 155 w/cm 2 4350 counts data_green green count range = 0; = 530nm; irradiance 212 w/cm 2 15000 20000 25000 counts range = 1; = 530nm; irradiance 212 w/cm 2 4350 counts data_blue blue count range = 0; = 470nm; irradiance 215 w/cm 2 15000 20000 25000 counts range = 1; = 470nm; irradiance 215 w/cm 2 4350 counts v ref voltage at r ext pin 0.52 v v il scl and sda input low voltage 0.55 v v ih scl and sda input high voltage 1.25 v i sda sda current sinking capability 45 ma notes: 5. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6. 640nm red, 530nm green and 470 nm blue leds are used to generate a nominal count of 20000 for the red, green and blue data ou tput to characterize part to part variation in production test.
isl29120 4 fn8314.0 may 29, 2012 principles of operation photodiodes and adc the isl29120 contains three photodiode arrays, which convert light into current. the spectral re sponse for red, green and blue color ambient intensity sensing is as shown in figure 2. after light is converted to current during the light to signal process, the current output is converted to a digital count by an on-chip analog-to-digital converter (adc). the adc converter resolution is selectable from 4, 8, 12 or 16 bits. the adc conversion time is inversely proportional to the adc resolution. the adc converter uses an integrating architecture. this conversion method is ideal for converting small signals in the presence of a periodic noise. a 100ms integration time (16-bit mode) for instance, rejects 50hz an d 60hz power line as well as florescent flicker noise. the adc integration time is determ ined by an internal oscillator and the n-bit (n = 4, 8, 12, 16) counter inside the adc. a good balancing act of integration time and resolution depends on the application for optimu m system performance. the adc provides two programmable ranges to dynamically accommodate different lighting conditions. for dim conditions, the adc can be configured at its high sensitivity (low optical) range. for bright conditions, the adc can be configured at its low sensitivity (higher optical) range. note that the effective optical sensitivity of the isl29120 in terms of counts/ w/cm 2 is directly proportional to the adc integration time. i 2 c interface there are eight 8-bit registers inside the isl29120 for configuration, control and stat us indication. the two command registers at address 0x00 and 0x01 define the operation of the device and provide status of the interrupt events. two 8-bit read only registers at address 0x02 and 0x03 are for the adc output. these registers contain the result s of the latest a/d conversion. registers 0x04 and 0x05 contain the ?low threshold? value and registers 0x06 and 0x07 store the ?high threshold? value for interrupt generation. the isl29120?s i 2 c interface slave address is internally hard-wired as 1000110x, where x is r (read) or w (write) bit. figure 4 shows a sample one-byte read. figure 5 shows a sample one-byte write. the i 2 c bus master always drives the scl (clock) line, while either the master or the slave can drive the sda (data) line. figure 5 shows a sample write. every i 2 c transaction begins with the master asserting a start condition (sda falling while scl remains high). the following byte is driven by the master, and includes the slave address and read/write bit. the receiving device is responsible for pulling sda low during the acknowledgement period. every i 2 c transaction ends with the master asserting a stop condition (sda rising while scl remains high). for more information about the i 2 c standard, consult the philips? i 2 c specification documents. figure 4. i 2 c read timing diagram sample start w a a a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a a6 a5 a4 a3 a2 a1 a0 w a a a ad7d6d5d4d3d2d1d0 1357 1357 123 45 6 9 2 4 6 stop start sda driven by master device address sda driven by isl29120 data byte0 register address out device address i 2 c data sda driven by master sda driven by master 2468 924689 78135789 i 2 c sda i 2 c sda i 2 c clk in figure 5. i 2 c write timing diagram sample start w a a a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a b7 b6 b5 b4 b3 b2 b1 b0 a a 12615948 stop sda driven by master functions register address device address sda driven by master sda driven by master i 2 c data i 2 c sda in i 2 c sda out i 2 c clk in aa 345 7 89 234 678 12 3 5 67 9 a
isl29120 5 fn8314.0 may 29, 2012 register set there are eight registers that are available in the isl29120. table 1 su mmarizes their functions. command register i 0x00 the first command register has the following functions: operation mode: bits[7:5]. these three bits determine the operation mode of the device. interrupt flag: bit[2]. this is the interrupt status bit. the bit is set high when the interrupt threshol ds have been triggered. once triggered, the int pin stays low and the status bit stays high. both the interrupt pin and the status bit are cleared at the end of command register i read. interrupt persist: bits[1:0]. the interrupt pin and the interrupt flag are triggered/set when the data sensor reading is out of the interrupt threshold window after m consecutive data conversion cycles. the interrupt persist bits determine m. command register ii 0x01 the second command register has the following functions: resolution: bits[3:2] determine the adc?s resolution and the integration time. the integration ti me is the period the device?s analog-to-digital (a/d) converter samples the photodiode current for a measurement. 1. range 0x01[0]: the full scale optical range (fsor). optical sensitivity for the ?low? range is 4.75 times the optical sensitivity in ?high? range. table 1. register set addr reg name bit 765 4 321 0default 00h commandi op2 op1 op0 0 0 iflg prst1 prst0 00h 01h commandii 0 0 0 0 res1 res0 0 range 00h 02h data lsb d7 d6 d5 d4 d3 d2 d1 d0 00h 03h data msb d15 d14 d13 d12 d11 d10 d9 d8 00h 04h int_lt_lsb tl7 tl6 tl5 tl4 tl3 tl2 tl1 tl0 00h 05h int_lt_msb tl15 tl14 tl13 tl12 tl11 tl10 tl9 tl8 00h 06h int_ht_lsb th7 th6 th5 th4 th3 th2 th1 th0 ffh 07h int_ht_msb th15 th14 th13 th12 th11 th10 th9 th8 ffh table 2. operation mode 0x00[7:5] operation 000 power-down 001 red sensor once 010 blue sensor once 011 green sensor once 100 reserved 101 red sensor continuous 110 blue sensor continuous 111 green sensor continuous table 3. interrupt flag 0x00[2] operation 0 no interrupt event 1 interrupt event triggered table 4. interrupt persistence 0x00[1:0] number of data conversion cycles 00 1 01 4 10 8 11 16 table 5. adc resolution data width 0x01[3:2] integration time (ms) resolution 00 90 16 bits 01 5.6 12 bits 10 0.35 8 bits 11 0.022 4 bits table 6. range 0x01[0] fsr 0low 1high
isl29120 6 fn8314.0 may 29, 2012 data registers (0x02 and 0x03) isl29120 has two 8-bit read-only registers to hold the lsbyte and msbyte data from the adc. the most significant byte (msb) is accessed at address 0x03, and the least significant byte (lsb) is accessed at address 0x02. for 16-bit resolution, the data is from d0 to d15; for 12-bit resolution, the data is from d0 to d11; for 8-bit resolution, the data is from d0 to d7. the registers are refreshed after every conversion cycle. interrupt threshold registers registers 0x04 and 0x05 set the low (lo) threshold for the interrupt pin and the interrupt flag. register 0x04 is the lsbyte and 0x05 is the msbyte. by default, the interrupt threshold lo is 00 hex for both lsbyte and msbyte. registers 0x06 and 0x07 set the high (hi) threshold for the interrupt pin and the interrupt flag. register 0x06 is the lsbyte and 0x07 is the msbyte. by default, the interrupt threshold hi is 0xff for both lsbyte and msbyte. note that there is only one set of threshold registers as isl29120 performs r, g and b conversions sequentially. if different thresholds are required for each color, then these threshold registers must be re-configured prior to issuing a convert start command. if a common threshold setting for the r, g and b is desired then the threshold register can be initialized at power-up. interrupt threshold regist ers should be programmed appropriately for the selected adc conversion resolution. for example, for 12-bit mode, only the corresponding 12 bits of the threshold registers must be programmed and the remaining bits should be set to zero. interrupt function an interrupt event (iflg) is indicated by 0x00[2]. the user must clear this bit during the device initialization. the isl29120 will issue an interrupt indication by se tting the iflg bit if the count in register 0x02 and 0x03 are outside the user's programmed window in interrupt threshold registers. read register 0x00 to clear the interrupt flag. interrupt flags should also be cleared following a interrupt thresh old configuration change. an interrupt persistency 0x01[1:0] option is available for interrupt event control for the rgb ambient light measurement. persistency requires x-in-a-row interrupt flags before the int pin is driven low. the user must read register 0x0 to clear the interrupt. noise/flicker rejection integrating adc?s provide excellent flicker/noise-rejection for periodic sources whose frequency is an integer multiple of the conversion rate. for instance, a 60hz ac unwanted signal?s sum from 0ms to k*16.66ms (k = 1,2...k i ) is zero. similarly, setting the device?s integration time to be an integer multiple of the periodic noise signal significantly improves the light sensor output signal in the presence of noise. typical application circuit a typical application for the isl29120 is shown in figure 6. the isl29120?s i 2 c address is internally hardwired as 1000110x. the device can be connected to a system?s i 2 c bus with other i 2 c compliant devices. suggested pcb footprint it is important that users check the ?surface mount assembly guidelines for optical dual flat pack no lead (odfn) package? before starting odfn product board mounting. http://internal.intersil.com/content/dam/intersil/documents/tb 47/tb477.pdf pcb layout considerations the isl29120 is relatively insensitive to pcb layout. there are only a few considerations that will ensure best performance. route the supply and i 2 c traces away from sources of digital switching noise. use a 1f power-supply decoupling capacitors close to the device. a series resist or in the power supply to isolate switching noise elsewhere in th e system is recommended. the 499k ? resistor should be placed clos e to the device and away from any noise sources. soldering considerations convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. the plastic odfn package does not require a custom reflow soldering profile, and is qualified to +260c. a standard reflow soldering profile with a +260c maximum is recommended. rgb spectral sensitivity typical spectral response of th e isl29120?s red, green and blue channels is shown in figure 2. it should be observed that there is a considerable cross-spectral se nsitivity among three colors. in addition, all three channels have a strong sensitivity to light in infra-red spectrum. it is therefore imperative that the a color sense system-based on isl29120 be calibrated for the desired application using a mathematical model to compen sate for the cross-spectral coupling between the red, green and blue channels. for operation in infra-red rich environments, such as sunlight or incandescent lighting, use of an external infrared filter is required for meaningful spectral color sensing. table 7. data registers address contents 0x02 d0 is lsb for 4, 8, 12 or 16-bit resolution; d3 is msb for 4-bit resolution; d7 is msb for 8-bit resolution 0x03 d15 is msb for 16-bit resolution; d11 is msb for 12-bit resolution figure 6. isl29120 typical application circuit vdd_pullup smbmaster int sda scl int sda scl vdd vdd gnd rext 499k ? c1 1f r1 4 6 5 1 3 2 isl29120 pull-up resistors 2.7k ? to 10k ? r2 100 ?
isl29120 7 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8314.0 may 29, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl29120 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php figure 7. 6 ld odfn sensor location outline 1 3 4 6 2 5 sensor offset 0.54 0.37 0.40 blue green red revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change may 29, 2012 fn8314.0 initial release.
isl29120 8 fn8314.0 may 29, 2012 package outline drawing l6.2x2.1 6 lead optical dual flat no-lead plastic package (odfn) rev 3, 5/11 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 a b pin #1 b 0.10 ma c c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 5 1 6 6 2.10 2.00 2.10 2.50 (1.35) (6x0.30) 0.65 (6x0.55) (6x0.20) (4x0.65) 1.30 ref 1.35 0.65 0.65 6x0.35 0.05 package 6x 0.300.05 index area outline 4 max 0.75
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