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data sheet ics8s89874bki revision a october 22, 2010 1 ?2010 integrated device technology, inc. 1:2 differential-to-lvpecl buffer/divider ICS8S89874I general description the ICS8S89874I is a high speed 1:2 differ ential-to- lvpecl buffer/ divider. the ICS8S89874I has a selectable 1, 2, 4, 8, 16 output divider, which allows the device to be used as either a 1:2 fanout buffer or frequency divider. the clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. the device is packaged in a small, 3mm x 3mm vfqfn package, making it ideal for use on space-constrained boards. features ? two lvpecl/ecl output pairs ? frequency divide select options: 1 (pass through), 2, 4, 8, 16 ? in, nin input can accept the following differential input levels: lvpecl, lvds, cml ? output frequency: 2ghz (maximum) ? output skew: 15ps (maximum) ? part-to-part skew: 250ps (maximum) ? additive phase jitter, rms: 0.20ps (typical) ? lvpecl supply voltage r ange: 2.375v to 3.63v ? ecl supply voltage range: -3.63v to -2.375v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package ICS8S89874I 16-lead vfqfn 3mm x 3mm x 0.925mm package body k package top view block diagram pin assignment 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 q0 nq0 q1 nq1 in v t v ref_ac nin s2 nc v cc nreset s1 v cc v ee s0 enable mux enable ff decoder 00 2 01 4 10 8 11 16 0 1 50 ? 50 ? q0 nq0 q1 nq1 in v t nin s2 s0 s1 nreset v ref_ac pullup pullup pullup pullup
ics8s89874bki revision a october 22, 2010 2 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q0, nq0 output diffe rential output pair. lvpec l/ecl interface levels. 3, 4 q1, nq1 output diffe rential output pair. lvpec l/ecl interface levels. 5, 15, 16 s2, s1, s0 input pullup select pins. lvcmos/lvttl interface levels. 6 nc unused no connect. 7, 14 v cc power positive supply pins. 8 nreset input pullup when low, resets the divider. pulled high when left unconnected. input threshold is v cc /2. includes a 37k ? pullup resistor. lvttl/lvcmos interface levels. 9 nin input inverting differen tial lvpecl clock input. r t = 50 ? termination to v t . 10 v ref_ac output reference voltage for ac-coupled applications. 11 v t input termination input. 12 in input non-inverting lvpec l differential clock input. r t = 50 ? termination to v t . 13 v ee power negative supply pin. symbol parameter test conditions minimum typical maximum units r pullup input pullup resistor 37 k ?
ics8s89874bki revision a october 22, 2010 3 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider function tables table 3a. control input function table figure 1. nreset timing diagram table 3b. truth table inputs outputs nreset selected source q0, q1 nq0, nq1 0 in/nin disabled; low disabled; high 1 in/nin enabled enabled inputs outputs nreset s2 s1 s0 1 0 x x reference clock 1 (pass through) 1 1 0 0 reference clock 2 1 1 0 1 reference clock 4 1 1 1 0 reference clock 8 1 1 1 1 reference clock 16 0 1 x x q = low, nq = high; clock disabled 0 0 x x q = low, nq = high; clock disabled t pd t rr v out swing v cc /2 v in v in swing nreset nin in nqx qx
ics8s89874bki revision a october 22, 2010 4 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc -0.5v to + 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma input current, in, nin 50ma v t current, i vt 100ma v ref_ac input sink/source, i ref_ac 2ma operating temperature range, t a -40c to +85c package thermal impedance, ja , (junction-to-ambient) 74.7 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typi cal maximum units v cc positive supply voltage 2.375 3.3 3.63 v i ee power supply current 45 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage 0 0.8 v i ih input high current v cc = v in = 3.63v or 2.625v 10 a i il input low current v cc = 3.63v or 2.625v, v in = 0v -150 a
ics8s89874bki revision a october 22, 2010 5 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider table 4c. differential dc characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: guaranteed by design. table 4d. lvpecl dc characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: input and output par ameters vary 1:1 with v cc . note 1: outputs terminated with 50 ? to v cc ? 2v. symbol parameter test conditio ns minimum typical maximum units r in differential input resi stance (in, nin) 40 50 60 ? v ih input high voltage (in, nin) 1.2 v cc v v il input low voltage (in, nin) 0 v ih ? 0.15 v v in input voltage swing 0.15 1.2 v v diff_in differential input voltage swing 0.3 v i in input current; note 1 (in, nin) 35 ma v ref_ac bias voltage v cc ? 1.45 v cc ? 1.37 v cc ? 1.32 v symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.175 v cc ? 0.82 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.575 v v out output voltage swing 0.6 1.0 v v diff_out differential output voltage swing 1.2 2.0 v
ics8s89874bki revision a october 22, 2010 6 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider ac electrical characteristics table 5. ac characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters characterized at 1ghz, 800mv input signal, unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: defined as skew between outputs on different devices o perating at the same supply voltage , same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 4: this parameter is defined in accordance with jedec standard 65. note 5: pass through, 1 mode. symbol parameter test conditions minimum typical maximum units f out output frequency output swing 450mv 2 ghz f in input frequency 2, 4, 8, 16 2.5 ghz t pd propagation delay; (differential); note 1 input swing: <400mv 460 640 840 ps input swing: 400mv 430 615 810 ps t sk(o) output skew; note 2, 4 15 ps t sk(pp) part-to-part skew; note 3, 4 250 ps t jit buffer additive jitt er; rms; refer to additive phase jitter section; note 5 155.52mhz, integration range: 12khz ? 20mhz 0.20 ps t rr reset recovery time 600 ps t r / t f output rise/fall time 20% to 80% 70 250 ps
ics8s89874bki revision a october 22, 2010 7 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. the source generator ifr2042 and agilent 8133 were the external input to drive the input clock, in, nin. additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.20ps (typical) ssb phase noise dbc/hz offset from carr ier frequency (hz)
ics8s89874bki revision a october 22, 2010 8 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider parameter measurement information output load ac test circuit part-to-part skew single-ended & differential input voltage swing output rise/fall time differential input level output skew propagation delay scope qx nqx lvpecl v ee v cc 2v -0.375v to -1.63v t sk(pp) part 1 part 2 qx nqx qy nqy v in v diff_in differential voltage swing = 2 x single-ended v in 20% 80% 80% 20% t r t f v swing nq0, nq1 q0, q1 v ih cross points v in v il in nin v cc v ee t sk(o) qx nqx qy nqy t pd nq0, nq1 q0, q1 in nin
ics8s89874bki revision a october 22, 2010 9 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider applications information 3.3v differential i nput with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, cml and other differential signals. both signals must meet the v in and v ih input requirements. figures 2a to 2d show interface examples for the in/nin input with built-in 50 ? terminations driven by the most common driver types. th e input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. n/nin input with built-in 50 ? driven by an lvds driver figure 2c. in/nin input with built-in 50 ? driven by a cml driver figure 2b. in/nin input with built-in 50 ? driven by an lvpecl driver figure 2d. in/nin input with built-in 50 ? driven by a cml driver with built-in 50 ? pullup in nin vt receive r with built-in 50 lvds 3.3v 3.3v zo = 50 zo = 50 in nin vt cml ? open collector receive r with built-in 50 3.3v 3.3v zo = 50 zo = 50 in nin vt receive r with built-in 50 r1 50 lvpecl 3.3v 3.3v zo = 50 zo = 50 cml ? built-in 50 pull-up in nin vt receiver with built-in 50 3.3v 3.3v zo = 50 zo = 50
ics8s89874bki revision a october 22, 2010 10 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider 2.5v lvpecl input with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, cml and other differential signals. both signals must meet the v in and v ih input requirements. figures 3a to 3d show interface examples for the in/nin with built-in 50 ? termination input driven by the most common driver types. th e input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. in/nin input with built-in 50 ? driven by an lvds driver figure 3c. in/nin input with built-in 50 ? driven by a cml driver figure 3b. in/nin input with built-in 50 ? driven by an lvpecl driver figure 3d. in/nin input with built-in 50 ? driven by a cml driver with built-in 50 ? pullup in nin vt receiver with built-in 50 lvds 3.3v or 2.5v 2.5v zo = 50 zo = 50 in nin vt cml receive r with built-in 50 2.5v 2.5v zo = 50 zo = 50 in nin vt receiver with built-in 50 r1 18 lvpecl 2.5v 2.5v zo = 50 zo = 50 cml - built-in 50 pull-up in nin vt receiver with built-in 50 2.5v 2.5v zo = 50 zo = 50
ics8s89874bki revision a october 22, 2010 11 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider recommendations for unused input and output pins inputs: lvcmos control pins all control pins has internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both si des of the different ial output pair should either be left floating or terminated. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low im pedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to groun d) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 r2 50 rtt z o = 50 z o = 50 + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 r2 84 3.3v r3 125 r4 125 z o = 50 z o = 50 lvpecl input 3.3v 3.3v + _
ics8s89874bki revision a october 22, 2010 12 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider termination for 2.5v lvpecl outputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. figure 5a. 2.5v lvpecl driver termination example figure 5c. 2.5v lvpecl driver termination example figure 5b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ?
ics8s89874bki revision a october 22, 2010 13 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the out er edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics8s89874bki revision a october 22, 2010 14 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider power considerations this section provides information on power dissipation and junction temperature for the ICS8S89874I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS8S89874I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.63v * 45ma = 163.35mw power (outputs) max = 32.62mw/loaded output pair if all outputs are loaded, the total power is 2 * 32.62mw = 65.24mw power dissipation for internal termination r t power (r t ) max = (v in_max ) 2 / r t_min = (1.2v) 2 / 80 ? = 18mw total power_ max = (3.63v, with all outputs switchin g) = 163.35mw + 65.24mw + 18mw = 246.59mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bond pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.247w * 74.7c/w = 103.5c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 16 lead vfqfn, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics8s89874bki revision a october 22, 2010 15 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.82v (v cc_max ? v oh_max ) = 0.82v for logic low, v out = v ol_max = v cc_max ? 1.58v (v cc_max ? v ol_max ) = 1.58v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.82v)/50 ? ] * 0.82v = 19.35mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v co_max ? v ol_max ) = [(2v ? 1.58v)/50 ? ] * 1.58v = 13.27mw total power dissipation per output pair = pd_h + pd_l = 32.62mw v out v cc v cc - 2v q1 rl 50
ics8s89874bki revision a october 22, 2010 16 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider reliability information table 7. ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for ICS8S89874I is: 489 pin compatible with ics889874 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics8s89874bki revision a october 22, 2010 17 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider package outline and package dimensions package outline - k suffix for 16 lead vfqfn table 8. package dimensions reference document: jede c publication 95, mo-220 top vie w index a re a d cham fer 4x 0.6 x 0.6 max optional a 0. 0 8 c c a3 a1 seating plan e e2 e2 2 l (n -1)x e (r e f.) (ref.) n & n eve n n e d2 2 d2 (ref.) n& n od d 1 2 e 2 (typ.) if n & n are eve n (n -1)x e (re f.) b thermal bas e n de d de de e anvil singulation or sawn singulation n-1 n chamfer 1 2 n-1 1 2 n radius n-1 1 2 n aa dd cc bb 4 4 4 4 4 4 bottom view w/type b id bottom view w/type c id bottom view w/type a id there are 3 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type b: dummy pad between pin 1 and n. 3. type c: mouse bite on the paddle (near pin 1) jedec variation: veed-2/-4 all dimensions in millimeters symbol minimum maximum n 16 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.30 n d & n e 4 d & e 3.00 basic d2 & e2 1.00 1.80 e 0.50 basic l 0.30 0.50
ics8s89874bki revision a october 22, 2010 18 ?2010 integrated device technology, inc. ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8s89874bkilf 874b ?lead-free? 16 lead vfqfn tube -40 c to 85 c 8s89874bkilft 874b ?lead-free? 16 lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS8S89874I data sheet 1:2 differential-to-lvpecl buffer/divider disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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