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general description the MAX19541 monolithic 12-bit, 125msps analog-to- digital converter (adc) is optimized for outstanding dynamic performance at high-if frequencies of 300mhz and beyond. this device operates with con- version rates up to 125msps while consuming only 861mw. at 125msps and an input frequency of 240mhz, the MAX19541 achieves a spurious-free dynamic range (sfdr) of 71.5dbc. the MAX19541 features an excel- lent signal-to-noise ratio (snr) of 65.4db at 10mhz that remains flat (within 3db) for input tones up to 250mhz. this makes the MAX19541 ideal for wideband applica- tions such as power-amplifier predistortion in cellular base-station transceiver systems. the MAX19541 operates in either parallel mode where the data outputs appear on a single parallel port at the sampling rate, or in demux parallel mode, where the out- puts appear on two separate parallel ports at one-half the sampling rate. see the mode of operation section. the MAX19541 operates on a single 1.8v supply. the analog input is differential and can be ac- or dc-cou- pled. the adc also features a selectable on-chip divide-by-2 clock circuit that allows clock frequencies as high as 250mhz. this helps to reduce the phase noise of the input clock source, allowing for higher dynamic performance. for best performance, a differ- ential lvpecl sampling clock is recommended. the digital outputs are cmos compatible and the data for- mat can be selected to be either two? complement or offset binary. a pin-compatible, 12-bit, 170msps version of the MAX19541 is also available. refer to the max19542 data sheet for more information. the MAX19541 is available in a 68-pin qfn with exposed paddle (ep) and is specified over the extend- ed (-40? to +85?) temperature range. applications base-station power amplifier linearization cable head-end receivers wireless and wired broadband communication communications test equipment radar and satellite subsystems features ? 125msps conversion rate ? snr = 65db, f in = 100mhz at 125msps ? sfdr = 77dbc, f in = 100mhz at 125msps ? ?.7 lsb inl, ?.25 dnl (typ) ? 861mw power dissipation at 125msps ? on-chip selectable divide-by-2 clock input ? parallel or demux parallel digital cmos outputs ? reset option for synchronizing multiple adcs ? data clock output ? offset binary or two?-complement output ? evaluation kit available (MAX19541evkit) MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications ________________________________________________________________ maxim integrated products 1 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 av cc agnd av cc qfn top view av cc ognd ov cc ora da11 da10 da9 da8 da7 52 53 da6 da5 agnd agnd av cc clkp clkn av cc agnd ov cc ognd db0 ov cc db2 db1 db3 da0 orb ognd ov cc dclkp dclkn ov cc db11 db10 db9 35 36 37 db8 db7 db6 note: exposed paddle connected to agnd. agnd inn inp agnd av cc demux reset av cc av cc av cc agnd refadj refio agnd 48 da1 av cc 64 agnd 65 66 67 itl agnd av cc 68 t/b 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 db4 db5 34 33 49 50 da3 da2 51 da4 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 clkdiv 17 MAX19541 pin configuration ordering information 19-3432; rev 0; 11/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ep = exposed paddle. evaluation kit available part temp range pin- package pkg code MAX19541egk -40? to +85? 68 qfn-ep* g6800-4
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 125mhz, demux = 0, differential lvpecl clock input drive, 0.1? capacitor on refio, internal reference, t a = t min to t max , unless otherwise noted. t a +25? guaranteed by production test, t a < +25? guaranteed by design and characterization. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc to agnd ......................................................-0.3v to +2.1v ov cc to ognd .....................................................-0.3v to +2.1v av cc to ov cc .......................................................-0.3v to +2.1v agnd to ognd ....................................................-0.3v to +0.3v analog inputs (inp, inn) to agnd ..........-0.3v to (av cc + 0.3v) all digital inputs to agnd........................-0.3v to (av cc + 0.3v) refio, refadj to agnd ........................-0.3v to (av cc + 0.3v) all digital outputs to ognd ....................-0.3v to (ov cc + 0.3v) maximum current into any pin .........................................?0ma esd on all pins (human body model).............................?000v continuous power dissipation (t a = +70?) 68-pin qfn (derate 41.7mw/? above +70?) .........3333mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity inl f in = 10mhz (note 1) -2.5 ?.7 +2.5 lsb differential nonlinearity dnl f in = 10mhz, no missing codes (note 1) -0.75 ?.25 +0.75 lsb transfer curve offset v os (note 1) -3 +3 mv offset temperature drift 40 mv/? analog inputs (inp, inn) full-scale input voltage range v fs (note 1) 1300 1410 1510 mv p-p full-scale range temperature drift 130 ppm/? common-mode input range v cm 1.365 ?.15 v input capacitance c in 3pf differential input resistance r in 3.00 4.3 6.25 k ? full-power analog bandwidth fpbw 900 mhz reference (refio, refadj) reference output voltage v refio 1.22 1.245 1.27 v reference temperature drift 90 ppm/? refadj input high voltage v refadj used to disable the internal reference av cc - 0.3 v sampling characteristics maximum sampling rate f sample 125 mhz minimum sampling rate f sample 20 mhz clock duty cycle set by clock-management circuit 40 to 60 % aperture delay t ad figure 4 620 ps aperture jitter t aj 0.2 ps rms
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications _______________________________________________________________________________________ 3 electrical characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 125mhz, demux = 0, differential lvpecl clock input drive, 0.1? capacitor on refio, internal reference, t a = t min to t max , unless otherwise noted. t a +25? guaranteed by production test, t a < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units clock inputs (clkp, clkn) differential clock input amplitude (note 2) 200 500 mv p-p clock input common-mode voltage range 1.15 ?.25 v clock differential input resistance r clk 11 ?5% k ? clock differential input capacitance c clk 5pf dynamic characteristics (at -2dbfs) f in = 10mhz 63.7 65.4 f in = 100mhz 63.3 65 f in = 180mhz 64.1 signal-to-noise ratio snr f in = 240mhz 63.4 db f in = 10mhz 63.1 65.2 f in = 100mhz 62.5 64.2 f in = 180mhz 63.4 signal-to-noise and distortion sinad f in = 240mhz 62.7 db f in = 10mhz 72 82 f in = 100mhz 70.5 77 f in = 180mhz 75 spurious-free dynamic range sfdr f in = 240mhz 71.5 dbc f in = 10mhz -88.7 -72 f in = 100mhz -73.1 -70.5 f in = 180mhz -72.8 worst harmonics (hd2 or hd3) f in = 240mhz -71.5 dbc two-tone intermodulation distortion imd 100 f in1 = 150mhz at -7dbfs, f in2 = 153mhz at -7dbfs, f sample = 125mhz -75 dbc cmos digital outputs (da0?a11, db0?b11, ora, orb) logic-high output voltage v oh ov cc - 0.1 v logic-low output voltage v ol 0.1 v lvcmos digital inputs (clkdiv, t /b, demux, itl) digital input-voltage low v il 0.2 x av cc v digital input-voltage high v ih 0.8 x av cc v
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications 4 _______________________________________________________________________________________ note 1: static linearity and offset parameters are computed from a straight line drawn between the end points of the code transition transfer function. the full-scale range (fsr) is defined as 4096 x slope of the line. note 2: parameter guaranteed by design and characterization; t a = t min to t max . note 3: psrr is measured with both analog and digital supplies connected to the same potential. electrical characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 125mhz, demux = 0, differential lvpecl clock input drive, 0.1? capacitor on refio, internal reference, t a = t min to t max , unless otherwise noted. t a +25? guaranteed by production test, t a < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units input resistance r in 46.5 k ? input capacitance c in 5pf timing characteristics c lkp - to- d a0d a11 p r op ag ati on d el ay t pdl figures 5, 6, 7 2.5 ns clk-to-dclkp propagation delay t cpdl figures 5, 6, 7 2.1 ns dclkp rising edge to da0?a11 t pdl - t cpdl figures 5, 6, 7 (note 2) 180 400 710 ns cmos output rise time t rise 20% to 80%, c l = 5pf 1 ns cmos output fall time t fall 20% to 80%, c l = 5pf 1 ns reset hold t hr figure 4 100 ps reset setup t sr figure 4 500 ps output data pipeline delay t latency figure 4 11 clock cycles power requirements analog supply voltage range av cc 1.7 1.8 1.9 v digital supply voltage range ov cc 1.7 1.8 1.9 v analog supply current i avcc f in = 100mhz 460 500 ma digital supply current i ovcc f in = 100mhz 18 25 ma analog power dissipation p diss f in = 100mhz 861 945 mw offset (note 3) 1.8 mv/v power-supply rejection ratio psrr gain (note 3) 1.5 %fs/v
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications _______________________________________________________________________________________ 5 fft plot (16,384-point data record) MAX19541 toc01 analog input frequency (mhz) 4 5 6 60 40 50 20 30 10 0 amplitude (db) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in = 11.5284138mhz f sample = 125.0043232mhz a in = -0.959dbfs snr = 66.416db sinad = 66.211db sfdr = 83.199dbc hd2 = -95.203dbc hd3 = -83.199dbc 3 2 7 fft plot (16,384-point data record) MAX19541 toc02 analog input frequency (mhz) 2 3 4 5 60 40 50 20 30 10 0 amplitude (db) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in = 60.0225226mhz f sample = 125.0043232mhz a in = -0.985dbfs snr = 66.359db sinad = 65.581db sfdr = 74.285dbc hd2 = -87.016dbc hd3 = -74.285dbc 7 6 fft plot (16,384-point data record) MAX19541 toc03 analog input frequency (mhz) 60 40 50 20 30 10 0 amplitude (db) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in = 183.48565448mhz f sample = 125.0043232mhz a in = -0.982dbfs snr = 64.812db sinad = 63.424db sfdr = 70.001dbc hd2 = -79.233dbc hd3 = -70.001dbc 7 5 6 4 2 3 fft plot (16,384-point data record) MAX19541 toc04 analog input frequency (mhz) 3 4 6 7 60 40 50 20 30 10 0 amplitude (db) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in = 240.0977201mhz f sample = 125.0043232mhz a in = -1.001dbfs snr = 63.96db sinad = 62.798db sfdr = 70.011dbc hd2 = -70.011dbc hd3 = -78.367dbc 5 2 analog input frequency (mhz) 200 150 100 50 0250 snr/sinad vs. analog input frequency (f sample = 125.0043mhz, a in = -1dbfs) MAX19541 toc05 snr/sinad (db) 58 61 64 67 70 55 snr sinad sfdr (dbc) 45 50 55 60 65 70 75 80 85 90 40 analog input frequency (mhz) 200 150 100 50 0250 sfdr vs. analog input frequency (f sample = 125.0043mhz, a in = -1dbfs) MAX19541 toc06 hd2/hd3 (dbc) -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -110 analog input frequency (mhz) 200 150 100 50 0 250 hd2/hd3 vs. analog input frequency (f sample = 125.0043mhz, a in = -1dbfs) MAX19541 toc07 hd3 hd2 -95 -90 -85 -80 -70 -75 -65 -60 -100 thd (dbc) analog input frequency (mhz) 200 150 100 50 0250 thd vs. analog input frequency (f sample = 125.0043mhz, a in = -1dbfs) MAX19541 toc08 -5 -10 -15 -20 -25 38 44 50 56 62 68 32 -30 0 analog input amplitude (dbfs) snr/sinad vs. analog input amplitude (f sample = 125.0043mhz, f in = 60.0225mhz) MAX19541 toc09 snr/sinad (db) snr sinad typical operating characteristics (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 125mhz, a in = -1dbfs; see tocs for detailed information on test conditions, differential input drive, differential lvpecl clock input drive, 0.1? capacitor on refio, internal reference, digital outputs differential r l = 100 ? , t a = +25?.)
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications 6 _______________________________________________________________________________________ sfdr (dbc) 55 60 65 70 75 80 85 50 -5 -10 -15 -20 -25 -30 0 analog input amplitude (dbfs) sfdr vs. analog input amplitude (f sample = 125.0043mhz, f in = 60.0225mhz) MAX19541 toc10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -100 hd2/hd3 (dbc) -5 -10 -15 -20 -25 -30 0 analog input amplitude (dbfs) hd2/hd3 vs. analog input amplitude (f sample = 125.0043mhz, f in = 60.0225mhz) MAX19541 toc11 hd3 hd2 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -100 thd (dbc) -5 -10 -15 -20 -25 -30 0 analog input amplitude (dbfs) thd vs. analog input amplitude (f sample = 125.0043mhz, f in = 60.0225mhz) MAX19541 toc12 snr/sinad vs. f sample (f in = 60.0225mhz. a in = -1dbfs) MAX19541 toc13 f sample (mhz) snr/sinad (db) 180 160 40 60 80 120 100 140 61 62 63 64 65 66 67 68 60 20 200 snr sinad sfdr vs. f sample (f in = 60.0225mhz, a in = -1dbfs) MAX19541 toc14 f sample (mhz) sfdr (dbc) 180 160 40 60 80 120 100 140 55 60 65 70 75 80 85 90 50 20 200 hd2/hd3 vs. f sample (f in = 65.0225mhz, a in = -1dbfs) MAX19541 toc15 f sample (mhz) hd2/hd3 (dbc) 180 160 40 60 80 120 100 140 -100 -105 -95 -85 -90 -80 -75 -70 -65 -60 -55 -50 -110 20 200 hd3 hd2 thd vs. f sample (f in = 60.0225mhz, a in = -1dbfs) MAX19541 toc16 f sample (mhz) thd (dbc) 180 160 40 60 80 120 100 140 -85 -80 -75 -70 -65 -60 -90 20 200 two-tone imd plot (16,384-point data record) MAX19541toc17 analog input frequency (mhz) amplitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 f in1 = 150.0067138mhz f in2 = 152.9822805mhz f sample = 125.0043232mhz a in1 = a in2 = -7dbfs imd = - 75dbc f in2 f in1 2f in1 - f in2 2f in2 - f in1 60 40 50 20 30 10 0 inl vs. digital output code (512k-point data record) MAX19541 toc18 digital output code inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 f in = 13.0390862mhz typical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 125mhz, a in = -1dbfs; see tocs for detailed information on test conditions, differential input drive, differential lvpecl clock input drive, 0.1? capacitor on refio, internal reference, digital outputs differential r l = 100 ? , t a = +25?.)
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications _______________________________________________________________________________________ 7 dnl vs. digital output code (524k-point data record) MAX19541 toc19 digital output code dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 04096 f in = 13.0390862mhz gain bandwidth plot (f sample = 125.0043232mhz, a in = -1dbfs) MAX19541 toc20 analog input frequency (mhz) gain (db) 100 -6 -5 -4 -3 -2 -1 0 1 -7 1 10 1000 snr/sinad vs. temperature (f sample = 125mhz, a in = -2dbfs) MAX19541 toc21 temperature ( c) snr/sinad (db) 60 35 10 -15 62 63 64 65 66 67 61 -40 85 f in = 100mhz snr sinad sfdr vs. temperature (f sample = 125mhz, a in = -2dbfs) MAX19541 toc22 temperature ( c) sfdr (dbc) 60 35 10 -15 70 69 71 73 72 75 74 76 77 78 68 -40 85 f in = 100mhz total power dissipation vs. f sample (f in = 60mhz, a in = -1dbfs) MAX19541 toc23 f sample (mhz) p diss (w) 160 140 40 60 80 100 120 0.78 0.80 0.82 0.84 0.86 0.88 0.90 0.92 0.76 20 180 200 full-scale adjustment range vs. adjustment resistance MAX19541 toc24 r adj (k ? ) ifull-scale voltage (v) 800 600 400 200 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.14 0 1000 r adj between refadj and refio r adj between refadj and gnd 1.12 100 300 500 700 900 snr/sinad vs. supply voltage (f in = 60.0225mhz, a in = -1dbfs) MAX19541 toc25 supply voltage (v) snr/sinad (db) 2.0 1.9 1.8 1.7 60 62 64 66 68 58 1.6 2.1 av cc = ov cc snr sinad internal reference vs. supply voltage MAX19541 toc26 supply voltage (v) v refio (v) 2.0 1.9 1.8 1.7 1.245 1.244 1.243 1.242 1.241 1.246 1.240 1.6 2.1 typical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 125mhz, a in = -1dbfs; see tocs for detailed information on test conditions, differential input drive, differential lvpecl clock input drive, 0.1? capacitor on refio, internal reference, digital outputs differential r l = 100 ? , t a = +25?.)
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications 8 _______________________________________________________________________________________ pin description pin name function 1, 6, 11?4, 20, 25, 62, 63, 65 av cc analog supply voltage. bypass each av cc pin with a 0.1? capacitor for best decoupling results. additional board decoupling might be required. see the grounding, bypassing, and layout considerations section. 2, 5, 7, 10, 18, 19, 21, 24, 64, 66 agnd analog converter ground. connect the converter? exposed paddle (ep) to agnd. 3 refio reference input/output. drive refadj high to allow an external reference source to be connected to the MAX19541. drive refadj low to activate the internal 1.23v bandgap reference. connect a 0.1? capacitor from refio to agnd. 4 refadj reference adjust input. refadj allows for full-scale range adjustments by placing a resistor or trim potentiometer between refadj and agnd (decreases fs range) or refadj and refio (increases fs range). if refadj is connected to av cc , the internal reference can be overdriven with an external source connected to refio. if refadj is connected to agnd, the internal reference is used to determine the full-scale range of the data converter. 8 inp positive analog input terminal 9 inn negative analog input terminal 15 reset active-high reset input. reset controls the latency of the MAX19541. reset has an internal pulldown resistor. see the reset operation section. 16 demux output-mode-select input. drive demux low for the parallel output mode (full-rate cmos outputs on a ports only). drive demux high for the demux parallel or demux interleaved modes (half-rate outputs on both ports a and b) depending on the state of the itl input. see the modes of operation section. 17 clkdiv clock-divider input. clkdiv is an lvcmos-compatible input that controls the sampling frequency relative to the input clock frequency. clkdiv has an internal pulldown resistor: clkdiv = 0: sampling frequency is 1/2 the input clock frequency. clkdiv = 1: sampling frequency is equal to the input clock frequency. 22 clkn complementary clock input. clkn ideally requires an lvpecl-compatible input level to maintain the converter? excellent performance. 23 clkp true clock input. clkp ideally requires an lvpecl-compatible input level to maintain the converter? excellent performance. 26, 45, 61 ognd digital converter ground. ground connection for digital circuitry and output drivers. 27, 28, 41, 44, 60 ov cc d i g i tal s up p l y v ol tag e. byp ass o v c c w i th a 0.1? cap aci tor for b est d ecoup l i ng r esul ts. ad d i ti onal b oar d d ecoup l i ng m i g ht b e r eq ui r ed . s ee the g r ound i ng , byp assi ng , and layout c onsi d er ati ons secti on. 29 db0 port b cmos digital output bit 0 (lsb) 30 db1 port b cmos digital output bit 1 31 db2 port b cmos digital output bit 2 32 db3 port b cmos digital output bit 3 33 db4 port b cmos digital output bit 4 34 db5 port b cmos digital output bit 5 35 db6 port b cmos digital output bit 6 36 db7 port b cmos digital output bit 7 37 db8 port b cmos digital output bit 8
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications _______________________________________________________________________________________ 9 pin description (continued) pin name function 38 db9 port b cmos digital output bit 9 39 db10 port b cmos digital output bit 10 40 db11 port b cmos digital output bit 11 (msb) 42 dclkn inverted cmos digital clock output. dclkn provides a cmos-compatible output level and can be used to synchronize external devices to the converter clock. when demux is high, the frequency at dclkn is half the sampling clock? frequency. 43 dclkp true cmos digital clock output. dclkp provides a cmos-compatible output level and can be used to synchronize external devices to the converter clock. when demux is high, the frequency at dclkp is half the sampling clock? frequency. 46 orb port b cmos digital output overrange 47 da0 port a cmos digital output bit 0 (lsb) 48 da1 port a cmos digital output bit 1 49 da2 port a cmos digital output bit 2 50 da3 port a cmos digital output bit 3 51 da4 port a cmos digital output bit 4 52 da5 port a cmos digital output bit 5 53 da6 port a cmos digital output bit 6 54 da7 port a cmos digital output bit 7 55 da8 port a cmos digital output bit 8 56 da9 port a cmos digital output bit 9 57 da10 port a cmos digital output bit 10 58 da11 port a cmos digital output bit 11 (msb) 59 ora port a cmos digital output overrange 67 itl interleaved/parallel-select input. drive itl low for the demux parallel mode. drive itl high for the demux interleaved mode. 68 t /b output-format-select input. t /b is an lvcmos-compatible input that controls the digital output format of the MAX19541. t /b has an internal pulldown resistor: t /b = 1: binary output format. t /b = 0: two?-complement output format. ep agnd exposed paddle. connect ep to the analog ground (agnd) for optimum performance. the exposed paddle is located on the backside of the chip. ep is internally connected to the die substrate.
MAX19541 detailed description theory of operation the MAX19541 uses a fully differential, pipelined archi- tecture that allows for high-speed conversion, opti- mized accuracy and linearity, while minimizing power consumption. both positive (inp) and negative/comple- mentary analog input terminals (inn) are centered around a 1.365v common-mode voltage, and accept a ?50mv differential analog input voltage swing each, resulting in a typical 1.41v p-p differential full-scale sig- nal swing. inputs inp and inn are buffered prior to entering each track-and-hold (t/h) stage and are sampled when the differential sampling clock signal transitions high. the adc following the first t/h stage then digitizes the sig- nal, and controls a digital-to-analog converter (dac). digitized and reference signals are then subtracted, resulting in a fractional residue signal that is amplified before it is passed on to the next stage through another t/h amplifier. this process is repeated until the applied input signal has successfully passed through all stages of the 12-bit quantizer. finally, the digital outputs of all stages are combined and corrected for in the digital correction logic to generate the final output code. the result is a 12-bit parallel digital output word in user- selectable two? complement or binary output formats with cmos-compatible output levels. see the functional diagram (figure 1) for a more detailed view of the MAX19541? architecture. 12-bit, 125msps adc with cmos outputs for wideband applications 10 ______________________________________________________________________________________ MAX19541 clock- divider control clkdiv clock management dclkp da0?a11, ora db0?b11, orb dclkn 12 bits 12 bits demux itl 2.15k ? 2.15k ? clkp clkn inp inn cm buffer refio refadj cmos data ports clk generator reference t/h 12-bit pipeline quantizer core reset buffer figure 1. MAX19541 functional diagram
analog inputs (inp, inn) inp and inn are the fully differential inputs of the MAX19541. differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced ac performance as the signals are pro- gressing through the analog stages. the MAX19541 analog inputs are self-biased at a 1.365v common- mode voltage and allow a 1.41v p-p differential input voltage swing. both inputs are self-biased through 2.15k ? resistors, resulting in a typical differential input resistance of 4.3k ? (figure 2). it is recommended dri- ving the analog inputs of the MAX19541 in an ac-cou- pled configuration to achieve the best dynamic performance. see the transformer-coupled, differential analog input drive section for a detailed discussion of this configuration. on-chip reference circuit the MAX19541 features an internal 1.24v bandgap ref- erence circuit (figure 3), which, in combination with an internal reference-scaling amplifier, determine the full- scale range of the MAX19541. bypass refio with a 0.1? capacitor to agnd. to compensate for gain errors or increase the adc? full-scale range, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100k ? trim potentiometer) between refadj and agnd or refadj and refio. see figure 8 and the applications information section for a detailed description of this process. clock inputs (clkp, clkn) drive the clock inputs of the MAX19541 differentially with an lvpecl-compatible clock to achieve the best dynamic performance. the clock signal source must be high-quali- ty, low phase noise to avoid any degradation in the noise performance of the adc. the clock inputs (clkp, clkn) are internally biased to typically 1.15v, accept a typical 0.5v p-p differential signal swing, and are usually driven in an ac-coupled configuration. see the differential, ac- coupled clock input section for more circuit details on how to drive clkp and clkn appropriately. the MAX19541 features an internal clock-management circuit (duty-cycle equalizer). the clock-management circuit ensures that the clock signal applied to inputs clkp and clkn is processed to provide a near 50% duty-cycle clock signal. this desensitizes the perfor- mance of the converter to variations in the duty cycle of the input clock source. note that the clock duty-cycle equalizer cannot be turned off externally. clock outputs (dclkp, dclkn) the MAX19541 features cmos-complementary clock outputs (dclkp, dclkn) to latch the digital output data with an external latch or receiver. additionally, the clock outputs can be used to synchronize external devices (e.g., fpgas) to the adc. there is a 2.1ns delay time between the rising (falling) edge of clkp (clkn) and the rising (falling) edge of dclkp (dclkn). see figure 4 for timing details. MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications ______________________________________________________________________________________ 11 2.15k ? inp 2.15k ? agnd inn to common-mode input to common-mode input av cc figure 2. simplified analog input architecture MAX19541 reference buffer adc full scale = reft - refb 1v av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refio refadj* 0.1 f *refadj can be shorted to agnd through a 1k ? resistor or potentiometer. reft refb figure 3. simplified reference architecture
MAX19541 divide-by-two clock control (clkdiv) the MAX19541 offers a clock control line (clkdiv) that allows the reduction of clock jitter and phase noise in a system as higher frequency oscillators usually exhibit better phase noise and jitter characteristics. connect clkdiv to ognd to enable the adc? internal divide- by-2 clock divider, which allows the user to use an oscillator of twice the maximum sampling frequency. the sampling frequency now becomes 1/2 of the input clock frequency. clkdiv has an internal pulldown resistor and can be left open for applications that require this divide-by-2 mode. connecting clkdiv to ov cc disables the divide-by-2 mode. reset operation the reset input defines the pipeline latency of the MAX19541. drive reset high to place the MAX19541 in reset mode with the cmos outputs tri-stated. during the time when reset is high, no sample information is available at the outputs. for pipeline latency, the first sample is defined at the first rising edge of clkp after reset goes low. the conversion information is avail- able at the outputs after 11 clock cycles. synchronize reset with the input clock of the device by observing the minimum reset hold (t hr ) and reset setup (t sr ) times (figure 4). reset is only used to control the latency of the device and, in applications where this is not critical, drive reset low or leave unconnected. reset has an internal pulldown resistor. 12-bit, 125msps adc with cmos outputs for wideband applications 12 ______________________________________________________________________________________ clkn clkp reset n + 1 n + 11 n + 12 n t ad t sr t hr sampling event sampling event sampling event sampling event inn inp t cl t ch figure 4. reset timing diagram
system timing requirements figures 5, 6, and 7 depict the relationship between the clock input and output, analog input, sampling event, and data output. the MAX19541 samples on the rising (falling) edge of clkp (clkn). in all these figures, clkdiv is assumed to be high; otherwise, the sampling events would occur at every other rising edge of clkp. output data is latched on the next rising (falling) edge of the dclkp (dclkn) clock, but has an internal laten- cy of 11 input clock cycles. modes of operation the MAX19541 features three modes of operation. in each mode of operation, the conversion data is output in a different format. parallel mode drive demux low to place the MAX19541 in the parallel mode. in this mode, the output clock has the same fre- quency as the sampling frequency and conversion data is output at full rate on parallel ports da0?a11. note that the sampling frequency may not be the same as the input clock frequency. see the divide-by-two clock control (clkdiv) section. in parallel mode, sam- ples are taken on the rising edge of clkp. conversion data appears at the outputs on the rising edge of dclkp after the latency period of 11 clock cycles and is stable for one clock period (figure 5). if an overrange condition occurs, it is reflected on the ora port. MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications ______________________________________________________________________________________ 13 figure 5. parallel mode timing diagram t pdl t cpdl t latency clkn clkp reset dclkn dclkp da0?a11, ora n + 1 n + 11 n + 12 n + 1 n + 1 n - 10 n - 11 n n n t ad sampling event sampling event sampling event sampling event sampling event inn inp t cl t ch n - 11 n - 10 n - 1
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications 14 ______________________________________________________________________________________ t pdl t cpdl t latency sampling event sampling event sampling event sampling event sampling event sampling event inn inp clkn clkp reset dclkn dclkp da0?a11, ora n + 12 n + 1 n + 3 n n n + 2 n + 2 n db0?b11, orb demux parallel mode t cl t ch t ad figure 6. demux parallel mode timing diagram demux parallel mode drive demux high and itl low to place the MAX19541 in the demux parallel mode. in this mode, the output clock? frequency is 1/2 the sampling frequency. the sampling frequency may not be the same as the input clock frequency. see the divide-by-two clock control (clkdiv) section. each conversion starts with a sam- pling event on the rising edge of clkp. conversion data now appears on both da0?a11 and db0?b11. the first conversion result is output on the a ports on the rising edge of dclkp after 12 input clock cycles from the initial sampling event. the second conversion result is output on the b ports on the rising edge of dclkp after 11 input clock cycles from the initial sam- pling event. both conversion results are output simulta- neously (figure 6). the conversion results on ports a and b remain stable for one period of dclkp after they become valid. thus, the overall throughput rate is the same as in parallel mode; however, now each data line is allowed to be valid for a longer time (two sampling periods, one digital clock period). overrange condi- tions are reflected on the appropriate output port, ora or orb, depending on which conversion they occur.
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications ______________________________________________________________________________________ 15 figure 7. demux interleaved mode timing diagram demux interleaved mode drive demux high and itl high to place the MAX19541 in the demux interleaved mode of operation. in this mode, the output clock? frequency is 1/2 the sampling frequency. the sampling frequency may not be the same as the input clock frequency. see the divide-by- two clock control (clkdiv) section. each conversion starts with a sampling event on the rising edge of clkp. conversion data now appears on both da0?a11 and db0?b11. the first conversion result is output on the a ports on the rising edge of dclkp after 12 input clock cycles from the initial sampling event. the second conversion result is output on the b ports on the rising edge of dclkn after 12 input clock cycles from the initial sampling event. in this way, the two conversion results are interleaved with respect to each other (figure 7). the conversion results on ports a and b remain stable for one period of dclkp and dclkn, respectively, after they become valid. overrange conditions are reflected on the appropriate output port, ora or orb, depending on which conver- sion they occur. the demux interleaved mode is the recommended demux mode of operation due to the fact that output bus switching is more evenly distributed over sample clock edges. demux interleaved mode t pdl t cpdl t latency sampling event sampling event sampling event sampling event sampling event sampling event inn inp clkn clkp reset dclkn dclkp da0?a11, ora n + 12 n + 1 n + 3 n n n + 2 n + 2 n db0?b11, orb t cl t ch t ad
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications 16 ______________________________________________________________________________________ table 1. MAX19541 digital output coding inp analog input voltage level inn analog input voltage level overrange ora/orb binary digital output code (d_11?_0) two?-complement digital output code (d_11?_0) > v ref + 0.35v < v ref - 0.35v 1 1111 1111 1111 (exceeds +fs, or set) 0111 1111 1111 (exceeds +fs, or set) v ref + 0.35v v ref - 0.35v 0 1111 1111 1111 (+fs) 0111 1111 1111 (+fs) v ref v ref 0 1000 0000 0000 or 0111 1111 1111 (fs/2) 0000 0000 0000 or 1111 1111 1111 (fs/2) v ref - 0.35v v ref + 0.35v 0 0000 0000 0000 (-fs) 1000 0000 0000 (-fs) < v ref + 0.35v > v ref - 0.35v 1 00 0000 0000 (exceeds -fs, or set) 10 0000 0000 (exceeds -fs, or set) digital outputs (da0?a11, dclkp, dclkn, ora, db0?b11, orb) and control input t /b digital outputs da0/db0?a11/db11, dclkp, dclkn, ora/orb are cmos compatible, and data on da0/db da11/db11 are presented in either binary or two?- complement format (table 1). the t /b control line is an lvcmos-compatible input that allows the user to select the desired output format. drive t /b high to select data to be output in offset binary format and drive it low to select data to be output in two? complement format on the 12-bit parallel bus. t /b has an internal pulldown resistor and can be left unconnected in applications using only two?-complement output format. the cmos outputs are powered from a separate power supply that can be operated between 1.7v and 1.9v. the MAX19541 offers an additional differential output pair (ora, orb) to flag overrange conditions, where overrange is above positive or below negative full scale. an overrange condition is identified with ora/orb tran- sitioning high. note: keep the capacitive load on the digital outputs as low as possible. use digital buffers on the digital out- puts of the adc when driving larger loads to improve overall performance and reduce system timing con- straints. further improvements in dynamic performance can be achieved by adding small series resistors (100 ? ) to the digital output paths, close to the adc.
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications ______________________________________________________________________________________ 17 MAX19541 reference buffer adc full scale = reft - refb 1v av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refio refadj 13k ? to 100k ? 0.1 f reft refb MAX19541 reference buffer adc full scale = reft - refb 1v av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refio refadj 0.1 f 13k ? to 100k ? reft refb figure 8. circuit suggestions to adjust the adc? full-scale range (simplified schematic) applications information full-scale range adjustments using the internal bandgap reference the MAX19541 supports a full-scale adjustment range of ?0%. to decrease the full-scale range, an external resistor value ranging from 13k ? to 1m ? can be added between refadj and agnd. a similar approach can be taken to increase the adcs full-scale range. add a variable resistor, potentiometer, or predetermined resis- tor value between refadj and refio to increase the full-scale range of the data converter. figure 8 shows the two possible configurations and their impact on the overall full-scale range adjustment of the MAX19541. do not use resistor values of less than 13k ? to avoid instability of the internal gain regulation loop for the bandgap reference. use the following formula to calcu- late the percentage change of the reference voltage: the percentage change is positive when r adj is added between refadj and refio, and is negative when r adj is added between refadj and gnd. vx k r ref adj (%) . % = 125 100 ?
MAX19541 differential, ac-coupled, lvpecl- compatible clock input the MAX19541 dynamic performance depends on a very clean clock source. the phase noise floor of the clock source has a negative impact on the snr perfor- mance. spurious signals on the clock signal source also affect the adc? dynamic range. the preferred method of clocking the MAX19541 is differentially with lvpecl- compatible input levels. the fast data transition rates of these logic families minimize the clock-input circuitry? transition uncertainty, thereby improving the snr perfor- mance. apply a 50 ? reverse-terminated clock signal source with low phase noise ac-coupled into a fast dif- ferential receiver such as the mc100lvel16 (figure 9). the receiver produces the necessary lvpecl output levels to drive the clock inputs of the data converter. transformer-coupled, differential analog input drive the MAX19541 provides the best sfdr and thd with fully differential input signals and it is not recommended driving the adc inputs in single-ended configuration. in differential input mode, even-order harmonics are usu- ally lower since inp and inn are balanced, and each of the adc inputs requires only half the signal swing com- pared to a single-ended configuration. wideband rf transformers provide an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX19541 for optimum dynamic per- formance. a secondary-side termination of a 1:1 transformer (e.g., mini-circuit? adt1-1wt) into two separate 24.9 ? ?.1% resistors (use tight resistor tolerances to mini- mize effects of imbalance; 0.1% would be an ideal choice) placed between top/bottom and center tap of the transformer is recommended to maximize the adc? dynamic range. this configuration optimizes thd and sfdr performance of the adc by reducing the effects of transformer parasitics. however, the source impedance combined with the shunt capaci- tance provided by a pc board and the adc? parasitic capacitance limit the adc? full-power input bandwidth to approximately 600mhz. to further enhance thd and sfdr performance at high input frequencies (>100mhz), a second transformer (figure 10) should be placed in series with the single- ended-to-differential conversion transformer. this trans- former reduces the increase of even-order harmonics at high frequencies. for more detailed information on transformer termina- tion methods, refer to the application note: secondary- side transformer termination improves gain flatness in high-speed adcs from the maxim website: www.maxim-ic.com. 12-bit, 125msps adc with cmos outputs for wideband applications 18 ______________________________________________________________________________________ mc100lvel16 vgnd agnd ognd d_0?_11, or_ av cc v clk 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f single-ended input terminal 150 ? 150 ? clkp clkn ov cc 12 2 8 45 7 6 3 50 ? 510 ? 510 ? MAX19541 inp inn figure 9. differential, ac-coupled, lvpecl-compatible clock input configuration
single-ended, ac-coupled analog input although not recommended, the MAX19541 can be used in single-ended mode (figure 11). analog signals can be ac-coupled to the positive input inp through a 0.1? capacitor and terminated with a 49.9 ? resistor to agnd. terminate the negative input with a 24.9 ? resis- tor and ac ground it with a 0.1? capacitor. grounding, bypassing, and board layout considerations the MAX19541 requires board layout design tech- niques suitable for high-speed data converters. this adc provides separate analog and digital power sup- plies. the analog and digital supply voltage inputs av cc and ov cc accept 1.7v to 1.9v input voltage ranges. although both supply types can be combined and supplied from one source, it is recommended using separate sources to cut down on performance degradation caused by digital switching currents that can couple into the analog supply network. isolate ana- log and digital supplies (av cc and ov cc ) where they enter the pc board with separate networks of ferrite beads and capacitors to their corresponding grounds (agnd, ognd). to achieve optimum performance, provide each supply with a separate network of a 47? tantalum capacitor in parallel with 10? and 1? ceramic capacitors. additionally, the adc requires each supply pin to be bypassed with separate 0.1? ceramic capacitors (figure 12). locate these capacitors directly at the adc supply pins or as close as possible to the MAX19541. choose surface-mount capacitors, whose preferred location should be on the same side as the converter, to save space and minimize the inductance. if close placement on the same side is not possible, these bypassing capacitors may be routed through vias to the bottom side of the pc board. multilayer boards with separated ground and power planes produce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the adc? package. the two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. a major concern with this approach are the dynamic currents that may need to travel long dis- tances before they are recombined at a common source ground, resulting in large and undesirable MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications ______________________________________________________________________________________ 19 agnd ognd d_0?_11, or_ av cc inp 50 ? 25 ? inn ov cc 12 MAX19541 0.1 f single-ended input terminal 0.1 f figure 11. single-ended ac-coupled analog input configuration agnd ognd d_0?_11, or_ av cc inp inn ov cc 12 MAX19541 0.1 f 25 ? 25 ? 0.1 f adt1-1wt adt1-1wt 10 ? 10 ? single-ended input terminal figure 10. analog input configuration with back-to-back transformers and secondary-side termination
MAX19541 ground loops. ground loops can add to digital noise by coupling back to the analog front end of the converter, resulting in increased spur activity and a decreased noise performance. alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground. to minimize the effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sec- tions of the adc. this does not require additional ground splitting, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. the MAX19541 is packaged in a 68-pin qfn-ep pack- age (package code: g6800-4), providing greater design flexibility, increased thermal dissipation, and optimized ac performance of the adc. the ep must be soldered down to agnd. in this package, the data converter die is attached to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pc board side of the package. this allows a solid attachment of the package to the board with standard infrared (ir) flow-soldering techniques. thermal efficiency is one of the factors for the selection of a package with an exposed pad for the MAX19541. the exposed pad improves thermal dissipation and ensures a solid ground connection between the adc and the pc board? analog ground layer. take considerable care when routing the digital output traces for a high-speed, high-resolution data converter. it is essential to keep trace lengths at a minimum and place minimal capacitive loading?ess than 5pf?n any digital trace to prevent coupling to sensitive analog sections of the adc. route high-speed digital signal traces away from sensitive analog traces, and remove digital ground and power planes from underneath digital outputs. keep all signal lines short and free of 90 turns. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. however, the static linearity parameters for the MAX19541 are mea- sured using the histogram method with a 10mhz input frequency. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. the MAX19541? dnl specification is measured with the histogram method based on a 10mhz input tone. 12-bit, 125msps adc with cmos outputs for wideband applications 20 ______________________________________________________________________________________ agnd note: each power-supply pin (analog and digital) should be decoupled with an individual 0.1 f capacitor as close as possible to the adc. bypassing-adc level bypassing-board level analog power- supply source ognd d_0?_11, or_ 1 f 10 f 0.1 f 0.1 f 47 f av cc ov cc 12 MAX19541 av cc digital/output driver power- supply source 1 f 10 f47 f ov cc figure 12. grounding, bypassing, and decoupling recommendations for the MAX19541
dynamic parameter definitions aperture jitter figure 13 depicts the aperture jitter (t aj ), which defines the sample-to-sample variation in the aperture delay. aperture jitter is measured in ps rms . aperture delay aperture delay (t ad ) is the time defined between the 620ps rising edge of the sampling clock and the instant when an actual sample is taken (figure 13). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the snr calcula- tion and should be considered when determining the snr of an adc. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components excluding the fundamen- tal and the dc offset. in the case of the MAX19541, sinad is computed from a curve fit. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal component) to the rms value of the next-largest noise or harmonic distortion compo- nent. sfdr is usually measured in dbc with respect to the carrier frequency amplitude or in dbfs with respect to the adc? full-scale range. two-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 2nd-order (or higher) inter- modulation products. the individual input tone levels are usually set to 7db below full scale and intermodula- tion products im2 through im5 are considered for the imd calculation. the various intermodulation products are defined as follows: ? 2nd-order intermodulation distortion (im2): f in1 + f in2 , f in2 - f in1 ? 3rd-order intermodulation distortion (im3): 2f in1 + f in2 , 2f in1 - f in2 , 2f in2 + f in1 , 2f in2 - f in1 ? 4th-order intermodulation distortion (im4): 3f in1 + f in2 , 3f in1 - f in2 , 3f in2 + f in1 , 3f in2 - f in1 ? 5th-order intermodulation distortion (im5): 4f in1 + f in2 , 4f in1 - f in2 , 4f in2 + f in1 , 4f in2 - f in1 full-power bandwidth a large -1dbfs analog input signal is applied to an adc and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. the -3db point is defined as the full-power input bandwidth frequency of the adc. MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications ______________________________________________________________________________________ 21 hold analog input sampled data (t/h) t/h t ad t aj track track clkp clkn figure 13. aperture jitter/delay specifications
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications 22 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm
MAX19541 12-bit, 125msps adc with cmos outputs for wideband applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm

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