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? freescale semiconductor, inc., 2005. all rights reserved. MPC92433 rev 2, 06/2005 freescale semiconductor technical data 1428 mhz dual output lvpecl clock synthesizer the MPC92433 is a 3.3 v compatible, pll based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. with output frequencies from 42.50 mhz to 1428 mhz and the support of two differential pecl output signals, the device meets the needs of the most demanding clock applications. features ? 42.50 mhz to 1428 mhz synthesized clock output signal ? two differential, lvpecl-compatible high-frequency outputs ? output frequency programmable through 2-wire i2c bus or parallel interface ? on-chip crystal oscillator for reference frequency generation ? alternative lvcmos compatible reference clock input ? synchronous clock stop functionality for both outputs ? lock indicator output (lvcmos) ? lvcmos compatible control inputs ? fully integrated pll ? 3.3 v power supply ? 48-lead lqfp ? 48-lead pb-free package available ? sige technology ? ambient temperature range: ?40c to +85c typical applications ? programmable clock source for server, computing, and telecommunication systems ? frequency margining ? oscillator replacement the MPC92433 is a programmable high-frequency clock source (clock synthesizer). the internal pll generates a high- frequency output signal based on a low-frequency reference signal. the frequency of the output signal is programmable and can be changed on the fly for frequency margining purposes. the internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. alternatively, a lvc mos compatible clock signal can be used as a pll reference signal. the frequency of the internal crystal oscillator is divided by a selectable divider and then multiplied by the pll. the vco within the pll operates over a range of 1360 to 2856 mhz. its output is scaled by a divider that is configured by either the i 2 c or parallel interfaces. the crystal oscillator frequency fxtal, the pll pre-divider p, the feedback-divider m, and the pll post-divider n determine the output frequency. the feedback path of the pll is internal. the pll post-divider n is configured through either the i 2 c or the parallel interfaces, and can provide one of seven division ratios (2, 4, 6, 8, 12, 16, 32). this divider extends the performance of the part while providing a 50 ? duty cycle. the high- frequency outputs, q a and q b , are differential and are capable of driving a pair of transmission lines terminated 50 ? to v cc ? 2.0 v. the second high-frequency output, q b , can be configured to run at either 1x or 1/2x of the clock frequency or the first output (q a ). the positive supply voltage for the internal pll is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. the configuration logic has two sections: i 2 c and parallel. the parallel interface uses the values at the m[9:0], na[2:0], nb, and p parallel inputs to configure the internal pll dividers. the parallel programming interface has priority over the serial i 2 c interface. the serial interface is i 2 c compatible and provides read and write access to the internal pll configuration registers. the lock state of the pll is indicated by the lvcmos-compatible lock output. 1. fa suffix: leaded terminations. 2. ae suffix: lead-free, epp and rohs-compliant. MPC92433 1428 mhz low voltage clock synthesizer fa suffix (1) 48-lead lqfp package case 932-03 ae suffix (2) 48-lead lqfp package pb-free package case 932-03
advanced clock drivers devices 2 freescale semiconductor MPC92433 figure 1. MPC92433?generic logic diagram figure 2. 48-lead package pinout (top view ) p xtal pll nb na m f ref f vco f qa f qb ref_clk xtal1 xtal2 ref_sel test_en sda scl adr[1:0] pload m[9:0] na[2:0] nb p clk_stopx bypass mr qa qb lock pll configuration registers i 2 c control it is recommended to use an external rc filter for the analog v cc_pll supply pin. please see the application section for details. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 3 4 5 6 7 8 9 101112 37 38 39 40 41 42 43 44 45 46 47 48 MPC92433 m9 m8 m7 m6 m5 gnd m4 m3 m2 m1 m0 v cc gnd na2 na1 na0 pload v cc mr sda scl adr1 adr0 p v cc nb v cc qa qa gnd v cc qb qb gnd lock test_en v cc bypass gnd v cc v cc_pll ref_sel ref_clk gnd clk_stopa clk_stopb xtal1 xtal2
advanced clock drivers devices freescale semiconductor 3 MPC92433 table 1. signal configuration pin i/o type function xtal1, xtal2 input analog crystal oscillator interface ref_clk input lvcmos pll external reference input ref_sel input lvcmos selects the reference clock input qa output differential lvpecl high frequency clock output qb output differential lvpecl high frequency clock output lock output lvcmos pll lock indicator m[9:0] input lvcmos pll feedback divider configuration na[2:0] input lvcmos pll post-divider configuration for output qa nb input lvcmos pll post-divider configuration for output qb p input lvcmos pll pre-divider configuration p_load input lvcmos selects the programming interface sda i/o lvcmos i 2 c data scl input lvcmos i 2 c clock adr[1:0] input lvcmos selectable two bits of the i 2 c slave address bypass input lvcmos selects the static circuit bypass mode test_en input lvcmos factory test mode enable. this input must be set to logic low level in all applications of the device. clk_stopx input lvcmos output qx disable in logic low state mr input lvcmos device master reset gnd supply ground negative power supply v cc_pll supply v cc positive power supply for the pll (analog power supply). it is recommended to use an external rc filter for the analog power supply pin v cc_pll . v cc supply v cc positive power supply for i/o and core
advanced clock drivers devices 4 freescale semiconductor MPC92433 table 2. function table control default (1) 1. default states are set by internal i nput pull-up or pull-down resistors of 75 k ?. 01 inputs ref_sel 1 selects ref_clk input as pll reference cl ock selects the xtal interface as pll reference clock m[9:0] 01 1111 0100b (2) 2. if f ref = 16 mhz, the default configuration will result in an output frequency of 250 mhz. pll feedback divider (10-bit) parallel programming interface na[2:0] 010 pll post-divider paralle l programming interface. see table 9 nb 0 pll post-divider parallel pr ogramming interface. see table 9 p 1 pll pre-divider parallel programming interface. see table 8 pload 0 selects the parallel programming interface. the internal pll divider settings (m, na, nb and p) are equal to the setting of the hardware pins. leaving the m, na, nb and p pins open (floating) results in a default pll configuration with f out = 250 mhz. see application/programming section. selects the serial (i 2 c) programming interface. the internal pll divider settings (m, na, nb and p) are set and read through the serial interface. adr[1:0] 00 address bit = 0 address bit = 1 sda, scl see programming the MPC92433 bypass 1 pll function bypassed f qa =f ref n a and f qb =f ref (n a n b ) pll function enabled f qa = (f ref p) m n a and f qb = (f ref p) m (n a n b ) test_en 0 application mode. test mode disabled. factory test mode is enabled clk_stopx 1 output q x is disabled in logic low state. synchronous disable is only guaranteed if nb = 0. output q x is synchronously enabled mr the device is reset. the output frequency is zero and the outputs are asynchronously forced to logic low state. after releasing reset (upon the rising edge of mr and independent on the state of pload ), the MPC92433 reads the parallel interface (m, na, nb and p) to acquire a valid startup frequency configuration. see application/programming section. the pll attempts to lock to the reference signal. the t lock specification applies. outputs lock pll is not locked pll is frequency locked
advanced clock drivers devices freescale semiconductor 5 MPC92433 table 3. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c in input capacitance 4.0 pf inputs ja lqfp 48 thermal resistance junction to ambient jesd 51-3, single layer test board jesd 51-6, 2s2p multilayer test board 69 64 53 50 c/w c/w c/w c/w natural convection 200 ft/min natural convection 200 ft/min jc lqfp 48 thermal resistance junction to case tbd tbd c/w mil-spec 883e method 1012.1 table 4. absolute maximum ratings (1) symbol characteristics min max unit condition v cc supply voltage ?0.3 3.9 v v in dc input voltage (2) ?0.3 v cc + 0.3 v v out dc output voltage ?0.3 v cc + 0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature ?65 125 c 1. absolute maximum continuous ratings are those maximum val ues beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicat ed may adversely affect device reliability. functional operation at absolute-maxim um-rated conditions is not implied. 2. all input pins including sda and scl pins.
advanced clock drivers devices 6 freescale semiconductor MPC92433 table 5. dc characteristics (v cc = 3.3 v 5%, t j = ?40c to +85c) symbol characteristics min typ max unit condition lvcmos control inputs (m[9:0], n[2:0], addr[1:0], nb, p, clk_stopx , bypass , mr , ref_sel, test_en, pload ) v ih input high voltage 2.0 ? v cc + 0.3 v lvcmos v il input low voltage ? ? 0.8 v lvcmos i in input current (1) ? ? 200 a v in = v cc or gnd i 2 c inputs (scl, sda) v ih input high voltage 2.0 ? v cc + 0.3 v lvcmos v il input low voltage ? ? 0.8 v lvcmos i in input current ? ? 10 a lvcmos output (lock) v oh output high voltage 2.4 ? ? v i oh = ?4 ma v ol output low voltage ? ? 0.4 v i ol = 4 ma i 2 c open-drain output (sda) v ol input low voltage ? ? 0.4 v i ol = 4 ma differential clock output qa, qb (2) v oh output high voltage v cc ? 1.05 ? v cc ? 0.74 v lvpecl v ol output low voltage v cc ? 1.95 ? v cc ? 1.60 v lvpecl v o(p-p) output peak-to-peak voltage 0.5 0.6 1.0 v supply current i cc_pll maximum pll supply current ? ? 10 ma v cc_pll pins i cc maximum supply current ? ? 150 ma all v cc pins 1. inputs have pull-down resistors affecting the input current. 2. outputs terminated 50 ? to v tt = v cc ? 2 v.
advanced clock drivers devices freescale semiconductor 7 MPC92433 table 6. ac characteristics (v cc = 3.3 v 5%, t j = ?40c to +85c (1) (2) 1. ac specifications are subject to change. 2. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f xtal crystal interface frequency range 15 16 20 mhz f ref fref_ext reference frequency range 15 20 mhz f vco vco frequency range (3) 3. the input frequency f xtal , the pll divider m and p must match the vco frequency range: f vco = f xtal m p. the feedback divider m is limited to 170 <= m <= 357 (for p=2) and 340 <= m <= 714 (for p=4) for stable pll operation. 1360 2856 mhz f max output frequency (4) n= 2 n= 4 n= 6 n= 8 n= 12 n= 16 n= 32 4. output frequency for q a , q b if n b =0. with n b =1 the q b output frequency is half of the q a output frequency. 680 340 226.67 170 113.30 178.50 42.50 1428 714 476 357 238 178.50 89.25 mhz mhz mhz mhz mhz mhz mhz f scl serial interface (i 2 c) clock frequency 0 0.4 mhz t p,min minimum pulse width (p_load )50 ns dc output duty cycle 45 50 55 % t sk(o) output-to-output skew nb=0 (f qa = f qb ) nb=1 (f qa = 2 f qb ) 38 96 ps ps t r , t f output rise/fall time (qa, qb) 0.05 0.3 ns 20% to 80% t r , t f output rise/fall time (sda) 250 ns c l = 400 pf t p_en output enable time (clkstopx to qa, qb) 0 2 t qx t qx = output period t p_dis output disable time (clkstopx to qa, qb) 0 1.5 t qx t qx = output period t jit(cc) cycle-to-cycle jitter (rms) (5) n= 2, 4, 6, 8 n= 12 n= 16, 32 5. maximum cycle jitter measured at the lowest vco frequency. refer to figure 8 for the cycle jitter vs. frequency characterisit ics. 15 20 30 ps ps ps t jit(per) period jitter (rms) (6) n= 2 n= 4 n= 6 n= 8 n= 12 n= 16 n= 32 6. maximum period jitter measured at the lowest vco frequency. refer to figure 9 for the period jitter vs. frequency characteris itics. 8 10 12 13 17 23 29 ps ps ps ps ps ps ps n ref(unlock) number of missing reference clock cycles to declare an out of lock condition (7) 7. see the lock detect section on page 13. 2 t lock maximum pll lock time 10 ms
advanced clock drivers devices 8 freescale semiconductor MPC92433 output frequency configuration the MPC92433 is a programmable frequency source (synthesizer) and supports an output frequency range of 42.5 ? 1428 mhz. the output frequency f out is a function of the reference frequency f ref and the three internal pll dividers p, m, and n. f out can be represented by this formula: f out = (f ref p) m (n a , b ) (1) the m, n and p dividers require a configuration by the user to achieve the desired output frequency. the output divider, n a, determines the achievable output frequency range (see table 7 ). the pll feedback-divider m is the frequency multiplication factor and the main variable for frequency synthesis. for a given reference frequency f ref , the pll feedback-divider m must be configured to match the specified vco frequency range in order to achieve a valid pll configuration: f vco = (f ref p) m and (2) 1360 f vco 2856 (3) the output frequency may be changed at any time by changing the value of the pll feedback divider m. the smallest possible output frequency change is the synthesizer granularity g (difference in f out when incrementing or decrementing m). at a given reference frequency, g is a function of the pll pre-divider p and post-divider n: g = f ref (p n a,b ) (4) the n b divider configuration determines if the output q b generates a 1:1 or 2:1 frequency copy of the q a output signal. the purpose of the pll pre-divider p is to situated the pll into the specified vco frequency range f vco (in combination with m). for a given output frequency, p = 4 results in a smaller output frequency granularity g, p = 2 results a larger output frequency granularity g and also increases the pll bandwidth compared to the p = 2 setting. the following example illustrates the output frequency range of the MPC92433 using a 16-mhz reference frequency. example output frequency configuration if a reference frequency of 16 mhz is available, an output frequency at q a of 250 mhz and a small frequency granularity is desired, the following steps would be taken to identify the appropriate p, m, and n configuration: 1. use table 7 to select the output divider, n a , that matches the desired output frequency or frequency range. according to table 7 , a target output frequency of 250 mhz falls in the f out range of 170 to 357 mhz and requires to set n a = 8 2. calculate the vco frequency f vco = f out n a , which is 2000 mhz in this example. 3. determine the pll feedback divider: m = f vco p. the smallest possible output granularity in this example calculation is 500 khz (set p = 4). m calculates to a value of 2000 4 = 500. 4. configure the MPC92433 with the obtained settings: m[9:0] = 0111110100b (binary number for m=500) n a [2:0] = 010 (8 divider, see ta b l e 9 ) p = 1 (4 divider, see ta b l e 8 ) n b = 0 (f out, qb = f out, qa ) 5. use either parallel or serial interface to apply the setting. the i 2 c configuration bytes for this example are: pll_h=01010010b and pll_l=11110100b. see table 13 and table 14 for register maps. table 7. frequency ranges (f ref =16 mhz) f out (q a ) [mhz] n a mpg [mhz] 680?1428 n a =2 170-357 2 4 340-714 4 2 340?714 n a =4 170-357 2 2 340-714 4 1 226.67?476 n a =6 170-357 2 1.33 340-714 4 0.66 170?357 n a =8 170-357 2 1 340-714 4 0.5 113.33?238 n a =12 170-357 2 0.66 340-714 4 0.33 85?178.5 n a =16 170-357 2 0.5 340-714 4 0.25 42.5?89.25 n a =32 170-357 2 0.25 340-714 4 0.125
advanced clock drivers devices freescale semiconductor 9 MPC92433 pll divider configuration programming the MPC92433 the MPC92433 has a parallel and a serial configuration interface. the purpose of the parallel interface is to directly configure the pll dividers through hardware pins without the overhead of a serial protocol. at device startup, the device always obtains an initial pll frequency configuration through the parallel interface. the parallel interface does not support reading the pll configuration. the serial interface is i 2 c compatible. it allows reading and writing devices settings by accessing internal device registers. the serial interface is designed for host-controller access to the synthesizer frequency settings for instance in frequency-margining applications. using the parallel interface the parallel interface supports write-access to the pll frequency setting directly through 15 configuration pins (p, m[9:0], na[2:0], and nb). the parallel interface must be enabled by setting pload to logic low level. during pload = 0, any change of the logical state of the p, m[9:0], na[2:0], and nb pins will immediately affect the internal pll divider settings, resulting in a change of the internal vco- frequency and the output frequency. the parallel interface mode disables the i 2 c write-access to the internal registers; however, i 2 c read-access to the internal configuration registers is enabled. upon startup, when the device reset signal is released (rising edge of the mr signal), the device reads its startup configuration through the parallel interface and independent on the state of pload. it is recommended to provide a valid pll configuration for startup. if the parallel interface pins are left open, a default pll configuration will be loaded. after the low-to-high transition of pload , the configuration pins have no more effect and the configuration registers are made accessible through the serial interface. using the i 2 c interface pload = 1 enables the programming and monitoring of the internal registers through the i 2 c interface. device register access (write and read) is possible through the 2-wire interface using sda (configuration data) and scl (configuration clock) signals. the MPC92433 acts as a slave device at the i 2 c bus. for further information on i 2 c it is recommended to refer to the i 2 c bus specification (version 2.1). pload = 0 disables the i 2 c-write-access to the configura- tion registers and any data written into the register is ignored. however, the MPC92433 is still visible at the i 2 c interface and i 2 c transfers are acknowledged by the device. read-ac- cess to the internal registers during pload = 0 (parallel pro- gramming mode) is supported. note that the device automatically obtains a configuration using the parallel interface upon the release of the device reset (rising edge of mr ) and independent on the state of pload . changing the state of the pload input is not supported when the device performs any transactions on the i 2 c interface. programming model and register set the synthesizer contains two fully accessible configuration registers (pll_l and pll_h) and a write-only command register (cmd). programming the synthesizer frequency through the i 2 c interface requires two steps: 1) writing a valid pll configuration to the configuration registers and 2) loading the registers into the pll by an i 2 c command. the pll frequency is affected as a result of the second step. this two-step procedure can be performed by a single i 2 c transaction or by multiple, independent i 2 c transactions. an alternative way to achieve small pll frequency changes is to use the increment or decrement commands of the table 8. pre-pll divider p pvalue 0f ref 2 1f ref 4 table 9. post-pll divider n a and n b n a2 n a1 n a0 n b f out (q a ) f out (q b ) 000 0 f vco 2 f vco 2 001 0 f vco 32 f vco 32 010 0 f vco 8 f vco 8 011 0 f vco 12 f vco 12 100 0 f vco 4 f vco 4 101 0 f vco 6 f vco 6 110 0 f vco 16 f vco 16 111 0n/a n/a 000 1 f vco 2 f vco 4 001 1n/a n/a 010 1 f vco 8 f vco 16 011 1n/a n/a 100 1 f vco 4 f vco 8 101 1 f vco 6 f vco 12 110 1 f vco 16 f vco 32 111 1n/a n/a table 10. feedback divider configuration feedback divider m 9876543210 pin m9 m8 m7 m6 m5 m4 m3 m2 m1 m0 default 0111110100 table 11. pll pre/post divider configuration (n, p) post-d. na 210 post-d. nb nb pre-d. p p pin na2 na1 na0 pin nb pin p default 010 default 0 default 1
advanced clock drivers devices 10 freescale semiconductor MPC92433 synthesizer, which have an immediate effect on the pll frequency. figure 3. i 2 c mode register set figure 3 illustrates the synthesizer register set. pll_l and pll_h store a pll configuration and are fully accessible (read/write) by the i 2 c bus. cmd (write only) accepts commands (load, get, inc, dec) to update registers and for direct pll frequency changes. set the synthesizer frequency: 1) write the pll_l and pll_h registers with a new configuration (see table 13 and table 14 for register maps) 2) write the load command to update the pll dividers by the current pll_l, pll_h content. read the synthesizer frequency: 1) write the get commands to update the pll_l, pll_h registers by the pll divider setting 2) read the pll_l, pll_h registers through i 2 c change the synthesizer frequency in small steps: 1) write the inc or dec command to change the pll frequency immediately. repeat at any time if desired. load and get are inverse command to each other. load updates the pll dividers and get updates the configuration registers. a fast and convenient way to change the pll frequency is to use the inc (increment m) and dec (decrement m) commands of the synthesizer. inc (dec) directly increments (decrements) the pll-feedback divider m and immediately changes the pll frequency by the smallest step g (see tab l e 7 for the frequency granularity g). the inc and dec commands are designed for multiple and rapid pll frequency changes as required in frequency margining applications. inc and dec do not require the user to update the pll dividers by the load command, inc and dec do not update the pll_l and pll_h registers either (use load for an initial pll divider setting and, if desired, use get to read the pll configuration). note that the synthesizer does not check any boundary conditions such as the vco frequency range. applying the inc and dec commands could result in invalid vco frequencies (vco frequency beyond lock range). register maps register 0x00 (pll_l) contains the least significant bits of the pll feedback divider m. register content: m[7:0] pll feedback-divider m, bits 7?0 register 0x01 (pll_h) contains the two most significant bits of the pll feedback divider m, four bits to control the pll post-dividers n and the pll pre-divider p. the bit 0 in pll_h register indicates the lock condition of the pll and is set by the synthesizer automatically. the lock state is a copy of the pll lock signal output (lock). a write-access to lock has no effect. register content: m[9:8] pll feedback-divider m, bits 9?8 na[2:0] pll post-divider n a , see ta b l e 9 nb pll post-divider n b , see ta b l e 9 p pll pre-divider p, see ta b l e 8 lock copy of lock output signal (read-only) note that the load command is required to update the pll dividers by the content of both pll_l and pll_h registers. register 0xf0 (cmd) is a write-only command register. the purpose of cmd is to provide a fast way to increase or decrease the pll frequency and to update the registers. the register accepts four commands, inc (increment m), dec (decrement m), load and get (update registers). it is recommended to write the inc, dec commands only after a valid pll configuration is achieved. inc and dec only affect the m-divider of the pll (pll feedback). applying inc and dec commands can result in a pll configuration beyond the specified lock range and the pll may lose lock. the MPC92433 does not verify the validity of any commands such as load, inc, and dec. the inc and dec commands change the pll feedback divider without updating pll_l and pll_h. configuration latches i 2 c registers i 2 c access synthesizer ? pll pn m load/get pll_l (r/w) 0x00 pll_h (r/w) 0x01 cmd (w) 0xf0 table 12. configuration registers address name content access 0x00 pll_l least significant 8 bits of m r/w 0x01 pll_h most significant 2 bits of m, p, n a , n b , and lock state r/w 0xf0 cmd command register (write only) w only table 13. pll_l (0x00, r/w) register bit 76543210 name m7 m6 m5 m4 m3 m2 m1 m0 table 14. pll_h (0x01, r/w) register bit 76543210 name m9 m8 na2 na1 na0 nb p lock
advanced clock drivers devices freescale semiconductor 11 MPC92433 i 2 c ? register access in parallel mode the MPC92433 supports the configuration of the synthesizer through the parallel interlace (pload = 0) and serial interface (pload = 1). register contents and the divider configurations are not changed when the user switches from parallel mode to serial mode. however, when switching from serial mode to parallel mode, the pll dividers immediately reflect the logical state of the hardware pins m[9:0], na[2:0], nb, and p. applications using the parallel interface to obtain a pll configuration can use the serial interface to verify the divider settings. in parallel mode (pload = 0), the MPC92433 allows read-access to pll_l and pll_h through i 2 c (if pload = 0, the current pll configuration is stored in pll_l, pll_h. the get command is not necessary and also not supported in parallel mode). after changing from parallel to serial mode (pload = 1), the last pll configuration is still stored in pll_l, pll_h. the user now has full write and read access to both configuration registers through the i 2 c bus and can change the configuration at any time. programming the i 2 c interface the 7-bit i 2 c slave address of the MPC92433 synthesizer is a combination of a 5-bit fixed addresses and two variable bits which are set by the hardware pins adr[1:0]. bit 0 of the MPC92433 slave address is used by the bus controller to select either the read or write mode. ?0? indicates a transmission (i 2 c-write) to the MPC92433. ?1? indicates a request for data (i 2 c-read) from the synthesizer. the hardware pins adr1 and adr0 and should be individually set by the user to avoid address conflicts of multiple MPC92433 devices on the same i 2 c bus. write mode (r/w = 0) the configuration registers are written by the bus controller by the initiation of a write transfer with the MPC92433 slave address (first byte), followed by the address of the configuration register (second byte: 0x00, 0x01 or 0xf0), and the configuration data byte (third byte). this transfer may be followed by writing more registers by sending the configuration register address followed by one data byte. each byte sent by the bus controller is acknowledged by the MPC92433. the transfer ends by a stop bit sent by the bus controller. the number of configuration data bytes and the write sequence are not restricted. table 15. cmd (0xf0): pll command (write-only) command op-code description inc xxxx0001b (0x01) increase internal pll frequency m:=m+1 dec xxxx0010b (0x02) decrease internal pll frequency m:=m-1 load xxxx0100b (0x04) update the pll divider config. pll divider m, n, p:=pll_l, pll_h get xxxx1000b (0x08) update the configuration registers pll_l, pll_h:=pll divider m, n, p table 16. pll configuration in parallel and serial modes pll configuration parallel serial (registers pll_l, pll_h) m[9:0] set pins m9?m0 m[9:0] (r/w) na[2:0] set pins na2...na0 na[2:0] (r/w) nb set pin nb nb (r/w) p set pin p p (r/w) lock status lock pin 26 lock (read only) table 17. i 2 c slave address bit 76543 2 1 0 value 10110pin adr1 pin adr0 r/w table 18. complete configuration register write transfer 1 bit 7 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit start slave address r/w ack &pll_h ack config-byte 1 ack &pll_l ack config-byte 2 ack stop 10110xx (1) 1. xx = state of adr1, adr0 pins 0 0x01 data 0x00 data master master mast slave master slave master slave master slave master slave mast
advanced clock drivers devices 12 freescale semiconductor MPC92433 read mode (r/w = 1) the configuration registers are read by the bus controller by the initiation of a read transfer. the MPC92433 supports read transfers immediately after the first byte without a change in the transfer direction. immediately after the bus controller sends the slave address, the MPC92433 acknowledges and then sends both configuration register pll_l and pll_h (back-to-back) to the bus controller. the cmd register cannot be read. in order to read the two synthesizer registers and the current pll configuration setting, the user can 1) read pll_l, pll_h, write the get command (loads the current configuration into pll_l, pll_h) and read pll_l, pll_h again. note that the pll_l, pll_h registers and divider settings may not be equivalent after the following cases: a. writing the inc command b. writing the dec command c. writing pll_l, pll_h registers with a new configuration and not writing the load command. device startup general device configuration it is recommended to reset the MPC92433 during or immediately after the system powers up (mr = 0). the device acquires an initial pll divider configuration through the parallel interface pins m[9:0], na[2:0], n, and p (1) with the low-to-high transition of mr (2) . pll frequency lock is achieved within the specified lock time (t lock ) and is indicated by an assertion of the lock signal which completes the startup procedure. it is recommended to disable the outputs (clk_stopx = 0) until pll lock is achieved to suppress output frequency transitions. the output frequency can be reconfigured at any time through either the parallel or the serial interface. note that a pll configuration obtained by the parallel interface can be read through i 2 c independent on the current programming mode (parallel or serial). refer to the i2c ? register access in parallel mode section for additional information on how to read a pll startup configuration through the i 2 c interface. starting-up using the parallel interface the simplest way to use the MPC92433 is through the parallel interface. the serial interface pins (sda, sdl) and addr[1:0]) can be left open and pload is set to logic low. after the release of mr and at any other time the pll/output frequency configuration is directly set to through the m[9:0], na[2:0], nb, and p pins. start-up using the serial (i 2 c) interface figure 4. start-up using i 2 c interface set pload = 1, clk_stopx = l and leave the parallel interface pins (m[9:0], na[2:0], n, and p) open. the pll dividers are configured by the default configuration at the low- to-high transition of mr . this initial pll configuration can be re-programmed to the final vco frequency at any time through the serial interface. after the pll achieved lock at the desired vco frequency, enable the outputs by setting clk_stopx = h. pll lock and re-lock (after any configuration change through m or p) is indicated by lock being asserted. table 19. configuration register read transfer 1 bit 7 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit start slave address r/w ack pll_l ack pll_h ack stop 10110xx (1) 1. xx = state of adr1, adr0 pins 1 data data master master mast slave slave mast slave master slave 1. the parallel interface pins m[9:0], na[2:0], n, and p may be left open (floating). in this case the initial pll configuration will have the default setting of m = 500, p = 1, na[2:0] = 010, nb = 0, resulting in an internal vco frequency of 2000 mhz (f ref = 16 mhz) and an output frequency of 250 mhz. 2. the initial pll configuration is independent on the selected programming mode (pload low or high) v cc mr p, m , n pload lock clk_stopx qa, qb stable & valid selects i 2 c acquiring lock pll lock disabled (low) t plh active
advanced clock drivers devices freescale semiconductor 13 MPC92433 lock detect the lock detect circuitry indicates the frequency-lock status of the pll by setting and resetting the pin lock and register bit lock simultaneously. after acquiring an internal frequency lock state, the assertion of the lock signal is delayed at least 256 reference clock cycles to prevent signaling temporary pll locks during frequency transitions. the lock signal is deasserted when the pll lost lock, for instance when the reference clock is removed: the lock signal goes low after missing at least two f ref clock cycles (n ref(unlock) ). the pll may also lose lock when the pll feedback-divider m or pre-divider p is changed or the dec/inc command is issued. the pll may not lose lock as a result of slow reference frequency changes. in any case of losing lock, the pll attempts to re-lock to the reference frequency. output clock stop asserting clk_stopx will stop the respective output clock in logic low state. the clk_stopx control is internally synchronized to the output clock signal, therefore, enabling and disabling outputs does not produce runt pulses. see figure 5 .the clock stop controls of the qa and qb outputs are independent on each other. if the qb runs at half of the qa output frequency and both outputs are enabled at the same time, the first clock pulse of qa may not appear at the same time of the first qb output. (see figure 6 .) concident rising edges of qa and qb stay synchronous after the assertion and de-assertion of the clk_stopx controls. asserting mr always resets the output divider to a logic low output state, with the risk of producing an output runt pulse. figure 5. clock stop timing for nb = 0 (f qa = f qb ) figure 6. clock stop timing for nb = 1 (f qa = 2 f qb ) clk_stopx qx (disable) (enable) (enable) t p_dis t p_en clk_stopa,b qa qb (disable) (enable) (enable)
advanced clock drivers devices 14 freescale semiconductor MPC92433 frequency operating range table 20. MPC92433 frequency operating range for p=2 f vco [mhz] (parameter: f ref in mhz) output frequency for f xtal =16 mhz (parameter n) m m[9:0] 15 16 18 20 2 4 6 8 12 16 32 170 0010101010 1360 1530 1700 680 340 226.67 170 113.33 85 42.50 180 0010110100 1440 1620 1800 720 360 240.00 180 120.00 90 45.00 190 0010 111110 1425 1520 1710 1900 760 380 253.33 190 126.67 95 47.50 200 0011001000 1500 1600 1800 2000 800 400 266.67 200 133.33 100 50.00 210 0011010010 1575 1680 1890 2100 840 420 280.00 210 140.00 105 52.50 220 0011011100 1650 1760 1980 2200 880 440 293.33 220 146.67 110 55.00 230 0011100110 1725 1840 2070 2300 920 460 306.67 230 153.33 115 57.50 240 0011110000 1800 1920 2160 2400 960 480 320.00 240 160.00 120 60.00 250 001111 1010 1875 2000 2250 2500 1000 500 333.33 250 166.67 125 62.50 260 0100000100 1950 2080 2340 2600 1040 520 346.67 260 173.33 130 65.00 270 0100001110 2025 2160 2430 2700 1080 540 360.00 270 180.00 135 67.50 280 0100011000 2100 2240 2520 2800 1120 560 373.33 280 186.67 140 70.00 290 0100100010 2175 2320 2610 1160 580 386.67 290 193.33 145 72.50 300 0100101100 2250 2400 2700 1200 600 400.00 300 200.00 150 75.00 310 0100110110 2325 2480 2790 1240 620 413.33 310 206.67 155 77.50 320 0101000000 2400 2560 1280 640 426.67 320 213.33 160 80.00 330 0101001010 2475 2640 1320 660 440.00 330 220.00 165 82.50 340 0101010100 2550 2720 1360 680 453.33 340 226.67 170 85.00 350 0101011110 2625 2800 1400 700 466.67 350 233.33 175 87.50 357 0101100101 2667.5 2856 1428 714 476.00 357 238.00 178.50 89.25
advanced clock drivers devices freescale semiconductor 15 MPC92433 table 21. MPC92433 frequency operating range for p=4 f vco [mhz] (parameter: f ref in mhz) output frequency for f xtal =16 mhz (parameter n) mm[9:0] 15 16 1820 2468121632 340 0101010100 1360 1530 1700 680 340 226.67 170 113.33 85.0 42.50 350 01010 11110 1400 1575 1750 700 350 233.33 175 116.67 87.5 43.75 360 0101101000 1440 1620 1800 720 360 240.00 180 120.00 90.0 45.00 370 0101110010 1387.5 1480 1665 1850 740 370 246.67 185 123.33 92.5 46.25 380 0101111100 1425.0 1520 1710 1900 760 380 253.33 190 126.67 95.0 47.50 390 0110000110 1462.5 1560 1755 1950 780 390 260.00 195 130.00 97.5 48.75 400 0110010000 1500.0 1600 1800 2000 800 400 266.67 200 133.33 100.0 50.00 410 0110110010 1537.5 1640 1845 2050 820 410 273.33 205 136.67 102.5 51.25 420 0110100100 1575.0 1680 1890 2100 840 420 280.00 210 140.00 105.0 52.50 430 0110101110 1612.5 1720 1935 2150 860 430 286.67 215 143.33 107.5 53.75 440 0110111000 1650.0 1760 1980 2200 880 440 293.33 220 146.67 110.0 55.00 450 0111000010 1687.5 1800 2025 2250 900 450 300.00 225 150.00 112.5 56.25 460 0111001100 1725.0 1840 2070 2300 920 460 306.67 230 153.33 115.0 57.50 470 0111010110 1762.5 1880 2115 2350 940 470 313.33 235 156.67 117.5 58.75 480 0111100000 1800.0 1920 2160 2400 960 480 320.00 240 160.00 120.0 60.00 490 0111101010 1837.5 1960 2205 2450 980 490 326.67 245 163.33 122.5 61.25 500 011111 0100 1875.0 2000 2250 2500 1000 500 333.33 250 166.67 125.0 62.50 510 0111111110 1912.5 2040 2295 2550 1020 510 340.00 255 170.00 127.5 63.75 520 1000001000 1950.0 2080 2340 2600 1040 520 346.67 260 173.33 130.0 65.00 530 1000010010 1987.5 2120 2475 2650 1060 530 353.33 265 176.67 132.5 66.25 540 1000011100 2025.0 2160 2520 2700 1080 540 360.00 270 180.00 135.0 67.50 550 1000100110 2062.5 2200 2565 2750 1100 550 366.67 275 183.33 137.5 68.75 560 1000110000 2100 2240 2610 2800 1120 560 373.33 280 186.67 140.0 70.00 570 1000111010 2137.5 2280 2565 2850 1140 570 380.00 285 190.00 142.5 71.25 580 1001000100 2175.0 2320 2610 1160 580 386.67 290 193.33 145.0 72.50 590 1001001110 2212.5 2360 2655 1180 590 393.33 295 196.67 147.5 73.75 600 1001011000 2250.0 2400 2700 1200 600 400.00 300 200.00 150.0 75.00 610 1001100010 2287.5 2440 2745 1220 610 406.67 305 203.33 152.5 76.25 620 1001101100 2325.0 2480 2790 1240 620 413.33 310 206.67 155.0 77.50 630 1001110110 2362.5 2520 2835 1260 630 420.00 315 210.00 157.5 78.75^ 640 1010000000 2400.0 2560 1280 640 426.67 320 213.33 160.0 80.00 650 1010001010 2437.5 2600 1300 650 433.33 325 216.67 162.5 81.25 660 1010010100 2475.0 2640 1320 660 440.00 330 220.00 165 82.5 670 10100 11110 2512.5 2680 1340 670 446.67 335 223.33 167.5 83.75 680 1010101000 2550.0 2720 1360 680 453.33 340 226.67 170.0 85.00 690 1010110010 2587.5 2760 1380 690 460.00 345 230.00 172.5 86.25 700 1010 111100 2625.0 2800 1400 700 466.67 350 233.33 175.0 87.50 714 1011001010 2677.5 2856 1428 714 476.00 357 238.00 178.5 89.25
advanced clock drivers devices 16 freescale semiconductor MPC92433 v cc_pll filter the MPC92433 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the v cc_pll pin impacts the device ac characteristics. the MPC92433 provides separate power supplies for the digital circuitry (v cc ) and the internal pll (v cc_pll ) of the device. the purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. in digital system environments where it is more difficult to minimize noise on the power supplies a second level of isolation is recommended: a power supply filter on the v cc_pll pin for the MPC92433. figure 7. v cc_pll power supply filter figure 7 illustrates a recommended power supply filter scheme. the MPC92433 is most susceptible to noise with spectral content in the 100 khz to 1 mhz range. therefore, the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the v cc_pll pin of the MPC92433. from the data sheet, the v cc_pll current (the current sourced through the v cc_pll pin) is maximum 10 ma, assuming that a minimum of 2.985 v must be maintained on the v cc_pll pin. the resistor shown in figure 7 must have a resistance of 10 ? 15 ? to meet the voltage drop criteria. the minimum values for r f and the filter capacitor c f are defined by the filter characteristics: the rc filter should provide an attenuation greater than 40 db for noise whose spectral content is above 100 khz. in the recommended filter shown in figure 7 the filter cut-off frequency is around 3.0 ? 4.5 khz and the noise attenuation at 100 khz is better than 42 db. as the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. the on-chip crystal oscillator the MPC92433 features an integrated on-chip crystal oscillator to minimize system implementation cost. the integrated oscillator is a pierce-type that uses the crystal in its parallel resonance mode. it is recommended to use a 15 to 20 mhz crystal with a load specification of c l =10pf. crystals with a load specification of c l = 20 pf may be used at the expense of an resulting slightly higher frequency than specified for the crystal. externally connected capacitors on both the xtal_in and xtal_out pins are not required but can be used to fine-tune the crystal frequency as desired. the crystal, the trace and optional capacitors should be placed on the board as close as possible to the MPC92433 xtal_in and xtal_out pins to reduce crosstalk of active signals into the oscillator. short and wide traces further reduce parasitic inductance and resistance. it is further recommended to guard the crystal circuit by placing a ground ring around the traces and oscillator components. r f = 10?15 ? v cc c f = 22 f 10 nf 33...100 nf v cc_pll v cc MPC92433 7 table 22. recommended crystal specifications parameter value crystal cut fundamental at cut resonance mode parallel crystal frequency 16 ? 20 mhz shunt capacitance c 0 5 ? 7 pf load capacitance c l 10 pf
advanced clock drivers devices freescale semiconductor 17 MPC92433 jitter performance of the MPC92433 figure 8 and figure 9 illustrate the rms jitter performance of the MPC92433 across its specified vco frequency range. for some output dividers n, the cycle-to-cycle and period jitter is a function of the vco frequency and the output divider n. the general trend is that as the output frequency increases (higher vco frequency and lower n-divider) the MPC92433 output jitter decreases. optimum jitter performance can be achieved at higher vco and output frequencies. for the output dividers of n=2, 4 and 6 the cycle-to-cycle jitter does not depend on the vco frequency. for the output dividers of 2, 4 and 8 the period jitter does not depend on the vco frequency. the maximum cycle-to-cycle and period jitter published in table 6 (ac characteristics) correspond to the jitter performance at the lowest vco frequency limit. the vco frequency can be calculated using formula (2). ac test reference and output termination the MPC92433 lvpecl outputs are designed to drive 50 transmission lines and require a dc termination to v tt =v cc ?2v. figure 10 illustrates the ac test reference for the MPC92433 as used in characterization and test of this circuit. if a separate termination voltage (v tt ) is not available, applications may use alternative output termination methods such as shown in figure 11 and figure 12 . the high-speed differential output signals of the MPC92433 are incompatible to single-ended lvcmos signals. in order to use the synthesizer in lvcmos clock signal environments, the dual-channel translator device mc100es60t23 provides the necessary level conversion. the mc100es60t23 has been specifically designed to interface with the MPC92433 and supports clock frequencies up to 300 mhz. figure 8. MPC92433 cycle-to-cycle jitter figure 9. MPC92433 period jitter . figure 10. MPC92433 ac test reference z = 50 ? r t = 50 ? z = 50 ? r t = 50 ? v tt z = 50 ? qa qb pulse generator z = 50 ? f ref = 16 mhz synthesizer dut MPC92433
advanced clock drivers devices 18 freescale semiconductor MPC92433 figure 11. thevenin termination figure 12. resistor network termination figure 13. interfacing with lvcmos logic for f < 300 mhz z = 50 ? qx v cc 130 ? 82 ? MPC92433 z = 50 ? qx 50 ? 46.4 ? smd resistor network MPC92433 50 ? z = 50 ? qa 50 ? v tt z = 50 ? qb v tt MPC92433 mc100es60t23
advanced clock drivers devices freescale semiconductor 19 MPC92433 outline dimensions notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. dimensioning and tolerancing per asme y14.5m, 1994. controlling dimension: millimeter. datum plan ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. datums t, u, and z to be determined at dataum plane ab. dimensions s and v to be determined at seating plane ac. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. minimum solder plate thickness shall be 0.0076. exact shape of each corner is optional. a a1 z 0.200 ab t-u 4x z 0.200 ac t-u 4x b b1 1 12 13 24 25 36 37 48 s1 s v v1 detail y 9 t u z p ae ae t, u, z detail y m? top & bottom l? w k aa e c h 0.250 r detail ad gauge plane ad g 0.080 ac ab ac base metal n j f d t- u m 0.080 z ac section ae-ae min 1.400 0.170 1.350 0.170 0.050 0.090 0.500 0.090 0? 0.150 max 1.600 0.270 1.450 0.230 0.150 0.200 0.700 0.160 7? 0.250 dim a a1 b b1 c d e f g h j k m n p l r s s1 v v1 w aa millimeters 7.000 bsc 3.500 bsc 7.000 bsc 3.500 bsc 0.500 bsc 12? ref 0.250 bsc 9.000 bsc 4.500 bsc 9.000 bsc 4.500 bsc 0.200 ref 1.000 ref fa suffix 48-lead lqfp package case 932-03 issue f
how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com MPC92433 rev. 2 06/2005 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved.

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