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| p r o d u c t i n n o v a t i o n f r o m PA97DR PA97DRu features ? high voltage 900v (450v) ? low quiescent current 600a ? high output current 10 ma applications ? mass spectrometers ? scanning coils ? high voltage instrumentation ? programmable power supplies up to 880v ? semiconductor measurement equip - ment power operational amplifiers PA97DR p r o d u c t i n n o v a t i o n f r o m 2 2 3 3 $ 3 2 $ $ $ $ 2 2 3 3 3 2 3 3 2 3 2 0 6 5 2 3 7 4 m * / * / m 7 4 3 2 " 2 # description the PA97DR is a high voltage mosfet operational amplifer designed as a low cost solution for driving continuous output currents up to 10 ma and pulse cur - rents to 15 ma into capacitive loads. the safe operat - ing area (soa) has no second breakdown limitations. the mosfet output stage is biased class c for low quiescent current operation. external compensation provides fexibility in choosing bandwidth and slew rate for the application. apexs sip05 package uses a minimum of board space allowing for high density circuit boards. equivalent schematic copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com jan 2009 apex ? PA97DRurevg
p r o d u c t i n n o v a t i o n f r o m PA97DR 2 PA97DRu parameter symbol min max units supply voltage, +v s to -v s 900 v output current, source, sink, within soa 15 ma power dissipation,continuous @ tc = 25oc 5 w input voltage, differential (note 3) -20 20 v input voltage, common mode (see text) -v s v s v temperature, pin solder, 10s max. 220 c temperature, junction (note 2) 150 c temperature range, storage ?65 150 c operating temperature, case ?55 125 c c haracteristics and s pecifications absolute maximum ra tings parameter test conditions min typ max units input offset voltage, initial 0.5 5 mv offset voltage vs. temperature full temperature range 10 50 v/c offset voltage vs. supply 10 25 v/v offset voltage vs. time 75 v/khz bias current, initial 200 2000 pa bias current vs. supply 4 pa/v offset current, initial 50 500 pa input impedance, dc 10 11 ? input capacitance 4 pf common mode voltage range (note 3) v s =250v v s ? 30 v common mode rejection, dc v cm = 90v 80 98 db noise 10khz bw, r s = 1k, c c = 10pf 2 vrms gain open loop @ 15hz r l = 5k, c c = 10pf 94 111 db gain bandwidth product @ 1mhz r l = 5k, c c = 10pf 1 mhz power bandwidth r l = 5k, c c = 10pf 2 khz phase margin, a v = 100 full temperature range 60 output voltage swing (note 3) i o = 10ma v s ? 24 v s ? 20 v current, continuous 10 ma slew rate, a v = 100 c c = 10pf 8 v/s settling time, to 0.1% c c = 10pf, 2v step 2 s resistance 10ma load 100 s pecifications p r o d u c t i n n o v a t i o n f r o m PA97DR PA97DRu notes: 1. unless otherwise noted: t c = 25c, dc input specifcations are value given. power supply voltage is typical rating. c c = 10pf. 2. long term operation at the maximum junction temperature will result in reduced product life. derate internal power dissipation to achieve high mttf. 3. although supply voltages can range up to 450v the input pins cannot swing over this range. the input pins must be at least 30v from either supply rail but not more than 500v from either supply rail. see text for a more complete description of the common mode voltage range. 4. rating applies if the output current alternates between both output transistors at a rate faster than 60hz. 5. derate max supply rating .625 v/c below 25c case. no derating needed above 25c case. caution the PA97DR is constructed from mosfet transistors. esd handling procedures must be ob - served. parameter test conditions min typ max units power supply voltage (note 5) 50 300 450 v current, quiescent, amplifer only 0.6 1 ma thermal resistance, ac, junction to case (note 4) full temp range, f > 60hz 20 oc/w resistance, dc, junction to case full temp range, f < 60hz 25 oc/w resistance, junction to air full temp range 40 oc/w temperature range, case C25 +85 oc 5 & . 1 & 3 " 5 6 3 & 5 ? $ . . . . ' 3 & 2 6 & / $ : ' ) [ 1 ) " 4 & 3 & 4 1 0 / 4 & 1 ) " 4 & t ? , . ' 3 & 2 6 & / $ : ' ) [ * / 1 6 5 / 0 * 4 & 7 0 - 5 " ( & 7 / o 7 v ) [ 0 6 5 1 6 5 $ 6 3 3 & / 5 * 0 n " * / 1 6 5 / 0 * 4 & , 7 0 - 5 " ( & % 3 0 1 ' 3 0 . 4 6 1 1 - : 7 4 m 7 0 7 4 " ' & 0 1 & 3 " 5 * / ( " 3 & " $ $ q ' 0 6 5 1 6 5 $ 6 3 3 & / 5 ' 3 0 . 7 4 0 3 m 7 4 n " ? 4 % $ 5 $ ? $ % $ 5 $ ? $ % $ 5 $ ? $ 4 6 1 1 - : 5 0 0 6 5 1 6 5 % * ' ' & 3 & / 5 * " - 7 4 m 7 0 7 . ' 3 & 2 6 & / $ : ' ) [ 4 . " - - 4 * ( / " - 3 & 4 1 0 / 4 & 0 1 & / - 0 0 1 ( " * / " e # , , . . $ $ q ' / 0 3 . " - * ; & % 2 6 * & 4 $ & / 5 $ 6 3 3 & / 5 * 9 5 0 5 " - 4 6 1 1 - : 7 0 - 5 " ( & 7 4 7 2 6 * & 4 $ & / 5 $ 6 3 3 & / 5 0 6 5 1 6 5 7 0 - 5 " ( & 4 8 * / ( 1 0 8 & 3 % & 3 " 5 * / ( * / 5 & 3 / " - 1 0 8 & 3 % * 4 4 * 1 " 5 * 0 / 1 8 4 8 * / ( ' 3 0 . 7 4 4 8 * / ( ' 3 0 . 7 4 , , ' 3 & 2 6 & / $ : ' ) [ , 1 0 8 & 3 3 & 4 1 0 / 4 & 0 6 5 1 6 5 7 0 - 5 " ( & 7 0 7 1 1 , $ $ q ' 5 5 $ 5 5 " p r o d u c t i n n o v a t i o n f r o m PA97DR PA97DRu external connections * 0.01f or greater ceramic power supply bypassing required. cc = 10pf minimum, 1kv npo (cog). phase compensation gain c c 10 10pf 5 & . 1 & 3 " 5 6 3 & 5 ? $ . . . . ' 3 & 2 6 & / $ : ' ) [ 1 ) " 4 & 3 & 4 1 0 / 4 & 1 ) " 4 & t ? , . ' 3 & 2 6 & / $ : ' ) [ * / 1 6 5 / 0 * 4 & 7 0 - 5 " ( & 7 / o 7 v ) [ 0 6 5 1 6 5 $ 6 3 3 & / 5 * 0 n " * / 1 6 5 / 0 * 4 & , 7 0 - 5 " ( & % 3 0 1 ' 3 0 . 4 6 1 1 - : 7 4 m 7 0 7 4 " ' & 0 1 & 3 " 5 * / ( " 3 & " $ $ q ' 0 6 5 1 6 5 $ 6 3 3 & / 5 ' 3 0 . 7 4 0 3 m 7 4 n " ? 4 % $ 5 $ ? $ % $ 5 $ ? $ % $ 5 $ ? $ 4 6 1 1 - : 5 0 0 6 5 1 6 5 % * ' ' & 3 & / 5 * " - 7 4 m 7 0 7 . ' 3 & 2 6 & / $ : ' ) [ 4 . " - - 4 * ( / " - 3 & 4 1 0 / 4 & 0 1 & / - 0 0 1 ( " * / " e # , , . . $ $ q ' / 0 3 . " - * ; & % 2 6 * & 4 $ & / 5 $ 6 3 3 & / 5 * 9 5 0 5 " - 4 6 1 1 - : 7 0 - 5 " ( & 7 4 7 2 6 * & 4 $ & / 5 $ 6 3 3 & / 5 0 6 5 1 6 5 7 0 - 5 " ( & 4 8 * / ( 1 0 8 & 3 % & 3 " 5 * / ( * / 5 & 3 / " - 1 0 8 & 3 % * 4 4 * 1 " 5 * 0 / 1 8 4 8 * / ( ' 3 0 . 7 4 4 8 * / ( ' 3 0 . 7 4 , , ' 3 & 2 6 & / $ : ' ) [ , 1 0 8 & 3 3 & 4 1 0 / 4 & 0 6 5 1 6 5 7 0 - 5 " ( & 7 0 7 1 1 , $ $ q ' 5 5 $ 5 5 " typical application low power, piezoelectric positioning piezo positioning may be applied to the focusing of seg - mented mirror systems. the composite mirror may be com - posed of hundreds of elements, each requiring focusing un - der computer control. in such complex systems the PA97DR reduces the costs of power supplies and cooling with its ad - vantages of low cost and low quiescent power consumption while increasing circuit density with the sip package. ' 3 1 " % 3 * / 3 1 * & ; 0 % 3 * 7 & 4 m 7 4 7 0 6 5 7 $ 0 . 1 6 5 & 3 ' 0 $ 6 4 $ 0 . . " / % 7 0 - 5 " ( & $ $ m * / * / $ $ $ $ 0 6 5 m 7 t 7 t $ $ patented 7-pin sip package style dr p r o d u c t i n n o v a t i o n f r o m PA97DR PA97DRu general please read the general operating considerations section, which covers stability, supplies, heatsinking, mount - ing, current limit, soa interpretation, and specifcation interpretation. additional information can be found in the ap - plication notes. for information on the package outline, heatsinks, and mounting hardware, consult the accessory and package mechanical data section of the handbook. current limit the PA97DR has no provision for current limiting the output. common mode input range operational amplifers are usually designed to have a common mode input voltage range that approximates the power supply voltage range. however, to keep the cost as low as possible and still meet the requirements of most applications the common mode input voltage range of the PA97DR is restricted. the input pins must always be a least 30v from either supply voltage but never more than 500v. this means that the pa97 cannot be used in ap - plications where the supply voltages are extremely unbalanced. for example, supply voltages of +800v and C100v would not be allowed in an application where the non-inverting pin is grounded because in normal operation both input pins would be at 0v and the difference voltage between the positive supply and the input pins would be 800v. in this kind of application, however, supply voltages +500v and -100v does meet the input common mode voltage range requirements since the maximum difference voltage between the inputs pins and the supply voltage is 500v (the maximum allowed). the output has no such restrictions on its voltage swing. the output can swing within 24v of either supply voltage regardless of value so long as the total supply voltage does not exceed 900v . input protection although the PA97DR can withstand differential input voltages up to 20v, additional external protection is recommended. in most applications 1n4148 or 1n914 signal diodes are suffcient (d1, d2 in figure 2a). in more de - manding applications where low leakage or low capacitance are of concern 2n4416 or 2n5457-2n5459 jfets connected as diodes will be required (q1, q2 in figure 2b). in either case the input differential voltage will be clamped to .7v. this is suffcient overdrive to produce maximum power bandwidth. note that this protection does not automatically protect the amplifer from excessive common mode input voltages. power supply protection unidirectional zener diode transient suppressors are recommended as pro - tection on the supply pins. the zeners clamp transients to voltages within the power supply rating and also clamp power supply reversals to ground. whether the zeners are used or not, the system power supply should be evaluated for transient performance including power-on overshoot and pow - er-off polarity reversal as well as line regulation. conditions which can cause open circuits or polarity reversals on either pow - er supply rail should be avoided or protected against. reversals or opens on the negative supply rail is known to induce input stage failure. unidirectional transzorbs prevent this, and it is desirable that they be both electrically and physically as close to the amplifer as possible. external components the compensation capacitor cc must be rated for the total supply voltage. 10pf npo (cog)capacitor rated at 1kv is recommended. of equal importance is the voltage rating and voltage coeffcient of the gain setting feedback resistor. typical volt - age ratings of low wattage resistors are 150 to 250v. up to 900 v can appear across the feedback resistor. high voltage rated resistors can be obtained. however a 1 megohm feedback resistor composed of fve 200k resistors in series will produce the proper voltage rating. 1 " % 3 7 4 m * / * / ; ; % % 7 4 m * / * / ; ; 1 " % 3 2 2 " # m 7 4 m 7 4 figure 2. p r o d u c t i n n o v a t i o n f r o m PA97DR PA97DRu cautions the operating voltages of the PA97DR are potentially lethal. during circuit design develop a functioning circuit at the lowest possible voltages. clip test leads should be used for "hands off" measurements while troubleshooting. with no internal current limit, proper choice of load impedance and supply voltage is required to meed soa limitia - tions. an output short circuit will destroy the amplifer within milliseconds. stability the PA97DR is stable at gains of 10 or more with a npo (cog) compensation capacitor of 10pf. the compensation capacitor, cc, in the external connections diagram must be rated at 1000v working voltage and mounted closely to pins 4 and 6 to prevent spurious oscillation. a compensation capacitor less than 10pf is not recommended. cont acting cirrus logic support for all apex precision power product questions and inquiries, call toll free 800-546-2739 in north america. for inquiries via email, please contact tucson.support@cirrus.com. international customers can also request support by contacting their local cirrus logic sales representative. to fnd the one nearest to you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnifcation, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives con - sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop - erty or environmental damage (critical applications). cirrus products are not designed, authorized or warranted to be suitable for use in products surgically implanted into the body, automotive safety or security devices, life support prod - ucts or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the cus - tomers risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customers customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs, apex precision power, apex and the apex precision power logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. |
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