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general description the max9691/max9692/max9693 are ultra-fast ecl comparators capable of very short propagation delays. their design maintains the excellent dc matching char- acteristics normally found only in slower comparators. the max9691/max9692/max9693 have differential inputs and complementary outputs that are fully com- patible with ecl-logic levels. output current levels are capable of driving 50 ? terminated transmission lines. the ultra-fast operation makes signal processing possi- ble at frequencies in excess of 600mhz. the max9692/max9693 feature a latch-enable (le) function that allows the comparator to be used in a sample-hold mode. when le is ecl high, the compara- tor functions normally. when le is driven ecl low, the outputs are forced to an unambiguous ecl-logic state, dependent on the input conditions at the time of the latch input transition. if the latch-enable function is not used on either of the two comparators, the appropriate le input must be connected to ground; the companion le input must be connected to a high ecl logic level. these devices are available in so, qsop, and tiny ?ax packages for added space savings. ________________________applications high-speed line receivers peak detectors threshold detectors high-speed triggers features 1.2ns propagation delay 100ps propagation delay skew 150ps dispersion 0.5ns latch setup time 0.5ns latch-enable pulse width available in max and qsop packages +5v, -5.2v power supplies max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable ________________________________________________________________ maxim integrated products 1 in+ r l r l in- v t q out q out max9691 noninverting input r l r l v t inverting input noninverting input inverting input q out q out r l r l latch enable the outputs are open emitters, requiring external pulldown resistors. these resistors may be in the range of 50 ? to 200 ? connected to -2.0v, or 240 ? to 2000 ? connected to -5.2v. max9693 max9693 le le latch enable le le _________________________________________________________ functional diagrams 19-1789; rev 2; 1/12 ordering information ordering information continued at the end of data sheet. pin configurations appear at end of data sheet. part temp range pin-package max9691 eua -40 c to +85 c 8 ?ax max9691esa -40 c to +85 c 8 so max9691epa -40 c to +85 c 8 pdip selector guide part comparators per package latch enable pin- package max9691 1 no 8 max, 8 so, 8 pdip max9692 1 yes 10 max, 16 so, 16 pdip max9693 2 yes 16 qsop, 16 so, 16 pdip for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: devices are also available in lead(pb)-free/rohs-compli- ant packages. specify lead-free by adding a ??after the part number. ?ax is a registered trademark of maxim integrated products, inc.
max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +5v, v ee = -5.2v, r l = 50 ? to v t , v t = -2v, le = 0, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage (v cc ) ...............................................-0.3v to +6v supply voltage (v ee )................................................-6v to +0.3v input voltage....................................(v cc + 0.3v) to (v ee - 0.3v) output short-circuit duration ....................................continuous differential input voltage ......................................................?v latch enable ...............................................(v ee - 0.3v) to +0.3v output current ....................................................................50ma input current ....................................................................?5ma continuous power dissipation (t a = +70?) 8-pin ?ax (derate 4.8mw/? above 70?)...............387.8mw 8-pin so (derate 7.4mw/? above +70?)..................588.2mw 8-pin pdip (derate 9.1mw/? above +70?) ...........727.3mw 10-pin ?ax (derate 8.8mw/? above +70?) ...........707.3mw 16-pin qsop (derate 9.6mw/? above +70?) .........771.5mw 16-pin so (derate 13.3mw/? above +70?) ..........1066.7mw 16-pin pdip (derate 10.5mw/? above +70?) .......842.1mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units t a = +25 c -6.5 6.5 input offset voltage v os t a = t min to t max -11.5 +11.5 mv temperature coefficient ? v os / ? t 10 ?/? t a = +25 c 0.2 5 input offset current i os t a = t min to t max 8 ? t a = +25 c620 input bias current i b t a = t min to t max 30 ? input voltage range v cm note 1 -2.5 +3.0 v common-mode rejection ratio cmrr -2.5v v cm +3.0v (note 1) 60 80 db positive power-supply rejection ratio +psrr 4.5v v cc 5.5v 60 db negative power-supply rejection ratio -psrr -5.7v v ee -4.7v 60 db open-loop gain aol v cm = 0v 70 db differential input resistance r in -10mv < v in < 10mv 60 k ? differential input clamp voltage 1.7 v input capacitance c in 3pf latch enable input current high i ih(le) v ih(le) = 1.1v 60 120 ? latch enable input current low i il(le) v il(le) = 1.5v 0.2 10 ? latch e nab l e log i c h i g h v ol tag ev ih ( le ) -1.1 v latch enable logic low voltage v il ( le ) -1.5 v t a = t min -1.2 -0.87 t a = t max -0.99 -0.70 logic output high voltage v oh t a = +25? -1.06 -0.76 v t a = t min -1.93 -1.57 t a = t max -1.89 -1.51 logic output low voltage v ol t a = +25? -1.89 -1.55 v
max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +5v, v ee = -5.2v, r l = 50 ? to v t , v t = -2v, le = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units t a = +25? 34 46 max9693 t a = t min to t max 50 t a = +25? 18 26 supply current i cc max9691/ max9692 t a = t min to t max 36 ma note 1: guaranteed by design. note 2: v in = 100mv, v od = 10mv. ac electrical characteristics (v cc = 5v, v ee = -5.2v, r l = 50 ? to v t , v t = -2v, le = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units max9691/max9692/max9693 t a = +25? 1.2 1.8 propagation delay (notes 1, 2) t p d+ , t p d- t a = t min to t max 2.0 ns rise/fall time t r , t f 10% to 90% 500 ps propagation delay skew ? pd 100 ps dispersion p dsp v od from 10mv to 100mv 150 ps max9692/max9693 t a = +25? 1.0 1.8 latch-enable time (note 1) t le (? t a = t min to t max 2.0 ns latch- enab le p ul se wi d th (n ote 1) t p w ( le ) 0.5 1.0 ns setup time (note 1) t s 0.5 1.0 ns hold time (note 1) t h 0.5 1.0 ns channel-to-channel propagation match t pdm note 2 (max9693 only) 100 ps
max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable 4 _______________________________________________________________________________________ 400 600 800 1000 1200 1400 04050 20 30 10 60 70 80 90 100 worst-case propagation delay vs. input overdrive max9691/3-01 input overdrive (mv) propagation delay (ps) 0 3000 2000 1000 4000 5000 6000 0 200 150 50 100 250 300 350 400 450 500 worst-case propagation delay vs. source impedance max9691/3-02 source impedance ( ? ) propagation delay (ps) 600 1000 800 1400 1200 1600 1800 010 5 152025 worst-case propagation delay vs. c load max9691/3-03 c load (pf) propagation delay (ps) 600 700 800 900 1000 1100 1200 1300 1400 -40 -15 10 35 60 85 worst-case propagation delay vs. temperature max9691/3-04 temperature ( c) propagation delay (ps) v od = 100mv -1.1 -1.0 -0.8 -0.9 -0.7 -0.6 -40 10 -15 35 60 85 output high voltage vs. temperature max9691/3-05 temperature ( c) v oh (v) r pulldown = 200 ? r pulldown = 100 ? r pulldown = 50 ? -1.80 -1.74 -1.76 -1.78 -1.72 -1.70 -1.68 -1.66 -1.64 -1.62 -1.60 -40 10 -15 35 60 85 output low voltage vs. temperature max9691/3-06 temperature ( c) v ol (v) r pulldown = 200 ? r pulldown = 100 ? r pulldown = 50 ? -2000 -1500 -1000 -500 0 500 1000 1500 2000 -40 -15 10 35 60 85 input offset voltage vs. temperature max9691/3-08 temperature (?) input offset voltage (?) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -40 -15 10 35 60 85 input bias current vs. temperature max9691/3-09 temperature ( c) input bias current ( a) typical operating characteristics (v cc = +5v, v ee = -5.2v, r l = 50 ? to v t , v t = -2v, v od = 10mv, t a = +25?, unless otherwise noted.) -5000 -3000 -4000 -1000 -2000 1000 0 2000 4000 3000 5000 -5 -3 -2 -1 -4 012 4 35 input bias current vs. differential input voltage max9691/3-10 differential input voltage (v) input bias current (?)
max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable _______________________________________________________________________________________ 5 typical operating characteristics (continued) (v cc = +5v, v ee = -5.2v, r l = 50 ? to v t , v t = -2v, v od = 10mv, t a = +25?, unless otherwise noted.) propagation delay max9691/3-11 v in 200mv/div 1ns/div q out - q out 200mv/div v in = 100mv v od = 10mv 100mhz output response max9691/3-12 -1.0v q out 200mv/div q out 200mv/div -1.8v -1.8v -1.0v 1ns/div pin description pin max9691 max9692 ?ax max9692 pdip/so max9693 name function 11211v cc positive supply. bypass to gnd with a 0.1? capacitor. 2 2 3 in+ positive input 3 3 4 in- negative input 4686v ee negative supply. bypass to gnd with a 0.1? capacitor. 5 7 11 q out output 6 8 12 q out complimentary output 7 9 16 gnd2 device ground 8 10 1 gnd1 device ground ? 5, 7, 9, 10, 13, 14, 15 n.c. no connection. not internally connected. 5 6 le latch enable input 1 q outa channel a output 2 q outa channel a complementary output 3, 14 gnd device ground 4 lea channel a latch enable input 5 lea channel a latch enable complementary input 7 ina- channel a negative input 8 ina+ channel a positive input 9 inb+ channel b positive input 10 inb- channel b negative input 12 leb channel b latch enable complementary input 13 leb channel b latch enable input 15 q outb channel b complementary output 16 q outb channel b output
max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable 6 _______________________________________________________________________________________ __________ applications information layout because of the max9691/max9692/max9693s?large gain-bandwidth characteristic, special precautions must be taken to use them. a pc board with a ground plane is mandatory. mount 0.01? ceramic decoupling capacitors as close to the power-supply pins as possi- ble, and process the ecl outputs in microstrip fashion, consistent with the load termination of 50 ? to 200 ? (for v t = -2v). for low-impedance applications, microstrip layout and terminations at the input may also be help- ful. pay close attention to the bandwidth of the decou- pling and terminating components. chip components can be used to minimize lead inductance. connect gnd1 and gnd2 together to a solid copper ground plane for the max9691/max9692. gnd1 biases the input gain stages, while gnd2 biases the ecl output stage. if the le function is not used, connect the le pin to gnd (max9692/max9693) and the complementary le to ecl logic high level (max9693 only). do not leave the inputs of an unused comparator floating for the max9693. input slew-rate requirements as with all high-speed comparators, the high gain- bandwidth product of these devices creates oscillation problems when the input goes through the linear region. for clean switching without oscillation or steps in the output waveform, the input must meet certain minimum slew-rate requirements. the tendency of the part to oscillate is a function of the layout and source impedance of the circuit employed. poor layout and larger source impedance will increase the minimum slew-rate requirement. figure 1 shows a high-speed receiver application with 50 ? input and output termination. with this configura- tion, in which a ground plane and microstrip pc board are used, the minimum slew rate for clean output switching is 1v/?. in many applications, adding regenerative feedback will assist the input signal through the linear region, which will lower the minimum slew-rate requirement considerably. for example, with the addition of positive feedback components, r f = 1k ? and c f = 10pf, the minimum slew-rate requirement can be reduced by a factor of four. as high-speed receivers, the max9691/max9692/ max9693 are capable of processing signals in excess of 600mhz. figure 2 is a 100mhz example with an input signal level of 14mv rms . v in -2v 50 ? c f r f 50 ? 50 ? 50 ? q q le figure 1. regenerative feedback?igh-speed receiver with 50 ? input and output termination 0v -0.9v -1.7v output 500mv/div input 20mv/div 2ns/div figure 2. signal processed at 100mhz with input signal level of 14mv rms
max9691/max9692/max9693 the timing diagram (figure 3) illustrates the series of events that complete the compare function, under worst-case conditions. the top line of the diagram illus- trates two latch-enable pulses. each pulse is high for the compare function and low for the latch function. the first pulse demonstrates the compare function; part of the input action takes place during the compare mode. the second pulse demonstrates a compare function interval during which there is no change in the input. the leading edge of the input signal (illustrated as a large-amplitude, small-overdrive pulse) switches the comparator after time interval t pd . output q and q tran- sistors are similar in timing. the input signal must occur at time t s before the latch falling edge, and must be maintained for time t h after the edge to be acquired. after t h , the output is no longer affected by the input sta- tus until the latch is again strobed. a minimum latch pulse width of t pw(le) is needed for the strobe opera- tion, and the output transitions occur after a time t le(? . the max9691/max9692/max9693 will not false trip (i.e., output invert) if one of the inputs is in the valid common-mode range while the other input is outside the common-mode range. latch enable differential input voltage q q latch compare t s t h v od v in t le(+) v os 50% 50% 50% t pw(le) t pd figure 3. timing diagram single/dual, ultra-fast, ecl-output comparators with latch enable _______________________________________________________________________________________ 7
max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable 8 _______________________________________________________________________________________ definition of terms v os input offset voltage. the voltage required between the input terminals to obtain 0v dif- ferential at the output. v in input voltage pulse amplitude v od input voltage overdrive t pd+ input to output high delay. the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output low-to-high transition. t pd- input to output low delay. the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output high-to-low transition. t le(+) latch-enable to output high delay. the prop- agation delay measured from the 50% point of the latch-enable signal low-to-high transition to the 50% point of an output low-to-high tran- sition. t le(-) latch-enable to output low delay. the prop- agation delay measured from the 50% point of the latch-enable signal low-to-high transition to the 50% point of an output high-to-low tran- sition. t pw (le) latch-enable pulse width. the minimum time the latch-enable signal must be high to acquire and hold an input signal. t s setup time. the minimum time before the negative transition of the latch-enable pulse that an input signal must be present to be ac- quired and held at the outputs. t h hold time. the minimum time after the nega- tive transition of the latch-enable signal that an input signal must remain unchanged to be acquired and held at the output. ? pd propagation delay skew. the difference in propagation delay between the q and q out- puts crossing each other in both directions. p dsp propagation delay dispersion. the change in propagation delay as a result of the overdrive of the input signal varying. t pdm propagation delay match (max9693 only). the difference in propagation delay between two separate channels. part temp range pin-package max9692 eub -40 c to +85 c 10 ?ax max9692ese -40 c to +85 c 16 narrow so max9692epe -40 c to +85 c 16 pdip max9693 ese -40 c to +85 c 16 narrow so max9693eee -40 c to +85 c 16 qsop max9693epe -40 c to +85 c 16 pdip ordering information (continued) chip information process: bicmos note: devices are also available in lead(pb)-free/rohs-compli- ant packages. specify lead-free by adding a ??after the part number.
max9691/max9692/max9693 pin configurations dip/so/ max max9691 q out q out v ee 1 2 8 7 gnd1 gnd2 in+ in- v cc 3 4 6 5 top view max max9692 1 2 3 4 5 10 9 8 7 6 gnd1 gnd2 q out q out n.c. in- in+ v cc v ee le pdip/so 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 gnd1 gnd2 n.c. n.c. n.c. q out n.c. n.c. v cc in+ le in- n.c. n.c. v ee max9692 max9693 dip/so/qsop 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 q outa q outb q outb gnd leb leb v cc inb- inb+ q outa gnd v ee lea lea ina- ina+ q out single/dual, ultra-fast, ecl-output comparators with latch enable _______________________________________________________________________________________ 9 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 ?ax u8+1 21-0036 90-0092 8 so s8+2 21-0041 90-0096 8 pdip p8+5 21-0043 10 ?ax u10+2 21-0061 90-0330 16 qsop e16+1 21-0055 90-0167 16 so s16+3 21-0041 90-0097 16 pdip p16+1 21-0043
max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable 10 ______________________________________________________________________________________ d d package information (continued) for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status.
max9691/max9692/max9693 package information (continued) for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. single/dual, ultra-fast, ecl-output comparators with latch enable ______________________________________________________________________________________ 11
max9691/max9692/max9693 single/dual, ultra-fast, ecl-output comparators with latch enable maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/00 initial release 1 10/02 updated ordering information. 7 2 1/12 revised ordering information , absolute maximum ratings , and pin description . 1, 2, 5, 7

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