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1. general description cbtl06dp212 is a high performance multi- channel generation 2 multiplexer meant for displayport (dp) v1.2, v1.1a or embedded display port applications operating at data rate of 1.62 gbit/s, 2.7 gbit/s or 5.4 gbit/s. it is designed using nxp proprietary high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1 multiplexing of four high-speed differential ac -coupled dp channels. further, it is capable of switching/multiplexing of hot plug detect (hpd) signal as well as auxiliary (aux) and display data channel (ddc) signals. in order to support gpus/cpus that have dedicated aux and ddc i/os, cbtl06dp212 provides an additional level of multiplexing of aux and ddc signals delivering true flexibility and choice. a typical application of cbtl06dp212 is on motherboards where one of two gpu displayport sources needs to be selected to connect to a displayport sink device or connector. a controller chip sele cts which path to use by setting a select signal high or low. due to the bidirectional nature of the signal paths, cbtl06dp212 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors. 2. features and benefits ? 1 : 2 switching or 2 : 1 mult iplexing of displayport (v1.2 - 5.4 gbit/s) signals ? 4 high-speed differential channels with 2 : 1 multiplexing/switch ing for displayport main link signals ? 1 channel with 4 : 1 multiplexing/switching for aux or ddc signals ? 1 channel with 2 : 1 multiplexi ng/switching for hpd signal ? high-bandwidth: 5 ghz at ? 3db ? low insertion loss: ? ? 0.5 db at 100 mhz ? ? 3db at 5ghz ? low crosstalk: ? 35 db at 3 ghz ? low off-state isolation: ? 30 db at 3 ghz ? low return loss: ? 8db at 3ghz ? very low intra-pair skew (5 ps typical) ? very low inter-pair skew (< 80 ps) ? switch/multiplexer posit ion select cmos input ? ddc and aux ports tolerant to being pulled to +5 v via 2.2 k ? resistor ? supports hdmi/dvi incorrect dongle connection ? single 3.3 v power supply ? operation current of 2 ma typical cbtl06dp212 high-performance displaypor t gen2 2 : 1 multiplexer rev. 2 ? 3 november 2011 product data sheet
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 2 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer ? esd 8 kv hbm, 1 kv cdm ? esd 2 kv hbm, 500 v cdm for control pins ? available in 5 mm ? 5 mm, 0.5 mm ball pitch tfbga48 package 3. applications ? motherboard applications requiring displayport and pci express switching/multiplexing ? docking stations ? notebook computers ? chip sets requiring flexible allocation of pci express or displayport i/o pins to board connectors 4. ordering information [1] total height including solder balls after printed circuit board mounting = 1.15 mm maximum. 5. marking [1] industrial temperature range. table 1. ordering information type number solder process package name description version CBTL06DP212EE pb-free (snagcu solder compound) tfbga48 plastic thin fine-pitc h ball grid array package; 48 balls; body 5 ? 5 ? 0.8 mm [1] sot918-1 table 2. package marking line marking description a6d212 [1] basic type number b xxxxxxx diffusion lot number c zpgyyww manufacturing code: z = diffusion site p = assembly site g = lead-free yy = year code ww = week code
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 3 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 6. functional diagram fig 1. functional diagram cbtl06dp212 vdd in1_n+ out_n? aux+ aux ? 0 1 aux+ or scl out_n+ in1_n? 002aaf878 in2_n+ in2_n? 4 4 4 aux1+ 00 10 aux1 ? aux2+ aux2 ? 01 ddc_clk1 ddc_dat1 11 ddc_clk2 ddc_dat2 0 1 hpd_1 hpd_2 gpu_sel ddc_aux_sel tst0 aux ? or sda hpdin gnd
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 4 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 7. pinning information 7.1 pinning fig 2. pin configuration for tfbga48 transparent top view fig 3. ball mapping 002aaf879 transparent top view CBTL06DP212EE h j g f e d c a b 24689 1357 ball a1 index area 1 a 002aaf943 gpu_sel vdd in1_0? in1_1? in1_2? in1_3+ in1_3? 23456789 b out_0? out_0+ gnd in1_0+ in1_1+ in1_2+ tst0 in2_0+ in2_0? c ddc_aux _sel gnd d out_1? out_1+ in2_1+ in2_1? e out_2? out_2+ in2_2+ in2_2? f out_3? out_3+ in2_3+ in2_3? g gnd gnd h aux ? aux+ hpd_2 gnd ddc_clk2 aux2+ gnd ddc_clk1 aux1+ j hpdin hpd_1 vdd ddc_dat2 aux2 ? ddc_dat1 aux1 ?
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 5 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 7.2 pin description table 3. pin description symbol ball type description gpu_sel a1 3.3 v cmos single-ended input selects between two mu ltiplexer/switch path s. when high, path 2 left-side is connected to its corresponding right-side i/o. when low, path 1 left-side is connected to its corresponding right-side i/o. ddc_aux_sel c2 3.3 v cmos single-ended input selects between ddc and aux paths. when high, the clk and dat i/os are connected to their respective ddcout terminals. when low, the aux+ and aux ? i/os are connected to their respective ddcout terminals. tst0 b7 3.3 v cmos single-ended input test pin for nxp use only. should be tied to vdd in normal operation. in1_0+ b4 differential i/o four high-speed differential pairs for displayport or pci express signals, path 1, left-side. in1_0 ? a4 differential i/o in1_1+ b5 differential i/o in1_1 ? a5 differential i/o in1_2+ b6 differential i/o in1_2 ? a6 differential i/o in1_3+ a8 differential i/o in1_3 ? a9 differential i/o in2_0+ b8 differential i/o four high-speed differential pairs for displayport or pci express signals, path 2, left-side. in2_0 ? b9 differential i/o in2_1+ d8 differential i/o in2_1 ? d9 differential i/o in2_2+ e8 differential i/o in2_2 ? e9 differential i/o in2_3+ f8 differential i/o in2_3 ? f9 differential i/o out_0+ b2 differential i/o four high-speed differential pairs for displayport or pci express signals, right-side. out_0 ? b1 differential i/o out_1+ d2 differential i/o out_1 ? d1 differential i/o out_2+ e2 differential i/o out_2 ? e1 differential i/o out_3+ f2 differential i/o out_3 ? f1 differential i/o aux1+ h9 differential i/o high-speed differential pair for aux signals, path 1, left-side. aux1 ? j9 differential i/o aux2+ h6 differential i/o high-speed differential pair for aux signals, path 2, left-side. aux2 ? j6 differential i/o ddc_clk1 h8 differential i/o pair of single-ended terminals for ddc clock and data signals, path 1, left-side. ddc_dat1 j8 differential i/o
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 6 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 8. functional description refer to figure 1 ? functional diagram ? . the cbtl06dp212 uses a 3.3 v power supply. all main signal paths are implemented using high-bandwidth pass-gate technology and are bidirectional. no clock or reset signal is needed for the multiplexer to function. the switch position for the main channels is selected using the select signal gpu_sel. additionally, the signal ddc_aux_sel select s between aux and ddc positions for the ddc / aux channel. the detailed operation is described in section 8.1 . 8.1 multiplexer/switc h select functions the internal multiplexer swit ch position is controlled by two logic inputs gpu_sel and ddc_aux_sel as described below. ddc_clk2 h5 differential i/o pair of single-ended terminals for ddc clock and data signals, path 2, left-side. ddc_dat2 j5 differential i/o aux+ h2 differential i/o high-speed differential pair for aux or single-ended ddc signals, right-side. aux ? h1 differential i/o hpd_1 j2 single-ended i/o single ended channel for the hpd signal, path 1, left-side. hpd_2 h3 single-ended i/o single ended channel for the hpd signal, path 2, left-side. hpdin j1 single-ended i/o single ended channel for the hpd signal, right-side. vdd a2, j4 power supply 3.3 v power supply. gnd b3, c8, g2, g8, h4, h7 ground ground. table 3. pin description ?continued symbol ball type description table 4. multiplexer/switch select control for inn and outn channels gpu_sel in1_n in2_n 0 active; connected to out_n high-impedance 1 high-impedance active; connected to out_n table 5. multiplexer/switch sele ct control for hpd channel gpu_sel hpd_1 hpd_2 0 active; connected to hpdin high-impedance 1 high-impedance active; connected to hpdin
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 7 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 9. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] charged device model: ansi/eos/esd-s5.3-1-1999, stand ard for esd sensitivity testing, charged device model - component level; electrostatic discharge association, rome, ny, usa. 10. recommended operating conditions [1] hpd input is tolerant to 5 v input, provided a 1 k ? series resistor between the voltage source and the pin is placed in series. see section 12.1 ? special considerations ? . [2] ddc/aux inputs are tolerant to 5 v input, provided a 2.2 k ? series resistor between the voltage source and the pin is placed in series. see section 12.1 ? special considerations ? . table 6. multiplexer/switch select control for ddc and aux channels ddc_aux_sel gpu_sel aux1 aux2 ddc_clk1, ddc_dat1 ddc_clk2, ddc_dat2 0 0 active; connected to aux high-impedance high-impedance high-impedance 0 1 high-impedance active; connected to aux high-impedance high-impedance 1 0 high-impedance hig h-impedance active; connected to aux high-impedance 1 1 high-impedance high-imped ance high-impedance active; connected to aux table 7. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +5 v t case case temperature ? 40 +85 ? c v esd electrostatic discharge voltage hbm [1] - 8000 v hbm; cmos inputs [1] - 2000 v cdm [2] - 1000 v cdm; cmos inputs [2] 500 v table 8. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v i input voltage cmos inputs ? 0.3 - v dd +0.3 v hpd inputs [1] ? 0.3 - v dd +0.3 v ddc/aux inputs [2] ? 0.3 - v dd +0.3 v other inputs ? 0.3 - +2.6 v t amb ambient temperature oper ating in free air ? 40 - +85 ?c
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 8 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 11. characteristics 11.1 general characteristics 11.2 displayport channel characteristics table 9. general characteristics symbol parameter conditions min typ max unit i dd supply current v dd =3.3v - 23ma p cons power consumption v dd =3.3v --10mw t startup start-up time supply voltage valid to channel specified operating characteristics --10 ? s t rcfg reconfiguration time gpu_sel or ddc_aux_sel state change to channel specified operating characteristics --1 ? s table 10. displayport channel characteristics symbol parameter conditions min typ max unit v i input voltage ? 0.3 - +2.6 v v ic common-mode input voltage 0 - 2.0 v v id differential input voltage peak-to-peak - - +1.2 v r on on-state resistance v dd =3.3v; v i =2v; i i =20ma - 6.5 - ? ddil differential insertion loss channel is on; f ? 100 mhz - ? 0.5 - db channel is on; f = 3.0 ghz - ? 2.5 - db channel is off; f ? 3.0 ghz - ? 30 - db ddrl differential return loss f = 100 mhz - ? 25 - db f=3.0ghz - ? 8- db ddnext differential near-end crosstalk adjacent channels are on f = 100 mhz - ? 65 - db f=3.0ghz - ? 35 - db b bandwidth ? 3.0 db intercept - 5 - ghz t pd propagation delay from left-side port to right-side port or vice versa -80-ps t sk(dif) differential skew time intra-pair - 5 - ps t sk skew time inter-pair - - 80 ps
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 9 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 11.3 aux and ddc ports [1] time from ddc/aux input changing state to aux output changing state. includes ddc/aux rise/fall time. 11.4 hpdin input, hpd_x outputs [1] time from hpdin changing state to hpd_x changing state. includes hpd rise/fall time. 11.5 gpu_sel and ddc _aux_sel inputs table 11. aux and ddc port characteristics symbol parameter conditions min typ max unit v i input voltage ? 0.3 - v dd +0.3 v v o output voltage no load - - v dd v v ic common-mode input voltage aux 0 - 2.0 v v id differential input voltage aux - - +1.4 v t pd propagation delay from left-side port to right-side port or vice versa [1] -80- ps table 12. hpd input and output characteristics symbol parameter conditions min typ max unit v i input voltage ? 0.3 - v dd +0.3 v v o output voltage no load - - v dd v t pd propagation delay from hpdin to hpd_x or vice versa [1] -80- ps table 13. gpu_sel and ddc_aux_ sel input characteristics symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i li input leakage current v dd =3.6v; 0.3v ? v i ? 3.9 v - - 10 ? a
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 10 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 12. application information 12.1 special considerations certain cable or dongle misplug scenarios make it possible for a 5 v input condition to occur on pins aux+ and aux ? , as well as hpdin. when aux+ and aux ? are connected through a minimum of 2.2 k ? each, the cbtl06dp212 will sink current but will not be damaged. similarly, hpdin may be c onnected to 5 v via at least a 1 k ? resistor. (correct functional operation to specification is not expected in these scenarios.) the latter also prevents the hpdin input from loading down the system hpd signal when power to the cbtl06dp212 is off. fig 4. application diagram out_n? hpdin out_n+ 002aaf944 2 : 1 mux aux ? a ux+ 4 : 1 mux 2 : 1 mux ddc_aux_sel gpu_sel cbtl06dp212 dp connector in1_n? in1_n+ gpu2_dp++ source in2_n? in2_n+ aux1 ? aux1+ gnd 100 k v dd 100 k aux2 ? aux2+ gnd 100 k v dd 100 k gpu1_dp++ source +3.3 v ddc_dat1 ddc_clk1 2 k ddc_dat2 ddc_clk2 hpd_1 hpd_2
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 11 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 13. package outline fig 5. package outline tfbga48 (sot918-1) references outline version european projection issue date iec jedec jeita sot918-1 mo-195 - - - - - - sot918-1 05-09-21 05-10-13 unit a max mm 1.15 0.25 0.15 0.90 0.75 0.35 0.25 5.1 4.9 5.1 4.9 a 1 dimensions (mm are the original dimensions) tfbga48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm x a 2 b d e e 2 4 e 1 4 e 0.5 v 0.15 w 0.05 y 0.08 y 1 0.1 0 2.5 5 mm scale b ball a1 index area a b c d e f h g j 2468 13579 e 2 e 1 e e ac b ? v m c ? w m ball a1 index area b a e d c y c y 1 detail x a a 1 a 2
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 12 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 13 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 6 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 4 and 15 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 6 . table 14. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 15. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 14 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 15. abbreviations msl: moisture sensitivity level fig 6. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 16. abbreviations acronym description aux auxiliary channel (in displayport definition) cdm charged-device model cmos complementary metal-oxide semiconductor cpu central processing unit dp displayport dvi digital video interface esd electrostatic discharge gpu graphics processor unit hbm human body model hdmi high-definition multimedia interface i/o input/output pci peripheral component interconnect
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 15 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 16. revision history table 17. revision history document id release date data sheet status change notice supersedes cbtl06dp212 v.2 20111103 product data sheet - cbtl06dp212 v.1 modifications: ? table 2 ? package marking ? : line a marking corrected from ?6dp212? to ?6d212? cbtl06dp212 v.1 20110221 product data sheet - -
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 16 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
cbtl06dp212 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 3 november 2011 17 of 18 nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 17.4 licenses 17.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com purchase of nxp ics with hdmi technology use of an nxp ic with hdmi technology in equipment that complies with the hdmi standard requires a license from hdmi licensing llc, 1060 e. arques avenue suite 100, sunnyvale ca 94085, usa, e-mail: admin@hdmi.org .
nxp semiconductors cbtl06dp212 high-performance displayport gen2 2 : 1 multiplexer ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 3 november 2011 document identifier: cbtl06dp212 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 6 8.1 multiplexer/switch select fu nctions . . . . . . . . . . 6 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 recommended operating conditions. . . . . . . . 7 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 11.1 general characteristics . . . . . . . . . . . . . . . . . . . 8 11.2 displayport channel characteristics . . . . . . . . . 8 11.3 aux and ddc ports . . . . . . . . . . . . . . . . . . . . . 9 11.4 hpdin input, hpd_x outputs . . . . . . . . . . . . . . 9 11.5 gpu_sel and ddc_aux_sel inputs. . . . . . . 9 12 application information. . . . . . . . . . . . . . . . . . 10 12.1 special considerations . . . . . . . . . . . . . . . . . . 10 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 14 soldering of smd packages . . . . . . . . . . . . . . 12 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 12 14.2 wave and reflow soldering . . . . . . . . . . . . . . . 12 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 17.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17.5 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 contact information. . . . . . . . . . . . . . . . . . . . . 17 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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