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? 2006 fairchild semiconductor corporation www.fairchildsemi.com tm december 2006 fm75 rev. 1.0.8 fm75 low-voltage two-wire digital temperature sensor with thermal alarm fm75 low-voltage two-wire digital temperature sensor with thermal alarm features user configurable to 9, 10, 11 or 12-bit resolution precision calibrated to 1c, 0c to 100c typical temperature range: -40c to 125c low operating current (less than 250a) low self heating (0.2c max. in still air) operating voltage range: 2.7v to 5.5v applications battery management fax management printers portable medical instruments hvac systems power supply modules disk drives computers automotive components description the fm75 contains a high-precision cmos temperature sensor, a delta-sigma analog-to-digital converter, and a smbus-compatible serial digital interface. typical accu- racy is 2c over the full temperature range of 40c to 125c and to 1c over the range of 0c to 100c, with 9- to 12-bit resolution (default is 9). thermal alarm output, over-limit signal (os) supports interrupt and comparator modes. os is active if the user- programmable trip-temperature is exceeded. when the temperature falls below the tr ip temperature, plus the user-programmable hysteresis limit, the os is disabled. available in a surface mount soic-8 (sop-8) package. application diagram figure 1. typical application diagram ordering information fm75 a0 a1 a2 sda scl 1 2 3 5 6 7 os 4 8 8-pin configuration user programmable address smbus interface 2.7 to 5.5v part number package temperature range packing method fm75m8x 8-lead soic -40c to +125c 2500 units, tape and reel
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 2 pin assignments figure 2. pin assignments pin descriptions pin # name direction description 1 sda input/output serial data. open drain to i/o-data pin for two-wire interface. 2sclinput serial clock. clock for two-wire serial interface. 3 os output over-limit signal. open drain thermostat output that indicates if the temperature exceeds user-pro grammable limits. default is active low. 4 gnd supply ground 5, 6, 7 a0, a1, a2 input address least significant bits (lsbs). user selectable address pins for the three lsbs of the serial interface address. 8v dd supply supply voltage v dd a0 a1 a2 sda scl os gnd 1 2 3 4 8 7 6 5 fm75
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 3 absolute maximum ratings the ?absolute maximum ratings? are those values beyon d which the safety of t he device cannot be guaranteed. the device should not be operated at these limits. the pa rametric values defined in the electrical characteristics tables are not guaranteed at the abs olute maximum ratings. the ?recommended operating conditions? table defines the conditions for actual device operation. note: 1. human body model: 100pf capac itor discharged through a 1.5k resistor into each pin. machine model: 200pf capacitor discharged directly into each pin. electrical characteristics (2) -40c e t a e +125c, v cc = 5.0v unless otherwise not ed. specifications are subj ect to change without notice. notes: 2. these specifications ar e guaranteed only for the te st conditions listed. 3. this specification only indicates how often temperature information is updated to the temperature register. the fm75 can be read at any time without inte rrupting the temperature conversion process. 4. accuracy (expressed in c) = the di fference between the fm75 output temper ature and the meas ured temperature. parameter min. typ. max. units supply voltage +7 v output voltage v cc + 0.5 v output current 10 ma storage temperature range -60 +150 c lead soldering temperature 220 c esd (1) human body model machine model 2000 250 v v symbol parameter conditions min. typ. max. units t min , t max specified temperature range -40 +125 c temperature conversion time (3) 90 ms accuracy (4) t a = +25c t a = +100c t a = -40c (t min ) t a = +125c (t max ) -2 -3 -4 -4 +2 +3 +4 +4 c
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 4 logic electrical characteristics symbol parameter conditions min. typ. max. units v ih minimum input voltage logic high v dd x 0.7 v dd + 0.5 v v il maximum input voltage logic low -0.3 v dd x 0.3 v v ol maximum output voltage logic low v dd = 5v, i ol = -3ma v dd = 3v, i ol = -1.5ma 0.36 0.36 v v i dd quiescent supply current interface inactive r/w activity on sda 250 350 500 700 a i dd-sd shutdown current interface inactive r/w activity on sda 0.15 83 1 150 a i in input leakage current v in = 0v or 5v, t a = 25c -40c < t a < 125c 0.1 1.0 a i ol output sink current t a = 25c, v ol = 0.4v 3 ma i leak output leakage current v oh = 5v, v dd = 0v 0.001 5 a t f output transition time c l = 400pf, i ol = -3ma 250 ns c in input capacitance all digital inputs 20 pf
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 5 serial port timing figure 3. serial port timing diagram symbol parameter conditions min. typ. max. units t scl scl clock period 1.0 100 s t t: l h , t t: h l scl clock transition time 300 ns t low scl clock low period 0.470 s t high scl clock high period 0.400 50 s t buf bus free time between a stop and a new start condition 1.0 s t su:dat data in set-up to scl high 100 ns t hd:dat data in hold time 100 ns t hd data out stable after scl low 0 ns t su:sta scl low set-up to sda low (repeated start condition) 100 ns t hd:sta scl high hold after sda low (start condition) 100 ns t su:sto sda high after scl high (stop condition) 100 ns t por time in which a fm75 must be operational after a power-on reset 500 ms sda data in t hd:sta t scl t su:sto t su:dat t hd t hd:dat scl sda data out scl 10% 10% 90% t t:lh t t:hl t low t high t buf t su:sta 90%
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 6 basic operation the fm75 temperature sensing circuitry continuously produces analog voltage proportional to the device tem- perature. at regular interval s, the fm75 converts the analog voltage to a two?s complement digital value, which is placed into the temperature register. the fm75 has an smbus-compatible digital serial inter- face that allows access to the data in the temperature register at any time. in addit ion, the serial interface pro- vides access to all other fm 75 registers to customize operation of the device. the fm75 temperature-to-digital conversion can have 9, 10, 11, or 12-bit resolution selected, providing 0.5c, 0.25c, 0.125c, and 0.0625 c temperature resolution, respectively. at power-up, the default conversion resolu- tion is 9-bits. the conversion resolution is controlled by the r0 and r1 bits in the configuration register. table 1 gives examples of the relationship between the output digital data and the external temperature. the 9-bit, 10-bit, 11-bit, and 12-bit columns in table 1 indicate the right-most bit in the output data stream that can con- tain temperature information for each conversion accu- racy. since the output digital data is in two?s-complement format, the most significant bi t of the temperature is the ?sign? bit. if the sign bit is ze ro, the temperature is posi- tive; if the sign bit is one, the temperature is negative. the fm75 has a shutdown mode that reduces the oper- ating current to 150na. this mode is controlled by the sd bit in the configuration register. power-up default conditions the fm75 powers up in the following default state: ? thermostat mode: comparator mode ? os polarity: active low ? fault tolerance: 1 fault (i.e., f0 = 0 and f1 = 0 in the configuration register) ?t os : 80c ?t hyst : 75c ? register pointer: 00 (temperature register) ? conversion resolution: 9 bits (i.e., r0 = 0 and r1 = 0 in the configuration register) after power-up, these cond itions can be reprogrammed via the serial interface. refer to the serial data bus operation section for fm75 programming instructions. thermal alarm function the fm75 thermal alarm function provides programma- ble thermostat capability and allows the fm75 to function as a stand-alone thermostat without using the serial interface. the over-limit sig nal (os) output is the alarm output. this signal is an open-drain output and, at power-up, this pin is configured with active-low polarity. table 1. relationship between temperature and digital output the os polarity is controlled by the pol bit in the config- uration register. the programmable upper trip-point tem- perature for the thermal alarm is stored in the t os register. the programmable hysteresis temperature (i.e., the lower trip point) is stored in the t hyst register. the thermal alarm has two modes of operation: compar- ator mode and interrupt mode . at power-up, the default is comparator mode. the ala rm mode is controlled by the cmp/intr bit in the configuration register. fault tolerance for both comparator and interrupt modes, the alarm ?fault tolerance? setting plays a role in determining when the os output is activated. fault tolerance refers to the number of consecutive time s an error condition must be detected before the user is notified. higher fault toler- ance settings can help eliminate false alarms caused by noise in the system. the ala rm fault tolerance is con- trolled by bits f0 and f1 in the configuration register. these bits can be used to set the fault tolerance to 1, 2, 4, or 6, as shown in table 4. at power-up, these bits both default to 0 (fault tolerance = 1). temperature digital output g i s f o r e b m u n d e s u s t i b y b n o i s r e v n o c n o i t u l o s e r t i b 9 t i b 0 1 t i b 1 1 t i b 2 1 s y a w l a o r e z l l a s e r u t a r e p m e t n o i t u l o s e r t i b - 2 1 0 0 0 0 n o i t u l o s e r t i b - 11 0 0 0 0 0 n o i t u l o s e r t i b - 10 0 0 0 0 0 0 n o i t u l o s e r t i b - 9000 0 0 0 0 c 5 2 1 + 01 1 11 0 1 10000 0 0 0 0 c 5 2 6 0 . 0 0 1 + 00 1 10 0 1 00001 0 0 0 0 c 5 2 1 . 0 5 + 01 1 00 1 0 00010 0 0 0 0 c 5 2 . 2 1 + 00 0 00 0 1 10100 0 0 0 0 c 0 00 0 00 0 0 00000 0 0 0 0 c 5 . 0 2 - 10 1 11 1 0 11000 0 0 0 0 c 5 2 . 3 3 - 11 0 10 1 1 11100 0 0 0 0 c 5 2 6 0 . 5 4 - 11 0 10 1 0 01111 0 0 0 0 c 5 5 - 10 0 11 0 0 10000 0 0 0 0
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 7 comparator mode in comparator mode, each time a temperature-to-digital (t-to-d) temperature conversion occurs, the new digital temperature is compared to the value stored in the t os and t hyst registers. if a fault tolerance number of con- secutive temperature meas urements are greater than the value stored in the t os register, the os output is acti- vated. for example, if bits f1 and f0 are equal to ?10? (fault tolerance = 4), four consecutive temperature mea- surements must exceed t os to activate the os output. once the os output is active, it remains active until the first time the measured temperature drops below the temperature stored in the t hyst register. the operation of the alarm in comparator mode with fault tolerance = 2 is illustrated in figure 4. interrupt mode in interrupt mode, the os output first becomes active after a fault tolerance number of consecutive tempera- ture measurements exceed the value stored in the t os register (similar to comparator mode). once os is active, it can only be cleared by a user read from any of the fm75 registers (temperat ure, configuration, t os , or t hyst ) or by putting the fm75 into shutdown mode (i.e., by setting the shutdown bit in the configuration register to ?1?). once cleared, the os output can only be activated the next time by a fault tole rance number of consecutive temperature measurements lower than the value stored in t hyst . once it is activated, the os output can only be deactivated by a user read or shutdown. in interrupt mode, the activate/clear cycl e for os has the following pattern: temperature > t os , clear, temperature < t hyst , clear, temperature > t os , clear, etc. the operation of the alarm in interrupt mode with fault tolerance = 2 is illus- trated in figure 4. figure 4. thermal alarm operation in comparator and interrupt modes for this example: fault tolerance = 2 output polarity = active low read (or shutdown) t os t hyst temperature-to-digital conversion os (comparator mode) os (interrupt mode)
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 8 registers the fm75 contains the following five registers: command register temperature register configuration register over-limit-signal temperature register (t os ) hysteresis temperature register (t hyst ) all of these registers can be accessed by the user via the digital serial interface at any time (see serial interface operation for instructions) . a detailed description of these registers and their functions is provided in the fol- lowing sections. a diagram of the register hierarchy is shown in figure 5. figure 5. register hierarchy command register the command register is a one-byte (8-bit) write-only register. the data stored in the command register indi- cates which of the other regi sters (temperature, configu- ration, t os , or t hyst ) to read from or write to during an upcoming operation. the comm and register ?points? to the selected register, as shown in figure 11. the command register is illustrated in figure 9. the p1 and p0 bits of the command register determine which register is accessed, as shown in table 2. the six most significant bits (msbs) of the command register must always be zero. writing a one into any of these bits causes the current opera tion to be terminated. the command register retains pointer information between operations; therefore, this register only needs to be updated once for consec utive read operations from the same register. all bits in the command register default to zero at power-up. figure 6. command register format table 2. register as signments for command bits p1 and p2 serial interface command register 1-byte write only temperature register 2-byte read only command reg. = 00000000 configuration register 1-byte read/write command reg. = 00000001 t hyst register t os register 2-byte read/write command reg. = 00000010 2-byte read/write command reg. = 00000011 command (p ointer) data read/write data sd a scl register p1 p0 temperature register 0 0 configuration register 0 1 t hyst register 1 0 t os register 1 1 0 0 0 000 p1 p0 msb lsb
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 9 temperature register the temperature register is a two-byte (16-bit) read-only register. digital temperatures from the t-to-d converter are stored in the temperature register in two?s comple- ment format and the contents of this register are updated at regular intervals, each time the t-to-d conversion is finished. the user can read data from the temperature register at any time. when a t-to-d conversion is completed, the new data is loaded into a comparator buffer to evaluate fault conditions and updates th e temperature register if a read cycle is not ongoing. the fm75 is continuously evaluating fault conditions regardless of read or write activity on the bus. if a read is ongoing, the previous temperature is read. t he readable temperature is updated upon the completion of the next t-to-d conver- sion not masked by a read cycle. the temperature register is illustrated in figure 7. depending on the resolution of the t-to-d conversion, the 9, 10, 11, or 12 msbs of the register contain temper- ature data. all unused bits following the digital tempera- ture are zero. the msb position of the temperature register always contains the sign bit for the digital tem- perature and bit 14 contains the temperature msb. bits in the temperature register default to zero at power-up. sb = two?s complement sign bit tmsb = temperature msb t = temperature data 9-bit lsb = temperature lsb for 9-bit conversions 10-bit lsb = temperature lsb for 10-bit conversions 11-bit lsb = temperature lsb for 11-bit conversions 12-bit lsb = temperature lsb for 12-bit conversions figure 7. temperature register format configuration register the configuration register is a one-byte (8-bit) read/write register (see figure 8). this register allows the user to control the fm75 shutdown mode as well as the follow- ing thermal alarm features: polarity, operating mode, and fault tolerance. the configuration register contains two bits that set the fault tolerance trip point. the fault toler- ance trip point is the number of consecutive times the internal circuit reads the te mperature and finds the tem- perature outside the limits programmed. the pro- grammed limits are defined by the t os register for the upper limit and by the t hyst register for the lower limit. table 4 shows the relationship between f1 and f0 and the number of consecutive errors or ?trips? needed to activate the alarm. the configuration register also con- tains the two bits that set the t-to-d conversion resolu- tion to 9, 10, 11, or 12 bits. table 3 shows the relationship between r1 and t0 and the conversion res- olution. all bits in the conf iguration register default to zero at power-up. r1 = resolution bit 1 (see table 3). r0 = resolution bit 0 (see table 3). f1 = fault tolerance bit 1 (see table 4). f0 = fault tolerance bit 0 (see table 4). pol = os output polarity: 0 = active low, 1 = active high. cmp/int = thermostat mode: 0 = comparator mode, 1 = inerrupt mode. sd = shutdown: 0 = norma l operation, 1 = shutdown mode. figure 8. configuration register format table 3. conversion resolution settings table 4. fault tolerance settings sb tmsb t ttt t t msb 8 14 13 12 11 10 9 9-bit lsb 00 0 0 7 lsb 6 5 4 3 2 1 10-bit lsb 11-bit lsb 12-bit lsb a-to-d conversion resolution r1 r0 9 bits 0 0 10 bits 0 1 11 bits 1 0 12 bits 1 1 fault tolerance r1 r0 100 201 410 611 x r1 r0 f1 f0 pol cmp/ int sd msb lsb 6 543 21
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 10 over-limit signal temperature register (t os ) the t os register is a two-byte (16-bit) read/write register that stores the user-programmable upper trip-point tem- perature for the thermal alarm in two?s-complement for- mat. at power-up, this register defaults to 80c (i.e. 0101 0000 0000 0000). the format of the t os register is identical to that of the temperature register (see figu re 9). the four lsbs of the t os register are hardwired to zero, so data written to these register bits is ignored. the msb position of the t os register contains the sign bit for the digital tempera- ture and bit 14 contains the temperature msb. the resolution setting for the t-to-d conversion deter- mines how many bits of the t os register are used by the thermal alarm. for example, for 9-bit conversions, the trip-point temperature is defi ned by the nine msbs of the t os register and all remaining bits are ignored. hysteresis temperature register (t hyst ) the t hyst register is a two-byte (16-bit) read/write regis- ter that stores the programmable lower trip-point temper- ature for the thermal alarm in two?s-complement format. at power-up, this register defaults to 75c (i.e. 0100 1011 0000 0000). the t hyst register is illustrated in figure 9. the format of this register is the same as that of the temperature register. the four lsbs of the t hyst register are hard- wired to zero, so data written to these bits is ignored. the resolution setting for the t-to-d conversion deter- mines how many bits of the t hyst register are used by the thermal alarm. for example, for 9-bit conversions, the hysteresis temperature is defined by the nine msbs of the t hyst register and all remaining bits are ignored. . figure 9. t hyst register and t os register format sb tmsb t ttt t t msb 8 14 13 12 11 10 9 9-bit lsb 00 0 0 7 lsb 6 5 4 3 2 1 10-bit lsb 11-bit lsb 12-bit lsb sb = two?s complement sign bit tmsb = temperature msb t = temperature data 9-bit lsb = temperature lsb for 9-bit conversions 10-bit lsb = temperature lsb for 10-bit conversions 11-bit lsb = temperature lsb for 11-bit conversions 12-bit lsb = temperature lsb for 12-bit conversions
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 11 serial data bus operation general operation writing to and reading from the fm75 registers is accom- plished via the smbus-compatible two-wire serial inter- face. smbus protocol requires that one device on the bus initiates and controls all read and write operations. this device is called the ?master? device. the master device also generates the scl signal, which is the clock signal for all other devices on the bus. all other devices on the bus are called ?slave? devices. the fm75 is a slave device. both the master and slave devices can send and receive data on the bus. during smbus operations, one data bit is transmitted per clock cycle. all smbus operations follow a repeating nine clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ack) or not acknowledge (nack) from the receiving device. note that there are no unu sed clock cycles during any operation?therefore there mu st be no breaks in the stream of data and acks/nacks during data transfers. conversely, too few clock cycles can lead to incorrect operation if an inadvertent 8-bit read from a 16-bit regis- ter occurs. for most operations, smbus protocol requires the sda line to remain stable (unmoving) whenever scl is high? i.e., transitions on the sda lin e can only occur when scl is low. the exceptions to this rule are when the master device issues a start or stop signal. the slave device cannot issue a start or stop signal. start condition: this condition occurs when the sda line transitions from high to low while scl is high. the master device uses this condition to indicate that a data transfer is about to begin. stop condition: this condition occurs when the sda line transitions from low to high while scl is high. the master device uses this condition to signal the end of a data transfer. acknowledge and not acknowledge: when data is transferred to the slave device, it sends an acknowledge (ack) after receiving every byte of data. a master device sends an acknowledge (ack) following only the first byte read from a two-byte register. the receiving device sends an ack by pulling sda low for one clock cycle. following the last byte, a master device sends a ?not acknowledge? (nack) followed by a stop condition. a nack is indicated by leaving sda high during the clock after the last byte. slave address each slave device on the bus has a unique 7-bit address so the master can identify which device is sending or receiving data. the fm75 address is as follows: the four msbs of the fm75 address are hardwired to 1001. the three lsbs are user configurable by tying the a0, a1, and a2 pins to either v dd or ground. this pro- vides eight different fm75 addresses, which allows up to eight fm75s to be connected to the same bus. writing to and reading from the fm75 all read and write operations must begin with a start sig- nal generated by the master device. after the start condi- tion, the master device must immediately send a slave address (7 bits), followed by a read/write bit. if the slave address matches the address of the fm75, the fm75 sends an ack after receiving the read/write bit by pulling the sda line low for one cl ock cycle. figures 11 -16 provide timing diagrams for all fm75 operations. setting the pointer for all operations, the pointer stored in the command register must be pointing to the register (temperature, configuration, t os or t hyst ) that is going to be written to or read from. to change the pointer value in the com- mand register, the read/writ e bit following the address must be 0. this indicates th at the master will write new information into the command register. after the fm75 sends an ack in response to receiving the address and read/write bit, the master device must transmit an appropriate 8-bit pointer value, as explained in the registers section. the fm75 sends an ack after receiving the new pointer data. the pointer set operation is illustrated in figure 11. any- time a pointer set is perform ed, it must be immediately followed by a read or write operation. note that the six msbs of the pointer value must be zero. if the six msbs are not zero, the fm75 does not send an ack and inter- nally terminates the operation. the command register retains the current pointer value between operations; therefore, once a register is indicated, subsequent read operations do not require a po inter set cycle. write oper- ations always require the pointer be reset. 1 0 0 1a1 a2 a0
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 12 reading if the pointer is already pointing to the desired register, the master can read from that register by setting the read/write bit (following the slave address) to a one. after sending an ack, the fm75 begins transmitting data dur- ing the following clock cycle. if the configuration register is being read, the fm75 transmits one byte of data (see figure 13). the master should respond with a nack, fol- lowed by a stop condition. if the temperature, t os, or t hyst register is being read, the fm75 transmits two bytes of data (see figure 12). the master must respond to the first byte of data with an ack and to the second byte of data with a nack followed by a stop condition. to read from a register other than the one currently indi- cated by the command regist er, a pointer to the desired register must be set. immediately following the pointer set, the master must perform a repeat start condition (see figure 11 and figure 15), which indicates to the fm75 that a new operation is about to occur. if the repeat start condition does not occur, the fm75 assumes that a write is taking place and the selected register is overwritten by the upcoming data on the data bus. after the start condition, the mast er must again send the device address and read/write bi t. this time, the read/ write bit must be set to one to indicate a read. the rest of the read cycle is the same as described in the previous paragraph for reading from a preset pointer location. writing all writes must be proceeded by a pointer set, even if the pointer is already pointing to the desired register. immediately following the pointer set, the master must begin transmitting the data to be written. if the master is writing to the configuration register, one byte of data must be sent (see figure 16). if the t os or t hyst regis- ter is being written, the master must send two bytes of data (see figure 14). after transmitting each byte of data, the master must release the serial data (sda) line for one clock cycle to allow the fm75 to acknowledge receiving the byte. the write operation should be termi- nated by a stop signal from the master. caution: inadvertent 8-bit read from a 16-bit register an inadvertent 8-bit read from a 16-bit register, with the d7 bit low, can cause the fm75 to pause in a state where the sda line is pulled low by the output data and is incapable of receiving eit her a stop or a start condition from the master. the only way to remove the fm75 from this state is to continue cl ocking for nine cycles until sda goes high, at which time issuing a stop condition resets the fm75, shown in figure 10. figure 10. inadvertent 8-bit read from 16-bit register where d7 = 0 and forces output low d7 d6 d5 d4 d3 d2 d1 d0 d7 address byte most significant data byte (from fm75) 1 0 0 1 a2 a1 a0 r/w master must detect error condition on fm75 a n nine additional clock cycles to reset the fm75 ack from fm75 no ack from master no ack from master start from master scl sda stop intended by master, but fm75 sda line locked low d6 d5 d4 d3 d2 d1 d0 n stop condition from master
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 13 timing diagrams figure 11. pointer set followed by immediate read from a two-byte register (temperature, t os , or t hyst register) figure 12. two-byte read from preset pointer lo cation (tem perature, t os , or t hyst register) figure 13. one-byte read from configuration register with preset pointer 000 00 0 p1 p0 a2 a1 a0 address byte pointer byte 11 00 r/w s a a ack from fm75 ack from ats75 . . . . . . . . note: this segment of this timing diagram is a generic pointer set cycle that must be followed by either an immediate read cycle or write cycle, as shown in this figure and in figures 10, 11, and 12. scl sda most significant data byte ( from fm75 ) least significant data byte (from fm75) d7 d6 d5 d4 d3 d2 d1 d0 a2 a1 a0 d7 d6 d5 d4 000 0 address byte 11 0 0 r/w s p aa n ack from fm75 ack from master no ack from master repeat start from master . . . . . . scl sda d7 d6 d5 d4 d3 d2 d1 d0 a2 a1 a0 d7 d6 d5 d4 0 0 0 0 address byte most significant data byte (from fm75) 11 0 0 r/w least significant data byte (from fm75) s p aan ack from fm75 ack from master no ack from master scl sda x d6d5 d4 d3d2d1d0 a2 a1 a0 address byte data byte ( from fm75 ) 11 0 0 r/w s p an ack from fm75 no ack from master scl sda
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 14 timing diagrams (continued) figure 14. pointer set followed by imme diate write to a 2-byte register (t os or t hyst register) figure 15. pointer set followed by immediate read from configuration register figure 16. pointer set followed by immediate write to the configuration register scl a ack from fm75 000 000 p1 p0 a2 a1 a0 address byte pointer byte 11 00 r/w s a ack from fm75 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 0 0 0 0 most significant data byte (from master) least significant data byte (from master) p a a ack from fm75 ack from fm75 . . . . . . . . . . . . . . . . a sda a2 a1 a0 address byte 11 0 0 r/w s repeat start from master 000000p1 p0 a2 a1 a0 address byte pointer byte 11 0 0 r/w saa ack from fm75 ack from fm75 a2 a1 a0 address byte (repeated here for clar ity, transmitted only once in the actual sequence ) 1 0 r/w a ack from fm75 xd6 d5 d4 d3 d2 d1 d0 data byte (from fm75) p n no ack from master 10 scl sda . . . . . . . . data byte ( from master ) address byte x d6 d5 d4 d3 d2 d1 d0 p a ack from fm75 00 0 000p1 p0 a2 a1 a0 pointer byte 11 00 r/w sa a ack from fm75 ack from fm75 scl sda
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 15 mechanical dimensions dimensions are in inches (millim eters) unless otherwise noted. figure 17. molded package, small outline, 0.15 wide, 8-lead (m8)
fm75 low-voltage two-wire digital temperature sensor with thermal alarm ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fm75 rev. 1.0.8 16

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