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rt9643 1 ds9643-04 april 2011 www.richtek.com features z z z z z integrated 5 channels power regulator ` ` ` ` ` dc/dc buck pwm regulator for v ddq (2.5v or 1.8v) ` ` ` ` ` linear regulator supports 1.5amp peak sinking/ sourcing capability for vtt ` ` ` ` ` 1.2v ultra-low-dropout linear controller for gmch vtt power ` ` ` ` ` 3.3vsb linear regulator supports 1.25a capability ` ` ` ` ` 5vdl switch control ` ` ` ` ` 3vdl switch control z z z z z conform to acpi specification ` ` ` ` ` support power management at s0, s3, and s5 state z z z z z 300khz fixed frequency switching z z z z z r ds(on) current sensing or optional current sense resistor for precision over current detect z z z z z embedded synchronous boot-strapped diode z z z z z power good signal indication for all voltages z z z z z thermal shutdown z z z z z 24-lead vqfn package z z z z z rohs compliant and 100% lead (pb)-free applications z ddr vddq and vtt voltage generator with acpi support z desktop system power z servers system power 5 channel acpi regulator with step-down dc/dc controller ordering information pin configurations (top view) vqfn-24l 5x5 general description the rt9643 is a combo regulator which is compliant to acpi specification for desktop/motherboard power mana gement and system application. the part features one switch regulator for ddr memory vddq power; three linear regulators including 1.5amp peak sourcing/sinking capability regulator for ddr vtt, a 1.2v ultra-low-dropout linear controller for chipset miscellaneous power, a 3.3vsb power with 1.25amp peak current capability; and 2 dual power control including 5vdl, and 3.3vdl control for s3 and s5 system power. the part totally feature 5 sets power which are compliant to acpi specification into a single small footprint package vqfn-24l 5x5. the part is generally operated to conform to acpi specification, in s3 state, there are o nly vddq and 3.3vsb regulators remain on while the vtt and uldo regulators are off. in the transition from s3 to s0, an external ss capacitor is attached for linear regulators to control its slew rates respectively to avoid inrush current induced. moreover, the pgood signal raises high in s0 stage while all 3 regulators go stable. in the stage of s5 (en = 0), there only 3.3vsb ldo remain on, while the other regulators are powered down. the vddq pwm regulator is a voltage mode implementation with external compensation to provide high load transient response. the vtt is regulated to follow 1/2 of vddq and is capable of sourcing or sinking 1.5a peak currents. note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. 1.2v_drv vtt_sns vtt_out 5v_main 5vsb_drv 1.2v_fb vcc_en pgood vcc 3vsb_out s3#i en 1 2 3 4 5 6 17 16 15 14 13 78910 12 11 18 vddq_in boot phase ugate isns lgate 22 21 20 19 24 23 gnd ref_in fb comp ss ilim gnd 25 package type qv : vqfn-24l 5x5 (v-type) rt9643 lead plating system p : pb free g : green (halogen free and pb free)
rt9643 2 ds9643-04 april 2011 www.richtek.com typical application circuit operation the rt9643 provides 5 functions: 1. a general purpose pwm regulator, used to generate vddq power for ddr memory. 2. a source-sink linear vtt regulator capable of sinking and sourcing 1.5a peak(minimum). 3. an adjustable low drop out controller which, in conjunction with an external n-channel power mosfet, provides a programmable low voltage output. it normally provides 1.2v for gtl fsb termination voltage. 4. generating a 5v dual voltage using an external n-channel to supply power from 5v main in s0, and an external p-channel to provide power from 5v standby (5vsb) in s3. 5.an internal ldo which regulates ? 3v dual ? in s3 mode from vcc(vsb). in s3, this regulator is capable of 1.25a peak currents with current limit protection (2a typ.). 100k pull up resistor to v out to obtain an output voltage. when the output voltage arrive 90% of normal value the power good will output voltage with 3ms delay time. when the output voltage falling arrive 75% of normal value the power good will turn off with less than 1ms delay time. but, there are two exceptions. one is the enable pull low the power good will turn off quickly. the second is the v cc falling arrive por value (4v typ.) the power good also will turn off quickly. v d d q q1 q2 c1 rt9643 vcc_en pgood phase 5v_main lgate isns gnd vcc 16 3 4 9 10 19, exposed pad (25) c o u t l 1 boot ilim ss 3vsb_out 17 8 23 q3 5vsb_drv 1.2v_fb 15 1.2v_drv r3 r1 r6 c5 c9 c6 r2 r9 c11 c10 r10 c8 c7 c2 12v r4 5v_main 5v dual q4 5vsb 3.3 main q5 c12 r7 r8 q6 1.2 out c17 vddq 5vsb c4 c3 r5 l2 ugate fb comp vddq_in vtt_sns ref_in vtt_out en chip enable s3#i > 11 12 22 7 5 24 6 18 13 20 21 14 1 2 c13 3v dual
rt9643 3 ds9643-04 april 2011 www.richtek.com table 1. while s5s0s3 state s3#i en(s5#) vcc_en 5vsb_drv vddq vtt_out 1.2 out 3v dua l 5v dual s5 x l l l off off off on off s3 l h l l on off off on +5vsb s0 h h h h on on on off +5vmain start up sequencing the vcc pin provides power to all logic and analog control functions of the regulator including : after vcc is above uvlo, the start-up sequence begins as shown in figure 1. figure 1 t0 to t3 : after initial power-up, the ic will ignore all logic inputs for a time period (t3-t0) of about : the 3v dual ldo is in regulation. the 3.3v ldo ? s slew rate is limited by the discharge slope of c ss . if 3v main has come up prior to this time, the 3v dual node will already be pre-charged through the body diode of q5 (see figure 1). t3 to t4 : the ic waits about 100 s before initiating soft-start on vddq to allow c ss time to fully discharged. the ic is in ? sleep ? or s5 state when en is low. in s5 only the 3.3v ldo is on. if the ic is in s5 at t4, c ss will be held to 0v. t4 to t5 : while first time to enter s0 , the ic will start vddq only if 5v_main is above its uvlo threshold (5v_main o.k.) and s3#i is high. t5 to t7 : after vddq is stabilized (when c ss is above about 1.5v) which will allow the 1.2v ldo and the vtt ldo to soft start. to ensure that the vddq output is not subjected to large transient currents during transition, the vtt and 1.2v ldo slew rates are limited by the slew rate of the c ss until the ldo is in regulation. in addition, the vtt regulator is current limited. t8 (s0 to s3) : dropping the s3#i signal. when this occurs, vcc_en goes low , and the 3.3v ldo turns on. the 1.2v ldo and the vtt ldo are turned off, and c ss is discharged to 2v. 5vsb_drv pulls low to turn on the p-channel 5v dual switch. 5 c x 6.5 t0 - t3 ss = uvlo ~4v 1.5v 2.0v 2.5v t0 t1 t2 t3 t4 t5 t6 t7 t8 5vsb ss vddq 3v dual vtt_out/ 1.2 out
rt9643 4 ds9643-04 april 2011 www.richtek.com to eliminate the ? bump ? add delay to the 5v_main pin as shown below. the 5v_main pin on the rt9643 does not supply power to the ic, it is only used to monitor the voltage level of the 5v_main supply. figure 2. s3 to s0 transition (5v dual) figure 3. adding delay to 5v_main another method to eliminate the potential for this ? bump ? is to use the pwr_ok to drive the 5v_main pin. some systems cannot tolerate the long delay for pwr_ok (>100ms) to assert, hence the solution in figure c may be preferable. s5 to s3 : during s5 to s3 transition, the ic will pull 5vs b_drv low with 500na curr ent sink to limit inrush in q4 if 5v main is below its uvlo threshold. at that time, 5v dual is charged. the limited gate drive controls the inrush current through q4 as it charges c1 (capacitance on 5v dual). depending on the cgd of q4, the current available from 5vsb, and the size of c1, c13 may be omitted. gd(q4) 7 q4(inrush) c c13 10 x 5 x c1 i + = ? s3 to s0 : the system signals this transition by raising the s3#i signal. s0 mode is not entered until 5v_main o.k.. then the following occurs : vcc_en rele ases and pull high by external resistor. 5vsb_drv pulls high to turn off the p-channel switch. the 3.3v ldo turns off. the 1.2v ldo and the vtt ldo are turned on and c ss is allowed to charge up in most systems, the atx power supply is enabled when s3#i goes to high. at that point, 5v_main and 3.3 main will start to rise. the rt9643 waits until 5v_main is above 4.5v to turn on q3 and q5. this can cause about a 10% ? bump ? in both 5v dual and 3.3v dual when q3 and q5 turn on, since at that point, 5v_main and 3.3 main are at 90% of their regulation value. 4.4v 5v dual 5v_main vcc_en s3#i 5v_main from atx 5v_main to rt9643
rt9643 5 ds9643-04 april 2011 www.richtek.com component description qty ref vendor see notes below cout see notes below c1,c12,c17 capacitor 1 f, 10%, 16vdc, x7r, 0603 2 c2,c4 tdk capacitor 10nf, 10%, 50vdc, x7r, 0603 1 c3 tdk capacitor 10nf, 10%, 16v, x7r, 0603 1 c6 walsin capacitor 220pf, 10%, 50vdc, npo, 0603 1 c9 walsin capacitor 10nf, 10%, 50vdc, x7r, 0603 2 c10, c11 tdk capacitor 220nf,10%, 10vdc, x7r, 0603 1 c5 walsin capacitor 100nf, 10%, 25vdc, x7r, 0603 1 c8 walsin inductor 1.8 h, 3.24m, 16 amps 1 l1 inter-technical inductor 0.39uh, 2.8m , 15 am ps 1 l2 inter-technical mosfet n-ch, 8.8m, 30v, 50a, d-pak, fsid: fdd6296 1 q1 fairchild mosfet n-ch, 6m, 30v, 75a, d-pak, fsid: fdd6606 1 q2 fairchild mosfet n-ch, 32m, 20v, 21a, d-pak, fsid: fdd6530a 3 q3,q5,q6 fairchild mosfet p-ch, 35m, -20v, -5.5a, ssot-6, fsid : dc602p 1 q4 fairchild resistor 1.82k, 1%, 0805 4 r1,r2,r9,r10 yageo resistor 56k, 1%, 0805 1 r5 any resistor 11.8k, 1%, 0805 1 r6 any resistor 3.01k, 1%, 0603 1 r7 any resistor 9.09k, 1%, 0603 1 r8 any resistor 10k, 1%, 0805 1 r4 any resistor 1k, 1%, 0805 1 r3 any rt9643 1 u1 richtek table 3. b.o.m of the application circuit
rt9643 6 ds9643-04 april 2011 www.richtek.com function block diagram functional pin description 1.2v_drv (pin1) gate drive for 1.2v linear controller. the pin will be turned off (low) in s3 and s5 state. 1.2v_fb (pin2) feedback for the 1.2v linear controller. the pin is applied for 1.2v ldo output regulation sense. the voltage can be disabled by pulling the pin higher than 0.9v. 5vsb_drv (pin3) 5vsb control switch. the pin is applied to drive an external p-channel mosfet to switch 5vdl power to 5vsb in s3 stage. the pin goes high in s0 and s5. 5v_main (pin4) 5v main power. when this pin is below 4.5v, transition from s3 to s0 is inhibited. vtt_sns (pin5) remote sense for vtt. the pin is applied to remote sense the output voltage of vtt. vtt_out (pin6) output of vtt. regulator power vtt output. vddq_in (pin7) input of external vddq. input power of vtt, the vtt is implemented to tracking 1/2 vddq. boot (pin8) pwm boot. the pin is applied for vddq pwm boot- strapped power for the embedded driver power. ugate (pin9) high side drive. high side mosfet driver output of vddq pwm. connect to gate of high side mosfet. soft-start and control circuit gate control uvl uv vr oc ra oscillator pgood vdd + + + + + + + + vcc fb vtt_sns fb1.2 boot ugate lgate phase isns gnd fb vddq_in vtt_ot vtt_sns ref_in ilim ss 3vsb_out 1.2v_fb 1.2v_drv pgood vcc vcc_en 5v_main s3#i en 5vsb_drv comp
rt9643 7 ds9643-04 april 2011 www.richtek.com phase (pin10) phase node of vddq pwm. the pin is applied to sense phase node of vddq pwm for gates switch control. isns (pin11) current sense input. monitors the voltage drop across the low side mosfet or external sense resistor for over current control. lgate (pin12) low side drive. the low side mosfet driver output. connect to gate of low side mosfet. pgood (pin13) power good indication signal. an open-drain output signal that will pull low if fb is outside of a 10% range of the 0.9v reference and the ldo outputs are > 80% or < 110% of its reference. pgood goes low when s3 is high. the power good signal from the pwm regulator enables the vtt regulator and the ldo controller. vcc (pin14) ic vcc. 5vsb is generally applied for bias power for ic logics and gate driver control. the ic stays at standby until this pin is higher than 4.35v. 3vsb_out (pin15) 3.3vsb ldo output. internal linear regulator and is capable to drive up to 1.25amp peak current. the power is turned off in s0 state, and on in s5 or s3 stage. vcc_en (pin16) vcc enable signal for dual power. the pin is applied to control vcc power on for 3.3vdl and 5vdl, the signal is an open drain output which pulls the gate of an two n- channel blocking mosfets low in s5 and s3. this pin goes high (open) in s0. s3#i (pin17) s3 input. when low, the vtt and 1.2v ldo regulators are turned off and 3.3vsb regulator is turned on the. pgood is set to low when s3#i is low . en (pin18) chip enable. typically tied to s5#. when this pin is low, the ic is operated in standby mode, all regulators are off and vcc_en is low. gnd [pin19, exposed pad (25)] ic ground. the ground power for whole chip. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. ilim (pin20) current limit setting pin. a external resistor is attached to set the current limit value. ss (pin21) soft start. a external capacitor is attached to control the slew rate of the converter during initialization as well as sets the initial slew rate of the ldo controllers when transitioning from s3 to s0. this pin is charged/discharged with a internal 5ua current source during initialization, and charged with 50ua during pwm soft-start. comp (pin22) compensation pin of vddq pwm. output of the pwm error amplifier. connect compensation network between this pin and fb. fb (pin23) vddq pwm feedback. the output feedback of vddq pwm. the pin is applied for voltage regulation, pgood, under voltage, and over-voltage protection and monitoring. ref_in (pin24) vtt voltage setting. the vtt regulator tracks the voltage set the pin, typically, it should be 1/2vddq
rt9643 8 ds9643-04 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply input voltage, v cc ----------------------------------------------------------------------------- 6.5v z phase voltage ------------------------------------------------------------------------------------------ gnd ? 5v to 24v z ugate voltage ------------------------------------------------------------------------------------------- v phase ? 0.3v to v boot + 0.3v z lgate v oltage ------------------------------------------------------------------------------------------- gnd ? 0.3v to v cc + 0.3v z boot to gnd -------------------------------------------------------------------------------------------- 24v z vcc_en to gnd ----------------------------------------------------------------------------------------- 24v z boot to phase ---------------------------------------------------------------------------------------- 6.5v z boot to ugate ----------------------------------------------------------------------------------------- 6.5v z ugate to phase --------------------------------------------------------------------------------------- 6.5v z input, output or i/o voltage --------------------------------------------------------------------------- gnd ? 0.3v to v cc + 0.3v z storage temperature range --------------------------------------------------------------------------- ? 65 c to 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------- 260 c z junction temperature range -------------------------------------------------------------------------- ? 20 c to 125 c z power dissipation, pd @ t a = 25 c vqfn-24l 5x5 -------------------------------------------------------------------------------------------- 1.923w z package thermal resistance (note 2) vqfn-24l 5x5, ja -------------------------------------------------------------------------------------- 52 c/w z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------- 2kv mm (machine mode) ------------------------------------------------------------------------------------ 200v recommended operating conditions (note 4) z supply voltage, v cc ------------------------------------------------------------------------------------ 5v 10% z ambient temperature range -------------------------------------------------------------------------- ? 10 c to 85 c electrical characteristics (rocommended operating conditions, unless otherwise specification) parameter symbol test condition min typ max unit converter & por lgate, ugate open, fb > 0.9, i(vtt) = 0, en = 1, s3#i = 1 -- 6 24 ma en = 1, s3#i=low, i(3.3)< 10ma -- 6 24 ma vcc current i vcc en = 0, i( 3.3) = 0 -- 2 4 ma rising v cc 4.0 4.2 4.4 v falling 3.9 4.05 4.2 v vcc uvlo threshold hyst eresis -- 150 -- mv rising 4.3 4.4 4.6 v falling 3.9 4.1 4.2 v 5v_mainuvlo threshold hyst eresis -- 300 -- mv to be continued
rt9643 9 ds9643-04 april 2011 www.richtek.com to be continued parameter symbol test condition min typ max unit oscillator frequency f osc 250 300 350 khz ramp amplitude pk-pk -- 1.8 -- v ramp offset -- 0.5 -- v reference and soft start internal reference voltage 0.891 0.900 0.909 v initial ramp after power-up -- 5 -- a soft start current during pwm/lod soft start -- 48 -- a ss discharge on resistance en = 0 -- 280 -- pwm converter load regulation i out from 0 to 16a -2 -- +2 % fb bias current 0.75 1 1.25 a under voltage shutdown 2 s noise filter 65 75 80 % isns over-current threshold rilim 145 170 195 a over voltage threshold 110 115 120 % pwm output driver sourcing -- 1.8 3 ugate output resistance sinking -- 1.8 3 sourcing - 1.8 3 lgate output resistance sinking -- 1.2 2 pgood (power good output) and control pins, vddq output lower threshold 2 s noise filter 86 -- 92 % upper threshold 2 s noise filter 108 -- 115 % pgood output low i pgood -- -- 0.5 v leakage current pull up to 5v -- -- 1 a vtt regulator vddq in current s0 mode, i vtt = 0 -- 35 70 ma i vtt = 0, t a = 25 c -20 -- 20 mv v ref in to vtt differential output voltage i vtt = 1.25a (pulsed) -40 -- 40 mv internal divider gain en=0 0.493 0.498 0.503 v/v vtt current limit pulse(300ms max ), t a = 25 c 1.5 3 4 a vtt leakage current s3#i = low ? 20 -- 20 a vtt sns input resistance vtt = 0.9v -- 110 -- k ? vtt pgood measured at vtt sns 80 -- 110 % drop-out voltage itt = 1.5a -0.8 -- 0.8 v
rt9643 10 ds9643-04 april 2011 www.richtek.com parameter symbol test condit ion m in typ m ax unit 1.2v ldo regulation i(1.2) from 0 to 5a 1.17 1.2 1.23 v drop-out voltage i(1.2 ) Q 5a, r ds(on) < 50m -- -- 0.3 v external gate drive v cc = 4.75v -- -- 4.5 v gate drive source current -- 1.2 -- ma gate drive sink current -- 1.2 -- ma fb 1.2v pgood threshold -- -- 0.8 v 3.3v ldo regulation i(3.3) from 0 to 1.25a, v cc > 4.75v 3.2 3.3 3.4 v drop-out voltage i(3.3) Q 1.25a -- -- 1.5 v control function s3#i, en input threshold 1 1.25 1.55 v s3#i, en input current -1 -- 1 a over-temperature shutdown -- 150 -- c over-temperature hysteresis -- 25 -- c v cc_en output low r ds(on) - - 170 300 vcc_en output high leakage v vcc _en = 12v -- 4 10 a 5vsb_drv output low resistance 5v_m ain ok - - 125 200 5vsb_drv sink current 5v_main < uvlo -- 500 -- na 5vsb_drvoutput high -- 820 1200 note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board (single-layer, 1s) of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is highly recommended. note 4. the operating conditions beyond the recommended range is not guaranteed.
rt9643 11 ds9643-04 april 2011 www.richtek.com source. the output voltage starts to go up when v css is larger than 0.4v. to prevent large duty cycles and high currents during the beginning of the pwm soft-start, once c ss has charged to 1.3v, the output voltage will be in regulation. the time it takes ss to reach 1.3v is : where t1.3 is in ms if c ss is in nf. the pwm regulator ? s latched faults are enabled until c ss charges up to 1.5v. when c ss reaches 2.5v, the vtt and 1.2v ldo will begin their soft-start ramps. after the vtt and 1.2v ldo regulators are in regulation, pgood is then allowed to go high (open). uvlo on v cc will discharge ss and reset the ic. current sensing section application information pwm regulator the rt9643 combines a single-phase synchronous buck pwm controller designed to drive two n-channel mosfets. it provides a highly accurate, programmable output voltage precisely regulated to low voltage requirement with an internal 0.9v reference. setting the output voltage the output voltage of the pwm regulator can be set in the range of 0.9v to 90% of its power input by an external resistor divider. the internal reference is 0.9v. the output is divided down by an external voltage divider to the fb pin (for example, r1 and r2 in typical application circuit). there is also a 1 a precision ( 5%) current sourced out of fb to ensure that if the pin is open, vddq will remain low. the output voltage therefore is : to minimize noise pickup on this node, keep the resistor to gnd (r2) below 2k. we selected r2 at 1.82k and solved for r1. the synchronous buck converter is optimized for 5v operation. oscillator the internal oscillator frequency is 300khz. the internal pwm ramp is reset on the rising clock edge. pwm soft start when the pwm regulator is enabled the circuit will wait until the vddq_in pin is below 100mv to ensure that the soft-start cycle does not begin with a large residual voltage on the pwm regulator output. when the pwm regulator is disabled, 50 is turned on from vddq_in to pgnd to discharge the output. the voltage at the positive input of the error amplifier is limited to v css which is charged with a 50 a current a 1 r1 0.9v v r2 0.9v out + ? = 1.82k 1.816k r2 a x 1 0.9 0.9) (v x r2 r1 out = ? ? = 50 c x 1.3 t ss 1.3 = the following discussion refers to figure 4. the current through r sense resistor (isns) is sensed shortly after low side mosfet is turned on. setting the current limit an isns is compared to the current established when a 0.9 v internal reference drives the ilim pin. r ilim , the r ds(on) of q2, and r sense determine the current limit : figure 4. current sense & limit - + current sense ilim x 10 0.9v ilim mirror 2.5v ilim det. r sense isns pgnd ilim r ilim ds(on) sense limit ilim r r x i 0.9 x 10 r = where i limit is the peak inductor current. since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the switching node side of r sense is an accurate representation of the load current.
rt9643 12 ds9643-04 april 2011 www.richtek.com ea c 1 r 2 fb ref v out comp z in c 2 c 3 r 3 + - r1 z fb figure 5. compensation network pgood signal pgood monitors the status of the pwm output as well as the vtt and 1.2v ldo regulators. pgood remains low unless all of the conditions below are met : 1. s3#i is high 2. ss is above 4v 3. fault latch is cleared 4. fb is between 90% and 110% of v ref 5. vtt and 1.2v ldo regulators are in regulation protection the converter output is monitored and protected against extreme overload, short circuit, over-voltage and under- voltage conditions. an internal ? fault latch ? is set for any fault intended to shut down the ic. when the ? fault latch ? is set, the ic will discharge vddq_in by driving l gate high until vddq_in < 0.5v. l gate will then go low until vddq_in > 0.8v. this behavior will discharge the output without causing undershoot (negative output voltage). when using the mosfet as the sensing element, the variation of r ds(on) causes proportional variation in the isns. this value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4%/ c (consult the mosfet datasheet for actual values), so the actual current limit set point will decrease proportional to increasing mosfet die temperature. a factor of 1.6 in the current limit set point should compensate for all mosfet r ds(on) variations, assuming the mosfet ? s heat sinking will keep its operating die temperature below 125 c. current limit (i limit ) should be set sufficiently high as to allow inductor current to rise in response to an output load transient. typically, a factor of 1.3 is sufficient. in addition, since i limit is a peak current cut-off value, we will need to multiply i load(max) by the inductor ripple current (20% is chosen). i limit > i load(max) x 1.6 x 1.3 x 1.2 gate driver section the adaptive gate control logic translates the internal pwm control signal into the mosfet gate drive signals providing necessary amplification, level shifting and shoot-through protection. also, it has functions that help optimize the ic performance over a wide range of operating conditions. since mosfet switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate to source voltages of both upper and lower mosfets. the lower mosfet drive is not turned on until the phase has decreased to less than approximately on e vt (~0.6volt). similarly, the upper mosfet is not turned on until the gate-to-source voltage of the lower mosfet has decreased to less than approximately one vt (~0.6 volt). this allows a wide variety of upper and lower mosfets to be used without a concern for simultaneous conduction, or shoot-through. there must be a low-resistance, low-inductance path between the driver pin and the mosfet gate for the adaptive dead-time circuit to work properly. any delay along that path will subtract from the delay generated by the adaptive dead-time circuit and shoot-through may occur. frequency loop compensation the loop is compensated using a feedback network around the error amplifier, which is a voltage output op amp. figure 5 shows a complete type3 compensation network. a type2 compensation configuration eliminates r3 and c3 and is shown in typical application circuit. type2 compensation can be used for most applications. for critical applications that require wide loop-bandwidth, and use very low esr output capacitors, type3 compensation may be required.
rt9643 13 ds9643-04 april 2011 www.richtek.com to discharge the output capacitors, a 50 load resistor is switched in from vddq_in to pgnd whenever the ic is in fault condition, or when en is low. after a latched fault, operation can be restored by recycling power or by toggling the en pin. under voltage shutdown if fb stays below the under voltage threshold for 2 s, the ? fault latch ? is set. this fault is prevented from setting the fault latch during pwm soft-start (ss < 1.5v). over current sensing if the circuit ? s current limit signal ( ? i lim det ? as shown in figure 4) i s high at the beginning of a clock cycle, a pulse skipping circuit is activated an d ugate is inhibite d. the circuit continues to pulse skip in this manner for the next 8 clock cycles. if at any time from the 9th to the 16 th clock cycle, the ? i lim det ? is again reached, the fault latch is set. if ? i lim det ? does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. this fault is prevented from setting the fault latch during soft-start (ss < 1.5v). 1. vddq_in (pwm output voltage) > 1v and 2. fb < 100mv any of these 3 faults will set the fault latch. these 3 faults can set the fault latch during the ss time (ss < 1.5v). to ensure that fb pin open will not cause a destructive condition, a 1 a current source ensures that the fb pin will be high if open. this will cause the regulator to keep the output low, and eventually result in an under-voltage fault shutdown (after pwm ss complete). over temperature protection rt9643 incorporates an internal over temperature circuit designed to protect the device during overload conditions. if the junction temperature reaches a nominal temperature of 150 c, the over temperature circuit will shut the chip. normal operation is restored at when the die temperature falls below 125 c with internal power on reset asserted, resulting in a full soft-start cycle. to accomplish this, the over temperature comparator should discharge the ss pin. vtt regulator the vtt regulator is a simple and high-speed linear regulator designed to generate termination voltage in double data rate (ddr) memory system. the regulator is capable of actively sinking or sourcing up to 1.25a while regulating an output voltage to within 40mv. the output termination voltage can be tightly regulated to track 1/2vddq_in by two internal voltage divider resistors (50k for each resistor) or two external voltage divider resistors from the output of the pwm regulator. the vtt regulator also incorporates a high-speed differential amplifier to provide ultra-fast response in line/ load transient. other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions. the vtt regulator is enabled when s3#i is high and the pwm regulator's internal pgood signal is true. the vtt regulator also includes its own pgood signal which is high when vtt_sns > 90% of ref_in. ldo controller the ldo controller combined with an external n-channel mosfet pass element is used to provide 1.2v for the figure 6. over current protection waveform time (10 s/div) ugate (10v/div) i l (10a/d iv) lgate (5v/div) pgood (5v/div) ovp / hs fault / fb short to gnd detection: a hs fault is detected when there is more than 0.5v from phase to pgnd 350ns after l gate reaches 4v (same time as the current sampling time). ovp fault detection occurs if fb > 115% vref for 16 clock cycles. during soft-start, the output voltage could potentially ? run away ? if either the fb pin is shorted to gnd or r1 is open. this fault will be detected if the following condition persists for more than 14 s during soft-start.
rt9643 14 ds9643-04 april 2011 www.richtek.com front-side bus gtl termination. the driving voltage on the gate drive pin can be pull up to within 0.5v of vcc. use low vth mosfet to assure rds(on) is small enough for full load operation. the soft start for the ldo is accomplished by clamping the input voltage to a smooth up-going ramp. the final input reference voltage after soft start is 0.9v. component selection components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum bom cost and maximum reliability. output inductor selection the selection of output inductor is based on the considerations of efficiency, output power and operating frequency. for a synchronous buck converter, the ripple current of inductor ( i l ) can be calculated as follows : generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. output capacitor selection the output capacitors determine the output ripple voltage ( v out ) and the initial voltage drop after a high slew-rate load transient. the selection of output capacitor depends on the output ripple requirement. the output ripple voltage is described as follows : for electrolytic capacitor application, typically 90~95% of the output voltage ripple is contributed by the esr of output capacitors. paralleling lower esr ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent esr and consequently the ripple voltage. input capacitor selection use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the mosfets. the buck converter draws pulsewise current from the input capacitor during the on time of upper mosfet. the rms value of ripple current flowing through the input capacitor is described as : the input bulk capacitor must be cable of handling this ripple current. sometime, for higher efficiency the low esr capacitor is necessarily. appropriate high frequency ceramic capacitors physically near the mosfets effectively reduce the switching voltage spikes. mosfet selection the selection of mosfets is based upon the considerations of r ds(on) , gate driving requirements, and thermal management requirements. the power loss of upper mosfet consists of conduction loss and switching loss and is expressed as : where t rise and t fall are rising and falling time of v ds of upper mosfet respectively. r ds(on) and q g should be simultaneously considered to minimize power loss of upper mosfet. the power loss of lower mosfet consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is express as : where t diode is the conducting time of lower body diode. special control scheme is adopted to minimize body diode conducting time. as a result, the r ds(on) loss dominates the power loss of lower mosfet. use mosfet with adequate r ds(on) to minimize power loss and satisfy thermal requirements. bypass capa citor notes input capacitor c1 is typically chosen based on the ripple current requirements. cout is typically selected based on both current ripple rating and esr requirement. c17 d) (1 c x l x f v x 8 1 esr x i v out 2 osc out l out ? + = d) (1 x d x i i out in(rms) ? = osc fall rise in out ds(on) out sw_upper _upper cond upper f x ) t (t x x v i 2 1 d x r x i p p p + + = + = osc diode f out osc in rr ds(on) out diode rr _lower cond lower f x t x x v i x 2 1 f x x v q d) (1 x r x i p p p p + + ? = + + = l x f x v v x ) v (v i osc in out out in l ? =
rt9643 15 ds9643-04 april 2011 www.richtek.com pwm layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. consider, as an example, the turn-off transition of the upper mosfet prior to turn-off, the upper mosfet was carrying the full load current. during turn-off, current stops flowing in the upper mosfet and is picked up by the low side mosfet or schottky diode. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selections, layout of the critical components, and use shorter and wider pcb traces help in minimizing the magnitude of voltage spikes. there are two sets of critical components in a dc-dc converter usin g the rt9643. the switching power components are most critical becaus e they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. the critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. the power components and the pwm controller should be placed firstly. place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. place the output inductor and output capacitors between the mosfets and the load. also locate the pwm controller near by mosfets. a multi-layer printed circuit board is recommended. figure 9 shows the connections of the critical components in the converter. note that the capacitors c in and c out each of them represents numerous physical capacitors. use a dedicated grounding plane and use vias to ground all critical components to this layer. apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes. use below pcb gerber files are our test board for your reference : copper filled polygons on the top and bottom circuit layers for the phase node, but it is not necessary to oversize this particular island. since the phase node is subjected to very high dv/dt voltages, the stray capacitance formed between these island and the surrounding circuitry will tend to couple switching noise. use the remaining printed circuit layers for small signal routing. the pcb traces between the pwm controller and the gate of mosfet and also the traces connecting source of mosfets should be sized to carry 2a peak currents. figure 7. component side and c12 selection will be largely determined by esr and load transient response requirements. figure 8. gnd
rt9643 16 ds9643-04 april 2011 www.richtek.com figure 10. bottom figure 9. power
rt9643 17 ds9643-04 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.250 0.350 0.010 0.014 d 4.950 5.050 0.195 0.199 d2 3.100 3.400 0.122 0.134 e 4.950 5.050 0.195 0.199 e2 3.100 3.400 0.122 0.134 e 0.650 0.026 l 0.350 0.450 0.014 0.018 a a1 a3 d e d2 e2 l b e 1 see detail a v-type 24l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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