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cmos 200 msps 14-bit quadrature digital upconverter ad9857 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 200 mh z intern al clock rate 14-bit data pat h excellent dyna mic performance: 80 db sf dr @ 6 5 mhz (10 0 k hz) a out 4 to 20 programmable refe rence clock multiplier reference clock multipli er pl l lock detect indicator internal 32-bit quadra ture dds fsk capability 8-bit output a m plitude contr o l single-pin power-down functi on four programmable, pin-sele ctable signal pr ofiles sin(x)/x correction (inverse si nc f u nction) simplified control interface 10 mhz serial, 2-wire or 3-wir e spi?-compatible 3.3 v single s u pply single-ende d or differenti a l in put reference c l ock 80-lea d lqfp s u rface-mount packaging three modes o f operation: quadrature m o dulator mode single-tone mode interpo l ating dac mo de applic ati o ns hfc data, te lephony, and vi de o modems wireless bas e s t ation agile, lo frequency synthesis b r o a dband communicatio n s func tio n a l block di agram mux 14 14-bit dac dac_rset iout iout 8 output scale value dac clock refclk refclk mode control pll lock clock input mode ad9857 parallel data in (14-bit) de mux pdclk/ fud 14 inverse cic filter inv cic q mux (4 ) cic (2 - 6 3 ) fixed inter- polator programmable interpolator mux quadrature modulator sin cos mux inverse sinc filter in ver se s i nc clock clock 32 tuning word timing and control dds core interp clock inte rp control half-band clocks inv e r s e cic control in ver se c i c c l oc k data clock clock multiplier (4 ? 20 ) mux profile select logic control registers reset cic overflow serial port s y nch sysc lk i 14 ps0 ps1 power- down logic digital power- down txenable 01018-c-001 fi g u r e 1 .
ad9857 rev. c | page 2 of 40 table of contents revision history ............................................................................... 3 general description ......................................................................... 4 specifications ..................................................................................... 5 absolute maximum ratings ............................................................ 8 explanation of test levels ........................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 modulated output spectral plots ............................................. 11 single-tone output spectral plots ........................................... 12 narrow-band sfdr spectral plots ........................................... 13 output constellations ................................................................ 14 modes of operation ...................................................................... 15 quadrature modulation mode ................................................. 15 single-tone mode ...................................................................... 16 interpolating dac mode .......................................................... 17 signal processing path ................................................................... 18 input data assembler ................................................................ 18 inverse cic filter ....................................................................... 19 programmable (2 to 63) cic interpolating filter ............. 21 quadrature modulator .............................................................. 21 dds core ..................................................................................... 21 inverse sinc filter ..................................................................... 22 output scale multiplier ............................................................. 22 14-bit d/a converter ................................................................ 22 reference clock multiplier ....................................................... 23 input data programming .............................................................. 24 control interfaceserial i/o ................................................... 24 general operation of the serial interface ............................... 24 instruction byte .......................................................................... 26 serial interface port pin descriptions ..................................... 26 control register descriptions .................................................. 27 profile #0 ...................................................................................... 27 profile #1 ...................................................................................... 28 profile #2 ...................................................................................... 28 profile #3 ...................................................................................... 28 latency ......................................................................................... 30 ease of use features ....................................................................... 32 profile select ................................................................................ 32 setting the phase of the dds .................................................... 32 reference clock multiplier ....................................................... 32 pll lock ...................................................................................... 32 single or differential clock ...................................................... 33 cic overflow pin ....................................................................... 33 clearing the cic filter .............................................................. 33 digital power-down .................................................................. 33 hardware-controlled digital power-down ........................... 34 software-controlled digital power-down ............................. 34 full sleep mode .......................................................................... 34 power management considerations ........................................ 34 support ........................................................................................ 35 outline dimensions ....................................................................... 38 ordering guide .......................................................................... 39
ad9857 rev. c| page 3 of 40 revision history 5/04? data sheet changed from rev. b to rev. c changes to 14-bit d/a converter section ..................................22 changes to register address 0ch, bit 1 equation ......................28 changes to register address 12h, bit 1 equation .......................28 changes to register address 18h, bit 1 equation .......................28 added support section...................................................................35 updated figure 38...........................................................................38 updated ordering guide ...............................................................39 4/02changed from rev. a to rev. b edit to functional block diagram ..................................................1 edits to specifications.......................................................................3 edits to figure 5 ................................................................................6 edits to figure 18 ............................................................................ 11 edits to figure 19 ............................................................................ 12 edits to figure 20 ............................................................................ 13 edits to figure 25 ........................................................................... 16 edits to figure 26 ............................................................................ 16 edit to equation 1 ........................................................................... 16 edit to figure 28 .............................................................................. 19 edit to notes on serial port operation section........................... 21 edit to figure 37 .............................................................................. 31
ad9857 rev. c | page 4 of 40 general description the ad9857 integrates a high speed direct digital synthesizer (dds), a high performance, high speed, 14-bit digital-to-analog converter (dac), clock multiplier circuitry, digital filters, and other dsp functions onto a single chip, to form a complete quadrature digital upconverter device. the ad9857 is intended to function as a universal i/q modulator and agile upconverter, single-tone dds, or interpolating dac for communications applications, where cost, size, power dissipation, and dynamic performance are critical attributes. the ad9857 offers enhanced performance over the industry- standard ad9856, as well as providing additional features. the ad9857 is available in a space-saving, surface-mount package and is specified to operate over the extended industrial temperature range of ?40c to +85c.
ad9857 rev. c| page 5 of 40 specifications v s = 3.3 v 5%, r set = 1.96 k?, external reference clock frequency = 10 mhz with refclk multiplier enabled at 20. table 1. parameter temp test evel min typ max nit ref clock input characteristics frequency range refclk multiplier disabled full vi 1 200 mhz refclk multiplier enabled at 4 full vi 1 50 mhz refclk multiplier enabled at 20 full vi 1 10 mhz input capacitance 25c v 3 pf input impedance 25c v 100 m? duty cycle 25c v 50 % duty cycle with refclk multiplier enabled 25c v 35 65 % differential input (vdd/2) 200 mv 25c v 1.45 1.85 v dac output characteristics resolution 14 bits full-scale output current 5 10 20 ma gain error 25c i 8.5 0 % fs output offset 25c i 2 a differential nonlinearity 25c v 1.6 lsb integral nonlinearity 25c v 2 lsb output capacitance 25c v 5 pf residual phase noise @ 1 khz offset, 40 mhz a out refclk multiplier enabled at 20 25c v ?107 dbc/hz refclk multiplier at 4 25c v ?123 dbc/hz refclk multiplier disabled 25c v ?145 dbc/hz voltage compliance range 25c i ?0.5 +1.0 v wideband sfdr 1 mhz to 20 mhz analog out 25c v ?75 dbc 20 mhz to 40 mhz analog out 25c v ?65 dbc 40 mhz to 60 mhz analog out 25c v ?62 dbc 60 mhz to 80 mhz analog out 25c v ?60 dbc narrowband sfdr 10 mhz analog out (1 mhz) 25c v ?87 dbc 10 mhz analog out (250 khz) 25c v ?88 dbc 10 mhz analog out (50 khz) 25c v ?92 dbc 10 mhz analog out (10 khz) 25c v ?94 dbc 65 mhz analog out (1 mhz) 25c v ?86 dbc 65 mhz analog out (250 khz) 25c v ?86 dbc 65 mhz analog out (50 khz) 25c v ?86 dbc 65 mhz analog out (10 khz) 25c v ?88 dbc 80 mhz analog out (1 mhz) 25c v ?85 dbc 80 mhz analog out (250 khz) 25c v ?85 dbc 80 mhz analog out (50 khz) 25c v ?85 dbc 80 mhz analog out (0 khz) 25c v ?86 dbc
ad9857 rev. c | page 6 of 40 parameter temp test level min typ max unit modulator characteristics (65 mhz a out ) (input data: 2.5 ms/s, qpsk, 4 oversampled, inverse sinc filter on, inverse cic on) i/q offset 25c iv 55 65 db error vector magnitude 25c iv 0.4 1 % inverse sinc filter (variation in gain from dc to 80 mhz, inverse sinc filter on) 25c v 0.1 db spurious power (off channel, measured in equivalent bandwidth), full-scale output 6.4 mhz bandwidth 25c iv ?65 dbc 3.2 mhz bandwidth 25c iv ?67 dbc 1.6 mhz bandwidth 25c iv ?69 dbc 0.8 mhz bandwidth 25c iv ?69 dbc 0.4 mhz bandwidth 25c iv ?70 dbc 0.2 mhz bandwidth 25c iv ?72 dbc spurious power (off channel, measured in equivalent bandwidth), output attenuated 18 db relative to full scale 6.4 mhz bandwidth 25c iv ?51 dbc 3.2 mhz bandwidth 25c iv ?54 dbc 1.6 mhz bandwidth 25c iv ?56 dbc 0.8 mhz bandwidth 25c iv ?59 dbc 0.4 mhz bandwidth 25c iv ?62 dbc 0.2 mhz bandwidth 25c iv ?63 dbc timing characteristics serial control bus maximum frequency 25c i 10 mhz minimum clock pulse width low (t pwl ) 25c i 30 ns minimum clock pulse width high (t pwh ) 25c i 30 ns maximum clock rise/fall time 25c i 1 ms minimum data setup time (t ds ) 25c i 30 ns minimum data hold time (t dh ) 25c i 0 ns maximum data valid time (t dv ) 25c i 35 ns wake-up time 1 25c i 1 ms minimum reset pulse width high (t rh ) 25c i 5 sysclk 2 2cycles minimum cs setup time 25c i 40 ns cmos logic inputs logic 1 voltage 25c iv 2.0 v logic 0 voltage 25c iv 0.8 v logic 1 current 25c i 5 a logic 0 current 25c i 5 a input capacitance 25c v 3 pf cmos logic outputs (1 ma load) logic 1 voltage 25c i 2.7 v logic 0 voltage 25c i 0.4 v
ad9857 rev. c| page 7 of 40 parameter temp test level min typ max unit power supply v s current 3 (all power specifications at v dd = 3.3 v, 25c, refclk = 200 mhz) full operating conditions 25c i 540 615 ma 160 mhz clock (16) 25c i 445 515 ma 120 mhz clock (12) 25c i 345 400 ma burst operation (25%) 25c i 395 450 ma single-tone mode 25c i 265 310 ma power-down mode 25c i 71 80 ma full-sleep mode 25c i 8 13.5 ma 1 wake-up time refers to recovery from full-sleep mode. the longest time required is for the reference clock multiplier pll to l ock up (if it is being used). the wake-up time assumes that there is no capacitor on dac_bp, and that the recommended pll loop filter values are used. the state of the r eference clock multiplier lock can be determined by observing the signal on the pll_lock pin. 2 sysclk refers to the actual clock frequency used on-chip by the ad9857. if the reference clock multipli er is used to multiply the external reference frequency, the sysclk frequency is the external frequency multiplied by the reference clock multiplier multiplication factor. if the reference clock multiplier is not used, the sysclk frequency is the same as the external refclk frequency. 3 cic = 2, inv sinc on, ftw = 40%, pll off, auto powe r-down between burst on, tx enable duty cycle = 25%.
ad9857 r e v. c | pa ge 8 o f 4 0 absolute maximum ra tings s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . table 2. p a r a m e t e r r a t i n g maximum junction temperature 150c v s 4 v digital input voltage ?0.7 v to +v s digital output c u rrent 5 ma storage temperature ?65c to +150c operating temperature ?40c to +85c lead temperature (soldering 10 s) 300c ja 35c/w jc 16c/w eplanation of test levels table 3. t e s t e v e l 1 100% production tested. 2 100% production tested at 25c and sample tested at specific temper atures. 3 sample tested o n ly. 4 parameter is guaranteed by design and characterization testing. 5 parameter is a typical va lue only. 6 devices are 100 % production tested at 25c and guaranteed by design and char acterization test ing for industrial operating temperature range. esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad9857 r e v. c| pa g e 9 of 40 pin conf igura t ion and fu nction descriptions 01018-c-000 80 79 78 77 76 71 70 69 68 75 74 73 72 21 22 23 24 25 26 27 28 29 30 31 32 33 1 2 3 4 5 6 7 8 9 10 11 13 12 60 59 58 57 56 55 54 53 52 51 50 49 48 nc = no connect ad9857 top view (not to scale) ps1 ps0 cs sc lk sd io sd o s y ncio dgnd dgnd dgnd dv dd dv dd dv dd tx e nable p dclk/fud dgnd dgnd dgnd dv dd dv dd dv dd dgnd dgnd dgnd cic_ ov rfl pll_lock d13 d12 d11 d10 d9 d8 d7 dvdd dvdd dvdd dgnd dgnd dgnd diffclken agnd avdd nc agnd pll_filter avdd agnd nc nc dac_rset dac_bp avdd pin 1 indicator 14 15 16 17 18 20 19 47 46 45 44 43 42 41 d6 d5 d4 d3 d2 d1 d0 agnd iout iout agnd avdd agnd nc 64 63 62 61 67 66 65 34 35 36 37 38 39 40 nc av dd agnd av dd av dd agnd agnd r eset dp d agnd av dd refclk refclk agnd f i gure 2. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin number mnemonic i/o function 20C14, 7C1 d0Cd6, d7C d13 i 14-bit paralle l data bus for i and q data. the requir ed numeric format is twos c o mplement with d13 as the sign bit and d12Cd0 as t h e magnitude bits . alternating 14-bit word s are d e multiplexed onto the i and q data pathways (ex c ep t when oper a ti ng in the interpolating dac mode, in which ca se every word is ro uted onto the i da ta path). when the txenable pi n is asserted high, the next accepted word i s presumed to b e i da ta, the nex t q data, and so forth. 8C10, 31C33, 73C75 dvdd 3.3 v digital po wer pin(s). 11C13, 28C30, 70C72, 76C78 dgnd digital ground pin(s). 21 ps1 i profile select pi n 1. t h e lsb of the two profil e s e lect pins. in c o njunction with ps0, selects one of four profile c o nfigurations. 22 ps0 i profile select pi n 0. t h e msb of the two profile s e lect pins. in c o njunction with p1, selects one of four profile c o nfigurations. 23 cs i serial port chip select pin. an active low signal that allo ws multi p le d evices to o p erate on a si ngle serial bus. 24 sclk i serial port data clock pin. the serial data cloc k for the serial port. 25 sdio i/o serial port input/ output da ta pin. bidirectiona l s e rial data pin for the serial por t. this pin can b e programmed to operate as a ser i al input on ly pin , via the control register bit 00h<7>. t h e d e fault state is bidirectional. 26 sdo o serial port output data pin. this pin serves as the serial data output pin when the sdio pin is configured for serial input on ly mode . the default state is three-state. 27 syncio i serial port synchronizati o n pin. synchronize s th e serial port without affecting the programm able register content s . this is an acti ve high input that aborts the curre nt serial c o mm unication cycle. 34, 41, 51, 52, 57 nc no connect.
ad9857 rev. c | page 10 of 40 pin number mnemonic i/o function 35, 37, 38, 43, 48, 54, 58, 64 avdd 3.3 v analog power pin(s). 36, 39, 40, 42, 44, 47, 53, 56, 59, 61, 65 agnd analog ground pin(s). 45 iout o dac output pin. norm al dac output current (analog). 46 iout o dac complementary output pin. comple mentary dac output current (analog). 49 dac_bp dac reference bypass. typically not used. 50 dac_rset i dac current set pin. sets dac reference current. 55 pll_filter o pll filter. r-c network for pll filter. 60 diffclken i clock mode select pin. a logic high on this pi n selects differential refclk input mode. a logic low selects the single-ended refclk input mode. 62 refclk i reference clock pin. in single-ended clock mode, this pin is the reference clock input. in differential clock mode, this pin is the positive clock input. 63 refclk i inverted reference clock pin. in differential cl ock mode, this pin is the negative clock input. 66 dpd i digital power-down pin. assertion of this pin shuts down the digital sections of the device to conserve power. however, if select ed, the pll remains operational. 67 reset i hardware reset pin. an active high inp ut that forces the device into a predefined state. 68 pll_lock o pll lock pin. active high output signif ying, in real time, when pll is in lock state. 69 cic_ovrfl o cic overflow pin. activity on this pin indicates that the cic filters are in overflow state. this pin is typically low unless a cic overflow occurs. 79 pdclk/fud i/o parallel data clock/frequency update pin. when not in single-tone mode, this pin is an output signal that should be used as a clock to sy nchronize the acceptance of the 14-bit parallel data-words on pins d13Cd0. in single-tone mode, th is pin is an input signal that synchronizes the transfer of a changed frequency tuning word (ftw ) in the active profile (psx) to the accumulator (fud = frequency update signal). when profiles are changed by means of the psCps1 pins, the fud does not have to be asserted to make the ftw active. 80 txenable i when txenable is asserted, the device processe s the data through the i and q data pathways; otherwise 0s are internally substi tuted for the i and q data entering the signal path. the first data word accepted when the txenable is asserted high is treated as i data, the ne xt data word is q data, and so forth.
ad9857 r e v. c| pa g e 11 of 4 0 typical perf orm ance cha r acte ristics modula ted ou tpu t s p ectral pl ots ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 start 0hz 5mhz/ stop 50mhz 0 db 01018-c-003 f i gure 3. q p sk at 4 2 mh z and 2.5 6 ms /s; 1 0 . 24 m h z e x ter n al cl ock wit h r e fcl k m u lt i p lie r = 1 2 , cic int e r p ol at i o n r a te = 3, 4 o v ers a mp led d a t a start 0hz 4mhz/ stop 40mhz ?8 ?16 ?24 ?32 ?40 ?48 ?56 ?64 ?72 ?80 0 db 01018-c-004 f i g u re 4. 64- qa m a t 28 m h z and 6 m s /s ; 3 6 m h z e x t e rn al clo c k wit h r e fclk m u lt i p lie r = 4 , cic in terpol at i o n r a te = 2, 3 o v ers a mp led d a t a start 0hz 8mhz/ stop 80mhz ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 0 db 01018-c-005 f i g u re 5. 16- qa m a t 65 m h z and 1. 2 8 m s /s ; 1 0 . 24 m h z e x tern al cl ock wit h r e fclk m u lt i p lie r = 1 8 , cic int e r p ol at i o n r a te = 9, 4 o v ers a mp led d a t a start 0hz start 0hz 5mhz/ stop 50mhz ?8 ?16 ?24 ?32 ?40 ?48 ?56 ?64 ?72 ?80 0 db 01018-c-006 f i g u re 6. 25 6- qa m at 3 8 m h z and 6 m s /s ; 4 8 m h z e x t e rn al c l ock with re fcl k mu lti p lie r = 4 , cic in terpol ati o n rate = 2, 4 o v ers a mp led d a t a
ad9857 rev. c | page 12 of 40 single-tone output spectral pl ots start 0hz 10mhz/ stop 100mhz ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 0 db 01018-c-007 f i g u re 7. 21 m h z si ng le - t on e o u t p ut start 0hz 10mhz/ stop 100mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 db 01018-c-008 f i g u re 8. 65 m h z si ng le - t on e o u t p ut start 0hz 10mhz/ stop 100mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 db 01018-c-009 f i g u re 9. 42 m h z si ng le - t on e o u t p ut start 0hz 10mhz/ stop 100mhz ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 0 db 01018-c-010 f i gure 10. 7 9 m h z singl e - t one o u tpu t
ad9857 r e v. c| pa g e 13 of 4 0 narrow-band sfdr spectral pl ots center 70.1mhz 10khz/ span 100khz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 0 db 01018-c-011 f i gure 11. 7 0 .1 mh z na rro w - b a nd sf dr, 1 0 mh z e x te rn al c l ock wit h r e fcl k m u lt i p lie r = 2 0 center 70.1mhz 10khz/ span 100khz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 db 01018-c-012 f i g u re 12. 7 0 .1 m h z na rro w-b a nd sf dr , 2 00 m h z e x ter n al cl ock wit h r e fclk m u lt i p lie r d i s a b l ed
ad9857 rev. c | page 14 of 40 outpu t co nstellati o n s ?1.3071895838 1.30718958378 const 200m/div ?1 1 01018-c-013 f i g u re 13. qps k , 6 5 m h z, 2. 56 m s /s const 2 00m/div ?1 ?1.3071895838 1.30718958378 1 01018-c-014 f i g u re 14. 6 4 - q a m , 42 m h z, 6 m s /s const 2 00m/div ?1 ?1.3071895838 1.30718958378 1 01018-c-015 f i g u re 15. gm sk m o dul a t i on, 13 m s /s const 200m/div ?1 ? 1.3071895838 1.30718958378 1 01018-c-016 f i g u re 16. 1 6 - q a m , 65 m h z, 2.5 6 m s /s const 2 00m/div ?1 ? 1.3071895838 1.30718958378 1 01018-c-017 f i g u re 17. 2 56- qa m , 4 2 m h z, 6 m s /s
ad9857 r e v. c| pa g e 15 of 4 0 modes of opera tion the ad9857 has thr e e o p era t ing m o des: ? qu a d r a t u r e m o d u la ti o n m o d e (d e f a u l t ) ? sing l e -tone mo de ? int e r p o l at i n g d a c m o d e m o de s e le c t ion is acco m p lish e d b y p r og ra mmin g a con t r o l r e g i s t er v i a t h e s e r i al p o r t . th e in v e rs e s i nc f i l t er a nd o u t p u t s c ale m u l t i p lier a r e a v a i la b l e in al l t h r e e m o des. quadrature modu lation mode i n q u a d ra t u r e m o d u la ti o n m o d e , bo t h th e i a n d q da t a pa th s a r e ac ti v e . a b l o c k dia g ram o f th e ad9857 op era t in g in t h e q u adr a t u r e m o d u l a t i o n mo de i s sh own i n f i gu r e 18. i n qu a d r a tu re mo d u l a t i o n mo d e , t h e pd c l k / f u d pi n i s an o u t p ut an d f u n c t i o n s as t h e p a r a l l el d a t a clo c k ( p d c l k ), w h ich s e r v es t o syn c hro n ize t h e in p u t o f da t a t o t h e ad9857. i n this m o de , th e i n p u t da ta m u s t be syn c h r o n i z ed wi t h th e ri si n g ed ge of pd c l k. t h e pd c l k op e r a t e s a t tw i c e t h e r a te o f ei t h er t h e i o r q da t a p a t h . this is d u e t o the fac t tha t the i a nd q da t a m u s t b e pre s e n te d to t h e p a r a l l el p o r t a s t w o 1 4 - b i t w o rds m u l t i p lexe d i n t i me . one i w o r d an d one q w o r d t o g e t h er c o m p ri se o n e in t e rn al sa m p l e . e a c h s a m p le is p r o p a g a t e d alo n g t h e i n t e rn a l d a ta pa th w a y i n pa r a ll e l f a s h i o n . the dds co r e pr o v ides a q u adr a t u r e (si n an d c o s) lo ca l os cil l a t o r sig n al t o th e q u adr a t u r e m o d u l a t o r , w h er e t h e i and q da t a a r e m u l t i p l i e d b y t h e r e s p e c t i v e phas e o f t h e ca r r i er a n d su m m e d to ge t h e r , to pro d u c e a qu a d r a t u re - m o d u l a t e d da t a st re am. a l l o f t h is o c c u r s in t h e d i g i t a l d o ma in, and o n ly t h e n is t h e d i gi ta l d a ta s t r e a m a p p l i e d t o t h e 1 4 - b i t d a c t o b e c o m e th e qu a d r a tu re - m o d u l a t e d a n a l o g outpu t s i g n a l . mux 14 14-bit dac dac_rset iout iout 8 output scale value dac clock refclk refclk mode control pll lock clock input mode ad9857 parallel data in (14-bit) de mux pdclk/ fud 14 inverse cic filter inv cic q mux (4 ) cic (2 - 6 3 ) fixed inter- polator programmable interpolator mux quadrature modulator sin cos mux inverse sinc filter in ver se s i nc clock clock 32 tuning word timing and control dds core inte rp clock inte rp control half-band clocks inv e r s e cic control in ver se c i c c l oc k data clock clock multiplier (4 ? 20 ) mux profile select logic control registers reset cic overflow serial port s y nch sysc lk i 14 ps0 ps1 power- down logic digital power- down txenable 01018-c-018 f i g u re 18. q u ad r a t u r e m o du lat i on m o de
ad9857 rev. c | page 16 of 40 single-tone mode a b l o c k di a g ram o f t h e ad985 7 o p era t i n g in t h e si n g le-t one m o de is sh o w n in f i gur e 19. i n t h e sin g l e -t on e m o de , b o t h t h e i a nd q d a t a p a t h s a r e dis a b l e d f r o m t h e 14 -b i t p a r a l l el d a t a p o r t u p t o a nd in c l udin g t h e mo d u l a t o r . th e pd clk/ fud p i n is a n i n p u t a nd f u n c t i o n s as a f r e q uen c y u p d a te (fud) co n t r o l sig n a l . this is ne cess a r y b e c a us e t h e f r e q ue n c y t u ni n g w o r d is p r og ra mm e d v i a t h e asy n chr o no us s e r i a l p o r t . the fud sig n a l ca us es t h e new f r eq uen c y t u ning w o r d t o b e com e ac t i v e . i n sin g le -t on e m o de , t h e cosine p o r t io n o f t h e d d s s e r v es as th e sig n al s o ur c e . the o u t p u t sig n al co n s is ts o f a sin g le f r eq ue n c y a s d e t e rm i n ed b y t h e t u n i n g w o r d s t o r ed i n t h e a ppropr i a t e c o nt ro l re g i s t e r , p e r e a c h prof i l e. i n t h e sin g le -ton e m o de, n o 14-b i t p a r a l l el da t a is a p pli e d to t h e ad9857. th e in t e r n al d d s co r e is us ed t o p r o d uce a sin g le f r e q u e nc y s i g n a l a c c o rd i n g to t h e tu n i ng word. t h e s i ng l e - t o n e sig n al t h e n m o v e s t o wa r d t h e ou t p ut, w h er e t h e in vers e s i n c f i l t er a nd t h e o u t p u t s c ali n g can b e a p plie d . f i nal l y , t h e dig i t a l sin g le-t on e sig n al is co n v er t e d to t h e a n alog doma in b y t h e 14-b i t d a c. mux 14 14-bit dac dac_rset iout iout 8 output scale value dac clock refclk refclk mode control pll lock clock input mode ad9857 pdclk/ fud inverse sinc filter in ver se sin c c l oc k clock 32 tuning word timing and control dds core clock multiplier (4 ? 20 ) mux profile select logic control registers reset serial port s y nch sysc lk ps0 ps1 power- down logic digital power- down 01018-c-001 cos f i g u re 19. sing l e - t one m o de
ad9857 r e v. c| pa g e 17 of 4 0 interpola t ing dac m o de a b l oc k d i a g ra m o f th e a d 9857 o p e r a t in g i n t h e in t e r p o l a t in g d a c m o de is sh o w n i n f i gur e 20. i n t h is m o de, t h e dds and m o d u l a t o r a r e b o th dis a b l e d and o n l y the i da t a p a th is ac t i v e . the q da t a p a t h is dis a b l e d f r o m the 14-b i t p a ral l e l da ta p o r t u p to and i n clu d i n g t h e mo d u l a tor . a s i n t h e qu a d r a tu re mo d u l a t i o n mo d e , t h e p d c l k pi n i s a n o u t p ut an d f u n c t i o n s as a clo c k w h ich s e r v es t o sy n c hr o n i z e t h e in p u t o f da ta t o th e ad9857. u n lik e t h e q u adra t u r e m o d u l a tio n m o de , h o we v e r , t h e pd cl k o p e r a t es a t t h e ra te o f t h e i da t a p a t h . this is b e c a us e o n l y i da t a is b e i n g p r es en te d t o t h e pa r a ll e l po r t a s o p posed t o th e in t e r l ea v e d i/ q f o rm a t o f th e qu a d r a tu re mo du l a t i on m o d e . i n t h e i n t e r p ol a t in g d a c mo de, t h e b a s e b a n d da t a s u p p lie d a t th e pa r a ll e l po r t r e m a i n s a t ba seba n d a t th e o u t p u t ; th a t i s , n o m o d u la ti o n ta k e s p l a c e . h o w e v e r , a sa m p le ra t e co n v e r si o n t a k e s place b a s e d o n t h e p r o g r a mme d i n ter p ol a t io n r a te. t h e in t e r p ol a t ion har d wa r e p e r f o r m s t h e n e ce ss a r y sig n a l p r o c essin g r e q u ir e d t o e l i m in a t e t h e a l ia s e d im a g es a t b a s e b a nd t h a t wou l d ot he r w i s e re su lt f r om a s a m p l e r a te c o n v e r s i on . t h e in ter p ol a t i n g d a c f u n c t i on is ef fe c t ively an o v ers a m p lin g o p era t ion wi t h t h e o r ig ina l i n p u t sp e c t r um i n t a c t b u t s a m p le d at a h i g h e r r a t e . mux 14 14-bit dac dac_rset iout iout 8 output scale value dac clock refclk refclk mode control pll lock clock input mode ad9857 parallel data in (14-bit) de mux pdclk/ fud 14 inverse cic filter inv cic mux (4 ) cic (2 - 6 3 ) fixed inter- polator programmable interpolator mux inverse sinc filter in ver se s i nc clock timing and control inte rp clock inte rp control half-band clocks inv e r s e cic control in ver se c i c c l oc k data clock clock multiplier (4 ? 2 0 ) mux profile select logic control registers reset cic overflow serial port s y nch sysc lk i ps0 ps1 power- down logic digital power- down txenable 01018-c-001 f i gure 20. inte rpo l ating d a c mod e
ad9857 rev. c | page 18 of 40 signal processing path to better understand the operation of the ad9857 it is helpful to follow the signal path from input, through the device, to the output, examining the function of each block (refer to figure 1). the input to the ad9857 is a 14-bit parallel data path. this assumes that the user is supplying the data as interleaved i and q values. any encoding, interpolation, and pulse shaping of the data stream should occur before the data is presented to the ad9857 for upsampling. the ad9857 demultiplexes the interleaved i and q data into two separate data paths inside the part. this means that the input sample rate (f data ), the rate at which 14-bit words are presented to the ad9857, must be 2 the internal i/q sample rate (f iq ), the rate at which the i/q pairs are processed. in other words, f data = 2 f iq . from the input demultiplexer to the quadrature modulator, the data path of the ad9857 is a dual i/q path. all timing within the ad9857 is provided by the internal system clock (sysclk) signal. the externally provided reference clock signal may be used as is (1), or multiplied by the internal clock multiplier (4?20) to generate the sysclk. all other internal clocks and timing are derived from the sysclk. input data assembler in the quadrature modulation or interpolating dac modes, the device accepts 14-bit, twos complement data at its parallel data port. the timing of the data supplied to the parallel port may be easily facilitated with the pdclk/fud pin of the ad9857, which is an output in the quadrature modulation mode and the interpolating dac mode. in the single-tone mode, the same pin becomes an input to the device and serves as a frequency update (fud) strobe. frequency control words are programmed into the ad9857 via the serial port (see the control register description). because the serial port is an asynchronous interface, when programming new frequency tuning words into the on-chip profile registers, the ad9857s internal frequency synthesizer must be synchronized with external events. the purpose of the fud input pin is to synchronize the start of the frequency synthesizer to the external timing requirements of the user. the rising edge of the fud signal causes the frequency tuning word of the selected profile (see the profile section) to be transferred to the accumulator of the dds, thus starting the frequency synthesis process. after loading the frequency tuning word to a profile, a fud signal is not needed when switching between profiles using the two profile select pins (ps0, ps1). when switching between profiles, the frequency tuning word in the profile register becomes effective. in the quadrature modulation mode, the pdclk rate is twice the rate of the i (or q) data rate. the ad9857 expects interleaved i and q data words at the parallel port with one word per pdclk rising edge. one i word and one q word together comprise one internal sample . each sample is propagated along the internal data pathway in parallel. in the interpolating dac mode, however, the pdclk rate is the same as the i data rate because the q data path is inactive. in this mode, each pdclk rising edge latches a data word into the i data path. the pdclk is provided as a continuous clock (i.e., always active). however, the assertion of pdclk may be optionally qualified internally by the pll lock indicator if the user elects to set the pll lock control bit in the appropriate control register. data supplied by the user to the 14-bit parallel port is latched into the device coincident with the rising edge of the pdclk. in the quadrature modulation mode, the rising edge of the txenable signal is used to synchronize the device. while txenable is in the logic 0 state, the device ignores the 14-bit data applied to the parallel port and allows the internal data path to be flushed by forcing 0s down the i and q data pathway. on the rising edge of txenable, the device is ready for the first i word. the first i word is latched into the device coincident with the rising edge of pdclk. the next rising edge of pdclk latches in a q word, etc., until txenable is set to a logic 0 state by the user. when in the quadrature modulation mode, it is important that the user ensure that an even number of pdclk intervals are observed during any given txenable period. this is because the device must capture both an i and a q value before the data can be processed along the internal data pathway. the timing relationship between txenable, pdclk, and data is shown in figure 21 and figure 22.
ad9857 r e v. c| pa g e 19 of 4 0 t dh i 0 txenable pdclk d<13:0> q n i n q 1 i 1 q 0 01018-c-021 t dh t ds t ds f i g u re 21. 1 4 -bit p a r a lle l p o r t tim i ng d i ag r a m q u ad r a t u r e m o du lat i on m o de t dh i 0 txenable pdclk d<13:0> i k i k? 1 i 3 i 2 i 1 01018-c-022 t dh t ds t ds f i g u re 22. 1 4 -bit p a r a lle l p o r t tim i ng d i ag r a mint e rpol a t ing da c m o de table 5. parallel data bus ti ming symbol definition minimum t ds data set u p tim e 4 ns t d data ol d tim e 0 ns inverse cic filter the i n v e rs e cas c ade d i n t e g r a t or co m b (c i c ) f i l t er p r e c o m p e n- s a t e s t h e d a t a t o o f fs et t h e slig h t a t t e n u a t io n g r a d ien t im p o s e d b y t h e cic f i l t er . s e e t h e p r og ra mma b l e (2 t o 63) ci c i n ter p ol a t i n g f i l t er s e c t io n. t h e i (o r q) da t a e n ter i n g t h e f i rst ha lf-b an d f i lt er o c c u p i es a m a x i m u m b a n d wi d t h o f o n e - ha lf f da t a as def i n e d b y n y q u ist (w her e f da t a is th e s a m p le ra t e a t t h e in p u t o f t h e f i rst ha lf-b and f i l t e r ). this is sh o w n g r a p hi ca l l y in f i gur e 23. inband attenuation gradient cic filter response f data /2 f data 4f data f 01018-c-023 f i gure 23. cic f ilter resp onse i f t h e cic f i l t er is em plo y e d , t h e in b a n d a t t e n u a t io n g r adie n t co u l d p o s e a p r ob lem fo r t h os e a p plic a t io ns r e q u ir in g a n ext r em e l y f l a t p a s s b a nd . f o r exa m ple , if t h e s p e c t r um o f t h e da ta as s u p p lied t o th e ad9857 i o r q p a th o c c u p i es a sig n if ica n t p o r t i o n o f t h e on e - h a l f f da t a r e g i o n , t h e hig h er f r eq ue n c i e s o f th e da ta s p ectr um r e ce i v e s s l i g h t l y m o r e a t t e n u a t i o n th a n th e lo w e r f r eq ue n c i e s (t h e w o r s t - case o v e r all d r o o p f r om f = 0 to one - h a l f f da t a is < 0.8 db). this ma y n o t b e accep t ab le in c e r t a i n a p pl ic a t ion s . t h e i n v e rs e ci c f i l t er has a r e sp o n s e cha r ac t e r i st ic t h a t is t h e in vers e o f t h e ci c f i l t er re sp ons e ove r t h e o n e - h a l f f da t a re g i on . the n e t r e s u l t is t h a t t h e p r o d uc t o f t h e t w o r e s p o n s e s yie l ds in a n ext r eme l y f l a t p a s s b a nd , t h e r eb y e l imina t ing t h e i n b a n d a t t e n u a t io n g r a d ien t in t r o d uce d b y t h e ci c f i l t er . th e p r ice t o b e p a i d is a sl ig h t a t t e n u a t io n o f t h e in p u t sig n a l o f a p p r o x - ima t e l y 0.5 db fo r a ci c in t e r p ola t ion ra te o f 2 a nd 0.8 db f o r i n te r p ol a t i o n r a te s of 3 to 6 3 . the i n v e rs e c i c f i l t er is im ple m e n t e d as a dig i t a l fir f i l t er wi t h a r e sp o n s e cha r ac t e r i s t ic t h a t is t h e in v e rs e o f t h e p r o g r a mmable ci c i n ter p ol a t or . the p r o d uc t of t h e two re sp ons e s y i el d s a ne ar ly f l a t re s p ons e ove r t h e b a s e b a n d n y q u i s t ba n d w id th . th e in v e r s e ci c f i l t e r p r o v id e s f r eq ue n c y c o m p e n s a t i on t h a t y i el d s a re sp ons e f l a t ne ss of 0 . 0 5 d b ove r th e b a s e band n y q u is t ban d wid t h, al lo win g t h e ad9857 t o p r o v ide exce l l en t snr o v er i t s p e r f o r ma n c e ran g e . the i n v e rs e c i c f i l t er can b e b y p a s s e d b y s e t t i n g c o n t r o l reg i st er 06h<0 >. i t is a u t o ma tical l y b y p a s s ed if th e ci c in t e r p ol a t ion ra t e is 1. w h e n e v er t h is st a g e is b y p a ss e d , p o w e r t o t h e st a g e is sh u t o f f, t h er eb y r e d u cin g p o w e r dis s i p a t io n.
ad9857 rev. c | page 20 of 40 f i x e d interp olator ( 4 ) this b l o c k is a f i xe d 4 in ter p ola t o r . i t is im ple m e n t e d as tw o half-b an d f i l t ers. th e o u t p u t o f t h is s t a g e is t h e or ig inal da t a up s a m p l e d by 4 . b e fo r e p r es en t i n g a det a i l e d de s c r i p t io n o f t h e ha lf-b an d f i lters, r e call th a t in t h e ca s e o f th e q u a d ra t u r e m o d u la ti o n m o d e t h e i n p u t d a ta s t r e a m i s r e p r e s e n ta ti v e o f c o m p l e x d a t a ; i . e . , t w o in p u t s a m p les ar e r e q u ir e d t o pr o d uce on e i/q da t a p a ir . th e i/q s a m p le r a t e is o n e-half th e in p u t da t a ra te . the i/q s a m p le r a te ( t he r a te a t w h i c h i or q s a m p l e s are pre s e n te d to t h e i n put o f t h e fi r s t h a l f - b a n d fi l t e r ) i s r e f e r r e d t o a s f iq . b e ca us e t h e ad9857 is a q u adra t u r e m o d u l a t o r , f iq r e p r es en ts t h e b a s e b a nd o f t h e in t e r n a l i / q s a m p le p a irs. i t sh o u ld b e em phasiz e d h e r e th a t f iq is n o t t h e s a m e as t h e b a s e ba nd o f the us er s sy m b ol ra te da t a , w h ich m u st b e u p s a m p le d b e fo r e p r es en t a t i o n t o t h e ad9857 (as expla i n e d l a t e r). the i/q s a m p le r a te (f iq ) p u ts a limi t on t h e m i nim u m b a ndwi d t h n e ce ss a r y to t r a n smi t t h e f iq sp e c t r um. this is t h e fami l i a r n y q u ist limi t an d is e q ua l t o on e - ha lf f iq , he re af te r re f e r r e d to a s f ny q . t o g e t h er , t h e two half-b a nd f i l t e r s p r o v ide a fac t o r -o f-fo ur in cr eas e in the s a m p ling ra t e (4 f iq or 8 f ny q ). their co m b in e d in s e r t io n los s is 0.01 db , s o vir t ual l y n o los s o f sig n al lev e l occur s th r o ugh th e t w o h a lf- b a n d f i l t e r s. b o th h a lf- b a n d f i l t ers a r e lin e a r phas e f i l t ers, s o t h a t vir t ual l y n o phas e d i s t o r ti o n i s in t r od uced wi th in th e pa ss ba n d o f th e f i l t e r s. t h is is a n im p o r t a n t f e a t ur e as p h as e dis t o r tio n is g e n e ral l y in t o lera b l e in a da ta tran smis sio n sys t e m . the half-b and f i l t ers a r e desig n e d s o t h a t t h eir co m p osi t e p e r f or m a nc e y i el d s a u s abl e p a ss b a nd of 8 0 % of t h e b a s e b a nd n y q u i s t fr e q u e n c y ( 0 . 2 o n t h e fr e q u e n c y s c a l e be l o w ) . w i t h i n tha t p a s s ban d , t h e r i p p le do es no t exceed 0.002 db . th e st o p ba nd ext e n d s f r o m 120% t o 400% o f th e b a s e band n y q u ist f r eq uen c y (0.3 t o 1.0 o n th e f r e q uen c y s c ale) and o f f e rs a mini m u m o f 85 db a t te n u a t ion. f i gur e 24 a nd f i gur e 25 sh o w th e co m p osi t e r e s p o n s e o f th e tw o h a lf- b a n d f i l t e r s t o g e th e r . frequency 0 0.2 0.4 10 0 ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 ?130 ?140 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.3 0.2 ?85 s a mp le rate 01018-c-024 f i g u re 24. h a lf -b an d 1 and 2 f r equ e nc y r e s p ons e ; f r eq ue nc y rel a t i v e to hb1 o u tput sa m p l e r a t e 0 0 0.05 0.10 0.15 0.20 0.25 0.010 0.008 0.006 0.004 0.002 ? 0.002 ? 0.004 ? 0.006 ? 0.008 ? 0.010 relative frequency (hb1 output sample rate = 1) gain ( d b) 01018-c-025 f i gure 25. c o mbined half-band 1 and 2 p a ss b a nd d e t a il; f r eq uenc y re lat i ve to hb 1 o u tput s a mple rate the us a b le b a nd w i d t h o f t h e f i l t er cha i n p u ts a limi t on t h e m a xi m u m da t a ra t e tha t ca n be p r o p a g a t e d th r o ugh th e ad9857. a lo ok a t t h e p a s s band detail o f th e half-ban d f i l t er r e sp o n s e (f igure 25) indic a tes t h a t i n o r der to ma in t a i n a n a m pli t ude er r o r o f n o m o r e t h an 1 db , sig n als ar e r e s t r i c t e d t o h a v i ng a b a n d w i d t h of no more t h an a b out 9 0 % of f ny q . t h u s , t o k e ep t h e b a n d w i d t h o f t h e da t a in t h e f l a t p o r t i o n o f t h e f i l t er p a s s b a nd , t h e u s er m u s t o v ers a m p le t h e b a s e b a nd da t a b y a t leas t a fac t o r o f tw o p r io r t o p r es en tin g i t t o the ad9857. n o te th a t w i t h o u t o v e r sa m p li n g , th e n y q u i s t ba n d w id th o f th e ba se ba n d da t a co rr e s po n d s t o t h e f ny q . b e c a u s e o f t h i s , t h e upp e r e n d of t h e d a t a b a nd w i d t h su f f e r s 6 d b or more of a tte n u a t i o n d u e to t h e f r e q u e nc y re sp ons e of t h e h a l f - b a nd f i l t ers. f u r t h e r m o r e, if t h e b a s e b a nd da t a a p pl ie d to t h e ad98 57 has b e en p u ls e sha p e d , t h er e is an addi t i o n al con c er n. t y p i ca l l y , p u ls e sha p in g is a p pli e d to t h e b a s e b a nd d a t a vi a a f i l t er ha vin g a ra is e d cosin e r e sp o n s e . i n s u c h c a s e s, a n val u e is used t o m o di f y th e b a n d w id th o f th e d a t a w h er e th e v a l u e o f is s u ch t h a t 1. a val u e o f 0 ca us es t h e da t a b a ndwi d t h t o co r r es p o n d t o t h e n y q u is t b a nd w i d t h. a val u e o f 1 ca us es t h e d a t a b a ndw i d t h to b e e x te nd e d to t w i c e t h e n y qu i s t b a ndw i d t h . t h us, wi th 2 o v e r sa m p li n g o f th e b a se ba n d d a ta a n d = 1, th e n y q u i s t ba n d w id th o f th e d a ta co rr e s po n d s w i t h th e i/ q n y q u ist b a ndwi d t h . a s st a t e d e a rlier , t h is r e su l t s in p r ob lem s n e a r t h e u p pe r ed g e o f th e da t a ba n d w id th d u e t o th e r o ll- o f f a t t e n u a t io n o f t h e half- b an d f i l t ers. f i gur e 26 i l l u s t ra t e s t h e r e la t i on sh i p b e t w e e n and t h e b a ndwi d t h o f r a is e d co si n e s h a p e d p u ls es. the p r ob le m a r e a is i n di ca t e d b y t h e s h adin g in t h e t a i l o f t h e pu ls e wi t h = 1 w h ich exte n d s i n t o t h e r o l l -o f f re g i on of t h e h a l f - b a n d f i lt e r . the ef fe c t o f ra is e d cosin e f i l t er in g o n b a s e b a nd p u ls e ba n d w id th , a n d th e r e la ti o n s h i p t o th e h a lf-ba n d f i l t e r r e s p o n se a r e s h own in f i gur e 26.
ad9857 r e v. c| pa g e 21 of 4 0 f f iq f f nyq (@1 ) f iq f half-band filter response = 0 = 0.5 = 1 bandwidth of i or q data 1 sample rate f iq : data vector rate at input to ad9857 f nyq (@1 ) f nyq (@2 ) f iq 2 oversample rate f nyq (@2 ) f nyq (@1 ) a) b) c) 01018-c-026 2 oversample rate f i g u re 26. e f f e c t of a l pha pr ogr a mm ab l e (2 to 63) cic interpola t ing filter the p r og ra mm a b le in t e r p ola t or is im ple m en t e d as a ci c f i l t er . i t i s pro g r a m m a b l e by a 6 - bit c o n t ro l w o rd , g i v i n g a r a n g e of 2 t o 63 in t e r p ola t ion. this i n t e r p ol a t o r has a lo w-p a ss f r e q uen c y cha r ac t e r i st ic t h a t is c o m p e n s a t e d b y t h e i n v e rs e ci c fi l t e r . the p r og ra mma b le in t e r p ola t or ca n be b y p a s s ed t o yie l d a 1 (n o in ter p ola t i o n) co nf igur a t i o n b y s e t t in g t h e b i t i n t h e a p p r o p r i a t e con t r o l r e g i s t er , p e r e a ch p r o f i l e . w h e n e v er t h e p r ogra mma b l e in t e r p o l a t o r is b y p a s s ed (1 ci c ra t e ), p o w e r to t h e st a g e is r e mo v e d . i f t h e p r og ra mma b l e i n t e r p ola t o r is b y p a s s e d , t h e i n v e rs e ci c f i l t er (s e e a b o v e) is a u t o ma t i cal l y b y p a s s ed , be ca u s e i t s com p en s a tio n is n o t n e e d ed in this c a s e . t h e output of t h e pro g r a m m a b l e i n te r p o l a t or i s t h e d a t a f r om th e 4 in t e r p ol a t o r u p s a m p le d b y a n addi tio n al 2 t o 63, acco r d in g t o the ra t e ch os en b y th e us er . this res u l t s in the in p u t da t a being u p s a m p le d b y a fac t o r o f 8 t o 252. the t r a n sfer f u n c t i on o f t h e cic in ter p ola t i n g f i l t er is 5 1 0 ) 2 ( ) ( ? ? ? ? ? ? = ? = ? ( 1 ) w h er e r is t h e i n ter p ol a t io n r a te, a nd f i s th e f r eq ue n c y r e la ti v e to s y s c l k . quadrature modulator t h e d i g i tal q u ad ra t u r e mo d u la t o r s t a g e is use d t o f r eq uen c y shif t t h e base ba n d s p ectr um o f th e in co m i n g da ta s t r e a m u p t o th e desir e d ca r r ier f r e q uen c y (this p r o c es s is k n o w n as up c o n v e r si on ). a t this p o in t t h e inco min g da t a has be en con v er t e d f r o m a n i n c o m i ng s a m p l i ng r a t e of f in t o a n i/q s a m p ling ra t e e q ual t o s y sclk. the pur p os e o f t h e u p s a m p lin g p r o c es s is t o ma k e t h e da ta s a m p lin g ra t e e q ual t o th e s a m p ling ra te o f th e c a r r ier sig n al . the ca r r i er f r eq uen c y is co n t r o l l ed n u m e r i cal l y b y a dir e c t dig i t a l s y n t h e s i zer (d ds). th e d d s us es t h e i n t e r n al r e fer e n c e cl o c k ( s y s c l k ) to ge ne r a te t h e de s i re d c a r r i e r f r e q u e nc y w i t h a hig h d e g r e e o f p r e c isio n. t h e c a r r ier is a p plie d t o t h e i and q m u l t i p liers i n quadra t u r e fas h io n (90 phas e of fs et) a n d s u mm e d t o yie l d a da t a s t r e a m t h a t r e p r es en ts t h e qu a d rat u re mo dul a ted c a r r i e r . the m o d u la t i on is don e d i g i t a l l y w h ich e l imin a t es t h e pha s e and g a i n i m b a l a nc e and c r o sst a l k issu e s ty pic a l l y ass o c i a t e d w i th a n a l o g m o d u la t o r s . n o t e t h a t th e m o d u la t e d s i g n a l i s ac t u al l y a n u m b er s t r e a m s a m p le d a t t h e ra te o f s y sclk, t h e s a me ra te a t w h i c h t h e o u t p u t d / a con v er t e r is clo c k e d . t h e q u ad ra t u r e m o d u la t o r o p er a t io n is also co n t r o lled b y s p ec tral in v e r t b i ts in each o f t h e fo ur p r o f i l es. the q u adra t u r e m o d u la ti o n ta k e s th e f o rm : ( ) ( ) + sin cos q i when t h e s p ec tr al in ver t b i t is s e t t o a l o g i c 1. ( ) ( ) ? sin cos q i when t h e s p ec tr al in ver t b i t is s e t t o a l o g i c 0. dds c o re the dir e c t dig i t a l syn t h e sizer ( d ds) b l o c k g e nera t e s t h e sin/c o s ca rri e r r e f e r e n c e si gn als th a t digi tall y m o d u la t e th e i/ q da t a p a t h s . t h e dd s f r e q u e nc y i s tu ne d v i a t h e s e r i a l c o n t ro l p o r t wi t h a 32 -b i t t u nin g w o r d (p er p r o f i l e). this al lo ws t h e ad9857 s ou t p u t ca r r ier f r eq ue n c y t o b e v e r y p r ecis e l y t u n e d wh ile s t ill p r o v id i n g o u t p u t f r eq ue n c y a g ili t y .
ad9857 rev. c | page 22 of 40 ) t h e eq ua ti o n r e la tin g o u t p u t f r e q ue n c y (f ou t ) o f th e ad9857 dig i t a l m o d u la to r t o th e f r e q uen c y t u nin g w o rd (ft w ord) a nd t h e sy ste m clo c k (s y s cl k) is ( 32 2 / sysclk ftword f out = (2) w h er e f ou t a nd sy s c l k f r e q u e nc i e s are i n hz an d ft w o rd is a decimal n u m b er f r o m 0 t o 2,147,483,647 (2 31 ?1). f o r exa m ple , f i n d t h e ft w o rd fo r f ou t = 41 mh z and s y sclk = 122. 88 mh z if f ou t = 41 mh z an d s y scl k = 122.88 mh z, t h en hex ftword aaaab 556 = (3) l o adin g 556 aaaabh in t o c o n t r o l b u s reg i s t ers 08hC0b h (f o r p r o f ile 1) p r og ra m s th e ad9857 f o r f ou t = 41 mh z, g i v e n a s y sclk f r eq uen c y o f 122.88 mh z. inverse sinc filter the s a m p le d car r ier da t a s t r e am is t h e i n p u t to t h e dig i t a l - t o - a n alog co n v er t e r (d a c ) in teg ra t e d on t o t h e ad9857. th e d a c out p u t sp e c t r u m is sha p e d b y t h e char ac te r i st ic s i n( x ) /x (o r s i n c ) en ve l o p e , d u e t o t h e i n t r in sic zer o -o rder h o ld ef fe c t as s o c i a t e d w i t h d a c-g e n e r a t e d sig n als. b e ca us e t h e s h a p e o f th e s i n c en ve lo p e is w e l l k n o w n, i t c a n be co m p en s a t e d f o r . t h i s e n vel o p e re stor a t i o n f u nc t i on i s prov i d e d by t h e opt i on a l in v e rs e s i nc f i l t er p r e c e d i n g t h e d a c. this f u nc t i o n is i m p l em en t e d a s a n fir f i l t e r , w h i c h h a s a tra n sf e r fun c ti o n tha t is t h e exac t i n v e rs e o f t h e s i n c r e s p o n s e . w h e n t h e i n v e rs e s i n c f i l t er is s e lec t ed , i t m o dif i es th e in co min g da ta str e a m s o t h a t t h e desir e d ca r r i er en v e lo p e , w h ich w o u l d ot h e r w is e b e s h a p ed b y t h e s i n c en v e lo p e , is r e s t o r e d . h o w e v e r , this co r r ec tio n is o n l y co m p let e f o r ca r r ier f r eq uen c ies u p t o a pprox i m a t el y 4 5 % of s y s c l k . n o t e als o t h a t t h e i n vers e s i nc f i l t er in t r o d uces a b o u t a 3.5 db los s a t lo w f r eq ue n c i e s a s co m p a r ed t o th e g a i n w i t h t h e in v e r s e s i n c f i l t er t u r n ed o f f . this is do n e t o f l a t t e n the o v eral l ga in f rom d c to 4 5 % of s y s c l k . the i n v e rs e s i nc f i l t er can b e b y p a s s e d if i t is no t n e e d e d . i f t h e in v e rs e s i nc f i l t er is b y p a ss e d , i t s clo c k is st op p e d , t h us r e d u cin g t h e p o w e r dissi p a t io n o f t h e p a r t . outpu t sc ale multiplier an 8- b i t m u l t i p lier (o u t p u t s c al e val u e i n t h e b l o c k dia g ram) p r eced in g th e d a c p r o v i d e s th e use r w i th a m e a n s o f a d j u s t in g t h e f i nal o u t p ut le v e l. th e m u l t i p lier val u e is p r og ra mm e d v i a t h e a ppropr i a t e c o n t ro l re g i ste r s , p e r e a ch prof i l e. t h e l s b w e ig h t is 2 C7 , whic h yie l ds a m u l t i p lier ra n g e o f 0 t o 1.9921875, o r n e a r ly 2. b e ca us e t h e q u adra t u r e m o d u l a t o r has a n i n t r in si c los s o f 3 db (1/ 2 ), p r ogra m m i n g th e m u l t i p lier f o r a val u e o f 2 ) r e s t o r e s t h e da t a t o t h e f u l l - s cale ra n g e o f t h e d a c w h e n t h e d e vice is op era t in g in t h e quadra t u r e m o d u la t i on m o de . b e ca us e the ad9857 defa u l ts t o th e m o d u l a tion m o de , the defa u l t v a l u e fo r t h e m u l t i p lier i s b5h (w hich cor r es p o n d s to 2 ). p r og ra mmin g t h e o u t p ut s c ale m u l t i p lier t o uni t y ga i n (80h) b y p a ss e s t h e st age, re d u c i ng p o we r diss i p a t ion. 14-bit d/a c o n v erter a 14- b i t d i gi tal-t o - a n a log co n v er t e r (d a c ) i s used t o co n v e r t t h e dig i t a l l y p r o c es s e d wa vefo rm in t o a n a n alog sig n al. the w o rs t-c a s e sp ur io us sig n als d u e t o t h e d a c a r e t h e ha r m o n ics o f t h e f u ndam e n t a l sig n al and t h eir al ias e s (ple as e s e e t h e ana l og d e vi ces d ds t e c h n i c a l t u t o r i a l , acces s ib le f r o m th e dd s t e ch ni c a l l i b r ar y a t w w w . a na lo g.co m /dds f o r a d e ta iled expla n a t ion o f a l ias e s). th e wi deb a nd 14- b i t d a c in t h e ad9857 ma in tain s s p ur io us-f r e e d y namic ra n g e (s fd r) p e r f or m a nc e of ? 6 0 d b c up to a ou t = 42 mh z a nd ?55 db c u p to a ou t = 65 mh z. the con v ersio n p r o c es s p r o d uc es alias e d com p o n e n ts o f t h e f u ndam e n t al sig n al a t n s y sclk fcarrier (n = 1, 2, 3). th e s e a r e typ i ca l l y f i l t er e d w i t h a n ext e r n al rlc f i l t er a t t h e d a c o u t p u t . i t is im p o r t an t f o r this a n alog f i l t er t o ha v e a su f f i c i e n t l y f l a t g a in and l i ne ar phas e re sp ons e ac ro ss t h e b a n d w i d t h of i n te re st to a v oi d mo d u l a t i o n i m p a i r me n t s . the ad9857 p r o v ides tr ue a nd co m p lem e n t e d c u r r en t o u t p u t s on a ou t a nd a ou t , r e s p e c t i v e ly . the f u l l -s cale o u t p u t c u r r en t is s et b y th e rs et r e sis t o r a t d a c_rs et . the val u e o f rs et f o r a pa r t i c ula r i o ut i s d e t e rm in ed us i n g th e f o llo w in g eq ua ti o n : iout rset / 93 . 39 = (4) f o r exa m ple , if a f u l l -s cale o u t p u t c u r r en t o f 20 ma is desir e d , th en rs e t = (39.93/0.02), o r a p p r o x ima t e l y 2 k?. e v er y do ub li n g o f t h e rs et val u e halv es t h e o u t p ut c u r r en t. the f u l l -s c a le ou t p u t c u r r en t ra n g e o f th e ad9 857 is 5 ma?20 ma. f u l l -s cale o u t p ut c u r r en ts o u tside o f t h is ra n g e deg r ade s f d r p e r f o r ma n c e . s f d r is als o s l ig h t l y a f f e c t ed b y o u t p u t m a t c hi n g ; t h e tw o o u t p u t s s h o u ld be t e rm i n a t ed eq uall y f o r be s t sf dr p e r f or m a nc e . the o u t p u t lo ad s h o u ld b e lo ca te d as clos e as p o s s i b l e t o t h e ad9857 p a c k a g e t o minimize s t ra y ca p a c i tan c e a nd ind u c t an ce . t h e l o a d m a y b e a s i m p l e re s i st or to g rou nd, an op am p c u r r en t-t o - v o l t a g e con v er t e r , o r a t r a n sfo r m e r - co u p le d cir c ui t. dr i v in g a n lc f i l t er w i t h o u t a t r a n sfo r m e r r e q u ir es t h a t t h e f i l t er b e doub ly t e r m ina t e d fo r b e s t p e r f o r ma nce . th er efo r e , t h e f i lte r i n put a n d output s h ou l d b o t h b e re s i st ivel y te r m i n a t e d wi t h t h e a p p r o p r i a t e v a l u es. th e p a ral l e l co m b ina t io n o f t h e tw o t e r m ina t ion s det e r m in es t h e lo ad tha t t h e ad9857 s e es fo r sig n als wi t h i n t h e f i l t er p a s s b a nd . f o r exa m ple , a 50 ? t e r m ina t e d in p u t/ ou t p u t lo w-p a s s f i l t er lo oks li k e a 25 ? lo ad t o th e ad9857.
ad9857 rev. c| page 23 of 40 the output compliance voltage of the ad9857 is ?0.5 v to +1.0 v. any signal developed at the dac output should not exceed 1.0 v, otherwise, signal distortion results. furthermore, the signal may extend below ground as much as 0.5 v without damage or signal distortion. the use of a transformer with a grounded center tap for common-mode rejection results in signals at the ad9857 dac output pins that are symmetrical about ground. as previously mentioned, by differentially combining the two signals, the user can provide some degree of common-mode signal rejection. a differential combiner might consist of a transformer or an op amp. the object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 hz hum or clock feed-through that is equally present on both input signals. the ad9857 true and complement outputs can be differentially combined using a broadband 1:1 transformer with a grounded, center-tapped primary to perform differential combining of the two dac outputs. reference clock multiplier it is often difficult to provide a high quality oscillator with an output in the frequency range of 100 mhz C 200 mhz. the ad9857 allows the use of a lower-frequency oscillator that can be multiplied to a higher frequency by the on-board reference clock multiplier, implemented with a phase locked loop architecture. see the ease of use features section for a more thorough discussion of the reference clock multiplier feature.
ad9857 rev. c | page 24 of 40 input da t a programming contr o l interfaceserial i/o the ad9857 s e r i al p o r t is a f l exi b le , sy n c hr ono u s, s e r i al co mm unic a t io ns p o r t al lo win g easy in t e r f ace t o ma n y ind u s t r y - st a n d a rd m i c r o c on t r o l l e r s and m i c ropro c e ss or s . t h e s e r i a l i / o is co m p a t i b le wi t h m o st sy n c hro n o u s t r a n sfer fo r m a t s, in c l u d in g bo t h th e m o t o r o l a 69 05/11 s p i and i n t e l 8051 s s r proto c o l s . the i n te r f ac e a l l o w s re ad/ w r i te ac c e ss to a l l re g i ste r s t h a t co nf igur e th e ad9857. s i n g le or m u l t i p le b y t e t r a n sf ers a r e su p p o r te d as wel l as ms b f i rst or ls b f i rst t r an sfer fo r m a t s. t h e ad9857 s s e r i al in t e r f ace p o r t c a n be co nf igur e d as a sin g le p i n i/o (s d i o) o r t w o unidir e c t i o n al p i n s fo r in/o u t (s d i o/sd o). general operation of the serial interface ther e a r e tw o phas es t o a comm unic a t ion c y cle w i t h t h e ad9857. p h as e 1 is th e in s t r u c t io n c y c l e , whic h is th e wr i t in g o f a n ins t r u c t io n b y t e in t o th e ad9857, co in ciden t wi th t h e f i rs t eig h t s c lk r i si n g e d g e s. th e ins t r u c t io n b y t e pr o v ides t h e ad9857 s e r i al p o r t co n t r o l l er wi t h inf o r m a t ion r e ga r d in g t h e d a t a t r an sfer c y cle , w h ich is ph as e 2 o f t h e comm unic a t ion c y cle . th e p h as e 1 in s t r u c t io n b y t e def i n e s w h et h e r t h e u p co min g da t a tra n sf er is r e ad o r wr i t e , t h e n u m b er o f b y t e s in t h e da t a t r an sfer (1-4), a n d t h e s t a r t i n g r e g i s ter addr es s fo r t h e f i r s t b y t e o f th e da ta tra n s f e r . the f i rs t eig h t s c lk r i sin g e d g e s o f e a ch co mm unica t io n c y cle a r e us ed t o wr i te th e in s t r u c t io n b y t e in t o t h e ad9857. th e r e ma inin g s c l k e d g e s a r e fo r p h as e 2 o f t h e c o mm uni c a t io n c y c l e . p h as e 2 is th e ac t u al da t a tra n sf er between the ad9857 a nd t h e sys t e m co n t r o l l er . p h as e 2 o f t h e co mm unica t io n c y cle is a tra n sf er o f 1, 2, 3, o r 4 da ta b y t e s as det e r m in e d b y the in st r u c t io n b y t e . t y p i c a l l y , usin g o n e comm u n i c a t ion c y cle in a m u l t i b y t e t r a n sfer is t h e p r efer r e d m e t h o d . h o w e v e r , sin g le-b y t e co mm uni c a t io n c y cles a r e us ef ul t o r e d u ce cp u o v erh e ad w h en r e g i s t er acces s re q u ir es o n e b y te o n ly . an exam ple o f t h is ma y be t o wr i te the ad9857 s l eep b i t. a t th e com p letio n o f a n y co mm unic a t ion c y c l e , th e ad9857 se ri al po r t c o n t r o l l e r e x pect s th e n e xt ei gh t ri s i n g s c l k ed g e s t o b e t h e i n st r u c t io n b y t e o f t h e n e xt comm un ica t ion c y cle . al l da ta in p u t to th e ad9857 is r e g i s t er ed on t h e r i sin g e d g e of sclk. al l da ta is dr i v en o u t o f t h e ad9857 on t h e fal l in g edge of s c l k . f i gur e 27 a nd f i gur e 28 i l l u st r a te t h e da t a wr i t e a nd da t a r e ad o p era t io ns o n t h e ad9857 s e r i al p o r t . f i gur e 29 thr o u g h f i gur e 32 s h o w th e g e n e ral op era t io n o f t h e ad9857 s e r i al p o r t . t pre t sclk t sclkpwh t sclkpwl t dsu t dhld cs sclk sdio 1st bit 2nd bit symbol definition min t pre t sclk t dsu t sclkpwh t sclkpwl t dhld cs setup time period of serial data clock serial data setup time serial data clock pulse width high serial data clock pulse width low serial data hold time 40ns 100ns 30ns 40ns 40ns 0ns 01018-c-027 f i g u re 27. ti m i ng d i ag r a m f o r d a t a writ e t o a d 9 8 57
ad9857 r e v. c| pa g e 25 of 4 0 sdo 1st bit 2nd bit sdio t dv cs sclk symbol definition max t dv data valid time 30ns 01018-c-028 f i g u re 28. ti m i ng d i ag r a m f o r d a t a r e ad f r om a d 9 8 57 i 7 sdio instruction cycle data transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01018-c-029 f i g u re 29. s e ri al p o r t writ ing tim i ng c lock st al l l o w d o7 instruction cycle data transfer cycle don't care i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 sdio s clk cs sdo d o6 d o5 d o4 d o3 d o2 d o1 d o0 01018-c-030 f i g u re 30. 3-w i r e s e ri al p o r t r e ad ti m i ng c l o ck st a l l l o w i 7 sdio instruction cycle data transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01018-c-031 f i g u re 31. s e ri al p o r t writ e ti ming c lo ck st a ll hig h i 7 sdio instruction cycle data transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d o7 d o6 d o5 d o4 d o3 d o2 d o1 d o0 01018-c-032 f i g u re 32. 2-w i r e s e ri al p o r t r e ad ti m i ng c l o ck st a l l h i g h
ad9857 rev. c | page 26 of 40 instruction byte the instruction byte contains the information shown in table 6. table 6. instruction byte information msb d6 d5 d4 d3 d2 d1 lsb r/ w n1 n0 a4 a3 a2 a1 a0 r/ w bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. logic high indicates a read operation. logic 0 indicates a write operation. n1, n0 bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle of the communications cycle. the bit decodes are shown in table 7. table 7. n1, n0 decode bits n1 n0 transfer 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes a4, a3, a2, a1, a0 bits 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9857. serial interface port pin descriptions sclk serial clock. the serial clock pin is used to synchronize data to and from the ad9857 and to run the internal state machines. sclk maximum frequency is 10 mhz. cs chip select. active low input that allows more than one device on the same serial communications lines. the sdo and sdio pins go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio serial data i/o. data is always written into the ad9857 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by bit 7 of register address 00h. the default is logic zero, which configures the sdio pin as bidirectional. sdo serial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. when the ad9857 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. syncio synchronizes the i/o port state machines without affecting the addressable registers contents. an active high input on the sync i/o pin causes the current communication cycle to abort. after sync i/o returns low (logic 0) another communication cycle may begin, starting with the instruction byte write. msb/lsb transfers the ad9857 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the control register 00h<6>bit. the default value of control register 00h<6> is low (msb first). when control register 00h<6> is set high, the ad9857 serial port is in lsb first format. the instruction byte must be written in the format indicated by control register 00h<6>. that is, if the ad9857 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the most significant byte. in msb first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. multibyte data transfers in lsb first format can be completed by writing an instruction byte that includes the register address of the least significant byte. in lsb first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. notes on serial port operation the ad9857 serial port configuration bits reside in bits 6 and 7 of register address 0h. it is important to note that the configuration changes immediately upon writing to this register. for multibyte transfers, writing to this register may occur during the middle of a communication cycle. care must be taken to compensate for this new configuration for the remainder of the current communication cycle. the ad9857 serial port controller address rolls from 19h to 0h for multibyte i/o operations if the msb first mode is active. the serial port controller address rolls from 0h to 19h for multibyte i/o operations if the lsb first mode is active. the system must maintain sync hronization with the ad9857 or the internal control logic is not able to recognize further instructions. for example, if the system sends an instruction byte for a 2-byte write, then pulses the sclk pin for a 3-byte write (8 additional sclk rising edges), communication synchronization is lost. in this case, the first 16 sclk rising edges after the instruction cycle properly writes the first two data bytes into the ad9857, but the next eight rising sclk edges are interpreted as the next instruction byte, not the final byte of the previous communication cycle.
ad9857 rev. c| page 27 of 40 when synchronization is lost between the system and the ad9857, the sync i/o pin provides a means to re-establish synchronization without reinitializing the entire chip. the sync i/o pin enables the user to reset the ad9857 state machine to accept the next eight sclk rising edges to be coincident with the instruction phase of a new communication cycle. by applying and removing a high signal to the sync i/o pin, the ad9857 is set to once again begin performing the communication cycle in synchronization with the system. any information that had been written to the ad9857 registers during a valid communication cycle prior to loss of synchronization remains intact. control register descriptions reference clock (refclk) multiplierregister address 00h, bits 0, 1, 2, 3, 4 a 5-bit number (m), the value of which determines the multiplication factor for the internal pll (bit 4 is the msb). the system clock (sysclk) is m times the frequency of the refclk input signal. if m = 01h, the pll circuit is bypassed and f sysclk =f refclk . if 04h m 14h, the pll multiplies the refclk frequency by m (4C20 decimal). any other value of m is considered an invalid entry. pll lock controlregister address 00h, bit 5 when set to a logic 0, the device uses the status of the pll lock indicator pin to internally control the operation of the 14-bit parallel data path. when set to a logic 1, the internal control logic ignores the status of the pll lock indicator pin. lsb firstregister address 00h, bit 6 when set to a logic 1, the serial interface accepts serial data in lsb first format. when set to a logic 0, msb first format is assumed. sdio input onlyregister address 00h, bit 7 when set to a logic 1, the serial data i/o pin (sdio) is configured as an input only pin. when set to a logic 0, the sdio pin has bidirectional operation. operating moderegister address 01h, bits 0, 1 00h: selects the quadrature modulation mode of operation. 01h: selects the single-tone mode of operation. 02h: selects the interpolating dac mode of operation. 03h: invalid entry. auto power-downregister address 01h, bit 2 when set to a logic 1, the device automatically switches into its low power mode whenever txenable is deasserted for a suf- ficiently long period of time. when set to a logic 0, the device only powers down in response to the digital power-down pin. full sleep moderegister address 01h, bit 3 when set to a logic 1, the device completely shuts down. reservedregister address 01h, bit 4 reservedregister address 01h, bit 5 this bit must always be set to 0. inverse sinc bypassregister address 01h, bit 6 when set to a logic 1, the inverse sinc filter is bypassed. when set to a logic 0, the inverse sinc filter is active. cic clearregister address 01h, bit 7 when set to a logic 1, the cic filters are cleared. when set to a logic 0, the cic filters operate normally. profile #0 tuning wordregister address 02h, bits 0, 1, 2, 3, 4, 5, 6, 7 the lower byte of the 32-bit frequency tuning word, bits 0C7. tuning wordregister address 03h, bits 0, 1, 2, 3, 4, 5, 6, 7 the second byte of the 32-bit frequency tuning word, bits 8C15. tuning wordregister address 04h, bits 0,1, 2, 3, 4, 5, 6, 7 the third byte of the 32-bit frequency tuning word, bits 16C23. tuning wordregister address 05h, bits 0, 1, 2, 3, 4, 5, 6, 7 the fourth byte of the 32-bit frequency tuning word, bits 24C31. inverse cic bypassregister address 06h, bit 0 when set to a logic 1, the inverse cic filter is bypassed. when set to a logic 0, the inverse cic filter is active. spectral invertregister address 06h, bit 1 the quadrature modulator takes the form: i cos() + q sin() when set to a logic 1. i cos() ? q sin() when set to a logic 0. cic interpolation rateregister address 06h, bits 2, 3, 4, 5, 6, 7 00h: invalid entry. 01h: cic filters bypassed. 02hC3fh: cic interpolation rate (2C63, decimal). output scale factorregister address 07h, bits 0, 1, 2, 3, 4, 5, 6, 7 an 8-bit number that serves as a multiplier for the data pathway before the data is delivered the dac. it has an lsb weight of 2 C7 (0.0078125). this yields a multiplier range of 0 to 1.9921875.
ad9857 rev. c | page 28 of 40 profile #1 tuning wordregister address 08h, bits 0, 1, 2, 3, 4, 5, 6, 7 the lower byte of the 32-bit frequency tuning word, bits 0C7. tuning wordregister address 09h, bits 0, 1, 2, 3, 4, 5, 6, 7 the second byte of the 32-bit frequency tuning word, bits 8C15. tuning wordregister address 0ah, bits 0, 1, 2, 3, 4, 5, 6, 7 the third byte of the 32-bit frequency tuning word, bits 16C23. tuning wordregister address 0bh, bits 0, 1, 2, 3, 4, 5, 6, 7 the fourth byte of the 32-bit frequency tuning word, bits 24C31. inverse cic bypassregister address 0ch, bit 0 when set to a logic 1, the inverse cic filter is bypassed. when set to a logic 0, the inverse cic filter is active. spectral invertregister address 0ch, bit 1 the quadrature modulator takes the form: i cos() + q sin() when set to a logic 1. i cos() ? q sin() when set to a logic 0. cic interpolation rateregister address 0ch, bits 2, 3, 4, 5, 6, 7 00h: invalid entry. 01h: cic filters bypassed. 02hC3fh: cic interpolation rate (2C63, decimal). output scale factorregister address 0dh, bits 0, 1, 2, 3, 4, 5, 6, 7 an 8-bit number that serves as a multiplier for the data pathway before the data is delivered the dac. it has an lsb weight of 2 C7 (0.0078125). this yields a multiplier range of 0 to 1.9921875. profile #2 tuning wordregister address 0eh, bits 0, 1, 2, 3, 4, 5, 6, 7 the lower byte of the 32-bit frequency tuning word, bits 0C7. tuning wordregister address 0fh, bits 0, 1, 2, 3, 4, 5, 6, 7 the second byte of the 32-bit frequency tuning word, bits 8C15. tuning wordregister address 10h, bits 0, 1, 2, 3, 4, 5, 6, 7 the third byte of the 32-bit frequency tuning word, bits 16C23. tuning wordregister address 11h, bits 0, 1, 2, 3, 4, 5, 6, 7 the fourth byte of the 32-bit frequency tuning word, bits 24C31. inverse cic bypassregister address 12h, bit 0 when set to a logic 1, the inverse cic filter is bypassed. when set to a logic 0, the inverse cic filter is active. spectral invertregister address 12h, bit 1 the quadrature modulator takes the form: i cos( ) + q sin( ) when set to a logic 1. i cos( ) ? q sin( ) when set to a logic 0. cic interpolation rateregister address 12h, bits 2, 3, 4, 5, 6, 7 00h: invalid entry. 01h: cic filters bypassed. 02hC3fh: cic interpolation rate (2C63, decimal). output scale factorregister address 13h, bits 0, 1, 2, 3, 4, 5, 6, 7 an 8-bit number that serves as a multiplier for the data pathway before the data is delivered the dac. it has an lsb weight of 2 C7 (0.0078125). this yields a multiplier range of 0 to 1.9921875. profile #3 tuning wordregister address 14h, bits 0, 1, 2, 3, 4, 5, 6, 7 the lower byte of the 32-bit frequency tuning word, bits 0C7. tuning wordregister address 15h, bits 0, 1, 2, 3, 4, 5, 6, 7 the second byte of the 32-bit frequency tuning word, bits 8C15. tuning wordregister address 16h, bits 0, 1, 2, 3, 4, 5, 6, 7 the third byte of the 32-bit frequency tuning word, bits 16C23. tuning wordregister address 17h, bits 0, 1, 2, 3, 4, 5, 6, 7 the fourth byte of the 32-bit frequency tuning word, bits 24C31. inverse cic bypassregister address 18h, bit 0 when set to a logic 1, the inverse cic filter is bypassed. when set to a logic 0, the inverse cic filter is active. spectral invertregister address 18h, bit 1 the quadrature modulator takes the form: i cos() + q sin() when set to a logic 1. i cos() ? q sin() when set to a logic 0. cic interpolation rateregister address 18h, bits 2, 3, 4, 5, 6, 7 00h: invalid entry. 01h: cic filters bypassed. 02hC3fh: cic interpolation rate (2C63, decimal). output scale factorregister address 19h, bits 0, 1, 2, 3, 4, 5, 6, 7 an 8-bit number that serves as a multiplier for the data pathway before the data is delivered the dac. it has an lsb weight of 2 C7 (0.0078125). this yields a multiplier range of 0 to 1.9921875.
ad9857 rev. c| page 29 of 40 table 8. control register quick reference register address (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 def. value profile 00h sdio input only lsb first pll lock control refclk multiplier 01h: bypass pll 04hC 14h: 4C 20 21h n/a 01h cic clear inverse sinc bypass reserved: must be 0 reserved full sleep auto power- down operating mode 00h: quad. mod. 01h: single-tone 02h: intrp. dac 00h n/a 02h frequency tuning word #1 <7:0> 00h 0 03h frequency tuning word #1 <15:8> 00h 0 04h frequency tuning word #1 <23:16> 00h 0 05h frequency tuning word #1 <31:24> 00h 0 06h cic interpolation rate 01h: bypass cic filter 02hC3fh: interpolation factor (2C63, decimal) spectral invert inverse cic bypass 08h 0 07h output scale factor bit weighting: msb = 2 0 , lsb = 2 C7 b5h 0 08h frequency tuning word #2 <7:0> unset 1 09h frequency tuning word #2 <15:8> unset 1 0ah frequency tuning word #2 <23:16> unset 1 0bh frequency tuning word #2 <31:24> unset 1 0ch cic interpolation rate 01h: bypass cic filter 02hC3fh: interpolation factor (2C63, decimal) spectral invert inverse cic bypass unset 1 0dh output scale factor bit weighting: msb = 2 0 , lsb = 2 C7 unset 1 0eh frequency tuning word #3 <7:0> unset 2 0fh frequency tuning word #3 <15:8> unset 2 10h frequency tuning word #3 <23:16> unset 2 11h frequency tuning word #3 <31:24> unset 2 12h cic interpolation rate 01h: bypass cic filter 02hC3fh: interpolation factor (2C63, decimal) spectral invert inverse cic bypass unset 2 13h output scale factor bit weighting: msb = 2 0 , lsb = 2 C7 unset 2 14h frequency tuning word #4 <7:0> unset 3 15h frequency tuning word #4 <15:8> unset 3 16h frequency tuning word #4 <23:16> unset 3 17h frequency tuning word #4 <31:24> unset 3 18h cic interpolation rate 01h: bypass cic filter 02hC3fh: interpolation factor (2C63, decimal) spectral invert inverse cic bypass unset 3 19h output scale factor bit weighting: msb = 2 0 , lsb = 2 C7 unset 3
ad9857 rev. c | page 30 of 40 latency the l a t e n c y t h r o u g h t h e a d 98 57 is e a sies t t o des c r i b e in ter m s o f sys t em clo c k (s y s clk) c y cles. l a t e n c y is a f u n c t i on o f t h e ad9857 co nf ig ura t io n (tha t is, whic h mo de and which o p tio n al fe a t ur es a r e en g a g e d). the la t e nc y is p r ima r i l y a f fe c t e d b y t h e p r ogra m m a b l e in t e r p o l a t o r s ra te . the fol l o w in g v a l u es s h o u ld b e co n s ider e d est i ma t e s b e ca us e o b se r v ed la t e n c y m a y be da ta de pen d en t . th e la t e n c y w a s calc u l a t ed usin g th e lin e a r de l a y m o de l f o r fir f i l t ers. s y sclk = refclk ref e r e n c e c l o c k m u l t i p l i er f a ct o r (1 if by p a s s e d , 4 C20) n = p r o g ramm abl e i n te r p ol a t i o n r a te (1 if by p a s s e d , 2 C63) table 9. stage modulator mode interpolator mode input demux 4 n 8 n inverse cic 12 n (optional) 12 n (optional) fixed interpolat or 72 n 72 n programmable interpolator 5 n + 9 5 n + 9 quadrature mo dulator 7 not used inverse sinc 7 (optional) 7 (optional) output scaler 6 (optional) 6 (optional) ex a m ple i n t e r p ol a te mo de cloc k m u l t i p li er = 4 i n v e rs e ci c = on i n te r p ol a t e r a te = 2 0 in v e r s e s i n c = o f f ou t p u t scale = o n iods clock per reference cks/ system clo ) ( ) ( ) ( ) ( latency 488.75 4 1955 6 9 20 5 20 72 20 12 20 8 = = + + + + + = lat e nc y for th e single- t on e m o de i n s i ng l e - t o n e mo d e , f r e q u e nc y hoppi ng i s a c c o m p l i s h e d b y al t e r n a t e l y s e le c t in g t h e t w o p r o f i l e in p u t pin s . the t i m e re qu i r e d to s w it ch f rom on e f r e q u e nc y to a n ot he r i s l e ss t h a n 3 0 sys t em clo c k c y cles (s y s clk) wi t h t h e i n v e rs e s i n c f i l t er and t h e o u t p ut s c ale r en ga g e d . w i t h t h e i n v e rs e s i nc f i l t er d i s e ng ag e d , t h e l a te nc y d rop s to l e ss t h an 2 4 s y s c l k c y cl e s . o t her f a c t ors affec t ing latenc y a n ot he r f a c t or af f e c t i n g l a te nc y i s t h e i n te r n a l cl o c k ph a s e r e la t i on s h i p a t t h e st a r t o f a n y b u rs t t r a n smis sion. f o r sys t em s t h a t n e e d t o main t a in exac t s y s c lk c y cle la t e nc y fo r al l b u rs ts, t h e us er m u st b e a w a r e o f t h e p o s s i b le dif f er e n ce in s y scl k c y c l e la t e n c y th r o u gh th e d e mu x , w h i c h p r eced e s th e s i gn al p r o c essin g chai n. t h e t i min g di a g r a m s o f f i gur e 33 a nd f i gur e 34 des c r i b e h o w t h e l a te n c y dif f ers dep e n d in g up o n t h e phas e r e l a t i on shi p b etwe e n t h e p d cl k an d t h e clo c k t h a t sa m p le s d a ta a t th e o u t p u t o f th e da t a a s sem b ler logi c (la b e l ed d e mu x o n th e b l oc k dia g ra m ) . rega r d in g f i gu r e 33 a nd f i gur e 34, t h e s y s c l k /n t r ace r e p r es en ts t h e cl o c k f r e q uen c y t h a t is di v i de d do wn f r o m s y sclk b y t h e ci c i n t e r p ol a t i o n ra te . tha t is, wi t h s y sc lk eq ual t o 200 m h z and t h e ci c in t e r p ol a t ion ra t e e q ual t o 2 (n = 2), th en s y sclk/n eq u a ls 100 mh z. th e s y s c lk/2 n a nd s y sc lk/4 n sig n a l s a r e divide d b y 2 an d 4 o f s y sclk/ n , r e s p ecti v e l y . f o r q u a d ra t u r e m o d u la ti o n m o d e , th e p d c l k i s th e s y sc l k / 2 n f r eq ue n c y a n d th e c l ock th a t s a m p le s da t a in t o th e s i gn al p r oces s i n g c h a i n i s t h e s y sc lk / 4 n f r eq ue n c y . n o t e th a t s y sc l k / 2 n ri s i n g ed g e s cr ea t e t h e tra n si t i o n o f th e sy s c l k / 4 n s i g n a l . f i g u r e 33 s h o w s th e tim i n g f o r a b u r s t tra n s m is s i o n th a t s t a r t s w h en t h e p d cl k (s y s cl k/2 n ) sig n al g e n e r a tes a r i sin g e d g e o n th e s y sc lk/ 4 n c l oc k . th e la t e n c y f r o m th e d < 13: 0> p i n s t o t h e o u t p ut o f t h e da t a as s e m b le r log i c is t h r e e p d clk c y cles. t h e output i s v a l i d on t h e f a l l i n g e d ge of s y s c l k / 4 n cl o c k a n d is s a m p le d in t o th e sig n al p r o c es sin g c h a i n o n t h e n e xt r i sin g e d ge o f t h e s y s c lk/4 n clo c k ( 1 /2 s y scl k /4 n clo c k c y cle la t e n c y). f i g u r e 34 s h o w s th e tim i n g f o r a b u r s t tra n s m is s i o n th a t s t a r t s w h en t h e p d cl k (s y s cl k/2 n ) sig n al g e n e r a tes a fal l in g e d g e o n th e s y sc lk/ 4 n c l oc k . th e la t e n c y f r o m th e d < 13: 0> p i n s t o t h e o u t p ut o f t h e da t a as s e m b le r log i c is t h r e e p d clk c y cles. this is iden tical t o f i gur e 33, b u t n o t e tha t o u t p u t is valid o n t h e r i sin g edg e o f s y sclk/4 n c l o c k an d is s a m p le d in t o the sig n al pro c e s s i ng ch a i n on t h e ne x t r i s i ng e d ge of t h e s y s c l k / 4 n cl o c k ( 1 f u l l s y s c lk/4 n cl o c k c y cl e l a te nc y ) . the dif f er ence i n l a t e n c y (as r e l a t e d t o s y sc lk clo c k c y cles) is s y s c l k / 2 n , or one p d c l k c y cl e.
ad9857 r e v. c| pa g e 31 of 4 0 i 0 txenable pdclk d<13:0> q 1 i 1 q 0 q 2 i 2 i 0 q 0 i 1 q 1 sysclk/n sysclk/2n sysclk/4n signal path i signal path q invcic clock latency through data assembler logic is 3 pdclk cycles inverse cic filter setup time don't care 01018-c-033 f i g u re 33. lat e nc y f r o m d < 1 3 : 0 > to si g n al p r oc es s i ng ch ain, f o ur pdcl k c y cles i 0 txenable pdclk d<13:0> q 1 i 1 q 0 q 2 i 2 i 0 q 0 i 1 q 1 sysclk/n sysclk/2n sysclk/4n signal path i signal path q invcic clock latency through data assembler logic is 3 pdclk cycles inverse cic filter setup time don't care q 3 i 3 01018-c-034 f i g u re 34. lat e nc y f r o m d < 1 3 : 0 > to si g n al p r oc es s i ng ch ain, f i ve p d clk c y cles
ad9857 rev. c | page 32 of 40 ease of use features profile select the profile select pins, ps0 and ps1, activate one of four internal profiles within the device. a profile is defined as a group of control registers. the ad9857 contains four identical register groupings associated with profile 0, 1, 2, and 3. they are available to the user to provide rapid changing of device parameters via external hardware. profiles are activated by simply controlling the logic levels on device pins p0 and p1 as defined in table 10. table 10. profile select matrix ps1 ps0 profile 0 0 0 0 1 1 1 0 2 1 1 3 each profile offers the following functionality: 1. control of the dds output frequency via the frequency tuning word. 2. control over the sum or difference of the quadrature modulator components via the spectral invert bit (only valid when the device is operating the quadrature modulation mode). 3. ability to bypass the inverse cic filter. 4. control of the cic interpolation rate (1 to 63), or bypass cic interpolator. 5. control of the output scale factor (which offers a gain range between 0 and 1.9921875.) the profile select pins are sampled synchronously with the pdclk signal for the quadrature modulation mode and the interpolating dac mode. for single-tone mode, they are sampled synchronously with sysclk (internal only). setting the phase of the dds a feature unique to the ad9857 (versus previous adi dds products) is the ability for the user to preset the dds accumulator to a value of 0. this sets the dds outputs to sin = 0 and cos = 1. to accomplish this, the user simply programs a tuning word of 00000000h, which forces the dds core to a zero-phase condition. reference clock multiplier for dds applications, the carrier is typically limited to about 40% of sysclk. for a 65 mhz carrier, the system clock required is above 160 mhz. to avoid the cost associated with high frequency references, and the noise coupling issues associated with operating a high frequency clock on a pc board, the ad9857 provides an on-chip programmable clock multiplier that multiplies the reference clock frequency supplied to the part. the available clock multiplier range is from 4 to 20, in integer steps. with the reference clock multiplier enabled, the input reference clock required for the ad9857 can be kept in the 10 mhz to 50 mhz range for 200 mhz system operation, which results in cost and system implementation savings. the reference clock multiplier function maintains clock integrity as evidenced by the system phase noise characteristics of the ad9857. external loop filter components consisting of a series resistor (1.3 k?) and capacitor (0.01 f) provide the compensation zero for the refclk multiplier pll loop. the overall loop performance has been optimized for these component values. control of the pll is accomplished by programming the 5-bit refclk multiplier portion of control register 00h. the pll may be bypassed by programming a value of 01h. when bypassed, the pll is shut down to conserve power. when programmed for values ranging from 04hC14h (4C20 decimal), the pll multiplies the refclk input frequency by the corresponding decimal value. the maximum output frequency of the pll is restricted to 200 mhz. whenever the pll value is changed, the user should be aware that time must be allocated to allow the pll to lock (approximately 1 ms). indication of the plls lock status is provided externally via the pll lock indicator pin. pll lock (see reference clock multiplier section.) the pll lock indicator (pll_lock) is an active high output pin, serving as a flag to the user that the device has locked to the refclk signal. the status of the pll lock indicator can be used to control some housekeeping functions within the device if the user sets the pll lock control bit to 0 (control register 00h<5>). assuming that the pll lock control bit is cleared (logic 0), the status of the pll lock indicator pin has control over certain internal device functions. specifically, if the pll lock indicator is a logic 0 (pll not locked), then the following static conditions apply: 1. the accumulator in the dds core is cleared. 2. the internal i and q data paths are forced to a value of zero. 3. the cic filters are cleared. 4. the pdclk is forced to a logic 0. 5. activity on the txenable pin is ignored. on the rising edge of the pll lock indicator, the static conditions mentioned above are removed and the device assumes normal operation.
ad9857 rev. c| page 33 of 40 if the user requires the pdclk to continue running, the pll lock control bit (control register 00h<5>) can be set to a logic 1. when the pll lock control bit is set, the pll lock indicator pin functionality remains the same, but the internal operations noted in 1 through 5 above does not occur. the default state of the pll lock control bit is set, suppressing internal monitoring of the pll lock condition. single or differential clock in a noisy environment, a differential clock is usually considered superior in performance over a single-ended clock in terms of jitter performance, noise ingress, emi, etc. however, sometimes it is desirable (economy, layout, etc.) to use a single-ended clock. the ad9857 allows the use of either a differential or single- ended reference clock input signal. a logic high on the diffclken pin selects a differential clock input, whereas a logic low on this pin selects a single-ended clock input. if a differential clock is to be used, logic high is asserted on the diffclken pin. the reference clock signal is applied to the refclk pin, and the inverted (complementary) reference clock signal is applied to refclk . if a single-ended reference clock is desired, logic low should be asserted on the diffclken pin, and the reference clock signal applied to refclk only . refclk is ignored in single-ended mode, and can be left floating or tied low. cic overflow pin any condition that leads to an overflow of the cic filters causes signal activity on the cic_ovrfl pin. the cic_ovrfl pin remains low (logic 0) unless an overflow condition occurs. when an overflow condition occurs, the cic_ovrfl pin does not remain high, but toggles in accordance with data going through the cic filter. clearing the cic filter the ad9857 cic filter(s) can become corrupted if certain illegal (nonvalid) operating conditions occur. if the cic filter(s) become corrupted, invalid results are apparent at the output and the cic_ovrfl output pin exhibits activity (toggling between logic 0 and logic 1 in accordance with the data going through the cic filter). examples of situations that may cause the cic filter to produce invalid results include: 1. transmitting data when the pll is not locked to the reference frequency. 2. operating the part above the maximum specified system clock rate (200 mhz). 3. changing the cic filter interpolation rate during transmission. if the cic filters become corrupted, the user can take advantage of the cic clear bit (control register 00h<7>) to easily clear the filter(s). by writing the cic clear bit to a logic 1, the ad9857 enters a routine that clears the entire data path, including the cic filter(s). the routine simply ignores the d<13:0> pins and forces logical zeros on to the i and q signal processing paths while holding the cic filter memory elements reset. the routine is complete once all data path memory elements are cleared. the cic clear bit is also reset, so that the user does not have to explicitly clear it. note: the time required to complete this routine is a function of clock speed and the overall interpolation rate programmed into the device. higher interpolation rates create lower clock frequencies at the filters preceding the cic filter(s), causing the routine time to increase. in addition to the capability to detect and clear a corrupted cic filter condition, there are several conditions within the ad9857 that cause an automatic data path flush, which includes clearing the cic filter. the following conditions automatically clear the signal processing chain of the ad9857: 1. power-on resetproper initialization of the ad9857 requires the master reset pin to be active high for at least 5 refclk clock cycles. after master reset becomes inactive, the ad9857 completes the data path clear routine as described above. 2. pll not locked to the reference clockif the pll lock control bit is cleared and the ad9857 detects that the pll is not locked to the reference clock input, the ad9857 invokes and completes the data path clear routine after lock has been detected. when the pll lock control bit is set, the data path clear routine is not invoked if the pll is not locked. the pll lock control bit is set upon initialization, disabling the clear routine functionality due to the pll. 3. digital power-downwhen the dpd pin is driven high, the ad9857 automatically invokes and completes the data path clear routine before powering down the digital section. 4. full sleep modeif the sleep mode control bit is set high, the ad9857 automatically invokes and completes the data path clear routine before powering down. digital power-down the ad9857 includes a digital power-down feature that can be hardware- or software-controlled. digital power-down allows the users to save considerable operating power (60%C70% reduction) when not transmitting and requires no startup time before the next transmission can occur. the digital power-down feature is ideal for burst mode applications where fast begin-to- transmit time is required. during digital power-down, the internal clock synchronization is maintained and the pdclk output continues to run. reduction in power is achieved by stopping many of the internal clocks that drive the signal processing chain. invoking the digital power-down causes supply current transients. therefore, some users may not want to invoke the dpd function to ease power supply regulation considerations.
ad9857 rev. c | page 34 of 40 hardware-controlled digital power-down t h e h a rdw a re - c on t r o l l e d me t h o d f o r re d u c i ng p o we r i s to a p pl y a logi c 1 t o th e d p d p i n . r e s t a r ti n g th e pa r t a f t e r a d i g i tal p o w e r - do wn is acco m p lish e d b y a p p l yin g a lo g i c 0 t o th e d p d p i n. t h e dpd pin go ing to l o g i c 0 ca n o c c u r si m u l t an e o usly wi t h t h e ac tiva tio n o f txen able. t h e use r n o tices so m e tim e de la y bet w een in v o ki n g t h e di gi tal p o w e r - do w n f u n c t i on an d t h e ac t u a l r e d u c t ion in p o w e r . this is d u e t o a n a u t o m a ti c r o u t in e tha t c l ea r s th e s i g n al p r oce s s i n g c h a i n be f o r e s t o p p i n g t h e c l ocks . clea ri n g th e si gn al p r oce s s i n g c h a i n bef o r e p o w e r i n g do wn ens u r e s tha t t h e ad9857 is r e ad y t o tra n s m i t w h en d i g i tal po w e r - d o w n m o d e i s dea c ti v a t e d (see th e clea ri n g t h e c i c f i l t e r sectio n f o r d e ta ils ) . software-contr olled digital power- down the s o f t war e -con t r ol le d m e t h o d fo r r e d u cin g d i g i t a l p o wer be tw e e n t r a n smis sio n s is sim p l y a n enab le o r dis a b l e o f a n a u t o ma t i c p o w e r - do w n f u n c t i on. w h en ena b le d , dig i t a l p o w e r - d o w n bet w een b u r s t s occur s a u t o m a ticall y a f t e r all d a t a h a s p a s s ed t h e ad9 857 sig n al p r o c es sin g p a t h . w h en t h e ad9 857 s e n s es t h e txen ab le in p u t in dica t e s the e n d o f a tra n s m i s s i o n , a n o n - c hi p tim e r i s used t o v e ri f y th a t th e da t a has com p let e d t r an smis sion b e fo r e s t o p p i n g t h e in t e r n al clo c ks t h a t dr i v e t h e sig n a l p r o c es sin g cha i n mem o r y e l emen ts . a s w i th th e h a r d w a r e a c t i v a t i o n m e th od , c l oc k s y n c h r o n i z a t i o n is ma in t a i n e d and t h e pd clk o u t p ut co n t in ue s t o r u n. an ac ti v e hig h sig n al o n txe n ab le a u t o ma tical l y r e s t a r ts th e in t e r n al clo c ks, al lo win g t h e n e xt b u rs t t r a n smi s sio n t o s t a r t imm e d i a t e l y . t h e a u t o ma ti c d i gi t a l po w e r - do w n be tw een b u r s t s i s e n a b le d b y wr i t i n g t h e c o n t r o l reg i s t er 01 h<2> b i t hig h . w r i t i n g t h e c o n t r o l reg i st e r 01h<2> b i t lo w dis a b l es t h e f u n c t i on. full sleep mode w h en co min g o u t o f f u l l s l eep m o de , i t is n e ces s a r y t o wa i t f o r th e p l l loc k in d i ca t o r t o g o h i gh . f u ll s l ee p m o d e fun c ti o n ali t y i s prov i d e d by pro g r a m m i ng on e of t h e c o n t ro l r e g i s t e r s (01h<3>). w h e n t h e f u l l -sle ep b i t is s et t o a l o g i c 1, t h e de vi ce sh u t s do w n b o t h i t s dig i t a l and a n a l o g s e c t io n s . d u r i n g f u l l s l eep mo de , t h e co n t en ts o f t h e r e g i s t ers o f th e ad9857 a r e ma in t a i n e d . thi s m o de y i elds t h e mini m u m p o ssi b l e d e vice p o w e r dissi p a t i o n. power ma nagemen t consi d era t io ns the t h er mal im p e dan c e f o r th e ad9857 80-lead l q fp p a c k a g e is ja = 35c/ w . the maxi m u m al lo wa b l e p o w e r dis s i p a t ion usin g t h is va l u e is ca lc u l a t e d usi n g t = p ja . ja t p = 35 85 150 ? = p w p 85 . 1 = the ad9857 p o w e r dis s i p a t io n is a t o r b e lo w this val u e w h en th e s y s c lk f r e q uen c y is a t 200 mh z o r lo w e r wi t h al l o p tio n a l fe a t ur es ena b le d. th e maxim u m p o w e r dis s i p a t i o n o c c u rs w h i l e o p era t in g the ad9857 as a q u adra t u r e mo d u l a t o r a t t h e m a xi m u m s y s t em c l oc k f r eq uen c y wi th t x en a b l e in a logi c hig h sta t e 100% o f th e tim e t h e de vice is p o w e r e d . u nder th es e co ndi t i on s, t h e de vice op era t e s wi t h al l p o s s i b le cir c ui ts ena b le d a t max i m u m sp e e d . sig n if ican t p o wer s a v i n g ma y b e s e en b y usin g a txe n able sig n al t h a t t o g g l es lo w d u r i n g t i m e s w h en t h e de v i ce do es n o t mo d u l a te . the t h er mal im p e dan c e o f the ad9857 p a c k a g e was m e as ur ed i n a c o n t ro l l e d t e m p e r a tu re e n v i ron me n t a t t e m p e r a tu re s ra n g in g f r o m 2 8 c t o 85c wi th n o air f l o w . th e de vice u nder t e s t was s o lder e d t o a n ad9857 eval u a tion bo a r d an d op era t ed u n d e r c o nd i t i o ns t h a t ge ne r a te m a x i m u m p o we r d i ss i p a t i o n . the t h er mal r e sis t an ce o f a p a cka g e can b e t h oug h t o f as a t h er mal r e sis t o r t h a t exis ts b e twe e n t h e s e micond uc t o r s u r f ace a nd t h e am b i e n t a i r . the t h er mal im p e dan c e o f a p a cka g e is deter m i n e d b y p a cka g e m a ter i a l a nd i t s ph y s ic a l di m e n s ion s . the dis s i p a t ion o f t h e h e a t f r o m t h e p a cka g e is dir e c t ly dep e n d e n t up on t h e am b i en t a i r co n d i t io n s and t h e ph ysical co nne c t io n m a de b e twe e n t h e i c p a ck a g e and t h e pc b . a d e q u a te d i ss ip a t i o n of p o we r f rom t h e a d 9 8 5 7 rel i e s up on a l l p o w e r a nd g r o u nd p i n s o f t h e d e v i ce b e i n g s o ld er e d dir e c t ly to co p p er plan es on a pc b . m a n y v a ri a b l e s c o n t ri b u t e t o th e o p e r a t in g j u n c ti o n t e m p era t ur e w i t h in a de vic e . the y i n cl ude: 1. p a cka g e sty l e 2. s e le c t ion m o de o f o p er a t io n 3. i n t e r n al sys tem clo c k s p e e d 4. supp l y vo lt ag e 5. a m b i en t t e m p era t ur e the p o w e r dis s i p a t io n o f t h e ad9857 in a g i v e n a p p l ic a t io n is det e r m i n e d b y s e v e ral o p er a t in g co n d i t ion s . s o m e o f t h es e co ndi t i on s, such as sup p ly vol t a g e and clo c k sp e e d , h a ve a dire c t rel a t i onsh i p wi t h p o we r diss i p a t ion. t h e mo st i m p o r t an t f a c t or s a f f e cti n g po w e r d i s s i p a t i o n f o ll o w .
ad9857 rev. c| page 35 of 40 supply voltage this affects power dissipation and junction temperature because power dissipation equals supply voltage multiplied by supply current. it is recommended that the user design for a 3.3 v nominal supply voltage in order to manage the effect of supply voltage on the junction temperature of the ad9857. clock speed this directly and linearly influences the total power dissipation of the device and, therefore, junction temperature. as a rule, the user should always select the lowest internal clock speed possible to support a given application to minimize power dissipation. typically, the usable frequency output bandwidth from a dds is limited to 40% of the system clock rate to keep reasonable requirements on the output low-pass filter. this means that for the typical dds application, the system clock frequency should be 2.5 times the highest output frequency. operating modes the ad9857 has three operating modes that consume significantly different amounts of power. when operating in the quadrature modulation mode, the ad9857 dissipates about twice the power as when operating as a single-tone dds. when operating as a quadrature modulator, the ad9857 has features that facilitate power management tactics. for example, the txenable pin may be used in conjunction with the auto power-down bit to frame bursts of data and automatically switch the device into a low power state when there is no data to be modulated. equivalent i/o circuits 01018-c-035 v dd dac outputs iout ioutb v dd digital out v dd digital in figure 35. equivalent i/o circuits support applications assistance is available for the ad9857 and the ad9857/pcb evaluation board. please call 1-800-analogd or visit www.analog.com/dds.
ad9857 rev. c | page 36 of 40 01018-c-036 a. top view c. power plane b. ground plane d. bottom view f i gure 36. a p plic ationC ex ample cir c u i ts
ad9857 r e v. c| pa g e 37 of 4 0 1 2 3 4 5 6 7 8 9 10 out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock 20 19 18 17 16 15 14 13 12 11 u7 74hc574 txenable poclk/fud dgnd dgnd dgnd dvdd dvdd dvdd dgnd dgnd dgnd cic_ovrfl pll_lock reset dpd agnd avdd refclk refclk agnd diff_clken agnd avdd nc agnd pll_filter avdd agnd nc nc dac_rset dac_bp avdd agnd iout iout agnd avdd agnd nc ps0 cs sclk sdio sdo syncio dgnd dgnd dgnd dvdd dvdd dvdd nc avdd agnd agnd_avdd agnd_avdd agnd_gnd agnd_gnd 1 2 3 4 5 6 7 8 9 10 out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd 20 19 18 17 16 15 14 13 12 11 vcc q0 q1 q2 q3 q4 q5 q6 q7 clock u1 74hc574 1a 1y 2a 2y 3a 3y gnd vcc 6a 6y 5a 5y 4a 4y u2 sn74hc14 1 2 3 4 5 6 7 u3 74hc125 en1 d1 q1 en2 d2 q2 gnd vcc en4 d4 q4 en3 d3 q3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 rbe rbe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd w12 cic test point j8 gnd avdd c20 0.01 f c19 0.01 f r4 1.3k ? w6 gnd vcc dpd gnd dvdd vcc gnd gnd vcc w1 vcc gnd vcc w13 ad9857 u5 p1 parallel port gnd 14 13 12 11 10 9 8 dvdd dvdd r5 3.9k ? r6 3.9k ? w4 gnd gnd avdd dvdd gnd sdio sdio syncio ps1 pso cs sclk d12 d12 d11 d11 d10 d10 d9 d9 d8 d8 d7 d7 j2 c25 22pf c26 56pf c27 68pf c28 47pf c22 33pf c23 15pf c24 5.6pf l1 68nh l2 100nh l3 120nh j4 2 1 3 4 j3 w3 w5 gnd 82.5mhz elliptic low-pass filter r7 50 ? r9 50 ? 5 6 gnd tformct w2 w11 gnd vcc txenable p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 p25 p50 p49 p48 p47 p46 p45 p44 p43 p42 p41 p40 p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 p29 p28 p27 p26 gnd u10 reset dpd syncio sdo sdio sclk cs ps0 ps1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 txenable dclk vee vbb vcc r1 2000 ? c1 0.01 f r12 50 ? gnd j1 j6 j7 r2 50v r3 50 ? r8 0 r10 0 clock input gnd gnd gnd vcc u6 5 4 8 2 3 7 6 mc100levl16 d q d q reset c2 0.1 f c29 10 f gnd avdd c3 0.1 f c4 0.1 f c5 0.1 f c6 0.1 f c7 0.1 f c8 0.1 f tb1 power connection gnd avdd dvdd vcc 123 4 gnd w8 w10 w9 w7 c9 0.1 f c30 10 f gnd vcc c10 0.1 f c11 0.1 f c12 0.1 f c13 0.1 f c14 0.1 f c31 10 f gnd dvdd c15 0.1 f c16 0.1 f c17 0.1 f sdio sdo d13 d13 1 d0 d0 ps1 21 22 d1 d1 19 d2 d2 18 d3 d3 17 d4 d4 16 d5 d5 15 d6 d6 14 dgnd 13 dgnd 12 dgnd 11 dvdd 10 9 8 7 6 5 4 3 2 60 41 20 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vcc 01018-c-037 f i g u re 37. s c he mat i c of a d 9 8 57 ev a l uat i o n pcb
ad9857 rev. c | page 38 of 40 outline dimensions 1.45 1.40 1.35 0.15 0.05 61 60 1 80 20 41 21 40 top view (pins down) pin 1 seating plane view a 1.60 max 0.75 0.60 0.45 0.20 0.09 0.10 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3. 5 0 14.00 bsc sq 16.00 bsc sq 0.65 bsc 0.38 0.32 0.22 compliant to jedec standards ms-026-bec f i gure 38. 80-l ead q u ad f l atpack (st - 80) di me nsio ns sho w n i n i n che s a n d ( m il lim e t e r s)
ad9857 rev. c| page 39 of 40 ordering guide model temperature range package description package option ad9857ast ?40c to +85c lqfp st-80 AD9857ASTZ 1 ?40c to +85c lqfp st-80 ad9857/pcb evaluation board 1 z = pb-free part.
ad9857 rev. c | page 40 of 40 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c01018C0 C 5/04(c)

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