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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. n1611 sy 20111031-s00002 no.a1997-1/15 LV4924VH overview the LV4924VH is a 2-channel full-bridge driver for digital power amplifiers. it requires a pwm modulator ic in the previous stage. this ic is a power cell that takes in pwm signals as an input and is used to form a digital amplifier system for tvs, amusement equipment, and other such systems. features ? btl output, class d amplifier system ? high-efficiency class d amplifier ? muting function reduces impulse noise at power on / off ? protection circuits incorporated for over-current, thermal, supply voltage drop, output offset detector ? built-in bootstrap diodes specification ? output 15w (v d =16v, r l =8 ? , f in =1khz, aes17, thd+n=10%) ? output 10w (v d =13v, r l =8 ? , f in =1khz, aes17, thd+n=10%) ? efficiency : 89% (v d =13v, r l =8 ? , f in =1khz, p o =10w) ? thd+n : 0.1% (v d =13v, r l =8 ? , f in =1khz, p o =1w, filter: aes17) maximum ratings / absolute maximum ratings /ta=25 c parameter symbol conditions ratings unit maximum supply voltage v d externally applied voltage 22 v maximum pwm pin voltage v in pwm_a1,pwm_a2,pwm_b1,pwm_b2 6 v maximum pull-up pin voltage vpup max npn open collector pin 20 v allowable power dissipation pd max exposed die-pad soldered *1 4.6 w maximum junction temperature tj max 150 c operating temperature topr -25 to 75 c storage temperature tstg -50 to 150 c *1 customer bread board rev.1.0: 90.0mm 70.0 mm 1.6 mm (two-layer) material: glass epoxy orderin g number: ena1997 bi-cmos ic class-d audio power amplifier power cell btl 10w2ch
LV4924VH no.a1997-2/15 recommended operating range at ta = 25 c parameter symbol conditions ratings unit min typ max recommended supply voltage range v d externally applied voltage 9 13 20 v recommended pwm pin voltage v in pwm_a1,pwm_a2,pwm_b1,pwm_b2 0 3.3 5 v recommended pull-up supply voltage vpup npn open collector pin - - 18 v recommended load resistance r l speaker load 4 8 - electrical characteristics ta=25 c, v d =13v, r l =8 ? , l=22 h (toko: a7040hn-220m), c=0.33 f (matsuo: 553m6302-334k) parameter symbol conditions ratings unit min typ max quiescent current i cco stby=h, mute=h, f in =384khz, duty=50% 30 38 45 ma current at mute imute stby=h, mute=l, v in =gnd 24 6ma standby current ist stby=l, mute=l, v in =gnd - - 10 a h input voltage v i h pwm_a, pwm_b, stby, mute 2.3 - 5.5 v l input voltage v i l pwm_a, pwm_b, stby, mute 0- 1.0v h input current i i h v in =5v - - 60 a l input current i i l v in =gnd -20 - - a output pin leakage current ioff npn open collector output off-stage 5.0v pull-up - - 1 a output pin current iol npn open collector output on-stage, v ol =0.4v 0.5 - - ma power tr on resistance *1 rds on id=1a - 220 - m ? turn on delay time td on f in =384khz, duty=50% - 30 50 ns turn off delay time td off f in =384khz, duty=50% - 30 50 ns rise-up time tr f in =384khz, duty=50% - 5 20 ns fall time tf f in =384khz, duty=50% - 5 20 ns *1 : the maximum power transistor on resistance(r ds on) is 270m (design guarantee value). note : the value of these characteristics were measured in san yo test environment. the actual value in an end system will vary depending on the printed circuit board pattern, the components used, and other factors. electrical characteristics (reference value: the table below shows th e reference value when fpga equivalent to the sanyo reference model is used.) parameter symbol conditions ratings unit min typ max output 1 p o 1 thd+n=10%, f in =1khz, aes17 - 10 - w output 2 p o 2 v d =16v, thd+n=10%, f in =1khz, aes17 - 15 - w total harmonic distortion thd+n p o =1w, f in =1khz, aes17 - 0.1 - % note : the value of these characteristics were measured in san yo test environment. the actual value in an end system will vary depending on the printed circuit board pattern, the components used, and other factors. audio data iis mclk bclk lrclk sdata fpga mclk bclk lrclk sdata LV4924VH pwm bd-mode
LV4924VH no.a1997-3/15 package dimensions unit : mm (typ) 3417 pin assignment sanyo : hssop36(275mil) 15.0 2.17 5.6 0.5 7.6 12 36 0.2 (4.7) (3.5) 0.22 0.65 1.625 (0.68) 0.05 1.7 max (1.5) side view top view bottom view 23 22 24 21 25 20 26 19 27 18 28 17 29 16 30 15 31 14 32 13 33 12 34 11 35 10 36 9 8 7 6 5 4 3 2 1 LV4924VH top view stby mute sos pvd2 out_ch2_p boot_ch2_p v dd a2 out_ch2_n boot_ch2_n out_ch1_p boot_ch1_p v dd a1 out_ch1_n boot_ch1_n pvd1 gnd gnd pvd1 pvd2 out_ch1_p out_ch1_n out_ch2_n out_ch2_p nc1 nc2 nc3 nc4 pwm_a1 pwm_b1 pwm_b2 pwm_a2 nc5 nc6 nc7 nc8 nc9 nc10 nc11
LV4924VH no.a1997-4/15 reference data for thermal design overall view of substrate mounted on a specified board (customer bread board rev.1.0): 90.0mm 70.0 mm 1.6 mm (two-layer) ma terial: glass epoxy pd max-ta pd max -- ta 0 3 1 --25 75 25 0 100 2 50 1.9 2.7 4.6 3.2 6 4 5 exposed die-pad soldered exposed die-pad not soldered ambient temperature , ta -- c allowable power dissipation, pd max -- w specified board : 90.0 70.0 1.6mm 3 glass epoxy 1. data of the exposed die-pad (heat spreader) substrate as mounted represents the value in the state where the exposed die-pad surface is wet for 90% or more. 2. for the set design, derating design should be made while ensuring allowance. stresses to become an object of dera ting are the voltage, current, junction te mperature, power loss and mechanical stresses including vibration, impact and tension. accordingly, these stresses must be as low or small as possible in the design. approximate targets for general derating are as follows: (1) maximum value 80% or less for the voltage rating. (2) maximum value 80% or less for the current rating. (3) maximum value 80% or less for the temperature rating. 3. after set design, be sure to verify the design with the product. also check the soldered state of the exposed die-pad, et c. and verify the reliability of the soldered joint. if any void or deterioration is observed in these sections, thermal conduction to the substrate is deteriorated, resulting in thermal damage of ic.
LV4924VH no.a1997-5/15 block diagram gnd gnd pin equivalent circuit pin no. pin name i/o description equivalent circuit 1 stby i standby mode control 1 pvd gnd 2 mute i muting control 2 pvd gnd v dd a continued on next page.
LV4924VH no.a1997-6/15 continued from preceding page. pin no. pin name i/o description equivalent circuit 3 sos i internal protection circuit detection output (or output of the thermal detection, over-current, voltage drop protection, offset detection circuit) of an npn open collector output type 3 pvd gnd 4 5 6 7 nc1 nc2 nc3 nc4 - - - - non connection non connection non connection non connection 8 9 10 11 pwm_a1 pwm_b1 pwm_b2 pwm_a2 i i i i pwm input (plus input) of out_ch1_p pwm input (negative input) of out_ch1_n pwm input (negative input) of out_ch2_n pwm input (plus input) of out_ch2_p pvd gnd v dd a fin gnd - ground 12 13 14 15 16 17 18 nc5 nc6 nc7 nc8 nc9 nc10 nc11 - - - - - - - non connection non connection non connection non connection non connection non connection non connection 19, 20 pvd2 - power pin 21, 22 26, 27 28, 29 33, 34 out_ch2_p out_ch2_n out_ch1_n out_ch1_p o o o o output pin, channel 2 plus output pin, channel 2 minus output pin, channel 1 minus output pin, channel 1 plus pvd gnd 23 boot_ch2_p i/o bootstrap i / o pin, channel 2 plus 24 v dd a2 o internal power supply decoupling capacitor connection 25 boot_ch2_n i/o bootstrap i / o pin, channel 2 minus 30 boot_ch1_n i/o bootstrap i / o pin, channel 1 minus 31 v dd a1 o internal power supply decoupling capacitor connection 32 boot_ch1_p i/o bootstrap i / o pin, channel 1 plus 35, 36 pvd1 - power pin
LV4924VH no.a1997-7/15 description of functions system standby the built-in 5v regulator is turned on / off by changing over "h" and "l" of "stby". the regulator is turned off with "stby" at "l" and on with "stby" at "h". this signal also causes initialization of the internal logi c initialization with "l" and the normal mode with "h". mute function the mute function is mainly for muting of the output and for reduction of pop noise at power on. muting the output the output pwm can be turned on / off by changing over "h" and "l" of "mute". the pwm output is stopped (putting all of pwm outputs at high impedance) with "m ute" at "l" and enters the normal operation mode with "mute" at "h". sequence at power on to reduce the pop noise, turn on power supply while controlling in the following timing (pwm=bd mode). in particular, all of inputs of pwm must be held at "l" at canceling of mute function. * please observe the following items for the destruction prevention of the output transistor. (1) under all conditions must control the period at the "h" level about the pwm input so as not to become more than 200 s when period of the "h" level mute and stby signals both.
LV4924VH no.a1997-8/15 sequence at power off to reduce the pop noise, turn off power supply while controlling in the following timing (pwm=bd mode). protection circuit LV4924VH incorporates the over-current protection circuit, thermal protection circuit, supply voltage drop protection circuit and output offset detection protection circuit. activation of any one of these circuits causes the sos output pin to become active and thus "l". over-current protection circuit this circuit is a protection circuit* to protect the output transistor from the over-current and compatible with any mode of lightning, ground fault, and load short-circuit. protection is done when the det ection current value (abo ut 6a) set inside ic is reached, forcing the output transistor to remain off for about 20 s. after forced off, the transistor returns automatically to the normal operation and performs protection again if the over-current continues to flow. output current self-recovery & normal operation control operation internal control signal * the over-current protection circuit functions only to avoid the abnormal state, such as output short-circuit, etc., temporarily, and does not guarantee to offer the protection to prevent damage to ic.
LV4924VH no.a1997-9/15 thermal protection circuit this circuit detects the temperature (150 c or more) inside lsi for protection. while this protection circuit is active, the output tr is turned off on both high- and low-sides, putting the output in the high-impedance state. this operation is also provided with the hysteresis. supply voltage drop protection circuit to avoid unstable operation at low voltages, this circuit m onitors the pvd pin voltage and turns on the amplifier when this voltage exceeds the attack voltage (v d = 7v typ.). in addition, to avoid unstable operation when the pvd pin voltage has dropped because of certain reasons, the recover voltage (v d = 6v typ.) is set. both attack and recover voltages have the hysteresis (about 1v) to prevent continuous on / off operation of the supply voltage drop protection circuit. pvd pin voltage internal control signal recovery voltage output offset detection protection circuit this circuit is a protection circuit intended to alleviate burn of the loudspeakers when dc outputs to the btl output for a certain period or more. the circuit detects the case in which each btl input of each channel continues to disagree (for about 300ms), turns off the output tr on both high- and low-sides, and puts the output in the high-impedance state.
LV4924VH no.a1997-10/15 application circuit gnd gnd * sos of pin 3 is the open collector output. therefore, to monitor this output with cpu, it is necessa ry to pull up (resistor: r1) at power supply of cpu, etc. when the output is not to be used (not to be m onitored), it is not necessary to pull-up the resistor.
LV4924VH no.a1997-11/15 characteristics data: l=22 h (toko: a7040hn-220m), c=0.33 f (matsuo: 553m6302-334k) ist -- v d 0.3 6 4 2 8 10 12 10 8 6 4121416 14 ipd -- ta 0 0.3 -40 0 60 100 i mute -- v d 0 3 4 2 1 5 18 i mute -- ta 0 icco -- v d 0 20 10 1 v dd 1,2 -- v d 0 2 v dd 1,2 -- ta 0.2 v d =13v, r l =8 in=low, stbyb=low muteb=low 0.1 0.2 -20 120 20 40 80 20 -40 0 60 100 -20 120 20 40 80 r l =8 in=duty50%[0 to 3.3v] stbyb=high, muteb=high v d =13v, r l =8 in=duty50%[0 to 3.3v] stbyb=high, muteb=high r l =8 3 v d =13v r l =8 16 18 20 22 24 r l =8 , in=low stbyb=high , muteb=low 22 6 7 8 v d =13v, r l =8 in=0, stbyb=high muteb=low 3 4 2 1 5 6 7 8 10 8 6 412141618 20 22 40 30 60 50 70 0 20 10 40 30 60 50 70 icco -- ta -40 0 60 100 -20 120 20 40 80 10 8 6 412141618 20 22 v dd a1,2[v] 4 5 6 1 0 2 3 v dd a1,2[v] 4 5 6 -40 0 60 100 -20 120 20 40 80 standby current, ist - a 0.1 0 0 supply voltage, v d - v standby current, ist - a ambient temperature, ta - c ambient temperature, ta - c ambient temperature, ta - c ambient temperature, ta - c supply voltage, v d - v supply voltage, v d - v supply voltage, v d - v quiescent current, icco - ma quiescent current, icco - ma muting current, imute - ma muting current, imute - ma
LV4924VH no.a1997-12/15 td on -- v d 0 20 814 12 10 16 18 20 22 td on -- ta -40 0 60 100 td off -- v d td off -- ta tr -- v d 0 30 tr -- ta tf -- v d ch sep. -- ta 10 30 -20 120 20 40 80 v d =13v r l =8 50 40 60 0 20 10 30 50 40 60 814 12 10 16 18 20 22 0 20 10 30 50 40 60 0 20 10 30 50 40 60 -40 0 60 100 -20 120 20 40 80 v d =13v r l =8 814 12 10 16 18 20 22 10 20 0 30 10 20 -40 0 60 100 -20 120 20 40 80 v d =13v r l =8 814 12 10 16 18 20 22 0 30 10 20 0 30 10 20 v d =13v r l =8 -40 0 60 100 -20 120 20 40 80 supply voltage, v d - v ambient temperature, ta - c ambient temperature, ta - c ambient temperature, ta - c ambient temperature, ta - c supply voltage, v d - v supply voltage, v d - v supply voltage, v d - v turn on delay time, td on - nsec turn on delay time, td on - nsec turn off delay time, td off - nsec turn off delay time, td off - nsec rise-up time, tr - nsec rise-up time, tr - nsec full time, tr - nsec full time, tr - nsec
LV4924VH no.a1997-13/15 0 100 20 8 pd - power 0 3 4 0 6 10 power@thd+n+1% -- v d 40 60 1 2 4 2 8 -40 0 60 100 -20 120 20 40 80 16 10 12 14 efficiency -- power 2 0610 48 80 pd - w 0 4 12 8 r l =8 efficiency - % power - w/ch 0 100 20 40 60 efficiency -- power 3 0915 612 80 efficiency - % power - w/ch power - w/ch pd - power 0 3 4 0 9 15 1 2 6 3 12 pd - w power - w/ch 5 power@thd+n=1% - w f in =1khz thd+n=1% 2ch-drive aes17 22 18 20 16 20 24 28 32 r l =4 r l =6 8 power@thd+n+10% -- v d 16 10 12 14 0 4 12 8 r l =8 power@thd+n=10% - w f in =1khz thd+n=10% 2ch-drive aes17 22 18 20 16 20 24 28 32 r l =4 r l =6 36 40 44 power@thd+n+1% -- ta 0 4 12 8 power@thd+n=1% - w 16 20 24 28 32 0 4 12 8 power@thd+n=10% - w 16 20 24 28 32 36 40 44 v d =13v f in =1khz thd+n=1% 2ch-drive aes17 r l =8 r l =4 r l =6 -40 0 60 100 -20 120 20 40 80 power@thd+n+10% -- ta v d =13v f in =1khz thd+n=10% 2ch-drive aes17 r l =8 r l =6 r l =4 supply voltage, v d - v ambient temperature, ta - c supply voltage, v d - v ambient temperature, ta - c
LV4924VH no.a1997-14/15 10 thd+n -- ta thd+n -- frequency -40 0 60 100 -20 120 20 40 80 100000 100 1000 10000 ch1 0.01 0.1 10 1 ch2 ch1 0.001 thd+n -- power 10 0.01 0.1 1 power - w 0.0001 100 v d =13v r l =8 p o =1w 2ch-drive aes17 0.01 0.1 10 1 100 v d =13v r l =8 f in =1khz p o =1w 2ch-drive aes17 ch2 10 thd+n -- ta thd+n -- frequency -40 0 60 100 -20 120 20 40 80 100000 100 1000 10000 0.01 0.1 10 1 ch2 ch1 100 v d =16v r l =8 p o =1w 2ch-drive aes17 0.01 0.1 10 1 100 v d =16v r l =8 f in =1khz p o =1w 2ch-drive aes17 ch2 ch1 0.01 0.1 10 1 100 v d =13v r l =8 2ch-drive aes17 100 f in =100hz f in =6.67khz f in =1khz 0.001 thd+n -- power 10 0.01 0.1 1 power - w 0.0001 0.01 0.1 10 1 100 v d =16v r l =8 2ch-drive aes17 100 f in =100hz f in =6.67khz f in =1khz ambient temperature, ta - c ambient temperature, ta - c frequency - hz frequency - hz total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- %
LV4924VH ps no.a1997-15/15 this catalog provides information as of november, 2011. specifications and inform ation herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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