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page 1 of 11 document no. 70-0298-03 www.psemi.com ?2009-2010 peregrine semiconductor corp. all right s reserved. figure 1. functional diagram figure 2. package photo 24-lead 4x4x0.85 mm qfn package product specification sp5t absorptive ultracmos? high-isolation rf switch 450-4000 mhz, vss ext option pe42451 features ? harp? -enhanced ultracmos? device ? five symmetric, absorptive rf ports ? high isolation: ? 68 db at 450 mhz ? 62 db at 900 mhz ? 55 db at 2100 mhz ? 53 db at 2600 mhz ? 50 db at 4000 mhz ? iip2 of 95 dbm, iip3 of 58 dbm ? high esd tolerance of 3500 v hbm ? optional external vss control (vss ext ) ? three pin cmos logic control ? no blocking capacitors required ? small rohs-compliant 24-lead 4x4 mm qfn package the pe42451 is a harp? -enhanced absorptive sp5t rf switch developed on the ultracmos? process technolo gy. this general purpose switch is comprised of five sy mmetric rf ports and has very high isolation. an on-chip cmos decode logic facilitates a three-pin low voltage cmos cont rol interface and an optional external vss feature (vss ext ). high esd tolerance and no blocking capacitor requirements ma ke this the ultimate in integration and ruggedness. peregrine?s harp? technology enhancements deliver h igh linearity and exceptional harmonics performance. i t is an innovative feature of the ultracmos? process, provi ding performance superior to gaas with the economy and i ntegration of conventional cmos. product description rf2 rf4 rf5 cmos control/driver and esd v1 v2 esd rf1 v3 rf3 esd 50 esd 50 esd 50 esd 50 esd 50 rfc vss ext (optional)
product specification pe42451 page 2 of 11 document no. 70-0298-03 ultracmos? rfic solutions ?2009-2010 peregrine semiconductor corp. all right s reserved. table 1. electrical specifications @ 25 c, v dd = 3.0 v (z s = z l = 50 # ) notes: 1. please refer to maximum operating power in table 2 electrical parameter path condition min typ max uni t operating frequency 450 4000 mhz insertion loss, il rfc - rfx rfc - rfx rfc - rfx rfc - rfx rfc - rfx 450 mhz 900 mhz 2100 mhz 2600 mhz 4000 mhz 1.6 1.65 1.95 2.05 2.25 1.95 2.05 2.30 2.40 2.75 db db db db db isolation, iso rfc/rfx - rfx rfc/rfx - rfx rfc/rfx - rfx rfc/rfx - rfx rfc/rfx - rfx 450 mhz 900 mhz 2100 mhz 2600 mhz 4000 mhz 58.5 53.0 46.5 46.5 41.5 68 62 55 53 50 db db db db db return loss, active port rfx 450 - 4000 mhz 16 db return loss, terminated port rfx 450 - 4000 mhz 15 db input 1 db compression 1 , p1db rfx - rfc all bands,100% duty cycle 35 dbm input ip2 rfx - rfc all bands, 100% duty cycle 95 dbm input ip3 rfx - rfc all bands, 100% duty cycle 58 dbm switching time, t sw "on" "off" 50% control to 90% rf 50% control to 10% rf 200 200 500 500 ns ns table 2. operating ranges parameter min typ max units v dd supply voltage 2.7 3.0 3.3 v vss ext negative power supply voltage 2 -3.3 -3.0 -2.7 v i dd max power supply current v dd = 3.3 v, p max = 33 dbm, temperature = -40c 50 a control voltage high 0.7 x v dd v dd v control voltage low 0 0.3 x v dd v i ctrl control current 3 1 a maximum operating power (rfx-rfc, all bands (50 $) , 100% duty cycle) 33 dbm maximum power into termination (rfx, all bands (50 $), 100% duty cycle) 24 dbm operating temperature range -40 +85 c symbol v dd vss ext i dd (max) v ih v il i ctrl p max p max t op i dd power supply current v dd = 3.0 v, p in = 0 dbm i dd 14 a note: 2. applied only when external vss power su pply used. pin 20 must be grounded when using internal vss sup ply. 3. pull-down resistor in evk schematic may incre ase control current.
product specification pe42451 page 3 of 11 document no. 70-0298-03 www.psemi.com ?2009-2010 peregrine semiconductor corp. all right s reserved. table 3. pin descriptions electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. table 4. absolute maximum ratings exceeding absolute maximum ratings may cause permanent damage. operation should be restricted t o the limits in the operating ranges table. symbol parameter/conditions min max units t st storage temperature range -60 +150 c p max maximum operating power (rfx-rfc, all bands (50 $) , 100% duty cycle) 33 dbm p max maximum power into termination (rfx, all bands (50 $), 100% duty cycle) 24 dbm v esd esd voltage hbm 6 , all pins 3500 v v esd esd voltage mm 7 , all pins 150 v notes: 6. human body model esd voltage (hbm, mil_ std 883 method 3015.7) 7. machine model esd voltage (jesd22-a115-a) mode v3 v2 v1 all off 0 0 0 rf1 on 0 0 1 rf2 on 0 1 0 rf3 on 0 1 1 rf4 on 1 0 0 rf5 on 1 0 1 all off 1 1 0 unsupported 1 1 1 table 5. truth table exposed ground paddle gnd rf5 gnd gnd gnd vdd v1 v2 gnd rfc gnd gnd vss ext / gnd rf4 24 23 22 21 20 19 18 17 16 15 14 13 23 4 5 6 1 v3 rf1 gnd gnd gnd rf3 gnd gnd rf2 gnd 78 9 10 11 12 figure 3. pin configuration (top view) moisture sensitivity level the moisture sensitivity level rating for the pe424 51 in the 24-lead 4x4 qfn package is msl1. note: 4. blocking capacitors needed only when non -zero dc voltage present. 5. pin 20 must be grounded when using internal vss supply switching frequency the pe42451 has a maximum 25 khz switching rate when the internal negative voltage generator is use d (pin 20=gnd). the rate at which the pe42451 can be switched is only limited to the switching time if a n external -3 v supply is provided (pin 20=vss ext ). pin # name description 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 21, 23, 24 gnd ground 2 rf5 4 rf i/o 5 rf4 4 rf i/o 8 rf3 4 rf i/o 11 rf2 4 rf i/o 14 rf1 4 rf i/o 16 v dd supply 17 v1 switch control input, cmos logic level 18 v2 switch control input, cmos logic level 19 v3 switch control input, cmos logic level 20 vss ext / gnd 5 external vss control / ground 22 rfc 4 rf common paddle gnd ground for proper device operation optional external vss control ( vss ext ) for proper operation, the vss ext control must be grounded or at the vss voltage specified in the operating ranges table ( table 2 ). when the vss ext control pin on the package is grounded the switch fet?s are biased with an internal low spur negative voltage generator. for applications that require th e lowest possible spur performance, vss ext can be applied to bypass the internal negative voltage generator to eliminate the spurs.
product specification pe42451 page 4 of 11 document no. 70-0298-03 ultracmos? rfic solutions ?2009-2010 peregrine semiconductor corp. all right s reserved. evaluation kit the sp5t switch ek board was designed to ease customer evaluation of peregrine?s pe42451. the rf common port is connected through a 50 $ transmission line via the top sma connector. rf1, rf2, rf3 and rf4 are connected through 50 $ transmission lines via side sma connectors. a through 50 $ transmission is available via sma connectors rfcal1 and rfcal2. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the evk board is constructed with four metal layers on dielectric materials of rogers 4003c and 4450 with a total thickness of 32 mils. layer 1 and layer 3 pro vide ground for the 50 ohm transmission lines. the 50 oh m transmission lines are designed in layer 2 for high isolation purpose and use a stripline waveguide des ign with a trace width of 9.4 mils and trace metal thic kness of 1.8 mils. the board stack up for 50 ohm transmis sion lines has 8 mil thickness of rogers 4003c between layer 1 and layer 2, and 10 mil thickness of rogers 4450 between layer 2 and layer 3. please consult manufacturer's guidelines for proper board material properties in your application. the pcb should be designed in such a way that rf transmission lines a nd sensitive dc i/o traces such as vss ext are heavily isolated from one another, otherwise the true performance of the pe42451 will not be yielded. figure 4. evaluation board layouts figure 5. evaluation board schematic peregrine specification 102/0569 peregrine specification 101/0479 rf cal use pcb 101-0479-03 stripline 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 j 1 header 14 1 2 rfcal1 1 2 rfc 1 2 rfcal2 1 2 rf1 r2 1m 1 2 r f4 1 2 rf5 c6 1f 1 gnd 2 rf5 3 gnd 4 gnd 5 rf4 6 gnd 7 gnd 8 rf3 9 gnd 10 gnd 11 rf2 12 gnd 13 gnd 14 rf1 15 gnd 16 vdd 17 v1 18 v2 19 v3 20 vss 21 gnd 22 rfc 23 gnd 24 gnd u1 pe4245x_24l_qfn 1 2 r f3 1 2 rf2 c1 dni r1 0 ohm r3 0 ohm c2 100pf r4 1m r5 0 ohm c3 100pf r6 1m r7 0 ohm c4 100pf r8 1m r9 0 ohm c5 100pf rf rf5 rf4 rfc rf1 rf2 rf3 v1 v2 v3 vdd vss
product specification pe42451 page 5 of 11 document no. 70-0298-03 www.psemi.com ?2009-2010 peregrine semiconductor corp. all right s reserved. figure 8. insertion loss: all paths performance plots @ 25 c and 3.0 v unless otherwis e specified figure 6. insertion loss: rfc-rfx @ 25 c figure 7. insertion loss: rfc-rfx @ 3.0 v
product specification pe42451 page 6 of 11 document no. 70-0298-03 ultracmos? rfic solutions ?2009-2010 peregrine semiconductor corp. all right s reserved. figure 11. isolation: rfx-rfx @ 25 c performance plots @ 25 c and 3.0 v unless otherwis e specified figure 9. isolation: rfc-rfx @ 25 c figure 10. isolation: rfc-rfx @ 3.0 v figure 12. isolation: rfx-rfx @ 3.0 v
product specification pe42451 page 7 of 11 document no. 70-0298-03 www.psemi.com ?2009-2010 peregrine semiconductor corp. all right s reserved. figure 15. return loss: rfc @ 25 c figure 13. return loss at active port @ 25 c figure 14. return loss at active port @ 3.0 v performance plots @ 25 c and 3.0 v unless otherwis e specified (continued) figure 17. return loss: all paths, terminated figure 16. return loss: rfc @ 3.0 v
product specification pe42451 page 8 of 11 document no. 70-0298-03 ultracmos? rfic solutions ?2009-2010 peregrine semiconductor corp. all right s reserved. 0 20 40 60 80 100 120 0 1000 2000 3000 4000 5000 6000 frequency [mhz] iip2 [dbm] tx1 tx2 tx3 tx4 tx5 0 10 20 30 40 50 60 70 0 1000 2000 3000 4000 5000 6000 frequency [mhz] iip3 [dbm] tx1 tx2 tx3 tx4 tx5 figure 19. nominal linearity performance (iip2) figure 18. nominal linearity performance (iip3) performance plots @ 25 c and 3.0 v unless otherwis e specified (continued)
product specification pe42451 page 9 of 11 document no. 70-0298-03 www.psemi.com ?2009-2010 peregrine semiconductor corp. all right s reserved. figure 20. package drawing peregrine specification 19/0130 max. 0.900 nom. 0.850 min. 0.800 a
product specification pe42451 page 10 of 11 document no. 70-0298-03 ultracmos? rfic solutions ?2009-2010 peregrine semiconductor corp. all right s reserved. figure 21. tape and reel drawing device orientation in tape top of device pin 1 tape feed direction a 0 = 4.35 b 0 = 4.35 k 0 = 1.1 figure 22. marking specifications 42451 yyww zzzzz yyww = date code zzzzz = last five digits of lot number table 6. ordering information order code part marking description package shippin g method pe42451mliaa 42451 pe42451g-24qfn 4x4mm-cut off tap e and reel green 24-lead 4x4mm qfn bulk or tape cut from reel PE42451MLIAA-Z 42451 pe42451g-24qfn 4x4mm-3000c gre en 24-lead 4x4mm qfn 3000 units / t&r ek42451-01 pe42451 -ek pe42451-24qfn 4x4mm-ek evalu ation kit 1 / box
product specification pe42451 page 11 of 11 document no. 70-0298-03 www.psemi.com ?2009-2010 peregrine semiconductor corp. all right s reserved. sales offices the americas peregrine semiconductor corporation 9380 carroll park drive san diego, ca 92121 tel: 858-731-9400 fax: 858-731-9499 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f-92380 garches, france tel: +33-1-4741-9173 fax : +33-1-4741-9173 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for pro duct development. specifications and features may chang e in any manner without notice. preliminary specification the data sheet contains preliminary data. addition al data may be added at a later date. peregrine reserves t he right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event p eregrine decides to change the specifications, peregrine wil l notify customers of the intended changes by issuing a cnf (customer notification form). the information in this data sheet is believed to b e reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s o wn risk. no patent rights or licenses to any circuits descri bed in this data sheet are implied or granted to any third part y. peregrine?s products are not designed or intended f or use in devices or systems intended for surgical implant, o r in other applications intended to support or sustain life, o r in any application in which the failure of the peregrine p roduct could create a situation in which personal injury or deat h might occur. peregrine assumes no liability for damages, includi ng consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered t rademarks and ultracmos, harp, multiswitch and dune are trade marks of peregrine semiconductor corp. high-reliability and defense products americas san diego, ca, usa phone: 858-731-9475 fax: 848-731-9499 europe/asia-pacific parc cezanne 1 380 avenue archimde, parc de la duranne 13857 aix-en-provence cedex 3, france phone: +33-4-4239-3361 fax: +33-4-4239-7227 peregrine semiconductor, asia pacific (apac) shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 peregrine semiconductor, korea #b-2607, kolon tripolis, 210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-943 south korea tel: +82-31-728-3939 fax: +82-31-728-3940 peregrine semiconductor k.k., japan teikoku hotel tower 10b-6 1-1-1 uchisaiwai-cho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213

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