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XA-H4 single-chip 16-bit microcontroller preliminary specification ic28 data handbook 1999 sep 24 integrated circuits
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 2 1999 sep 24 description the powerful 16-bit xa cpu core and rich feature set make the xa-h3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking. by supporting of up to 32 mb of external memory, these devices provide a low-cost solution to embedded applications of any complexity. features like dma, memory controller and four advanced usarts help solve i/o intensive tasks with a minimum of cpu load. the xa-h3 feature set is a subset of the XA-H4 (see table 1). the xa-h3/h4 devices are members of the philips xa (extended architecture) family of high performance 16-bit microcontrollers. the xa-h3 and XA-H4 are designed to significantly minimize the need for external components. features ? large memory support ? de-multiplexed address/data bus ? six programmable chip selects support for unified memory allows easy user modification of all code external isp flash support for easy code download ? dynamic bus sizing each of 6 chip selects can be programmed for 8-bit or 16-bit bus. ? dynamic bus timing each of 6 chip selects has individual programmable bus timing. ? 32 programmable general purpose i/o pins ? four usarts with 230.4 kbps capability ? eight dma channels additional XA-H4 features (not available on xa-h3) ? complete dram controller supports up to four banks of 8 mb each ? memory controller supports 16 mb in unified mode ? memory controller supports 32 mb in harvard mode ? serial ports are usarts synchronous capability up to 1 mbps, and include hdlc/sdlc support four match characters are supported on each usart in async mode hardware autobaud on all four usarts in async mode usarts are improved 85c30 style
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 3 table 1. xa-h3 and XA-H4 features comparison feature xa-h3 XA-H4 maximum external memory (harvard memory mode) 6 mb 32 mb (16 mb code, 16 mb data) maximum external memory (unified memory mode) 6 mb 16 mb memory controller supports both harvard and unified architectures yes yes de-multiplexed address/data bus yes yes dram controller no yes dma channels 8 8 dynamic bus sizing yes yes dynamic bus timing yes yes programmable chip selects 6 6 general purpose io pins 33 33 potential interrupt pins 16 16 interrupts (programmable priority) 7 standard sw 4 high priority sw 9 hardware event 7 standard sw 4 high priority sw 9 hardware event two counter/timers plus watchdog yes yes baud rate generators 1 4 4 serial ports 4 uarts 4 usarts maximum serial data rates asynch to 230.4 kbps (no sync) asynch to 230.4 kbps sync to 1 mbps match characters no 4 async chars per usart hardware autobaud no up to 230.4 kbps note: 1. can be used as additional counters if not needed as brgs. ordering information romless only temperature range c and package freq (mhz) package drawing number h4 = pxah40kfbe 40 to +85 c, 100-pin low profile quad flat package (lqfp) 30 sot407-1 note k=30 mhz, f = (40 to +85), be = lqfp
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 4 pin configuration su01269 XA-H4 top view 100 pin lqfp base part number pxah4 current part = pxah40kfbe k = 30 mhz, f = 40 to +85 c, be = lqfp pkg lqfp package = sot407-1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vss vdd a0 a1 a2 a3 a4 a5 a6 a7 (a21_22) a8 (a19_a20) a9 (a0_a18) a10 (a1) a11 (a2) a12 (a3) a13 (a4) a14 (a5) a15 (a6_a22) vss vdd a16 (a7_a20_a21) a17 (a8_a18_a19) a18 a19 d0 we cs0 cs1_ras1 cs2_ras2 cs3_ras3 clkout vss vdd d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 vdd vss d2 d1 vss vdd cd1_int2 int0 p2.0_rxd3 p2.1_txd3 p2.2_rtclk3 p2.3_comclk_trclk3 p2.4_cd3 p2.5_cts3 p2.6_rts3 p2.7_sync3_brg3 vss vdd p0.0_sync0_brg0 p0.1_rts0 p0.2_cts0 p0.3_cd0 p0.4_trclk0 p0.5_rtclk0 txd0 rxd0 gpout p0.6 p0.7 p1.7_brg2_sync2 p1.6_rts2 p1.5_cts2 p1.4_cd2 p1.3_trclk2 p1.2_rtclk2 p1.1_txd2 p1.0_rxd2 p3.7_int1_trclk1 p3.6_txd1 p3.5_rxd1 p3.4_cts1 p3.3_timer1_brg1_sync1 vdd xtalout xtalin vss p3.2_timer0_resetout p3.0_cs4_ras4_rtclk1 reset_in ble_casl bhe_cash wait_size16 oe p3.1_cs5_ras5_rts1 dram cas bits note: address lines output during various dram cas cycles are shown in parenthesis. see dram controller chapter in user manual for details. mold mark mold mark
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 5 logic symbol XA-H4 su01270 resetin xtal1 xtal2 d15 d0 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 3.0 3.7 txd0 rxd0 3.1 3.2 3.3 3.4 3.5 3.6 1.0 1.7 1.1 1.2 1.3 1.4 1.5 1.6 uart2 2.0 2.7 2.1 2.2 2.3 2.4 2.5 2.6 misc. uart1 port3 port1 port0 uart0 v dd v ss rxd3 txd3 rtclk3 comclk , trclk3 cd3 cts3 rts3 brg3 , sync3 rxd2 txd2 rtclk2 trclk2 cd2 cts2 rts2 brg2 , sync2 brg0 , sync0 rts0 cts0 cd0 trclk0 rtclk0 uart3 int2 cs4 , ras4 cs5 , ras5 resetout , timer0 timer1 int1 cd1 rtclk1 rts1 brg1 , sync1 cts1 rxd1 trclk1 txd1 wait, size16 we oe casl , ble cash , bhe clkout cs0 cs1 , ras1 cs2 , ras2 cs3 , ras3 int0 port2 gpout a19 a0 (dram a22 a0) XA-H4
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 6 XA-H4 block diagram su01271 usart 0 XA-H4 cpu core port 0 port 1 port 2 256 bytes data sram sfr bus port 3 timer 0 data timer 1 watchdog timer mmr bus dma r0 dma t0 memory bus controller 6 chip selects dynamic bus sizing dynamic bus timing external system bus usart 1 dma r1 dma t1 usart 2 dma r2 dma t2 usart 3 dma r3 dma t3 dram controller match chars autobaud match chars autobaud match chars autobaud match chars autobaud
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 7 XA-H4 memory maps su01272 000000h ffffffh 000000h ffffffh 000000h ffffffh unified memory (also known as von neuman architecture) harvard architecture data in dedicated 16 mb space code in dedicated 16 mb space code and data intermixed throughout 16 mb space
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 8 pin descriptions mnemonic lqfp pin no. type name and function see note v ss 1, 19, 28, 44, 59, 76, 88 i ground: 0 v reference. v dd 2, 20, 29, 43, 62, 77, 89 i power supply: this is the power supply voltage for normal, idle, and power down operation. resetin 55 i reset: a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. wait/ size16 52 i wait/size16: during reset, this input determines bus size for boot device (a1o = 16-bit boot device; a0o = 8-bit.) during normal operation this is the wait input (a1o = wait; a0o = proceed.) xtalin 60 i crystal 1: input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. xtalout 61 i crystal 2: output from the oscillator amplifier. cs0 49 o chip select 0: this output provides the active low chip select to the boot device (usually rom or flash.) it cannot be connected to dram. from reset, it is enabled and mapped to an address range based at 000000h. it can be remapped by software to a higher base in the address map (see the amemory interfaceo chapter in the XA-H4 user manual .) cs1 _ras1 48 o chip select 1 or ras 1: chip selects and ras 1 through 5 come out of reset disabled. they can be programmed to function as normal chip selects, or as ras strobes to dram. cs1 can be aswappedo with cs0 (see the swap operation and control bit in the amemory controllero chapter of the XA-H4 user manual .) cs1 is usually mapped to be based at 000000h after the swap, but is capable of being based anywhere in the 16 mb space. cs2 _ras2 47 o chip select 2 or ras 2: active low chip selects cs1 through cs5 come out of reset disabled. they can be programmed to function as normal chip selects, or as ras strobes to dram. cs2 through cs5 are not used with the aswapo operation (see the amemory controllero chapter in the XA-H4 user manual .) they are mappable to any region of the 16 mb address space. cs3 _ras3 46 o cs3 or ras 3: see chip select 2 for description. see pins 56, 57 for 2 additional chip selects we 50 o write enable: goes active low during all bus write cycles only. oe 51 o output enable: goes active low during all bus read cycles only. ble _casl 54 o byte low enable or cas _low_byte: goes active low during all bus cycles that access d7 d0, read or write, generic or dram. functions as cas during dram cycles. bhe _cash 53 o byte high enable or cas _high_byte: goes active low during all bus cycles that access data bus lines d15 d8, read or write, generic or dram. functions as cas during dram cycles. clkout 45 o clock output: this pin outputs a buffered version of the internal cpu clock. the clock output may be used in conjunction with the external bus to synchronize wait state generators, etc. the clock output may be disabled by software. warning: the capacitive loading on this output must not exceed 40 pf. a19 a0 24 21, 18 3 o address[19:0]: these address lines output a19 a0 during (sram, etc.) bus cycles. drams (h4 only) are connected only to pins 22, 21, 18 10 (pins a17 to a7; see user manual amif chaptero for connecting various dram sizes); the appropriate address values are multiplexed onto these 11 pins for ras and cas during dram bus cycles. d15 d0 42 30, 27 25 i/o data[15:0]: bi-directional data bus, d15 d0. p0.0 90 i/o p0.0_sync0 _brg0 : port 0 bit 0, or usart0 sync input or output, or usart0 brg output, or usart0 txclk output. 1 p0.1 91 i/o p0.1_rts0 : port 0 bit 1, or usart0 rts (request to send) output. 1 p0.2 92 i/o p0.2_cts0 : port 0 bit 2, or usart0 cts (clear to send) input. 1 p0.3 93 i/o p0.3_cd0 : port 0 bit 3, or usart0 carrier detect input. 1 p0.4 94 i/o p0.4_trclk0 : port 0 bit 4, or usart0 tr clock input. 1, 2 p0.5 95 i/o p0.5_rtclk0 : port 0 bit 5, or usart0 rt clock input. 1, 2 p0.6 99 i/o p0.6: port 0 bit 6 1 p0.7 100 i/o p0.7: port 0 bit 7 1
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 9 mnemonic see note name and function type lqfp pin no. txd0 96 o txd0: transmit data for usart0. rxd0 97 i rxd0: receive data for usart0. gpout 98 o gpout general purpose output bar: similar to gpio, but push/pull and inverted output only. warning: this output is inverted. the polarity of the pin is the opposite of the bit that drives it (gpout[7]) p1.0 68 i/o p1.0_rxd2: port 1 bit 0, or usart2 rxd input p1.1 69 i/o p1.1_txd2: port 1 bit 1, or usart2 txd output p1.2 70 i/o p1.2_rtclk2 : port 1 bit 2, or usart2 rt clock input 2 p1.3 71 i/o p1.3_trclk2 : port 1 bit 3, or usart2 tr clock input 2 p1.4 72 i/o p1.4_cd2 : port 1 bit 4, or usart2 carrier detect input p1.5 73 i/o p1.5_cts2 : port 1 bit 5, or usart2 clear to send input p1.6 74 i/o p1.6_rts2 : port 1 bit 6, or usart2 request to send output p1.7 75 i/o p1.7_brg2 _sync2 : port 1 bit 7, or usart2 sync input or output, or brg output, or txclk output (see usart clk diagrams in the user manual . ) p2.0 80 i/o p2.0_rxd3: port 2 bit 0, or usart3 rx data input p2.1 81 i/o p2.1_txd3: port 2 bit 1, or usart3 tx data output p2.2 82 i/o p2.2_rtclk3 : port 2 bit 2, or usart3 rt clock input 2 p2.3 83 i/o p2.3_comclk _trclk3 : port 2 bit 3, or usart3 tr clock input 2 p2.4 84 i/o p2.4_cd3 : port 2 bit 4, or usart3 carrier detect input p2.5 85 i/o p2.5_cts3 : port 2 bit 5, or usart3 clear to send input p2.6 86 i/o p2.6_rts3 : port 2 bit 6, or usart3 request to send output p2.7 87 i/o p2.7_sync3 _brg3 : port 2 bit 7, or usart3 sync input or output, or brg output, or txclk output (see usart clock diagrams in the user manual . ) p3.0 56 i/o p3.0_cs4 _ras4 _rtclk1 : port 3 bit 0, or cs4 or ras 4 output, or usart1 rt clock input active low chip selects cs1 through cs5 come out of reset disabled. they can be programmed to function as normal chip selects, or as ras strobes to dram. cs2 through cs5 are not used with the aswapo operation (see the amemory controllero chapter in the XA-H4 user manual .) they are mappable to any region of the 16 mb address space. 2 p3.1 57 i/o p3.1_cs5 _rts1 : port 3 bit 1, or cs5 output, or usart1 request to send output active low chip selects cs1 through cs5 come out of reset disabled. they can be programmed to function as normal chip selects, or as ras strobes to dram. cs2 through cs5 are not used with the aswapo operation (see the amemory controllero chapter in the XA-H4 user manual .) they are mappable to any region of the 16 mb address space. p3.2 58 i/o p3.2_timer0_resetout : port 3 bit 2, or timer0 input or output, or resetout output. resetout : if the resetout function is selected, this pin outputs a low whenever the XA-H4 processor is reset by an internal source (watchdog reset or the reset instruction.) warning: unlike the other 31 gpio pins, during power up reset, this pin can output a strongly driven low pulse. the duration of this low pulse ranges from 0 ns to 258 system clocks, starting at the time that v cc is valid. the state of the resetin pin does not affect this pulse. when used as gpio, this pin can be driven low by software without resetting the XA-H4. p3.3 63 i/o p3.3_timer1_brg1 _sync1 : port 3 bit 3, or timer1 input or output, or usart1 brg output, or usart1 sync input or output. p3.4 64 i/o p3.4_cts1 : port 3 bit 4, or usart1 clear to send input p3.5 65 i/o p3.5_rxd1: port 3 bit 5, or usart1 receive data input p3.6 66 i/o p3.6_txd1: port 3 bit 6, or usart1 transmit data output p3.7 67 i/o p3.7_int1 _trclk1 : port 3 bit 7, or external interrupt 1 input, or usart1 tr clock input 2 cd1 _int2 78 i/o cd1 _int2 : usart1 carrier detect , or external interrupt 2 int0 79 i/o external interrupt 0 notes: 1. see XA-H4 user guide, apins chapter,o for how to program selection of pin functions. 2. rtclk input is usually used for rx clock if an external clock is needed, but can be used for either rx or tx or both. trclk i s usually used for tx clock, but can be used for rx or tx or both.
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 10 control register overview there are two types of control registers in the XA-H4, these are sfrs (special function registers), and mmrs (memory mapped registers.) the sfr registers, with the exception of mrbl, mrbh, micfg, bcr, brth, brtl, and rstsrc are the standard xa core registers. see warnings about bcr, brth, and brtl in table 2. sfrs are accessed by adirect addressingo only (see ic25 xa user manual for direct addressing.) the mmrs are specific to the XA-H4 on-chip peripherals, and can be accessed by any addressing mode that can be used for off-chip data accesses. the mmrs are implemented in a relocatable block. see the amemory controllero chapter in the XA-H4 user manual for details on how to relocate the mmrs by writing a new base address into the mrbl and mrbh (mmr base low and high) registers. table 2. special function registers (sfr) name description sfr address bit functions and addresses msb lsb reset value bcr bus configuration reg reserved see warning 46ah warning never write to the bcr register in the XA-H4 it is initialized to 07h, the only legal value. this is not the same as for some other xa derivatives. 07h btrh bus timing reg high 469h warning immediately after reset, always write btrh = 51h, followed by writing btrl = 40h in that order follow these two writes with five nops this is ffh btrl bus timing reg low 468h writing btrl = 40h in that order . follow these two writes with five nops . this is not the same as for some other xa derivatives. efh mrbl# mmr base address low 496h ma15 ma14 ma13 ma12 mrbe x0h mrbh# mmr base address high 497h ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 xx micfg# clkout tri-st enable 1 = enabled 499h clkoe 01h cs code segment 443h 00h ds data segment 441h 00h es extra segment 442h 00h 33f 33e 33d 33c 33b 33a 339 338 ieh* interrupt enable high 427h ehswr3 ehswr2 ehswr1 ehswr0 eauto esc23 esc01 00h 337 336 335 334 333 332 331 330 iel* interrupt enable low 426h ea edmah edmal ex2 et1 ex1 et0 ex0 00h ipa0 interrupt priority a0 4a0h pt0 px0 00h ipa1 interrupt priority a1 4a1h pt1 px1 00h ipa2 interrupt priority a2 4a2h pdmal px2 00h ipa3 interrupt priority a3 4a3h reserved pdmah 00h ipa4 interrupt priority a4 4a4h psc23 psc01 00h ipa5 interrupt priority a5 4a5h pautob 00h ipa6 interrupt priority a6 4a6h phswr1 phswr0 00h ipa7 interrupt priority a7 4a7h phswr3 phswr2 00h 387 386 385 384 383 382 381 380 p0* port 0 430h ffh 38f 38e 38d 38c 38b 38a 389 388 p1* port 1 431h ffh 397 396 395 394 393 392 391 390 p2* port 2 432h ffh 39f 39e 39d 39c 39b 39a 399 398 p3* port 3 433h ffh
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 11 name reset value bit functions and addresses msb lsb sfr address description p0cfga port 0 configuration a 470h 5 p1cfga port 1 configuration a 471h 5 p2cfga port 2 configuration a 472h 5 p3cfga port 3 configuration a 473h 5 p0cfgb port 0 configuration b 4f0h 5 p1cfgb port 1 configuration b 4f1h 5 p2cfgb port 2 configuration b 4f2h 5 p3cfgb port 3 configuration b 4f3h 5 227 226 225 224 223 222 221 220 pcon* power control reg 404h pd idl 00h 20f 20e 20d 20c 20b 20a 209 208 pswh* program status word high 401h sm tm rs1 rs0 im3 im2 im1 im0 2 207 206 205 204 203 202 201 200 pswl* program status word low 400h c ac v n z 2 217 216 215 214 213 212 211 210 psw51* 80c51 compatible psw 402h c ac f0 rs1 rs0 v f1 p 3 rstsrc reset source reg 463h roen r_wd r_cmd r_ext 7 rth0 timer 0 reload high 455h 00h rth1 timer 1 reload high 457h 00h rtl0 timer 0 reload low 454h 00h rtl1 timer 1 reload low 456h 00h scr system configuration reg 440h pt1 pt0 cm pz 00h 21f 21e 21d 21c 21b 21a 219 218 ssel* segment selection reg 403h eswen r6seg r5seg r4seg r3seg r2seg r1seg r0seg 00h swe software interrupt enable 47ah swe7 swe6 swe5 swe4 swe3 swe2 swe1 00h 357 356 355 354 353 352 351 350 swr* 42ah swr7 swr6 swr5 swr4 swr3 swr2 swr1 00h 287 286 285 284 283 282 281 280 tcon* timer 0/1 control 410h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 high 451h 00h th1 timer 1 high 453h 00h tl0 timer 0 low 450h 00h tl1 timer 1 low 452h 00h tmod timer 0/1 mode 45ch gate c/t m1 m0 gate c/t m1 m0 00h
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 12 name reset value bit functions and addresses msb lsb sfr address description 28f 28e 28d 28c 28b 28a 289 288 tstat* timer 0/1 extended status 411h t1oe t0oe 00h 2ff 2fe 2fd 2fc 2fb 2fa 2f9 2f8 wdcon* watchdog control 41fh pre2 pre1 pre0 wdrun wdtof 6 wdl watchdog timer reload 45fh 00h wfeed1 watchdog feed 1 45dh x wfeed2 watchdog feed 2 45eh x notes: * sfrs marked with an asterisk (*) are bit addressable. # sfrs marked with a pound sign (#) are additional sfr registers specific to the xa-h3 and XA-H4. 1. the XA-H4 implements an 8-bit sfr bus, as stated in chapter 8 of the ic25 data handbook xa user guide . all sfr accesses must be 8-bit operations. attempts to write 16 bits to an sfr will actually write only the lower 8 bits. 16-bit sfr reads will return u ndefined data in the upper byte. 2. sfr is loaded from the reset vector. 3. f1, f0, and p reset to a0o. all other bits are loaded from the reset vector. 4. unimplemented bits in sfrs are axo (unknown) at all times. a1os should not be written to these bits since they may be used fo r other purposes in future xa derivatives. the reset value shown for these bits is a0o. 5. port configurations default to quasi-bidirectional when the xa begins execution after reset. thus all pncfga registers will c ontain ffh and pncfgb register will contain 00h. see warning in XA-H4 user manual about p3.2_timer0_resetout pin during first 258 clocks after power up. basically, during this period, this pin may output a strongly-driven low pulse. if the pulse does occur, it will terminate in a transition to high at a time no later than the 259th system clock after valid v cc power up. 6. the wdcon reset value is e6 for a watchdog reset; e4 for all other reset causes. 7. the rstsrc register reflects the cause of the last xa reset. one bit will be set to a1o, the others will be a0o. rstsrc[7] en ables the resetout function; a1o = enabled, a0o = disabled. see XA-H4 user manual for details; rstsrc[7] differs in function from most other xa derivatives. 8. the xa guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. this prevents loss of an interrupt or other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read-modify-write operation. XA-H4 sfr bits that are guarded in this manner are: tf1, tf0, ie1, and ie0 (in tcon), and wdtof (in wdcon).
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 13 table 3. memory mapped registers (mmr) mmr name read/write or read only size address offset description reset value usart0 registers usart0 write register 0 r/w 8 800h command register 00h usart0 write register 1 r/w 8 802h tx/rx interrupt & data transfer mode xx usart0 write register 2 r/w 8 804h extended features control xx usart0 write register 3 r/w 8 806h receive parameter and control 00h usart0 write register 4 r/w 8 808h tx/rx miscellaneous parameters & mode 00h usart0 write register 5 r/w 8 80ah tx parameter and control 00h usart0 write register 6 (XA-H4 only) r/w 8 80ch hdlc/sdlc address field or asynch match character 0 00h usart0 write register 7 r/w 8 80eh hdlc/sdlc flag or match character 1 xx usart0 write register 8 r/w 8 810h transmit data buffer xx usart0 write register 9 r/w 8 812h master interrupt control xx usart0 write register 10 r/w 8 814h miscellaneous tx/rx control register 00h usart0 write register 11 r/w 8 816h clock mode control xx usart0 write register 12 r/w 8 818h lower byte of baud rate time constant 00h usart0 write register 13 r/w 8 81ah upper byte of baud rate time constant 00h usart0 write register 14 r/w 8 81ch miscellaneous control bits xx usart0 write register 15 r/w 8 81eh external/status interrupt control f8h usart0 write register 16 r/w 8 828h match character 2 (wr16) 00h usart0 write register 17 r/w 8 82ah match character 3 (wr17) 00h usart0 read register 0 ro 8 820h tx/rx buffer and external status usart0 read register 1 ro 8 822h receive condition status/residue code reserved do not write 824h usart0 read register 3 ro 8 826h interrupt pending bits see wr16 and 17 82882ah see wr16 and 17 above usart0 read register 6 ro 8 82ch sdlc byte count low register usart0 read register 7 ro 8 82eh sdlc byte count high and fifo status usart0 read register 8 ro 8 830h receive buffer reserved 832h usart0 read register 10 ro 8 834h loop/clock status reserved 836-83eh usart1 registers usart1 write register 0 r/w 8 840h command register 00h usart1 write register 1 r/w 8 842h tx/rx interrupt & data transfer mode xx usart1 write register 2 r/w 8 844h extended features control xx usart1 write register 3 r/w 8 846h receive parameter and control 00h usart1 write register 4 r/w 8 848h tx/rx miscellaneous parameters & mode 00h usart1 write register 5 r/w 8 84ah tx parameter and control 00h usart1 write register 6 r/w 8 84ch hdlc/sdlc address field or match character 0 00h usart1 write register 7 r/w 8 84eh hdlc/sdlc flag or async match character 1 xx usart1 write register 8 r/w 8 850h transmit data buffer xx usart1 write register 9 r/w 8 852h master interrupt control xx usart1 write register 10 r/w 8 854h miscellaneous tx/rx control register 00h usart1 write register 11 r/w 8 856h clock mode control xx usart1 write register 12 r/w 8 858h lower byte of baud rate time constant 00h usart1 write register 13 r/w 8 85ah upper byte of baud rate time constant 00h
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 14 mmr name reset value description address offset size read/write or read only usart1 write register 14 r/w 8 85ch miscellaneous control bits xx usart1 write register 15 r/w 8 85eh external/status interrupt control f8h usart1 write register 16 r/w 8 868h match character 2 (wr16) 00h usart1 write register 17 r/w 8 86ah match character 3 (wr17) 00h usart1 read register 0 ro 8 860h tx/rx buffer and external status usart1 read register 1 ro 8 862h receive condition status/residue code reserved 864h usart1 read register 3 ro 8 866 interrupt pending bits see wr16 and wr17 8 86ch see wr16 and 17 above usart1 read register 6 ro 8 86eh sdlc byte count low register usart1 read register 7 ro 8 86eh sdlc byte count high and fifo status usart1 read register 8 ro 8 870h receive buffer reserved 872h usart1 read register 10 ro 8 874h loop/clock status reserved 876-87eh usart2 registers usart2 write register 0 r/w 8 880h command register 00h usart2 write register 1 r/w 8 882h tx/rx interrupt & data transfer mode xx usart2 write register 2 r/w 8 884h extended features control xx usart2 write register 3 r/w 8 886h receive parameter and control 00h usart2 write register 4 r/w 8 888h tx/rx miscellaneous parameters & mode 00h usart2 write register 5 r/w 8 88ah tx parameter and control 00h usart2 write register 6 r/w 8 88ch hdlc/sdlc address field or match character 0 00h usart2 write register 7 r/w 8 88eh hdlc/sdlc flag or match character 1 xx usart2 write register 8 r/w 8 890h transmit data buffer xx usart2 write register 9 r/w 8 892h master interrupt control xx usart2 write register 10 r/w 8 894h miscellaneous tx/rx control register 00h usart2 write register 11 r/w 8 896h clock mode control xx usart2 write register 12 r/w 8 898h lower byte of baud rate time constant 00h usart2 write register 13 r/w 8 89ah upper byte of baud rate time constant 00h usart2 write register 14 r/w 8 89ch miscellaneous control bits xx usart2 write register 15 r/w 8 89eh external/status interrupt control f8h usart2 write register 16 r/w 8 8a8h match character 2 (wr16) 00h usart2 write register 17 r/w 8 8aah match character 3 (wr17) 00h usart2 read register 0 ro 8 8a0h tx/rx buffer and external status usart2 read register 1 ro 8 8a2h receive condition status reserved 8a4h usart2 read register 3 ro 8 8a6h interrupt pending bits see wr16 and wr17 8 8ach see wr16 and 17 above usart2 read register 6 ro 8 8aeh sdlc byte count low register usart2 read register 7 ro 8 8aeh sdlc byte count high and fifo status usart2 read register 8 ro 8 8b0h receive buffer reserved 8b2h usart2 read register 10 ro 8 8b4h loop/clock status reserved 8b6-8beh
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 15 mmr name reset value description address offset size read/write or read only usart3 registers usart3 write register 0 r/w 8 8c0h command register 00h usart3 write register 1 r/w 8 8c2h tx/rx interrupt & data transfer mode xx usart3 write register 2 r/w 8 8c4h extended features control xx usart3 write register 3 r/w 8 8c6h receive parameter and control 00h usart3 write register 4 r/w 8 8c8h tx/rx miscellaneous parameters & mode 00h usart3 write register 5 r/w 8 8cah tx parameter and control 00h usart3 write register 6 r/w 8 8cch hdlc/sdlc address field or match character 0 00h usart3 write register 7 r/w 8 8ceh hdlc/sdlc flag or match character 1 xx usart3 write register 8 r/w 8 8d0h transmit data buffer xx usart3 write register 9 r/w 8 8d2h master interrupt control xx usart3 write register 10 r/w 8 8d4h miscellaneous tx/rx control register 00h usart3 write register 11 r/w 8 8d6h clock mode control xx usart3 write register 12 r/w 8 8d8h lower byte of baud rate time constant 00h usart3 write register 13 r/w 8 8dah upper byte of baud rate time constant 00h usart3 write register 14 r/w 8 8dch miscellaneous control bits xx usart3 write register 15 r/w 8 8deh external/status interrupt control f8h usart3 write register 16 r/w 8 8e8h match character 2 (wr16) 00h usart3 write register 17 r/w 8 8eah match character 3 (wr17) 00h usart3 read register 0 ro 8 8e0h tx/rx buffer and external status usart3 read register 1 ro 8 8e2h receive condition status/residue code reserved 8e4h usart3 read register 3 ro 8 8e6h interrupt pending bits usart3 read register 6 ro 8 8ech sdlc byte count low register usart3 read register 7 ro 8 8eeh sdlc byte count high and fifo status usart3 read register 8 ro 8 8f0h receive buffer reserved 8f2h usart3 read register 10 ro 8 8f4h loop/clock status reserved 8f6-8feh rx dma registers dma control register ch.0 rx r/w 8 100h control register 00h fifo control & status reg ch.0 rx r/w 8 101h control & status register 00h segment register ch.0 rx r/w 8 102h points to 64 k data segment 00h buffer base register ch.0 rx r/w 8 104h wrap reload value for a15 a8, a7 a0 reloaded to zero by hardware 00h buffer bound register ch.0 rx r/w 16 106h upper bound (plus 1) on a15 a0 0000h address pointer reg ch.0 rx r/w 16 108h current address pointer a15 a0 0000h byte count register ch.0 rx r/w 16 10ah corresponds to a15 a0 byte count, generates interrupt if enabled and byte count exceeded. 0000h data fifo register ch.0 lo rx r/w 16 10ch 10ch = byte 0 = older, 10dh = byte 1 = younger 00h 00h data fifo register ch.0 hi rx r/w 16 10eh 10eh = byte 2 = older, 10fh = byte 3 = younger 00h 00h dma control register ch.1 rx r/w 8 110h control register 00h fifo control & status register ch.1 rx r/w 8 111h control & status register 00h segment register ch. 1 rx r/w 8 112h points to 64 k data segment 00h
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 16 mmr name reset value description address offset size read/write or read only buffer base register ch. 1 rx r/w 8 114h wrap reload value for a15 a8, a7 a0 reloaded to zero by hardware 00h buffer bound register ch.1 rx r/w 16 116h upper bound (plus 1) on a15 a0 0000h address pointer reg ch.1 rx r/w 16 118h current address pointer a15 a0 0000h byte count register ch.1 rx r/w 16 11ah corresponds to a15 a0 byte count, generates interrupt if enabled and byte count exceeded. 0000h data fifo register ch.1 lo rx r/w 16 11ch 11ch = byte 0 = older, 11dh = byte 1 = younger 00h 00h data fifo register ch.1 hi rx r/w 16 11eh 11eh = byte 2 = older, 11fh = byte 3 = younger 00h 00h dma control register ch.2 rx r/w 8 120h control register 00h fifo control & status register ch.2 rx r/w 8 121h control & status register 00h segment register ch. 2 rx r/w 8 122h points to 64 k data segment 00h buffer base register ch. 2 rx r/w 8 124h wrap reload value for a15 a8, a7 a0 reloaded to zero by hardware 00h buffer bound register ch.2 rx r/w 16 126h upper bound (plus 1) on a15 a0 0000h address pointer reg ch.2 rx r/w 16 128h current address pointer a15 a0 0000h byte count register ch.2 rx r/w 16 12ah corresponds to a15 a0 byte count, generates interrupt if enabled and byte count exceeded. 0000h data fifo register ch.2 lo rx r/w 16 12ch 12ch = byte 0 = older, 12dh = byte 1 = younger 00h 00h data fifo register ch.2 hi rx r/w 16 12eh 12eh = byte 2 = older, 12fh = byte 3 = younger 00h 00h dma control register ch.3 rx r/w 8 130h control register 00h fifo control & status register ch.3 rx r/w 8 131h control & status register 00h segment register ch. 3 rx r/w 8 132h points to 64 k data segment 00h buffer base register ch. 3 rx r/w 8 134h wrap reload value for a15 a8, a7 a0 reloaded to zero by hardware 00h buffer bound register ch.3 rx r/w 16 136h upper bound (plus 1) on a15 a0 0000h address pointer reg ch.3 rx r/w 16 138h current address pointer a15 a0 0000h byte count register ch.3 rx r/w 16 13ah corresponds to a15 a0 byte count, generates interrupt if enabled and byte count exceeded. 0000h data fifo register ch.3 lo rx r/w 16 13ch 13ch = byte 0 = older, 13dh = byte 1 = younger 00h 00h data fifo register ch.3 hi rx r/w 16 13eh 13eh = byte 2 = older, 13fh = byte 3 = younger 00h 00h tx dma registers dma control register ch.0 tx r/w 8 140h control register 00h fifo control & status register ch.0 tx r/w 8 141h control & status register 00h segment register ch. 0 tx r/w 8 142h points to 64 k data segment 00h buffer base register ch. 0 tx r/w 8 144h wrap reload value for a15 a8, a7 a0 reloaded to zero by hardware 00h buffer bound register ch.0 tx r/w 16 146h upper bound (plus 1) on a15 a0 0000h address pointer reg ch.0 tx r/w 16 148h current address pointer a15 a0 0000h byte count register ch.0 tx r/w 16 14ah corresponds to a15 a0 byte count, generates interrupt if enabled and byte count exceeded. 0000h data fifo register ch.0 tx r/w 16 14ch 14c = byte0 = older 14d = byte 1 = younger 0000h
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 17 mmr name reset value description address offset size read/write or read only data fifo register ch.0 tx r/w 16 14eh 14e = byte2 = older 14f = byte3 = younger 0000h dma control register ch.1 tx r/w 8 150h control register 00h fifo control & status register ch.1 tx r/w 8 151h control & status register 00h segment register ch.1 tx r/w 8 152h points to 64 k data segment 00h buffer base register ch.1 tx r/w 8 154h wrap reload value for a15 a8, a7 a0 reloaded to zero by hardware 00h buffer bound register ch.1 tx r/w 16 156h upper bound (plus 1) on a15 a0 0000h address pointer reg ch.1 tx r/w 16 158h current address pointer a15 a0 0000h byte count register ch.1 tx r/w 16 15ah corresponds to a15 a0 byte count, generates interrupt if enabled and byte count exceeded. 0000h data fifo register ch.1 lo tx r/w 16 15ch byte0 & 1 0000h data fifo register ch.1 hi tx r/w 16 15eh byte2 & 3 0000h dma control register ch.2 tx r/w 8 160h control register 00h fifo control & status register ch.2 tx r/w 8 161h control & status register 00h segment register ch.2 tx r/w 8 162h points to 64 k data segment 00h buffer base register ch.2 tx r/w 8 164h wrap reload value for a15 a8, a7 a0 reloaded to zero by hardware 00h buffer bound register ch.2 tx r/w 16 166h upper bound (plus 1) on a15 a0 0000h address pointer reg ch.2 tx r/w 16 168h current address pointer a15 a0 0000h byte count register ch.2 tx r/w 16 16ah corresponds to a15 a0 byte count, generates interrupt if enabled and byte count exceeded. 0000h data fifo register ch.2 lo tx r/w 16 16ch byte0 & 1 0000h data fifo register ch.2 hi tx r/w 16 16eh byte2 & 3 0000h dma control register ch.3 tx r/w 8 170h control register 00h fifo control & status register ch.3 tx r/w 8 171h control & status register 00h segment register ch. 3 tx r/w 8 172h points to 64 k data segment 00h buffer base register ch. 3 tx r/w 8 174h wrap reload value for a15 a8, a7 a0 reloaded to zero by hardware 00h buffer bound register ch.3 tx r/w 16 176h upper bound (plus 1) on a15 a0 0000h address pointer reg ch.3 tx r/w 16 178h current address pointer a15 a0 0000h byte count register ch.3 tx r/w 16 17ah corresponds to a15 a0 byte count, generates interrupt if enabled and byte count exceeded. 0000h data fifo register ch.3 lo tx r/w 16 17ch byte0 & 1 0000h data fifo register ch.3 hi tx r/w 16 17eh byte2 & 3 0000h r/w 180-1feh reserved for future dma miscellaneous dma registers rx character time out register ch.0 r/w 8 200h 0 value disables counter interrupt 00h rx character time out register ch.1 r/w 8 202h same as above, for rx1 00h rx character time out register ch.2 r/w 8 204h same as above, for rx2 00h rx character time out register ch.3 r/w 8 206h same as above, for rx3 00h global dma interrupt register r/w 16 210h dma interrupt flags 0000h gpout r/w 8 260h gpout[7] drives pin 98 (gpout ) through an inverter. gpout[6-0] are unused, and must be written with zeroes. 8xh autobaud registers (h4 only) bdaee (h4 only) r/w 8 270h autobaud echo enable (h4 only) 00h bdcs (h4 only) r/w 8 272h autobaud control and status (h4 only) 00h
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 18 mmr name reset value description address offset size read/write or read only memory interface (mif) registers b0cfg r/w 8 280h mif bank 0 config 0fh b0am r/w 8 281h mif bank 0 base address 00h b0tmg r/w 8 282h mif bank 0 timing params b1cfg r/w 8 284h mif bank 1 config b1am r/w 8 285h mif bank 1 base address b1tmg r/w 8 286h mif bank 1 timing params b2cfg r/w 8 288h mif bank 2 config b2am r/w 8 289h mif bank 2 base address b2tmg r/w 8 28ah mif bank 2 timing params b3cfg r/w 8 28ch mif bank 3 config b3am r/w 8 28dh mif bank 3 base address b3tmg r/w 8 28eh mif bank 3 timing params b4cfg r/w 8 290h mif bank 4 config b4am r/w 8 291h mif bank 4 base address b4tmg r/w 8 292h mif bank 4 timing params b5cfg r/w 8 294h mif bank 5 config b5am r/w 8 295h mif bank 5 base address b5tmg r/w 8 296h mif bank 5 timing params mbcl r/w 8 2beh mif memory bank configuration lock register rfsh r/w 8 2bfh mif refresh control miscellaneous registers hi-pri soft ints & pin mux control reg. r/w 16 2d0h control bits for hi-priority soft ints, and pin mux 0000h xint2 r/w 8 2d2h external interrupt 2 control 00h functional description the XA-H4 functions are described in the following sections. because all blocks are thoroughly documented in either the ic25 xa data handbook , or the XA-H4 user manual , only brief descriptions are given in this datasheet in conjunction with references to the appropriate document. xa cpu the cpu is a 30 mhz implementation of the standard xa cpu core. see the xa data handbook (ic25) for details. the cpu core is identical to the g3 core. see the caveat in the next paragraph about the bus interface unit. bus interface unit (biu) this is the internal bus, not the bus at the pins. this internal bus connects the cpu to the mif (memory and dram controller.) warning: immediately after reset, always write btrh = 51h, followed by btrl = 40h, in that order. once written, do not change the values in these registers. follow these two writes with five nops. never write to the bcr register. it comes out of reset initialized to 07h, which is the only value that will work. su01273 xa cpu mif and dram controller biu dma channels x8 external memory and i/o bus internal cpu bus figure 1. xa cpu core biu (bus interface unit) timers 0 and 1 timers 0 and 1 are the standard xa-g3 timer 0 and 1. each has an associated i/o pin and interrupt. see the xa-g3 data sheet in the ic25 xa data handbook for details. many xa derivatives include a standard xa timer 2 and standard uarts. these blocks have been removed in order to provide other functions on the XA-H4. there is no timer 2 and the uarts have been replaced with full function usarts.
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 19 watchdog timer this timer is a standard xa-g3 watchdog timer. see the g3 datasheet in ic25. also, if you intend to use the watchdog timer to assert the resetout pin, see aresetout o in the XA-H4 user manual . the watchdog timer is enabled at reset, and must be periodically fed to prevent timeout. if the watchdog times out, it will generate an internal reset; if resetout is enabled, the internal reset will generate a resetout pulse (active low pulse on resetout pin.) reset on the XA-H4 there are two pins associated with reset. the resetin pin provides an external reset into the XA-H4. the port pin p3.2_timer0_resetout output can be configured as resetout . because resetout does not reflect resetin , the resetout pin can be tied directly back into the resetin pin without other pc board logic. this configuration will make all resets (internal or external) appear to the xa as external resets. see the XA-H4 user manual for a full discussion of the reset functions. resetin the resetin function is the standard xa-g3 resetin function. the resetin signal does not get passed on to resetout . see the XA-H4 user manual for details on reset. resetout the p3.2_timer0_resetout pin provides an external indication (if the resetout function is enabled in the rsrsrc register) via an active low output when an internal reset occurs (internal reset is reset instruction or watchdog time out.) if the resetout function is enabled, the resetout pin will be driven low when a watchdog reset occurs or the reset instruction is executed. this signal may be used to inform other devices in the system that the XA-H4 has been internally reset. the resetin signal does not get passed on to resetout . when activated, the duration of the resetout pulse is 256 system clocks. warning: at power on time, from the time that power coming up is valid, the p3.2_timer0_resetout pin may be driven low for any period from zero nanoseconds up to 258 system clocks. this is true independently of whether resetin is active or not. reset source register the reset source identification register (rstsrc) indicates the cause of the most recent xa reset. the cause may have been an externally applied reset signal, execution of the reset instruction, or a watchdog reset. figure 2 shows the fields in the rstsrc register. if the resetout function is tied back into the resetin pin, then all resets will be external resets, and will thus appear as external resets in the reset source register. rstsrc[7] enables the resetout function; 1 = enabled, 0 = disabled. see XA-H4 user manual for details; rstsrc[7] differs in function from most other xa derivatives. rstsrc.7 roen resetout function enable bit see xa-h3 user manual for details rstsrc.6 reserved for future use. should not be set to 1 by user programs. rstsrc.5 reserved for future use. should not be set to 1 by user programs. rstsrc.4 reserved for future use. should not be set to 1 by user programs. rstsrc.3 reserved for future use. should not be set to 1 by user programs. rstsrc.2 r_wd indicates that the last reset was caused by a watchdog timer overflow (see warning.) rstsrc.1 r_cmd indicates that the last reset was caused by execution of the reset instruction (see warning.) rstsrc.0 r_ext indicates that the last reset was caused by the external resetin input. rstsrc reset value = see below roen e e e e r_wd r_cmd r_ext not bit addressable bit symbol function warning: if resetout function is tied back into resetin pin, rstsrc will always show external reset only, because external reset always takes precedence over internal reset. su01237 reg type and address = sfr 463h lsb msb figure 2. rstsrc reset source register dram controller and memory / i/o bus interface (mif) in the memory or system bus interface terminology, generic bus cycles are synonymous with sram bus cycles, because these cycles are designed to service srams, flash, eeprom, peripheral chips, etc. chip select output pins function as either cs or ras (drams and thus ras on x-4h only) depending on whether the memory bank has been programmed as generic or dram. the XA-H4 has a highly programmable memory bus interface with a complete complete onboard dram controller. most drams (up to 8 mb per ras pin), srams, flash, roms, and peripheral chips can be connected to this interface with zero glue chips. the bus interface provides 6 mappable chip select outputs, five of which can be programmed to function as ras strobes to dram. cas generation, proper address multiplexing for a wide range of dram sizes, and refresh are all generated onboard. the bus timing for each individual
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 20 memory bank or peripheral can be programmed to accommodate slow or fast devices. each memory bank and its associated ras (chip select in dram mode) output, can be programmed to access up to an 8 mb mappable address space in either edo or fpm dram modes (up to a total of 32 mb of dram. warning: future XA-H4 derivatives may not support separate code and data spaces.) each memory bank and associated chip select programmed for agenerico (sram, flash, rom, peripheral chips, etc.) is capable of supporting a 1 mb address space. the memory interface can be programmed to support both intel style and 68000 bus style srams and peripherals. su01274 cs5 or ras5 (or p3.1, rts1 ) cs4 or ras4 (or p3.0, rtclk1 ) cs3 or ras3 cs2 or ras2 cs1 or ras1 cs0 a19a0 (on dram cycle, a22 a0 are time-multiplexed for ras/cas) d15d0 clkout bhe or cash ble or casl oe we wait, size16 XA-H4 memory interface dram controller sram controller dynamic bus sizing progammable bus timing figure 3. memory bus interface signal pins bus interface pins for the following discussion, see figure 3. chip select pins there are six chip select pins (cs5 cs0 ) mapped to six sets of bank control registers. the following attributes are individually programmable for each bank and associated chip select (or ras , if dram): bank on/off, address range, external device access time, detailed bus strobe sequence, dram cycle or generic bus cycle, dram size if dram, and bus width. pin cs0 is always generic in order to service the boot device, thus cs0 cannot be connected to dram. warning: on the external bus, all XA-H4 reads are 16-bit reads. if the cpu instruction only specifies 8-bits, then the cpu uses the appropriate byte, and discards the extra byte. thus a8-bit readso and a16-bit readso appear to be identical on the bus. on an 8-bit bus, this will appear as two consecutive 8-bit reads even though the cpu instruction specified a byte read. some 8-bit i/o devices (especially fifos) cannot operate correctly with 2 bytes being read for a 1 byte read. the most common ( and least expensive) solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. an added benefit of this technique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 21 clock output the clkout pin allows easier external bus interfacing in some situations. this output reflects the xtalin clock input to the xa (referred to internally as cclk or system clock), but is delayed to match the external bus outputs and strobes. the default is for clkout to be output enabled at reset, but it may be turned off (tri-state disabled) by software via the micfg mmr. warning: the capacitive loading on this output must not exceed 40 pf. cs oe a16a0 d7d0 we a9a0 d15d0 su01275 cs0 cs1 oe a19a0 d15d0 cs3 ble bhe we XA-H4 ras casl cash we a15a1 d15d0 32 k x 16 sram 1 m x 16 dram (mt4c1m16c3) d15d0 note: the 16-bit wide ram does not need the a0 pin from the processor. during byte writes to the ram, the a0 value will cause either ble or bhe pin to go active from the xa-h3, but not to both. for all word writes, word reads, code fetches, and byte reads, both ble and bhe will go active.during dram cycles only, the appropriate cas address will be multiplexed onto pins a17 a7 after the assertion of ras and prior to the assertion of bhe (cash ) and ble (casl .) see ac timing diagrams and the XA-H4 user manual for complete details. cs2 a17a8 d15d0 a15a1 oe 256 k x 16 dram (hm514260di) 128 k x 8 rom cash casl ras we a8a0 d15d0 oe cash casl ras a17a9 d15d0 a16a0 d7d0 figure 4. typical system bus configuration
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 22 table 4. memory interface control registers register name reg type description mrbh ammr base addresso high sfr 8 bits this sfr is used to relocate the mmrs. it contains address bits a23 a16 of the base address for the 4 kb memory mapped register space. see the XA-H4 user manual for using this sfr to relocate the mmrs. mrbl ammr base addresso low sfr 8 bits contains address bits a15 a12 of the base address for the 4 kb memory mapped register space. micfg mif configuration mmr 8 bits contains the clkout enable bit. mbcl memory bank configuration lock mmr 8 bits contains the bits for locking and unlocking the bicfg registers. bicfg bank i configuration mmr 8 bits contains the size, type, bus width, and enable bits for memory bank i. biam bank i base address/dram address multiplexer control mmr 8 bits contains the base address bits and dram address multiplex control bits for memory bank i. bitmg bank i timing mmr 8 bits contains the timing control bits for memory bank i. rfsh refresh timing mmr 8 bits contains the refresh time constant and dram refresh timer enable bit. eight channel dma controller the xa-h3/h4 has eight dma channels; one rx dma channel dedicated to each usart receive (rx) channel, and one tx dma channel dedicated to each usart transmit (tx) channel. all dma channels are optimized to support memory efficient circular data buffers in external memory. all dma channels can also support traditional linear data buffers. transmit dma channel modes the four tx channels have four dma modes specifically designed for various applications of the attached usarts. these modes are summarized in table 5. full details for all dma functions can be found in the dma chapter of the XA-H4 user manual . table 5. tx dma modes summary mode byte count source maskable interrupt description non-sdlc/hdlc tx chaining header in memory on stop dma channel picks up header from memory at the end of transmission. if the byte count in the header is greater than zero, then dma transmits the number of bytes specified in the byte count. if byte count equals 0, then a maskable interrupt is generated. this process repeats until the byte count in the data header is zero. see XA-H4 user manual for details. sdlc/hdlc tx chaining header in memory end of packet (not end of fragment) same as above, except dma header distinguishes between fragment of packet and full pack. see XA-H4 user manual for details. stop on tc processor loads byte count register (for each fragment) byte count completed (tx dma stops) processor loads byte count into dma. dma sends that number of bytes, generates maskable interrupt, and stops. periodic interrupt porcessor loads byte count register (only once) when byte counter reaches zero and is reloaded by dma hardware from the byte count register. dma runs until commanded to stop by processor. every time byte counter rolls over, a new maskable interrupt is generated.
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 23 receive dma channel modes the rx dma channels have four dma modes specifically designed for various applications of the attached usarts. these modes are summarized in table 6. for full details on implementation and use, see the XA-H4 user manual . table 6. rx dma modes summary mode byte count source maskable interrupt description sdlc/hdlc rx chaining dma stores byte count in header in memory with data packet. at end of received packet when a complete or aborted sdlc/hdlc packet has been received, the packet byte count and status information are stored in memory with the packet. a maskable interrupt is generated. periodic interrupt loaded by processor into dma, used only to determine the number of bytes between interrupts. processor can infer the byte count from the dma address pointer. when byte counter reaches zero and is reloaded by dma hardware from the byte count register. the dma channel runs until commanded to stop by the processor. it generates a maskable interrupt once per n bytes, where n is the number written once into the byte count register by the processor, thus an interrupt is generated once every n received bytes. asynchronous character time out byte count can be calculated by software from the dma address pointer. if no character is received within a specified time out period, then interrupt. processor specifies time out period between incoming characters. if no character is received within that time, a maskable interrupt is generated. asynchronous character match byte count can be calculated by software from the dma address pointer. when matched character is stored in memory. there are four match registers, each incoming character is received within that time, a maskable interrupt is generated. when a matched character is stored in memory by dma, a maskable interrupt is generated. su01240 data fifo 3 data fifo 1 data fifo 2 data fifo 0 dma control segment buffer base buffer bound address pointer byte count fifo control rx time out data fifo 3 data fifo 1 data fifo 2 data fifo 0 rx channel tx channel dma control segment buffer base buffer bound address pointer byte count fifo control figure 5. rx and tx dma registers
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 24 dma registers in addition to the 16-bit global dma interrupt register (which is shared by all eight dma channels), each dma channel has seven control registers and a four-byte data fifo. the four rx dma channels have one additional register, the rx character time out register. all dma registers can be read and written in memory mapped register (mmr) space. these registers are summarized below. ? global dma interrupt register (not shown in figure): all dma interrupt flags are in this register . ? dma control register: contains the master mode select and interrupt enable bits for the channel. ? segment register: holds a23a16 (the current segment) of the 24-bit data buffer address. ? buffer base register: holds a pointer (a15a8) to the lowest byte in the memory buffer. ? buffer bound register: points to the first out-of-bounds address above a circular buffer. ? address pointer register: points to a single byte or word in the data buffer in memory. the 24-bit dma address is formed by concatenating the contents of the segment register [a23a16] with the contents of the address pointer register [a15a0]. ? byte count register: holds the initial number of bytes to be transferred. in tx chaining mode, this register is not used because the byte count is brought into the byte counter from buffer headers in memory. ? fifo control & status register: holds the queuing order and full/empty status for the data fifo registers. ? data fifo registers: a four-byte data fifo buffer internal to the dma channel. ? rx char time out register (rxctor, rx dma channels only): holds the initial value for an 8-bit character timeout countdown timer which can generate an interrupt. four usarts ? asynchronous features: asynchronous transfers up to 921.6 kbps can monitor input stream for up to four match characters per receiver (h4 only) 5, 6, 7, or 8 data bits per character 1, 1.5, or 2 stop bits per character even or odd parity generate and check parity, rx overrun, and framing error detection break detection supports hardware autobaud detection and response up to 921.6 kbps. ? sdlc/hdlc features: automatic flag and abort character generation and recognition automatic crc generation and checking (can be disabled for apass-thruo) automatic zero-bit insertion and stripping automatic partial byte residue code generation 14-bit packet byte count stored in memory with received packet by dma ? synchronous character-oriented protocol features (XA-H4 only): automatic crc generation and checking external sync option ? data encoding/decoding options: fm0 (biphase space) fm1 (biphase mark) nrz nrzi ? programmable baud rate generator ? auto echo and local loopback modes autobaud detectors each usart has its own autobaud detector, capable of baud rate detection up to 921.6 kbaud. the detectors can be programmed to automatically echo the industry standard autobaud sequences. they can be programmed to update the necessary control registers in the usarts and turn on the receiver, which in turn will automatically initiate dma into memory of received data. thus, once the baud rate is determined, reception begins without intervention from the processor. when the baud rate is detected, a maskable interrupt is sent to the processor. see the aautobaudo chapter in the XA-H4 user manual for details. i/o port output configuration port input/output configurations are the same as standard xa ports: open drain, quasi-bidirectional, push-pull, and off (off means tri-state hi-z, and allows the pin to be used as an input. warning: at power on time, from the time that power coming up is valid, the p3.2_timer0_resetout pin may be driven low for any period from zero nanoseconds up to 258 system clocks. this is true independently of whether resetin is active or not. power reduction modes the XA-H4 supports idle and power down modes of power reduction. the idle mode leaves most peripherals running in order to allow them to activate the processor when an interrupt is generated. the power down mode stops the oscillator in order to absolutely minimize power. the processor can be made to exit power down mode via a reset or one of the external interrupt inputs (int0 or int1). this will occur if the interrupt is enabled and its priority is higher than that defined by im3 through im0. in power down mode, the power supply voltage may be reduced to the ram keep-alive voltage v ram . this retains the ram, register, and sfr contents at the point where power down mode was entered. warning: v dd must be raised to within the operating range before power down mode is exited. interrupts in the xa architecture, all exceptions, including reset, are handled in the same general exception structure. the highest priority exception is, of course, reset, and is non-maskable. all exceptions are vectored through the exception vector table in low memory. coming out of reset, these vectors must be stored in non-volatile memory based at location 000000. later in the boot sequence, dram or sram can be mapped into this address space if desired. there is a feature in the XA-H4 memory controller called abank swapo that supports replacing the rom vector table and other low memory with ram. see the XA-H4 user manual for details.
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 25 the XA-H4 has a standard xa cpu interrupt controller, implemented with 15 maskable event interrupts. event interrupts are defined as maskable interrupts usually generated by hardware events. however, in the XA-H4, 4 of the 15 event interrupts are generated by software writing directly to the interrupt flag bit. these 4 interrupts are referred to as ahigh priority software interrupts.o see the ic25 xa data handbook for a full explanation of the exception structure, including event interrupts, of the xa cpu. because the high priority software interrupts are not implemented on all xa derivitives, they are explained in the XA-H4 user manual . su01276 xa core interrupt controller interrupt enable/ disable bits master enable aeao interrupt to xa cpu dmah dmal 4 dma interrupts usart0/ usart1 timer 0 timer 1 high priority software ints hswr 30 cts0 cd0 int1 int0 int2 usart2/ usart3 cts1 cd1 _int2 cts2 cd2 cts3 cd3 autobaud 30 figure 6. XA-H4 interrupt structure overview
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 26 table 7. usart0 interrupts (interrupt structure is the same, except for bit locations, for all 4 usarts) potential usart0 interrupt individual enable bit mmr hex offset source bit mmr hex offset group enable bit(s) mmr hex offset group flag bit mmr hex offset master enable bit mmr hex offset rx character available rr0[0] 820[0] wr1[4:3] 802[4:3] even channel rx ip rr3[5] 826[5] usart0/1 master interrupt enable wr9[3] 812[3] sdlc eof (XA-H4 only) rr1[7] 822[7] crc/framing error rr1[6] 822[6] rx overrun rr1[5] 822[5] parity error wr1[2] 802[2] rr1[4] 822[4] tx buffer empty see wr1[1] rr0[2] 820[2] tx interrupt enable wr1[1] 802[1] even channel tx ip rr3[4] 826[4] break/abort break/ abort ie wr15[7] 81e[7] rr0[7] 820[7] master external/status interrupt enable wr1[0] 802[0] even channel external/status ip rr3[3] 826[3] tx underrun/eom tx underrun/eom ie wr15[6] 81e[6] rr0[6] 820[6] cts cts ie wr15[5] 81e[5] rr0[5] 820[5] sync/hunt (XA-H4 only) sync/ hunt ie wr15[4] 81e[4] rr0[4] 822[4] dcd dcd ie wr15[3] 81e[3] rr0[3] 820[3] zero count zero count ie wr15[1] 81e[1] rr0[1] 820[1] exception/traps precedence description vector address arbitration ranking reset (h/w, watchdog, s/w) 00000003 0 (high) break point 00040007 1 trace 0008000b 1 stack overflow 000c000f 1 divide by 0 00100013 1 user reti 00140017 1 trap 015 (software) 0040007f 1
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 27 event interrupts description event interrupt source flag bit interrupt vector address enable bit (sfr) priority register bit field (sfr) arb. rank high priority software interrupt 3 hswr3 mmr 2d0[15] 00bf00bc ehswr3 427[7] 33f phswr3 4a7[6:4] 17 high priority software interrupt 2 hswr2 mmr 2d0[14] 00bb00b8 ehswr2 427[6] 33e phswr2 4a7[2:0] 16 high priority software interrupt 1 hswr1 mmr 2d0[13] 00b700b4 ehswr1 427[5] 33d phswr1 4a6[6:4] 15 high priority software interrupt 0 hswr0 mmr 2d0[12] 00b300b0 ehswr0 427[4] 33c phswr0 4a6[2:0] 14 usart ausart2/3o interrupt multiple or from usart2 & usart3 00a700a4 esc23 427[1] 339 psc23 4a4[6:4] 11 usart ausart0/1o interrupt multiple or from usart0 & usart1 00a300a0 esc01 427[0] 338 psc01 4a4[2:0] 10 dma admaho interrupt multiple or from dma 009b0098 edmah 426[6] 336 pdmah 4a3[2:0] 8 dma admalo interrupt multiple or from dma 00970094 edmal 426[5] 335 pdmal 4a2[6:4] 7 external interrupt 2 (int2 ) ie2 mmr 2d2[0] 00930090 ex2 426[4] 334 px2 4a2[2:0] 6 timer 1 tf1 sfr 410[7] 287 008f008c et1 426[3] 333 pt1 4a1[6:4] 5 external interrupt 1 (int1 ) ie1 sfr 410[3] 283 008b0088 ex1 426[2] 332 px1 4a1[2:0] 4 timer 0 tf0 sfr 410[5] 285 00870084 et0 426[1] 331 pt0 4a0[6:4] 3 external interrupt 0 (int0 ) ie0 sfr 410[1] 00830080 ex0 426[0] 330 px0 4a0[2:0] 2 software interrupts description flag bit vector address enable bit interrupt priority software interrupt 1 swr1 01000103 swe1 (fixed at 1) software interrupt 2 swr2 01040107 swe2 (fixed at 2) software interrupt 3 swr3 0108010b swe3 (fixed at 3) software interrupt 4 swr4 010c010f swe4 (fixed at 4) software interrupt 5 swr5 01100113 swe5 (fixed at 5) software interrupt 6 swr6 01140117 swe6 (fixed at 6) software interrupt 7 swr7 0118011b swe7 (fixed at 7)
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 28 absolute maximum ratings parameter rating unit operating temperature under bias 55 to +125 c storage temperature range 65 to +150 c voltage on any other pin to v ss 0.5 to v dd +0.5 v v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer, not device power consumption) 1.5 w preliminary dc electrical characteristics v dd = 5.0 v +/ 10% or 3.3 v +/ 10% unless otherwise specified; t amb = 40 c to +85 c for industrial, unless otherwise specified. symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit i dd power supply current, operating 5.0 v, 30 mhz 64 80 ma 3.3 v, 30 mhz 55 70 ma i id power supply current, idle mode 5.0 v, 30 mhz 50 70 ma 3.3 v, 30 mhz 44 60 ma i pdi power supply current, power down mode 1 5.0 v, 3.0 v 500 m a v ram ram keep-alive voltage 1.5 v v il input low voltage 0.5 0.22 v dd v v ih input high voltage, except xtal1, rst 2.2 v v ih1 input high voltage to xtal1, rst for both 3.0 & 5.0 v 0.7 v dd v v ol output low voltage all ports 8 i ol = 3.2 ma, v dd = 4.5 v 0.5 v i ol = 1.0 ma, v dd = 3.0 v 0.4 v v oh1 output high voltage, all ports i oh = 100 m a, v dd = 4.5 v 2.4 v i oh = 30 m a, v dd = 3.0 v 2.0 v v oh2 output high voltage, all ports i oh = 3.2 ma, v dd = 4.5 v 2.4 v i oh = 1.0 ma, v dd = 3.0 v 2.2 v c io input/output pin capacitance 15 pf i il logical 0 input current, all ports 7 v in = 0.45 v 50 m a i li input leakage current, all ports 6 v in = v il or v ih 10 m a i tl logical 1 to 0 transition current, all ports 5 at v dd = 5.5 v 650 m a at v dd = 3.6 v 250 m a note: 1. v dd must be raised to within the operating range before power down mode is exited. 2. ports in quasi-bidirectional mode with weak pullup. 3. ports in push-pull mode, both pullup and pulldown assumed to be the same strength. 4. in all output modes. 5. port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. this current i s highest when v in is approximately 2 v. 6. measured with port in high impedance mode. 7. measured with port in quasi-bidirectional mode. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma (note: this is +85 c specification for v dd = 5 v) maximum i ol per 8-bit port: 26 ma maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions.
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 29 preliminary ac electrical characteristics (5.0 v +/10%) v dd = 5.0 v +/ 10%; t amb = 40 c to +85 c (industrial) symbol fig re parameter limits unit symbol fig u re parameter min max unit all cycles f c system clock frequency 0 30 mhz t c 23 system clock period = 1/fc 33.33 ns t chcx 23 xtalin high time t c * 0.5 ns t clcx 23 xtalin low time t c * 0.4 ns t clch 23 xtalin rise time 5 ns t chcl 23 xtalin fall time 5 ns t avsl all address valid to strobe low t c 21 ns t chah all address hold after clkout rising edge 9 1 ns t chav all delay from clkout rising edge to address valid 25 ns t chsh all delay from clkout rising edge to strobe high 9 1 21 ns t chsl all delay from clkout rising edge to strobe low 9 1 19 ns t codh 24 clkout duty cycle high (into 40 pf max.) t chcx 7 t chcx +3 ns t cpwh 11, 12, 17, 18, 19, 20 cas pulse width high t c 12 ns t cpwl 11, 19 cas pulse width low t c 10 ns all dram cycles t rp 22 ras precharge time, thus minimum ras high time 8 (n * t c ) 16 8 ns generic data read only t ahdr 7, 14 address hold (a19 a1 only, not a0) after cs , ble , bhe rise at end of generic data read cycle (not code fetch) t c 12 ns data read and instruction fetch cycles t dis 7, 8, 10, 11, 12, 14, 15, 17, 18, 19 data in valid setup to clkout rising edge 25 ns t dih 7, 8, 10, 14, 15, 17, 18 data in valid hold after clkout rising edge 2 0 ns t ohde 8, 10, 11, 14, 18 oe high to xa data bus driver enable t c 14 ns write cycles t chdv 9, 13 clock high to data valid 25 ns t dvsl 16, 20 data valid prior to strobe low t c 23 ns t shah 9, 16 minimum address hold time after strobe goes inactive t c 25 ns t shdh 9, 16 data hold after strobes (cs and bhe /ble ) high t c 25 ns refresh t clrl 21 cas low to ras low t c 15 ns wait input t ws 25 wait setup (stable high or low) to clkout rising edge 20 ns t wh 25 wait hold (stable high or low) after clkout rising edge 0 ns note: 1. see notes after the 3.3 v ac timing table
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 30 ac electrical characteristics (3.3 v +/10%) v dd = 3.3 v +/ 10%; t amb = 40 c to +85 c (industrial) symbol fig re parameter limits unit symbol fig u re parameter min max unit all cycles f c system clock (internally called cclk) frequency 0 30 mhz t c 23 system clock period = 1/fc 33.33 ns t chcx 23 xtalin high time t c * 0.5 ns t clcx 23 xtalin low time t c * 0.4 ns t clch 23 xtalin rise time 5 ns t chcl 23 xtalin fall time 5 ns t avsl all address valid to strobe low t c 21 ns t chah all address hold after clkout rising edge 9 1 ns t chav all delay from clkout rising edge to address valid 30 ns t chsh all delay from clkout rising edge to strobe high 9 1 28 ns t chsl all delay from clkout rising edge to strobe low 9 1 25 ns t codh 24 clkout duty cycle high (into 40 pf max.) t chcx 7 t chcx +3 ns t cpwh 11, 12, 17, 18, 19, 20 cas pulse width high t c 12 ns t cpwl 11, 19 cas pulse width low t c 10 ns all dram cycles t rp 22 ras precharge time, thus minimum ras high time 8 (n * t c ) 16 8 ns data read only t ahdr 7, 14 address hold (a19 a1 only, not a0) after cs , ble , bhe rise at end of data read cycle (not code fetch) t c 12 ns data read and instruction fetch cycles t dis 7, 8, 10, 11, 12, 14, 15, 17, 18, 19 data in valid setup to clkout rising edge 32 ns t dih 7, 8, 10, 14, 15, 17, 18 data in valid hold after clkout rising edge 2 0 ns t ohde 8, 10, 11, 14, 18 oe high to xa data bus driver enable t c 19 ns write cycles t chdv 9, 13 clock high to data valid 30 ns t dvsl 16, 20 data valid prior to strobe low t c 23 ns t shah 9, 16 minimum address hold time after strobe goes inactive t c 25 ns t shdh 9, 16 data hold after strobes (cs and bhe /ble ) high t c 25 ns refresh t clrl 21 cas low to ras low t c 15 ns wait input t ws 25 wait setup (stable high or low) prior to clkout rising edge 25 ns t wh 25 wait hold (stable high or low) after clkout rising edge 0 ns note: 1. on a 16-bit bus, if only one byte is being written, then only one of ble _casl or bhe _cash will go active. on an 8-bit bus, ble _casl goes active for all (odd or even address) accesses. bhe _cash will not go active during any accesses on an 8-bit bus. 2. the bus timing is designed to make meeting hold time very straightforward without glue logic. on all generic reads and fetche s, in order to meet hold time, the slave should hold data valid on the bus until the earliest of cs , bhe /ble , oe , goes high (inactive), or until the address changes. on all fpm dram reads and fetches, hold data valid on the bus until a new cas is asserted, or until oe goes high (inactive). 3. to avoid 3-state fights during read cycles and fetch cycles, do not drive data bus until oe goes active. 4. to meet hold time, edo dram drives data onto the bus until oe rises, or until a new falling edge of cas . 5. warning: clkout is specified at 40 pf max. more than 40 pf on clkout may significantly degrade the clkout waveform. load capacitance for all outputs (except clkout) = 80 pf. 6. not all combinations of bus timing configuration values result in valid bus cycles. please refer to the XA-H4 user manual for details. 7. when code is being fetched on the external bus, a burst mode fetch is used. this burst can be from 2 to 16 bytes long. on a 1 6-bit bus, a3 a1 are incremented for each new word of the burst. on an 8-bit bus, a3 a0 are incremented for each new byte of the burst code fetch.
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 31 8. t rp is specified as the minimum high time (thus inactive) on each of the 5 individual cs_ras [5:1] pins when such pin is programmed in the memory controller to service dram. the number of cclks (system clocks) in t rp is programmable, and is represented by n in the t rp equation in the ac tables. regardless of what value is programmed into the control register, n will never be less than 2 clocks . thus, at 30 mhz system clock, the minimum value for ras precharge is trp=((2 * t c ) 16= ((2 * 33.33) 16) = 50.6 ns. as the system clock frequency f c , is slowed down, t c (system clock period) of course becomes greater, and thus t rp becomes greater. 9. the min value for this parameter is guaranteed by design and is not tested in production to the specified limit. in those cas es where a maximum value is specified in the table for this parameter, it is tested. timing diagrams all references to numbered notes are to the notes following the ac electrical characteristics tables su01277 clkout a19a1 cs bhe /ble oe d15d0 t chav t chsl t avsl note 3 t dis t dih (note 2) t chsh a0 t chah t ahdr (does not include a0) note: on generic data reads, a0 can terminate a full clock period before a19a1, and therefore should not be used on some peripheral devices. figure 7. generic (sram, rom, flash, i/o devices, etc.) read on 16-bit bus
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 32 oe cs note: the processor can prefetch from one to eight words. su01131 clkout a[19:0] bhe /ble d[15:0] note 3 t chsl address address + 2 address + 4 t chav t chav t chsh t ohde driven by xa driven by xa t chav t dis t dih note 2 t dis t dis t dih (note 2) t dih note 2 t avsl figure 8. generic (sram, rom, flash, etc.) burst code fetch on 16-bit bus su01278 t shah t chdv note 1 t chsl t chsh d we bhe /ble cs a t chav clkout t shdh t avsl figure 9. generic (sram, i/o devices, etc.) write
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 33 su01279 t chsl t chsh d oe cas (bhe /ble) ras (cs) a t chav clkout t avsl t chav cas address ras address t chah t chsl t avsl t chsh valid data t dis t dih t ohde note 2 figure 10. dram single read cycle su01280 t chsl t chsh d[15:0] oe cas (bhe /ble) ras (cs) a t chav clkout t avsl t chav cas address ras address t chah t chsl t avsl t cpwh t ohde note 4 cas address +2 t chsh note 4 t dis t dis t cpwl t chav note 3 driven by slave device driven by xa word (from cas addr) word (from cas addr +2) t chah t chah 4 byte fetch (1 word = 2 bytes) is shown on 16-bit bus, burst can be 2 to 16 bytes (1 to 8 words). figure 11. dram edo burst code fetch on 16-bit bus
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 34 su01281 t chsl d[15:0] oe casl , cash ras a t chah clkout t avsl t chav cas address ras address t avsl t cpwh note 2 cas address +2 t dis t dis t chav instruction instruction t chav note: the processor can fetch from one to eight words (1 word = 2 bytes) t chav t chsl note 2 t chsl t chsh t chah t chsh t chah figure 12. dram fpm (fast page mode) burst code fetch su01282 t chsl t chsh d we cas (bhe /ble) ras (cs) a clkout t avsl t chav cas address ras address t chah t avsl note 1 t chsh valid data t chsl t chah note. oe is inactive during all writes. t chdv figure 13. dram write (on 16-bit bus, also 8-bit write on 8-bit bus)
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 35 su01283 t dih d7 d0 oe ble cs a19 a1 clkout t avsl t chav t ahdr note 2 t chsh t chsl t ohde on all cycles on 8-bit bus, bhe remains high (inactive) note: on the external bus, all XA-H4 reads are 16-bit reads. if the cpu instruction only specifies 8-bits, then the cpu uses the appropriate byte, and discards the extra byte. thus, a8-bit readso and a16-bit readso appear to be identical on the bus. on an 8-bit bus, this will appear as two consecutive 8-bit reads even though the cpu will only use one of the two bytes. warning: some 8-bit i/o devices (especially fifos) cannot operate correctly with 2 bytes being read for a one byte read. the most commo n (and least expensive) solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boun daries. an added benefit of this tech- nique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecuti ve bytes. a0 t dis t dis note 2 note 3 driven by xa driven by xa figure 14. generic (sram, flash, i/o device, etc.) read (16-bit or 8-bit) on 8-bit bus clkout oe , ble , cs d[7:0] t chav su01245 t chav t chav t chav even address address + 1 ls byte t dih t chsh t dis address + 2 address + 3 t chav note 3 ms byte ls byte ms byte t dis t dis t dis t dih t dih t dih note 2 note 2 note 2 note 2 note: bhe remains high (inactive) for all accesses on an 8-bit bus. a burst code fetch can be from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here. figure 15. burst code fetch on 8-bit bus, generic memory
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 36 su01246 clkout ble , we t chav t chsh t chsl t shah t shah t avsl t dvsl t shdh t avsl t chsl cs a0 a19 a1 d7 d0 note. oe is inactive during all writes. figure 16. generic 16-bit write on 8-bit bus su01284 t chav cas address t chah t avsl note 2 t chsl clkout oe d[7:0] casl (cash stays high) a ras t chav t chav t chav t chah cas address even cas address odd t avsl t chsl t dih note 2 t chsh t chsh ms byte ls byte t dis t dis t cpwh t chsl t chah figure 17. 16-bit read on 8-bit bus, dram (both fpm and edo)
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 37 su01285 t chav ras addr clkout oe d[7:0] casl a ras t avsl t chsl note 2 ms byte ls byte t dis t chah 123456789101112131415 cas addr even cas addr odd cas addr even cas addr odd note 2 t chsh t chsh t avsl ms byte ls byte t chsh t dih t cpwh t ohde t chsl 4-byte fetch is shown on 8-bit bus, burst can be 2 to 16 bytes. data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example). t dih figure 18. dram fpm (fast page mode) burst code fetch on 8-bit bus su01286 t chsl t chsh t avsl t chav ras address t ohde t avsl note 4 t cpwl t chah clkout oe d[7:0] casl a ras ls byte ms byte ls byte ms byte note 4 note 3 123456789101112 t cpwh t chsh t dis t chsl t chsh note. 4-byte fetch is shown on 8-bit bus, burst can be 2 to 16 bytes. to meet hold time, edo dram drives data until oe rises, or until a new falling edge of cas . data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 8, 10, and 12 in this example). cas addr even cas addr odd cas addr even cas addr odd figure 19. edo dram burst code fetch on 8-bit bus
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 38 t cpwh su01287 t chsl t avsl t chav clkout we d[7:0] casl a ras (cs ) ls byte t chsh ms byte t chav t chsl t chav t chav t chsl t chah t chah t chah t chsh t dvsl t dvsl t avsl cas address even cas address odd ras address figure 20. dram 16-bit write on 8-bit bus (fpm or edo drams) su01288 t chsl clkout cash , casl ras t clrl t chsh ras and cas terminate together. the active low portion of ras can be programmed to last from 3 to 6 clock cycles. the high portion of ras after refresh can be programmed to last from 2 to 4 clock cycles. see chapter 3 of the XA-H4 user manual. figure 21. refresh su01289 ras note: t rp minimum is specified for each of the 5 individual ras pins (cs _ras [5:1]) it is the minimum high time (thus ras inactive) between two dram bus cycles on the same ras pin. t rp figure 22. ras precharge time
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 39 xtalin su01146 v dd 0.5 0.2 v dd 0.1 t chcl t clcx t c t clch t chcx 0.7 v dd 0.45 v figure 23. external clock input drive su01147 clkout warning: clkout is specified into 40 pf max, do not overload. t codh figure 24. clkout duty cycle clkout su01148 wait t ws t wh t ws setup time of wait to rising edge of clkout. t wh hold time of wait after clkout high. figure 25. external wait pin timing
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 40 lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 41 notes
philips semiconductors preliminary specification XA-H4 single-chip 16-bit microcontroller 1999 sep 24 42 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. date of release: 09-99 document order number: 9397 750 06432

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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